JP6453375B2 - 半導体素子を選択的にトランスファーする方法及び半導体構造 - Google Patents
半導体素子を選択的にトランスファーする方法及び半導体構造 Download PDFInfo
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- JP6453375B2 JP6453375B2 JP2017075001A JP2017075001A JP6453375B2 JP 6453375 B2 JP6453375 B2 JP 6453375B2 JP 2017075001 A JP2017075001 A JP 2017075001A JP 2017075001 A JP2017075001 A JP 2017075001A JP 6453375 B2 JP6453375 B2 JP 6453375B2
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Description
a.第一表面及び第二表面を有する基板を提供し;
b.前記第一表面に複数の半導体エピタキシャルスタック層を提供し、前記複数の半導体エピタキシャルスタック層は、第一半導体エピタキシャルスタック層及び第二半導体エピタキシャルスタック層を含み、前記第二半導体エピタキシャルスタック層と前記第一半導体エピタキシャルスタック層とは隔てれられ、前記第一半導体エピタキシャルスタック層と前記基板との間の粘着力は、前記第二半導体エピタキシャルスタック層と前記基板との間の粘着力とは異なり;及び
c.前記基板から前記第一半導体エピタキシャルスタック層又は前記第二半導体エピタキシャルスタック層を選択的に分離するステップを含む。
Claims (9)
- 半導体構造であって、
第一表面を有する基板;
前記第一表面の上に位置し、且つ少なくとも1つの第一半導体素子と少なくとも1つの第二半導体素子を含む複数の半導体素子;及び
前記基板と前記複数の半導体素子との間に位置し、且つ粘着層及び犠牲層を含む粘着構造を含み、
前記粘着層と前記犠牲層との材質は、異なり、前記粘着層及び前記犠牲層は、前記第一半導体素子に直接接触し、
前記犠牲層は、前記第一半導体素子に一時的に粘着するために用いられ、
前記第二半導体素子は、粘着層により前記基板の前記第一表面に粘着する、半導体構造。 - 請求項1に記載の半導体構造であって、
前記粘着層と前記第一半導体素子との間的粘着力は、前記犠牲層と前記第一半導体素子との間の粘着力よりも大きい、半導体構造。 - 請求項1に記載の半導体構造であって、
前記第一半導体素子は、前記第一表面に対向する第二表面を有し、該第二表面は、前記粘着層及び前記犠牲層に接する、半導体構造。 - 請求項3に記載の半導体構造であって、
前記犠牲層は、前記第二表面と前記粘着層との間に位置する、半導体構造。 - 請求項3に記載の半導体構造であって、
前記粘着層は、前記第二表面の中央部のみに粘着する、半導体構造。 - 請求項1に記載の半導体構造であって、
前記粘着層の材料は、BCBを含む、半導体構造。 - 請求項1に記載の半導体構造であって、
前記犠牲層の材料は、SiOx又はSiNxを含む、半導体構造。 - 請求項1に記載の半導体構造であって、
前記第一表面と前記第一半導体素子との間に位置する前記粘着構造の厚みは、2μm〜6μmの間にある、半導体構造。 - 請求項1に記載の半導体構造であって、
前記基板の材料は、サファイア(Sapphire)、ダイヤモンド(Diamond)、グラス(Glass)、石英(Quartz)、アクリル(Acryl)、ZnO、AlN、LiAlO2、セラミック基板、又はSiを含む、半導体構造。
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