JP6450282B2 - Compound semiconductor substrate and method of manufacturing compound semiconductor substrate - Google Patents

Description

  The present invention relates to a compound semiconductor substrate and a method for manufacturing a compound semiconductor substrate, and more particularly to a compound semiconductor substrate having a SiC (silicon carbide) layer and a method for manufacturing the compound semiconductor substrate.

  SiC has a larger band gap than Si (silicon) and a high dielectric breakdown electric field strength. For this reason, SiC is expected as a material for a semiconductor device having a high breakdown voltage. Further, since SiC has a lattice constant close to that of GaN (gallium nitride), it can be used as a buffer layer for growing GaN. When SiC is used as a buffer layer for growing GaN, since both GaN and SiC have high breakdown field strength, a GaN semiconductor device with higher breakdown voltage can be realized.

  As a base substrate for growing SiC, a Si substrate or a bulk SiC substrate is widely used. Among these, the bulk SiC substrate has a problem that it is difficult to increase the diameter. In order to obtain inexpensive and large-diameter SiC, it is preferable to use a Si substrate as a base substrate. In this case, 3C-SiC (SiC having a 3C type crystal structure) is generally grown on the Si substrate.

  As a method for growing a high-quality 3C—SiC single crystal on Si, a gas source MBE (Molecular Beam Epitaxy) method is known (for example, Non-Patent Document 1). In this method, since 3C—SiC is grown at a low temperature, the stress in the layer can be reduced. For this reason, the gas source MBE method is an advantageous method from the viewpoint of increasing the diameter of 3C-SiC. In recent years, a 3C-SiC layer (hereinafter referred to as a 3C-SiC (111) layer) having a (111) plane of a thickness of 0.1 to 3.0 [mu] m manufactured on a Si substrate using a gas source MBE method is used. Is sometimes used as a base for growing GaN (for example, Non-Patent Document 2).

  FIG. 16 is a table showing physical property values of the wide gap semiconductor.

  Referring to FIG. 16, 3C-SiC is a wide gap semiconductor having a band gap of 2.23 eV. 3C-SiC has a high electron mobility equivalent to 4H-SiC. Furthermore, it is known that the interface state density of 3C—SiC at the oxide film interface is sufficiently low (for example, Non-Patent Document 3). Therefore, when 3C-SiC is used for a MOS transistor, handling when a large current flows can be made advantageous, and the mobility of electrons in the interface inversion layer can be improved.

  Conventionally, the production and evaluation of a 3C-SiC layer having a (100) plane as a main surface (hereinafter sometimes referred to as a 3C-SiC (100) layer) is more performed and evaluated than a 3C-SiC (111) layer. I have been. This is because the interface state density of the 3C—SiC (100) layer at the oxide film interface is lower than the interface state density of the 3C—SiC layer whose main surface is the other plane orientation. However, the 3C-SiC (100) layer has many crystal defects such as DPB (Double Positioning Boundary) and stacking faults (hereinafter sometimes referred to as SF (Stacking Fault)), and the crystal quality is low. was there.

  FIG. 17 is a diagram schematically illustrating DPB generated when 3C—SiC (100) grows on a Si (100) just substrate. In FIG. 17, the apex portion of the rectangle indicates the position of the Si atom or C atom.

  Referring to FIG. 17, the Si (100) just substrate is a Si substrate having an off angle, which is an inclination angle of the Si (100) plane with respect to the main surface of the substrate, of 1 degree or less. Six faces PP101 to PP106 of the 3C—SiC (100) layer are grown on the (100) face of the Si (100) just substrate. Each of the surfaces PP101 to PP106 is composed of an upper surface that is a (100) surface, two side surfaces that are (111) surfaces facing each other, and two side surfaces that are (-1-1-1) surfaces facing each other. It is configured. The two side surfaces that are the (111) plane are Si planes, and the two side surfaces that are the (-1-1-1) plane are C planes.

  The crystal structure of the Si (100) just substrate, which is the base of the 3C—SiC (100) layer, is four-fold symmetric with respect to the [100] direction (the (100) plane normal). On the other hand, the crystal structure of the 3C—SiC (100) layer is twice symmetrical with respect to the [100] direction. During crystal growth of 3C—SiC, as in the planes PP101, PP102, and PP103, the (−1-1-1) plane appears on the left and right side surfaces in the drawing, and the (111) plane is the upper and lower side surfaces in the drawing. And (-1-1-1) plane may appear on the upper and lower side surfaces in the drawing, and (111) plane may appear on the left and right side surfaces in the drawing, like the planes PP104, PP105, and PP106. . Each of planes PP101, PP102, and PP103 and each of planes PP104, PP105, and PP106 are equivalent when rotated 90 degrees about the normal line of (100) plane. The DPB is a crystal caused by a mismatch that occurs at a place where the side Si surface and the C surface are adjacent, such as a position BR101 between the surfaces PP103 and PP104 and a position BR102 between the surfaces PP103 and PP106. It is a defect.

  As a technique for reducing the DPB of the 3C—SiC (100) layer, a method using an off-substrate, an undulation substrate, or the like has been proposed (for example, Non-Patent Documents 4 to 6).

  FIG. 18 is a diagram schematically showing the growth of a SiC crystal when each of the off-substrate and the undulation substrate is used. FIG. 18A is a diagram when an off-substrate is used, and FIG. 18B is a diagram when an undulation substrate is used.

  Referring to FIG. 18A, an off substrate is one in which an off angle of several degrees is provided with respect to the normal line of the main surface of the Si (100) substrate. According to the method of forming the 3C—SiC layer on the off-substrate, each crystal of the SiC layer 101 grows in the direction of the arrow AR101, so that the generation of DPB can be suppressed.

  Referring to FIG. 18B, the undulation substrate is one in which irregularities having a specific shape are formed on the main surface of the Si (100) substrate. According to the method of forming the 3C—SiC layer on the undulation substrate, the crystal of the SiC layer 101 grows from each of the inclined surfaces facing each other (for example, the inclined surfaces PL101 and PL102), and defects of these crystals are associated. Since it disappears, DPB can be reduced.

Yokoyama Takashi et al., 52nd JSAP Spring Meeting, 30p-YK-1 H. Fang et al., J. Appl. Phys. 115, 063102 (2014) Yusuke Yamamoto et al., 75th JSAP Autumn Meeting, 17p-A17-10 K.shibahara et al., J. Cryst. Growth, 78, 538 (1986) K.shibahara et al., Appl. Phys. Lett., 50, 1888 (1987) N. Hatta et al., 2011 ICSCRM

  Since 3C-SiC has a higher breakdown electric field than Si, application to devices having a higher breakdown voltage than Si is expected. For this purpose, it is necessary to improve the quality of the 3C—SiC layer. However, the conventional technique has a problem that the quality of the 3C—SiC layer is low.

  In the method of forming the 3C-SiC layer on the off-substrate (the method of FIG. 18A) or the method of forming the 3C-SiC layer on the undulation substrate (the method of FIG. 18B), a substrate is manufactured. At the same time, complicated processing steps and growth steps are required, leading to high cost of the substrate.

  Furthermore, when trying to obtain a high-quality crystal by increasing the thickness of 3C-SiC formed on the Si (100) substrate, due to the difference in lattice constant and thermal expansion coefficient between Si and SiC, There has been a problem that excessive stress is applied to the Si substrate, causing cracks in the Si substrate or cracks in the SiC layer.

  The present invention is to solve the above-described problems, and an object thereof is to provide a compound semiconductor substrate having a high-quality 3C—SiC layer and a method for manufacturing the compound semiconductor substrate.

A compound semiconductor substrate according to one aspect of the present invention includes: a Si substrate having a surface constituted by a (111) plane; and a single layer having a surface constituted by a (111) plane formed on the surface of the Si substrate . 3C-SiC layer , no SiC layer is formed on the back surface of the Si substrate, the thickness of the 3C-SiC layer is not less than 100 μm and not more than 400 μm, and the surface of the 3C-SiC layer is irradiated with X-rays (2) When the φ scan is performed in the range of 0 to 360 degrees under the condition that (220) diffraction can be detected, the diffraction having the first to third largest diffraction intensities in the graph showing the φ dependence of the diffraction intensity When the average intensity of the peak is the average intensity AV1, and the average intensity of the diffraction peak having the fourth to sixth largest diffraction intensity in the graph is the average intensity AV2, the ratio of the two average intensity (AV2 / AV1) is 0. Greater Ri der than 0.5%, in the cross section surface of the 3C-SiC layer, the number of stacking faults appearing per unit length is 2,000 / cm or less greater than 0.

  In the compound semiconductor substrate, preferably, the 3C—SiC layer has a planar shape having a diameter of 2 inches or more and less than 8 inches.

  Preferably, in the compound semiconductor substrate, the 3C—SiC layer has a planar shape having a diameter of less than 4 inches.

  A method of manufacturing a compound semiconductor substrate according to another aspect of the present invention includes a step of forming an annular planar mask so as to cover an outer peripheral region of the Si (111) substrate surface, and having an opening in the center. After the step of forming the 3C-SiC layer in the region exposed without forming the mask on the Si (111) substrate surface and the step of heteroepitaxially growing the 3C-SiC layer in the region exposed without forming the mask, And removing the Si (111) substrate by using.

  Preferably, in the above manufacturing method, the opening has a diameter of 2 inches or more.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the compound semiconductor substrate provided with the high quality 3C-SiC layer and a compound semiconductor substrate can be provided.

It is a perspective view which shows typically compound semiconductor substrate SR in one embodiment of this invention. It is a figure which shows the 1st manufacturing process of compound semiconductor substrate SR in one embodiment of this invention. It is a figure which shows the 2nd manufacturing process of compound semiconductor substrate SR in one embodiment of this invention. It is a table | surface which shows typically the time change of the temperature of the Si substrate 11 at the time of forming the SiC layer 21 using CVD method. It is a figure which shows the 3rd manufacturing process of compound semiconductor substrate SR in one embodiment of this invention. 3 is a cross-sectional view schematically showing a force generated at an interface between the Si substrate 11 and the SiC layer 1. FIG. It is a figure which shows typically a mode that the crystal | crystallization of the SiC layer 21 grows on the (111) plane of the Si substrate 11. FIG. It is a table | surface which shows the preparation conditions and evaluation result of each sample in one Example of this invention. It is a figure which shows typically the structure of a 2 (theta)-(theta) scanning apparatus. 3 is a graph showing the result of 2θ-θ scan for sample C. FIG. It is a figure which shows typically the structure of a (phi) scanning apparatus. 5 is a graph showing the φ dependence of diffraction intensity for Sample C. 5 is a graph showing the φ dependence of diffraction intensity for Sample B. 4 is a graph showing the φ dependence of diffraction intensity for Sample A. FIG. 15A is an image of a cross section SEM of the sample C. FIG. FIG. 15B is an image of a cross-section TEM of the sample C. It is a table | surface which shows the physical-property value of a wide gap semiconductor. It is a figure which shows typically DPB produced when 3C-SiC (100) grows on a Si (100) just substrate. It is a figure which shows typically the growth of the SiC crystal at the time of utilizing each of an off board | substrate and an undulation board | substrate.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  [Configuration and Manufacturing Method of Compound Semiconductor Substrate]

  FIG. 1 is a perspective view schematically showing a compound semiconductor substrate SR in one embodiment of the present invention.

  Referring to FIG. 1A, compound semiconductor substrate SR in the present embodiment has a planar shape of a circle having a diameter of, for example, 2 inches or more. The compound semiconductor substrate SR includes the SiC layer 1. The SiC layer 1 has a 3C-SiC crystal structure, and has a surface 1a composed of (111) planes. The thickness W of the SiC layer 1 is not less than 2 μm and not more than 400 μm. When φ scan is performed in the range of 0 to 360 degrees under the condition that (220) diffraction can be detected by X-ray irradiation on the surface of the 3C-SiC layer 1, the φ dependence of diffraction intensity is shown. When the average intensity AV1 is the average intensity of the diffraction peak having the first to third highest diffraction intensity in the graph and the average intensity AV2 is the average intensity of the diffraction peak having the fourth to sixth highest diffraction intensity in the graph, The ratio of average intensity (AV2 / AV1) is greater than 0 and 0.5% or less. Preferably, SiC layer 1 has a thickness of 100 μm or more, and the number of SF appearing per unit length on the surface of the cross section of SiC layer 1 is greater than 0 and equal to or less than 2000 / cm. The SiC layer 1 is preferably a planar shape having a diameter of 2 inches or more and less than 8 inches, more preferably 2 inches or more and less than 4 inches.

  With reference to FIG. 1B, the compound semiconductor substrate SR may further include a Si substrate 11. The Si substrate 11 is used as a base when the SiC layer 1 is formed, and the Si and SiC substrate main surface is the (111) plane. The SiC layer 1 is formed on the surface 11 a of the Si substrate 11. The Si substrate 11 is preferably a Si (111) just substrate. The Si (111) just substrate is a Si substrate having an off angle, which is an inclination angle of the Si (111) surface with respect to the main surface of the substrate, of 1 degree or less.

  When the thickness W of the SiC layer 1 is smaller than the area of the planar shape of the SiC layer 1, the mechanical strength of the SiC layer 1 is low. In this case, the SiC layer 1 may be reinforced by the Si substrate 11 as shown in FIG. On the other hand, when thickness W of SiC layer 1 is larger than the area of the planar shape of SiC layer 1, mechanical strength of SiC layer 1 is increased. In this case, as shown in FIG. 1A, the mechanical strength can be maintained even with the SiC layer 1 alone. Hereinafter, what constitutes the compound semiconductor substrate SR by the SiC layer 1 alone may be referred to as a free-standing substrate.

  FIG. 2 is a diagram showing a first manufacturing process of the compound semiconductor substrate SR in one embodiment of the present invention. 2A is a cross-sectional view, and FIG. 2B is a plan view.

  Referring to FIG. 2A, the Si substrate 11 is prepared. The Si substrate 11 is made of a general-purpose Si (111) just substrate having a diameter of 4 inches, for example. The Si substrate 11 may be undoped Si or may be doped with p-type or n-type impurities. Next, a mask 12 is formed on the surface 11 a of the Si substrate 11.

With reference to FIG. 2B, the mask 12 is formed in an annular planar shape so as to cover the outer peripheral region of the surface 11 a of the Si substrate 11. The mask 12 has an opening 12a at the center thereof. The opening 12a has a diameter of, for example, 2 inches or more. At the center of the Si substrate 11 on which the mask 12 is not formed, the surface 11a is exposed in a planar shape of a circle having a diameter of 2 inches or more. The mask 12 is made of, for example, metal, SiC, or SiO ₂ . Note that the shape of the mask 12 is arbitrary, and any shape that covers a part of the surface 11a of the Si substrate 11 may be used.

  FIG. 3 is a diagram showing a second manufacturing process of the compound semiconductor substrate SR in one embodiment of the present invention.

  Referring to FIG. 3, next, for example, by using a low temperature CVD (Chemical Vapor Deposition) method, a region exposed on surface 11 a of Si substrate 1 where mask 12 is not formed and SiC layer 21 is formed on mask 12. Heteroepitaxially grown. The SiC layer 21 is formed with a thickness of 2 μm or more and 400 μm or less, preferably 100 μm or more.

  FIG. 4 is a table schematically showing temporal changes in the temperature of the Si substrate 11 when the SiC layer 21 is formed using the CVD method.

  Referring to FIG. 4, when forming SiC layer 21, Si substrate 11 on which mask 12 is formed is placed in a film forming chamber, and the pressure in the film forming chamber is reduced. Next, for example, the Si substrate 11 is heated from room temperature to a predetermined film formation temperature over a period of about 10 minutes. The film forming temperature is, for example, 1050 to 1100 ° C.

After the temperature of the Si substrate 11 reaches the film formation temperature, the source gas is introduced into the film formation chamber for 5 to 12 hours, for example. The source gas is, for example, monomethylsilane. The flow rate of the source gas is, for example, 20-30 sccm. The pressure in the film forming chamber during the introduction of the source gas is, for example, 2 × 10 ^{−4 to} 3 × 10 ⁻⁴ Torr (0.02 to 0.03 Pa). During the introduction of the source gas, the flow rate of the source gas may be periodically changed over time within the above range.

  After the introduction of the source gas is completed, the Si substrate 11 is cooled from the film formation temperature to a temperature lower than 200 ° C. over a period of, for example, about 65 minutes.

  In addition, before forming the SiC layer 21 using CVD method, you may carbonize with respect to the exposed surface 11a.

  FIG. 5 is a diagram showing a third manufacturing process of the compound semiconductor substrate SR in one embodiment of the present invention.

  Referring to FIG. 5, next, mask 12 is removed from surface 11a of Si substrate 11 using a stripping solution or the like. At this time, the SiC layer 21 formed on the mask 12 is removed together with the mask 12. A part of the SiC layer 21 remains on the surface 11 a of the Si substrate 11 to become the SiC layer 1. The SiC layer 1 is limited by the mask 12 to a circular area having a diameter of 2 inches in the center of the Si substrate 11.

  Next, the Si substrate 11 is removed by etching using a stripping solution such as hydrofluoric acid. In this case, the compound semiconductor substrate SR (self-standing substrate) shown in FIG. When the SiC layer 1 is thin, the Si substrate 11 is diced along the line LN1 in FIG. 5 while leaving the Si substrate 11 directly below the SiC layer 1. In this case, the compound semiconductor substrate SR shown in FIG. 1B is obtained. Furthermore, the Si substrate 11 may not be removed.

  [Effect of the embodiment]

  According to the present embodiment, the region for forming SiC layer 1 is limited to a part of surface 11 a of Si substrate 11 by mask 12. Thereby, SiC layer 1 can be made thick while suppressing generation of cracks in Si substrate 11 and cracks in SiC layer 1. As a result, defects are eliminated by increasing the thickness of the SiC layer 1, and the quality of the 3C-SiC layer can be improved.

  FIG. 6 is a cross-sectional view schematically showing the force generated at the interface between the Si substrate 11 and the SiC layer 1. FIG. 6A shows a case where the SiC layer 1 is formed without using the mask 12 as a comparative example. FIG. 6B is a diagram when the SiC layer 1 is formed using the mask 12 as in the present embodiment.

Referring to FIG. 6A, when mask 12 is not used, SiC layer 1 is formed on the entire surface 11a of Si substrate 11. The lattice constant (0.308 nm) of the SiC (111) surface is smaller than the lattice constant (0.384 nm) of the Si (111) surface, and the thermal expansion coefficient (2.6 × 10 ¹⁶ / K) of the Si (111) surface. ) Has a larger coefficient of thermal expansion (2.8 × 10 ¹⁶ / K) on the SiC (111) surface. For this reason, the SiC crystal is greatly contracted during cooling after the formation of the SiC layer 1, a contraction force indicated by an arrow F <b> 1 is generated on the entire interface of the Si substrate 11 with the SiC layer 1, and a moment M is generated in the Si substrate 11. As a result, the Si substrate 11 is deformed, the SiC layer 1 is deformed and cracked, and the SiC layer 1 cannot be thickened.

  Referring to FIG. 6B, when mask 12 is used, the region where SiC layer 1 is formed is limited to a part of surface 11 a of Si substrate 11. For this reason, even if the SiC crystal contracts greatly during cooling after the formation of SiC layer 1, the contraction force indicated by arrow F <b> 1 occurs only in part of region RG <b> 1 at the interface with SiC layer 1 in Si substrate 11. As a result, the deformation amount of the Si substrate 11 is small, the SiC layer 1 is not cracked, and the SiC layer 1 can be thickened. Thereby, defects in SiC layer 1 can be reduced as an effect of increasing the film thickness.

  In addition, according to the present embodiment, by growing 3C-SiC having the (111) plane as a surface, it is simple and inexpensive without performing complicated processing steps and growth steps when manufacturing a substrate. DPB and SF can be reduced by the method.

  FIG. 7 is a diagram schematically showing how the crystal of the SiC layer 21 grows on the (111) plane of the Si substrate 11. In FIG. 7, the apex portion of the triangle or quadrangle indicates the position of the Si atom or C atom.

  Referring to FIG. 7, four 3C-SiC surfaces PP1 to PP4 that become SiC layer 21 grow on the (111) surface, which is surface 11a (main surface) of Si substrate 11. Each of the surfaces PP1 to PP4 includes an upper surface that is a (111) plane, three side surfaces that are a (100) plane, and three side surfaces that are a (-1-1-1) plane. The upper surface which is the (111) plane is the Si plane, the three side faces which are the (100) plane are Si planes, and the three side faces which are the (-1-1-1) plane are C planes.

  The crystal structures of the Si substrate 11 and the SiC layer 21 are both three-fold symmetric with respect to the [111] direction (the (111) plane normal) and have the same rotational symmetry (120 degrees). . For this reason, the position of the Si atom in the Si crystal of the Si substrate 11 and the position of the Si atom in the 3C—SiC crystal of the SiC layer 21 are matched. All the (100) planes that are the opposite side faces in the planes PP1 to PP4 are Si planes. All of the (-1-1-1) planes, which are other opposing side faces in the planes PP1 to PP4, are C planes. As a result, the SFs contained in the crystals grown from the (100) planes of the planes PP1 to PP4 face each other, and these SFs disappear together. As a result, DPB and SF can be reduced.

  [Example]

  In this example, samples A to G as compound semiconductor substrates were produced under different production conditions, and the quality was evaluated. Samples B to D are examples (examples of the present invention), and samples A, E, F, and G are comparative examples.

  FIG. 8 is a table showing production conditions and evaluation results for each sample in one example of the present invention.

  Referring to FIG. 8, in Samples A to E, a Si (111) just substrate was used as the Si substrate for the purpose of forming a SiC (111) layer. In samples F and G, a Si (100) just substrate was used as the Si substrate for the purpose of forming a SiC (100) layer.

  Next, an SiC layer was formed on the Si substrate under the condition that 3C-SiC was formed. In sample A, the thickness of the SiC layer was 160 nm. In samples B and F, the thickness of the SiC layer was 2 μm. In samples C, E, and G, the thickness of the SiC layer was 100 μm. In sample D, the thickness of the SiC layer was 400 μm. The thickness of the SiC layer was observed using an ellipsometer. Further, in forming the SiC layer, in Samples A to D, the formation area of the SiC layer was limited to a circular area at the center of the Si substrate by using a mask. In samples E to G, a SiC layer was formed on the entire surface of the Si substrate without using a mask.

  After the formation of the SiC layer, the Si substrate was cooled to room temperature, and the presence or absence of cracking of the Si substrate on which the SiC layer was formed was visually evaluated. As a result, in Samples A to D and F, no cracks were confirmed on the Si substrate on which the SiC layer was formed. On the other hand, in Samples E and G, it was confirmed that the Si substrate on which the SiC layer was formed was cracked.

  Next, the surface orientation of the surface of the SiC layer in each of Samples A to D and F in which no cracks occurred after the SiC layer was formed was evaluated using a 2θ-θ scan. As a result, it was confirmed that each of the samples A to D was a single crystal substrate in which the surface of the SiC layer was configured with a (111) plane. It was confirmed that Sample F was a single crystal substrate in which the surface of the SiC layer was configured with a (100) plane. For samples E and G in which cracks occurred after the formation of the SiC layer, the φ scan, SF density, and the presence or absence of cracks when SiC was self-supported were not evaluated.

  Next, the DPB density in each of Samples A to D and F in which no cracks and cracks occurred after the SiC layer was formed was 360 degrees using X-rays irradiated from the [220] direction to the surface of the SiC layer. This was evaluated by performing a φ scan. As a result, in samples B to D, the peak intensity ratio described later was 0.5% or less, and it was found that DPB was reduced. In addition, the difference of the peak intensity ratio between each of samples BD was not seen. On the other hand, in Samples A and F, the peak intensity ratio was greater than 0.5%, and DPB was not sufficiently reduced. In particular, in sample F, four peaks showing the 4-fold symmetry of the crystal appeared. In addition, the density of DPB was not evaluated about the samples E and G in which the crack and the crack generate | occur | produced after SiC layer formation.

  Next, the cross sections of the samples A to D and F in which no cracks and cracks occurred were observed with a scanning electron microscope (SEM) and a transmission electron microscope (TEM), and SF existing on the substrate surface per unit length. The number (SF density) of was evaluated. As a result, in samples C and D, the SF density was 2000 lines / cm or less, and was about 1000 lines / cm. On the other hand, in samples A, B, and F, the SF density was larger than 2000 pieces / cm. In addition, SF density was not evaluated about the samples E and G in which the crack and the crack generate | occur | produced after SiC layer formation.

  Finally, in each of Samples A to D and F where cracks and cracks did not occur, the Si substrate was removed from the SiC layer to obtain a SiC self-supporting substrate. And the presence or absence of the generation | occurrence | production of the crack to a SiC layer was evaluated visually. As a result, in Samples C and D, the SiC layer was sufficiently thick, so that no crack was generated in the SiC layer. On the other hand, for Samples A, B, and F, since the SiC layer was thin, cracks occurred in the SiC layer.

  FIG. 9 is a diagram schematically showing the configuration of the 2θ-θ scanning apparatus.

  Referring to FIG. 9, the 2θ-θ scanning apparatus includes an irradiation source 51 and a detector 52. The irradiation source 51 irradiates the compound semiconductor substrate SR with X-rays at an incident angle θ. The detector 52 receives the reflected light from the compound semiconductor substrate SR. The irradiation source 51 is fixed. The tilt angle of the compound semiconductor substrate SR is continuously changed so that the incident angle θ changes. The detector 52 is moved in conjunction with the tilt angle of the compound semiconductor substrate SR so as to receive reflected X-rays at a position that is at an angle 2θ with respect to the X-ray incident direction. According to the 2θ-θ scan, the crystal plane constituting the surface can be evaluated.

  As the 2θ-θ scanning device, an X-ray device called Model D8 Discover made by Bruker, or an X-ray device called Model X′Pert PRO MDD made by Panaltical was used.

  FIG. 10 is a graph showing the result of the 2θ-θ scan for the sample C.

  Referring to FIG. 10, in sample C, a large diffraction peak derived from the (111) plane appeared when θ was between 30 degrees and 40 degrees. Further, when θ is between 70 degrees and 80 degrees, a small diffraction peak derived from the (222) plane appeared. No other diffraction peak was generated.

  FIG. 11 is a diagram schematically showing the configuration of the φ scanning device.

  Referring to FIG. 11, the φ scanning device includes an irradiation source 61 and a detector 62. The irradiation source 61 irradiates the surface of the SiC layer with X-rays from the SiC [220] direction. The detector 62 receives the reflected X-rays on the compound semiconductor substrate SR. The compound semiconductor substrate SR is rotated 360 degrees around the φ axis (the normal to the surface of the SiC layer). Thereby, a 360-degree φ scan is performed on the surface of the SiC layer. According to φ scan, DPB can be evaluated based on the peak of reflected X-ray intensity.

  As the φ scanning apparatus, an X-ray apparatus called Model D8 Discover made by Bruker, or an X-ray apparatus called Model X′Pert PRO MDD made by Panaltical was used.

  FIG. 12 is a graph showing the φ dependence of the diffraction intensity for Sample C.

  Referring to FIG. 12, in sample C, diffraction peaks P1, P2, and P3 having a period of 120 degrees showing the three-fold symmetry of SiC (111) predominantly appeared. Diffraction peaks P1, P2, and P3 were diffraction peaks having the first to third largest diffraction intensities. Further, diffraction peaks P4, P5, and P6 having a period of 120 degrees derived from DPB also appeared. Diffraction peaks P4, P5, and P6 were diffraction peaks having the fourth to sixth largest diffraction intensity. The ratio (AV2 / AV1) of the average intensities AV2 of the diffraction peaks P4, P5, and P6 to the average intensities AV1 of the diffraction peaks P1, P2, and P3 (hereinafter sometimes referred to as peak intensity ratio) is 0.5. % Or less and about 0.3%. Thereby, it turned out that the crystal structure of the 3C-SiC layer in the sample C has a high three-fold symmetry, and that DPB is reduced.

  FIG. 13 is a graph showing the φ dependence of the diffraction intensity for Sample B.

  Referring to FIG. 13, in sample B, diffraction peaks P1, P2, and P3 having a period of 120 degrees showing the three-fold symmetry of SiC (111) predominantly appeared. Diffraction peaks P1, P2, and P3 were diffraction peaks having the first to third largest diffraction intensities. Further, diffraction peaks P4, P5, and P6 having a period of 120 degrees derived from DPB also appeared. Diffraction peaks P4, P5, and P6 were diffraction peaks having the fourth to sixth largest diffraction intensity. The peak intensity ratio was 0.5% or less and about 0.3%. Thereby, it turned out that the crystal structure of the 3C-SiC layer in the sample B has high three-fold symmetry, and it has been found that DPB is reduced.

  FIG. 14 is a graph showing the φ dependence of the diffraction intensity for Sample A.

  Referring to FIG. 14, in sample A, diffraction peaks P1, P2, and P3 having a period of 120 degrees showing the 3-fold symmetry of SiC (111) appeared. Diffraction peaks P1, P2, and P3 were diffraction peaks having the first to third largest diffraction intensities. Further, diffraction peaks P4, P5, and P6 having a period of 120 degrees derived from DPB also appeared. Diffraction peaks P4, P5, and P6 were diffraction peaks having the fourth to sixth largest diffraction intensity. The peak intensity ratio was greater than 0.5% and about 7%. Thereby, it was found that the symmetry of the crystal structure of the 3C—SiC layer in Sample A was low, and DPB was not sufficiently reduced.

  FIG. 15A is a cross-sectional SEM image of the sample C, and FIG. 15B is a cross-sectional TEM image of the sample C.

  Referring to FIG. 15, almost no line indicating the presence of SF was found on the surface of sample C composed of the (111) plane, and the SF density was 2000 lines / cm or less.

  The above-described embodiments and examples are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1,21,101 SiC (silicon carbide) layer 1a SiC layer surface 11,111 Si (silicon) substrate 11a Si substrate surface 12 Mask 12a Mask opening 51,61 Irradiation source 52,62 Detector AR101 SiC layer crystal Growth direction BR101, BR102 Position where DPB (Double Positioning Boundary) is generated F1 Contracting force generated in SiC layer LN1 Line dicing Si substrate M Moment P1, P2, P3, P4, P5, P6 Diffraction peak PL101, PL102 Slope PP1, PP2, PP3, PP4, PP101, PP102, PP103, PP104, PP105, PP106 plane RG1 Area where contraction force is generated SR Compound semiconductor substrate W SiC layer thickness

Claims (5)

A Si substrate having a surface composed of (111) planes;
A single 3C-SiC layer formed on the surface of the Si substrate and having a surface composed of (111) planes ,
No SiC layer is formed on the back surface of the Si substrate,
The thickness of the 3C—SiC layer is 100 μm or more and 400 μm or less,
When φ scan is performed in the range of 0 to 360 degrees under the condition that (220) diffraction can be detected by X-ray irradiation on the surface of the 3C-SiC layer, the dependence of diffraction intensity on φ is shown. When the average intensity AV1 is the average intensity of the diffraction peak having the first to third highest diffraction intensity in the graph, and the average intensity AV2 is the average intensity of the diffraction peak having the fourth to sixth highest diffraction intensity in the graph, 2 One fraction of the mean intensity (AV2 / AV1) is state, and are less than 0.5% greater than 0,
The compound semiconductor substrate, wherein the number of stacking faults that appear per unit length on the surface of the cross section of the 3C—SiC layer is greater than 0 and equal to or less than 2000 / cm . The compound semiconductor substrate according to claim 1 , wherein the 3C—SiC layer has a planar shape having a diameter of 2 inches or more and less than 8 inches. The compound semiconductor substrate according to claim 2 , wherein the 3C—SiC layer has a planar shape having a diameter of less than 4 inches. Forming an annular planar mask having an opening in the center so as to cover the outer peripheral region of the Si (111) substrate surface;
After the step of forming the mask, heteroepitaxially growing a 3C-SiC layer in a region exposed without forming the mask on the Si (111) substrate surface;
And a step of removing the Si (111) substrate using a stripping solution after the step of heteroepitaxially growing the 3C-SiC layer. The method of manufacturing a compound semiconductor substrate according to claim 4 , wherein the opening has a diameter of 2 inches or more.