JP6443136B2 - Semiconductor devices, electronic equipment and mobile objects - Google Patents

Description

  The present invention relates to a semiconductor device, an electronic apparatus, and a moving object.

  For example, the MEMS vibrator of Patent Document 1 has a configuration in which a recess is provided on the upper surface of a silicon substrate, a vibration element is disposed in the recess, and the opening of the recess is covered with a lid. Thus, by providing a recess in the silicon substrate and disposing the vibration element in the recess, the height of the MEMS vibrator can be reduced. However, in the MEMS vibrator of Patent Document 1, since the connection portion between the side surface and the bottom surface of the concave portion is a corner, stress is easily concentrated at this corner, and a crack is generated in the silicon substrate starting from this corner, Crystal defects may occur. When such a problem occurs, the reliability of the MEMS vibrator decreases.

US Pat. No. 5,798,283

  An object of the present invention is to provide a semiconductor device, an electronic apparatus, and a moving body that can reduce stress concentration and exhibit excellent reliability.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following application examples.

[Application Example 1]
The semiconductor device of this application example includes a functional element,
A bottom surface on which the functional element is disposed;
A wall surface disposed around the bottom surface;
It has a 1st curved surface which is arrange | positioned between the said bottom face and the said wall surface, and has connected the said bottom face and the said wall surface.
Thereby, since it is difficult to form a corner between the bottom surface and the wall surface, the stress concentration on the portion is reduced. Therefore, a semiconductor device that can exhibit excellent reliability can be obtained.

[Application Example 2]
In the semiconductor device of this application example, it is preferable that the first curved surface is a concave surface.
Thereby, the bottom surface and the wall surface are more continuously connected by the first curved surface.

[Application Example 3]
In the semiconductor device of this application example, it is preferable that the wall surface has a second curved surface that is located on the side opposite to the bottom surface and connected to the wall surface.
Thereby, the stress concentration on the side opposite to the bottom surface of the wall surface can be reduced.

[Application Example 4]
In the semiconductor device of this application example, it is preferable that the second curved surface is a convex surface.
Thereby, a 2nd curved surface and a wall surface connect more continuously.

[Application Example 5]
In the semiconductor device of this application example, it is preferable that the wall surface is inclined so as to face the side opposite to the bottom surface.
Thereby, a wall surface and a 1st curved surface and a 2nd curved surface can be connected more continuously.

[Application Example 6]
In the semiconductor device of this application example, it is preferable that the wall surface has a third curved surface.
Thereby, stress concentration can be further reduced.

[Application Example 7]
In the semiconductor device of this application example, it is preferable that the third curved surface has a curved concave surface located on the first curved surface side and a curved convex surface located on the second curved surface side.
Thereby, a wall surface and a 1st curved surface connect more continuously, and a wall surface and a 2nd curved surface connect more continuously.

[Application Example 8]
In the semiconductor device of this application example, it is preferable to have a substrate including the bottom surface and the wall surface.
Thereby, a bottom face and a wall surface can be formed more easily.

[Application Example 9]
In the semiconductor device of this application example, it is preferable that a circuit that is electrically connected to the functional element is disposed on the substrate.
Thereby, a functional element and a circuit can be provided closer.

[Application Example 10]
In the semiconductor device of this application example, it is preferable that the semiconductor device has a lid portion disposed so as to face the bottom surface.
Thereby, a functional element can be protected.

[Application Example 11]
In the semiconductor device of this application example, it is preferable that the functional element is a vibration element.
Thereby, a semiconductor device can be used as an oscillator, for example.

[Application Example 12]
In the semiconductor device of this application example, the functional element is preferably a pressure sensor element.
Thereby, a semiconductor device can be used as a pressure sensor.

[Application Example 13]
An electronic apparatus according to this application example includes the semiconductor device according to the application example described above.
As a result, a highly reliable electronic device can be obtained.

[Application Example 14]
The moving body of this application example includes the semiconductor device of the above application example.
Thereby, a mobile body with high reliability is obtained.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. It is an expanded sectional view of the recessed part which the semiconductor device shown in FIG. 1 has. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment of this invention. It is a top view which shows the pressure sensor element which the semiconductor device shown in FIG. 13 has. It is a figure which shows the bridge circuit containing the pressure sensor element shown in FIG. 1 is a perspective view illustrating a configuration of a mobile (or notebook) personal computer including a semiconductor device of the present invention. It is a perspective view which shows the structure of a mobile telephone (PHS is also included) provided with the semiconductor device of this invention. It is a perspective view which shows the structure of a digital still camera provided with the semiconductor device of this invention. It is a perspective view which shows a mobile body provided with the semiconductor device of this invention.

  Hereinafter, a semiconductor device, an electronic apparatus, and a moving body of the present invention will be described in detail based on embodiments shown in the accompanying drawings.

<First Embodiment>
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. FIG. 3 is an enlarged cross-sectional view of a recess of the semiconductor device shown in FIG. 4 to 12 are cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. 1 is a cross-sectional view taken along line AA in FIG. In the following description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”.

≪Semiconductor device≫
A semiconductor device 1 shown in FIG. 1 is used as an oscillator that oscillates a signal having a predetermined frequency. As shown in FIG. 1, such a semiconductor device 1 includes a base substrate 2, a vibration element 3 as a functional element, a lid 4, a cavity (accommodating space) 5, and a semiconductor circuit (circuit) 6. ,have.

The base substrate 2 includes a semiconductor substrate (substrate) 21 having a recess 24 opened on the upper surface 211, a first insulating film 22 stacked on the inner surface of the recess 24, and a second stacked on the first insulating film 22. And an insulating film 23. The semiconductor substrate 21 is made of, for example, a silicon substrate, the first insulating film 22 is made of, for example, a silicon oxide film (SiO ₂ film), and the second insulating film 23 is made of, for example, a silicon nitride film (SiN film). It consists of For example, a silicon substrate obtained by epitaxially growing a silicon single crystal on a silicon single crystal substrate may be used. However, the semiconductor substrate 21 is not limited to a silicon substrate, and for example, an SOI substrate can be used. Further, the first insulating film 22 and the second insulating film 23 are not particularly limited as long as the semiconductor substrate 21 can be protected at the time of manufacturing and a short circuit of each part can be prevented.

  In addition, the semiconductor circuit 6 is formed in a portion outside the recess 24 of the semiconductor substrate 21. The semiconductor circuit 6 includes, for example, an oscillation circuit for exciting the vibration element 3. In addition, for example, an output frequency from the phase synchronization circuit (PLL circuit) or the oscillation circuit is multiplied by an integer as necessary. A multiplication circuit (frequency adjustment circuit), an output circuit that converts a signal into a predetermined output format, and a memory. Such a semiconductor circuit 6 includes circuit elements such as a MOS transistor, a capacitor, an inductor, a resistor, a diode, and a wiring as necessary. Thus, by making the semiconductor circuit 6 in the semiconductor device 1, for example, the overall size of the apparatus can be reduced as compared with the case where the semiconductor device 1 and the semiconductor circuit 6 are separate. . In addition, since the semiconductor circuit 6 can be disposed close to the vibration element 3, it is difficult for noise to be applied to the signal output from the vibration element 3, and the semiconductor device 1 with high accuracy can be obtained. In FIG. 1, only the MOS transistor 61 is illustrated as the semiconductor circuit 6 for convenience of explanation.

  As shown in FIGS. 1 and 2, a wall portion 71 and four columnar portions 72 (72 a to 72 d) having a columnar shape are provided in the recess 24.

  As shown in FIGS. 1 and 2, the four column portions 72 are provided inside the wall portion 71 (that is, in the cavity portion 5), and are separated from each other along the periphery of the vibration element 3 in a plan view. Is provided. These four pillar portions 72 support the lid portion 4, and hence bending deformation of the lid portion 4 below (inside the cavity portion 5) is reduced. Therefore, for example, contact between the lid 4 and the vibration element 3 (vibration part electrode 31) can be prevented. The four pillars 72 are used as a part of wiring (electrical path) for drawing out the electrode of the vibration element 3 to the outside. As described above, by using the column portion 72 as a part of the wiring, it is not necessary to separately route the wiring, the device configuration of the semiconductor device 1 is simplified, and the semiconductor device 1 can be downsized. . Such a column part 72 is made of, for example, polysilicon doped (diffused or implanted) with an impurity such as phosphorus or boron. Note that the number of column portions 72 is not limited to four.

  The wall portion 71 has a frame shape and is erected on the bottom surface of the concave portion 24 so as to surround the periphery of the vibration element 3 and the column portion 72 in plan view. The inside of the wall portion 71 is a hollow portion 5. The wall portion 71 includes a protruding portion 711 protruding inward so as to enter between the adjacent column portions 72a and 72b, and a protruding portion 712 protruding inward so as to enter between the adjacent column portions 72b and 72c. A protrusion 713 that protrudes inward so as to enter between the adjacent pillars 72c and 72d, and a protrusion 714 that protrudes inward so as to enter between the adjacent pillars 72d and 72a. . By providing such protrusions 711, 712, 713, and 714, the volume of the cavity 5 can be reduced. Therefore, the etching time for forming the cavity 5 can be shortened, or the evacuation time for vacuum-sealing the cavity 5 can be shortened. These four projecting portions 711 to 714 support the lid portion 4 together with the column portion 72. Therefore, the downward deformation of the lid 4 is further reduced.

Such a wall portion 71 is made of, for example, polysilicon. Further, a reinforcing portion 73 that reinforces the wall portion 71 is provided on the outer peripheral side of the wall portion 71 (that is, between the wall portion 71 and the inner surface of the recess 24). Thereby, the mechanical strength of the semiconductor device 1 can be increased. Such a reinforcing portion 73 is made of, for example, silicon dioxide (SiO ₂ ).

  The lid 4 is provided on the upper surface side of the base substrate 2 and closes the opening of the recess 24. As a result, a hermetically sealed cavity 5 is formed between the base substrate 2 and the lid 4. The cavity 5 is provided with the vibration element 3, whereby the vibration element 3 can be protected and the vibration element 3 can be driven in a predetermined environment.

  As shown in FIG. 1, the lid 4 includes a covering layer 41, a sealing layer 42 stacked on the covering layer 41, and a structure 43 stacked on the sealing layer 42 and the base substrate 2. And have.

  The covering layer 41 includes an insulating layer 411 and a conductive layer 412 stacked on the insulating layer 411. Further, the coating layer 41 has a plurality of communication holes 41 a that communicate between the inside and the outside of the cavity 5. The communication hole 41a is a release hole for removing the sacrificial layer in the cavity 5 by etching during manufacturing. The communication hole 41a is preferably arranged so as not to overlap with the vibration part electrode 31 in a plan view of the base substrate 2. Thereby, when sealing the communication hole 41a with the sealing layer 42, it can reduce that the sealing material which passed through the communication hole 41a adheres to the vibration part electrode 31, and the drive frequency ( (Resonance frequency) can be reduced.

  In addition, the conductive layer 412 has a contact portion 412 a that is provided through the insulating layer 411 and is electrically connected to the column portion 72. Such a contact portion 412 a is used as a part of wiring for connecting the vibration portion electrode 31 to the semiconductor circuit 6, similarly to the column portion 72.

  In such a covering layer 41, the insulating layer 411 is made of, for example, silicon nitride (SiN), and the conductive layer 412 is made of, for example, polysilicon doped (diffused or implanted) with impurities such as phosphorus and boron. It is configured.

  The sealing layer 42 is laminated on the covering layer 41 and closes the communication hole 41a. Thereby, the cavity 5 is hermetically sealed. Thus, by sealing the cavity 5 in an airtight manner, the atmosphere of the vibration element 3 accommodated in the cavity 5 can be stabilized. The cavity 5 is preferably in a vacuum state (depressurized state). Thereby, viscous resistance decreases and the vibration element 3 can be driven more efficiently and stably.

  In addition, the sealing layer 42 includes a contact portion 421 that is arranged on the contact portion 412a independently in an island shape from the periphery and is electrically connected to the contact portion 412a. Such a contact portion 421 is used as a part of wiring for connecting the vibration portion electrode 31 to the semiconductor circuit 6, similarly to the column portion 72 and the contact portion 412 a.

  As such a sealing layer 42, metal materials (conductive material), such as Al, Cu, W, Ti, TiN, can be used, for example.

  The structure 43 includes an interlayer insulating film 431, a wiring layer 432 formed on the interlayer insulating film 431, an interlayer insulating film 433 formed on the wiring layer 432 and the interlayer insulating film 431, and the interlayer insulating film 433. The wiring layer 434 is formed, and the surface protective layer 435 is formed on the wiring layer 434 and the interlayer insulating film 433. Among these, the wiring layers 432 and 434 function as wiring of the semiconductor circuit 6, and the semiconductor circuit 6 is drawn to the upper surface of the semiconductor device 1 by the wiring layers 432 and 434, and a part of the wiring layer 434 is external connection terminal 434. It has become. The surface protective layer 435 protects the semiconductor device 1 from moisture, dust, scratches, and the like.

In such a structure 43, the interlayer insulating films 431 and 433 are made of, for example, silicon dioxide (SiO ₂ ), and the wiring layers 432 and 434 are made of, for example, aluminum (Al). The protective layer 435 is made of, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), polyimide, epoxy resin, or the like.

  The vibration element 3 is a capacitance type (electrostatic drive type) vibration element, and includes a vibration part electrode 31 and a substrate electrode 32 provided on the base substrate 2 as shown in FIG. Yes.

  The vibrating portion electrode 31 is disposed between the fixed portion 311 provided on the bottom surface of the concave portion 24, the vibrating body 312 opposed to the fixed portion 311 with a gap therebetween, and between the vibrating body 312 and the fixed portion 311. And a support portion 313 that supports the body 312 on the fixing portion 311. The vibrating body 312 includes a base portion 312a supported by the support portion 313 and four vibration portions 312b, 312c, 312d, and 312e connected to the base portion 312a, and has a substantially cross shape. . In addition, the number of vibration parts is not limited to four of this embodiment, 1-3 may be sufficient and five or more may be sufficient.

  On the other hand, the substrate electrode 32 includes an electrode 321 provided on the bottom surface of the recess 24 and disposed opposite to the vibrating portion 312b, and an electrode 322 provided on the bottom surface of the recess 24 and disposed opposite to the vibrating portion 312d. Have.

  Each of the vibrating portion electrode 31 and the substrate electrode 32 is made of polysilicon doped (diffused or implanted) with impurities such as phosphorus and boron, for example.

In addition, the vibration part electrode 31 and the substrate electrode 32 are electrically connected to the semiconductor circuit 6 via the column part 72, respectively, and a predetermined frequency is provided between the semiconductor circuit 6 and the vibration part electrode 31 and the substrate electrode 32. When an alternating voltage (a frequency substantially equal to the resonance frequency of the vibration part electrode 31) is applied, the vibration parts 312b and 312d and the vibration parts 312c and 312e are generated by the electrostatic force generated between the vibration body 312 and the substrate electrode 32. And vibrate in reverse phase. Then, a signal (frequency signal) based on this vibration is output from the substrate electrode 32 (or the vibration part electrode 31), and a signal having a predetermined frequency can be output by processing the output signal by the semiconductor circuit 6. .
The configuration of the semiconductor device 1 has been briefly described above.

  Next, the shape of the recess 24 that is one of the main features of the semiconductor device 1 will be described in detail.

  As shown in FIG. 3, the recess 24 disposed in the semiconductor substrate 21 includes a bottom surface 241 where the vibration element 3 is disposed, a wall surface 242 disposed around the bottom surface 241, a bottom surface 241 and a wall surface 242. And a first curved surface 243 connecting them, and a second curved surface 244 arranged between the wall surface 242 and the upper surface 211 and connecting them.

  Thus, since the recessed part 24 has the 1st curved surface 243, since it becomes difficult to form an angle | corner between the bottom face 241 and the wall surface 242, the stress concentration to the said part can be reduced. Therefore, generation of cracks in the semiconductor substrate 21 and generation of crystal defects in the semiconductor substrate 21 can be reduced. Furthermore, since the second curved surface 244 makes it difficult for corners to be formed at the boundary between the recess 24 and the upper surface 211, the generation of cracks in the semiconductor substrate 21 and the generation of crystal defects in the semiconductor substrate 21 are further reduced. Can be reduced. If a crack occurs in the semiconductor substrate 21, the mechanical strength is lowered or the airtightness of the cavity 5 is lowered. In addition, if a crystal defect occurs in the semiconductor substrate 21 and this crystal defect reaches the pn junction of the MOS transistor 61 (the boundary between the p-type region and the n-type region), a leak path is generated. It becomes a factor. That is, by reducing the occurrence of cracks in the semiconductor substrate 21 and the occurrence of crystal defects in the semiconductor substrate 21, the semiconductor device 1 having higher reliability can be obtained.

  In particular, the first curved surface 243 is a curved concave surface. Therefore, the bottom surface 241 and the wall surface 242 are more continuously connected via the first curved surface 243. Thereby, the said effect can be exhibited more notably. In the present embodiment, the entire area of the first curved surface 243 is a curved concave surface, but, for example, a part may be a flat surface.

  Further, the second curved surface 244 is a curved convex surface. Therefore, the wall surface 242 and the upper surface 211 are more continuously connected via the second curved surface 244. Thereby, the said effect can be exhibited more notably. In addition, as will be described in the method for manufacturing the semiconductor device 1 described later, the etching residue on the wall surface 242 can be effectively reduced.

  In this embodiment, the curvature radius (average curvature radius) of the first curved surface 243 is larger than the curvature radius (average curvature radius) of the second curved surface 244. Since the vicinity of the first curved surface 243 is more likely to be the starting point of the cracks and crystal defects than the vicinity of the second curved surface 244, the radii of curvature of the first and second curved surfaces 243, 244 are set as described above. As a result, generation of cracks and crystal defects can be reduced more effectively, and an excessive increase in size of the recess 24 can be prevented. However, the relationship between the curvature radii of the first and second curved surfaces 243 and 244 is not limited to this, and the curvature radius of the first curved surface 243 and the curvature radius of the second curved surface 244 may be substantially equal. The radius of curvature of the first curved surface 243 may be smaller than the radius of curvature of the second curved surface 244.

  The wall surface 242 is inclined so as to face the opening side of the recess 24 (the side opposite to the bottom surface 241). As described above, since the wall surface 242 is inclined, the wall surface 242 and the first curved surface 243 can be connected more continuously, and the stress concentration in the vicinity of the boundary portion can be more effectively reduced. be able to. Similarly, the wall surface 242 and the second curved surface 244 can be connected more continuously, and the stress concentration near these boundary portions can be more effectively reduced. In addition, as will be described in the method for manufacturing the semiconductor device 1 described later, the etching residue on the wall surface 242 can be effectively reduced.

  Further, such a wall surface 242 is configured by a third curved surface 242a, and the third curved surface 242a is positioned on the first curved surface 243 side and is a curved concave surface 242a connected to the first curved surface 243. 'And a curved convex surface 242a "located on the second curved surface 244 side and connected to the second curved surface 244. The wall surface 242 is constituted by such a third curved surface 242a. Thus, the wall surface 242 and the first curved surface 243 can be further continuously connected, and the wall surface 242 and the second curved surface 244 can be further continuously connected. It can be demonstrated remarkably.

≪Semiconductor device manufacturing method≫
Next, while explaining the method for manufacturing the semiconductor device 1, the effect exerted from the shape of the recess 24 described above will be described. For convenience of explanation, the description of the manufacturing process of the circuit elements included in the semiconductor circuit 6 will be omitted below. Each circuit element can be built in the same process as described below, or in the process between the processes described below.

  First, a semiconductor substrate 21 which is a silicon substrate is prepared, and a recess 24 is formed on the upper surface of the semiconductor substrate 21 using a photolithography technique and an etching technique. Specifically, as shown in FIG. 4A, first, a semiconductor substrate 21 is prepared, and a mask M <b> 1 having an opening M <b> 11 smaller than the opening of the recess 24 is formed on the formation region of the recess 24. As the mask M1, various masks such as a resist mask and a metal mask can be used as long as they have etching resistance. Next, as shown in FIG. 4B, impurities such as Ar ions are implanted into the semiconductor substrate 21 through the mask M1. Thereby, Ar ions are implanted into the portion exposed from the opening M11, and the etching rate of the portion changes with respect to the other portion (the portion that overlaps with the mask M1 and is not implanted with Ar ions). Next, when the semiconductor substrate 21 is etched by isotropic dry etching through the mask M1, a recess 24 having a first curved surface 243 and a second curved surface 244 is obtained as shown in FIG. Finally, the mask M1 is removed from the semiconductor substrate 21.

  Note that a gas used for dry etching is not particularly limited as long as the semiconductor substrate 21 can be isotropically etched. For example, a gas obtained by mixing nitric acid with buffered hydrofluoric acid can be used. The method of forming the recess 24 is not limited to the above method. For example, the semiconductor substrate 21 is first etched by anisotropic dry etching through the mask M1, and then isotropic wet etching is performed. Thus, the recess 24 may be formed.

  Next, as illustrated in FIG. 5B, the first insulating film 22 and the second insulating film 23 are sequentially formed on the upper surface side of the semiconductor substrate 21. The first insulating film 22 and the second insulating film 23 are formed by, for example, forming a silicon oxide film on the surface of the semiconductor substrate 21 by a thermal oxidation method, and then forming a silicon nitride film on the silicon oxide film by a sputtering method, a CVD method, or the like. It is obtained by forming using.

  Next, a polysilicon film is formed on the second insulating film 23 by using a sputtering method, a CVD method, or the like, and at the same time, an impurity such as phosphorus or boron is implanted to form a conductive polysilicon film. Then, by patterning this polysilicon film, as shown in FIG. 6A, the substrate electrode 32, the fixing part 311, the wiring (not shown), a part of the column part 72, and a part of the wall part 71. Form. However, the method of forming each part is not limited to the above-described method. For example, after each part is patterned, each part may be doped with an impurity such as phosphorus or boron to impart conductivity.

  Next, as shown in FIG. 6B, a first sacrificial layer 91 made of a silicon oxide film is formed by a CVD method. The first sacrificial layer 91 has a support portion 313, a column portion 72, and a wall portion 71. A corresponding opening is formed. However, the first sacrificial layer 91 may be formed by a thermal oxidation method, a sputtering method or the like instead of the CVD method. The opening is formed using a photolithography technique and an etching technique.

  Next, a polysilicon film is formed on the first sacrificial layer 91 using a sputtering method, a CVD method, or the like, and at the same time, an impurity such as phosphorus or boron is implanted to form a conductive polysilicon film. Then, by patterning this polysilicon film, the support portion 313, the vibrating body 312, the column portion 72, and the wall portion 71 are formed.

  In this step, the shape of the recess 24 is effective. Therefore, this process will be described more specifically. First, as shown in FIG. 7A, the above-described conductive polysilicon film 95 is uniformly formed on the upper surface side of the semiconductor substrate 21, and the polysilicon is formed. On the film 95, a mask M2 corresponding to the shapes of the vibrating body 312, the column portion 72, and the wall portion 71 is formed. Next, the polysilicon film 95 is etched by anisotropic dry etching through the mask M2. Thereby, as shown in FIG.7 (b), the support part 313, the vibrating body 312, the pillar part 72, and the wall part 71 are formed.

  Here, since the wall surface 242 is inclined, as shown in FIG. 8, the thickness T1 of the portion located on the wall surface 242 of the polysilicon film 95 is thicker than the thickness T2 of the other portion (this fact) Is more conspicuous as the slope of the wall surface 242 becomes steeper). Therefore, when the polysilicon film 95 is etched, the polysilicon film 95 on the wall surface 242 may remain as an etching residue without being sufficiently removed. A simple model of this etching residue is shown in FIG. (A) of the figure shows a general etching residue in the configuration of this embodiment, and (b) illustrates a general etching residue in the conventional configuration. As is apparent from a comparison between the two, the second curved surface 244 is provided as in the present embodiment, and further, by making the wall surface 242 the third curved surface 242a, these surfaces become more gentle slopes, Etching residue 950 can be effectively reduced. In particular, by having the second curved surface 244, the etching residue 950 is reduced from protruding upward from the upper surface of the semiconductor substrate 21. Thereby, the work described later (work for removing the first insulating film 22 and the second insulating film 23 on the upper surface 211 of the semiconductor substrate 21 by chemical mechanical polishing (CMP)) can be performed more easily.

  Next, as shown in FIG. 10A, a second sacrificial layer 92 made of a silicon oxide film is formed by CVD, and a predetermined opening is formed in the second sacrificial layer 92. Next, as shown in FIG. 10B, an insulating layer 411 made of a silicon nitride film is formed on the second sacrificial layer 92, and polysilicon is formed on the insulating layer 411 by sputtering, CVD, or the like. At the same time, an impurity such as phosphorus or boron is implanted to form a conductive layer 412 made of a conductive polysilicon film. Then, communication holes 41 a are formed in the insulating layer 411 and the conductive layer 412.

  Next, the first insulating film 22 and the second insulating film 23 stacked on the upper surface 211 of the semiconductor substrate 21 are removed by chemical mechanical polishing (CMP) as shown in FIG. The upper surface 211 of 21 is exposed. Thereby, for example, a circuit element such as the MOS transistor 61 can be formed on the upper surface 211 of the semiconductor substrate 21. As described above, according to the present embodiment, since the etching residue 950 does not protrude from the upper surface of the semiconductor substrate 21 (see FIG. 9A), this process can be performed more smoothly. If the etching residue 950 protrudes from the upper surface of the semiconductor substrate 21 (see FIG. 9B), this protruding portion must be removed in this step, but this portion is the first insulation. Since it is harder than the film 22 and the second insulating film 23, it is difficult to remove the portion, and the time required for this step becomes longer.

  Next, as shown in FIG. 11B, the first and second sacrificial layers 91 and 92 are subjected to release etching. Specifically, the semiconductor substrate 21 is exposed to an etching solution such as buffered hydrofluoric acid. As a result, the first and second sacrificial layers 91 and 92 are release-etched through the communication hole 41a, so that the cavity 5 is formed and the vibration element 3 is released. Next, in a state where the cavity portion 5 is evacuated, as shown in FIG. 12A, a sealing layer 42 made of an aluminum layer is formed on the conductive layer 412, and the communication hole 41a is sealed. The contact portion 421 is formed by patterning the layer 42.

  Next, as shown in FIG. 12B, an interlayer insulating film 431 made of a silicon oxide film is formed on the semiconductor substrate 21, and the interlayer insulating film 431 is planarized by CMP (chemical mechanical polishing) or the like. Next, a wiring layer 432, an interlayer insulating film 433, a wiring layer 434, and a surface protective layer 435 are sequentially formed on the interlayer insulating film 431. Thus, the semiconductor device 1 shown in FIG. 1 is obtained.

Second Embodiment
FIG. 13 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. FIG. 14 is a plan view showing a pressure sensor element included in the semiconductor device shown in FIG. FIG. 15 is a diagram showing a bridge circuit including the pressure sensor element shown in FIG.

  Hereinafter, the semiconductor device according to the second embodiment of the present invention will be described. The description will focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  The semiconductor device of the second embodiment is the same as that of the first embodiment described above except that the configuration of the functional elements is different and the shape of the substrate is different. In addition, the same code | symbol is attached | subjected to the structure similar to embodiment mentioned above.

  As shown in FIG. 13, a diaphragm 215 that is thinner than the surrounding portion and bends and deforms by receiving pressure is provided in a portion overlapping the cavity 5 of the semiconductor substrate 21. The diaphragm 215 is formed by providing a bottomed recess 216 on the lower surface of the semiconductor substrate 21, and the lower surface serves as a pressure receiving surface 215a. When the pressure receiving surface 215a receives pressure, the diaphragm 215 bends according to the magnitude of the received pressure.

  As shown in FIG. 14, the pressure sensor element 8 as a functional element has four piezoresistive elements 81, 82, 83, 84 provided on a diaphragm 215. In addition, the piezoresistive elements 81 to 84 are electrically connected to each other through a wiring or the like, and constitute a bridge circuit 80 (Wheatstone bridge circuit) shown in FIG. 15 and connected to the semiconductor circuit 6. The bridge circuit 80 is connected to a drive circuit (not shown) that supplies a drive voltage AVDC. The bridge circuit 80 outputs a signal (voltage) corresponding to a change in resistance value of the piezoresistive elements 81 to 84 based on the deflection of the diaphragm 215. Based on the output signal, the semiconductor circuit 6 detects the pressure applied to the diaphragm 215.

  Each of the piezoresistive elements 81 to 84 is configured, for example, by doping (diffusing or injecting) an impurity such as phosphorus or boron into the semiconductor substrate 21. Further, the wiring connecting these piezoresistive elements 81 to 84 is constituted, for example, by doping (diffusing or injecting) impurities such as phosphorus and boron into the semiconductor substrate 21 at a higher concentration than the piezoresistive elements 81 to 84. Has been.

  The semiconductor circuit 6 includes, for example, a drive circuit for supplying a voltage to the bridge circuit 80, a temperature compensation circuit for temperature compensation of the output from the bridge circuit 80, and a pressure applied from the output from the temperature compensation circuit. The pressure detection circuit to be obtained, an output circuit for converting the output from the pressure detection circuit into a predetermined output format (CMOS, LV-PECL, LVDS, etc.) and the like are included.

  Also according to the second embodiment, the same effects as those of the first embodiment described above can be exhibited.

[Electronics]
Next, the electronic apparatus of the present invention will be described.

  FIG. 16 is a perspective view illustrating a configuration of a mobile (or notebook) personal computer including the semiconductor device of the present invention.

  In this figure, a personal computer 1100 includes a main body portion 1104 provided with a keyboard 1102 and a display unit 1106 provided with a display portion 1108. The display unit 1106 is rotated with respect to the main body portion 1104 via a hinge structure portion. It is supported movably. Such a personal computer 1100 incorporates, for example, a semiconductor device 1 used as an oscillator or a pressure sensor. Therefore, the personal computer 1100 can exhibit higher performance and higher reliability.

  FIG. 17 is a perspective view showing a configuration of a cellular phone (including PHS) including the semiconductor device of the present invention.

  In this figure, a cellular phone 1200 includes a plurality of operation buttons 1202, a earpiece 1204, and a mouthpiece 1206, and a display portion 1208 is disposed between the operation buttons 1202 and the earpiece 1204. Such a cellular phone 1200 incorporates a semiconductor device 1 used as an oscillator or a pressure sensor, for example. Therefore, the cellular phone 1200 can exhibit higher performance and higher reliability.

  FIG. 18 is a perspective view showing a configuration of a digital still camera including the semiconductor device of the present invention.

  In this figure, connection with an external device is also shown in a simplified manner. The digital still camera 1300 generates an imaging signal (image signal) by photoelectrically converting an optical image of a subject using an imaging element such as a CCD (Charge Coupled Device). A display unit 1310 is provided on the back of a case (body) 1302 in the digital still camera 1300, and is configured to display based on an imaging signal from the CCD. The display unit 1310 displays a subject as an electronic image. Functions as a viewfinder. A light receiving unit 1304 including an optical lens (imaging optical system), a CCD, and the like is provided on the front side (the back side in the drawing) of the case 1302.

  When the photographer confirms the subject image displayed on the display unit 1310 and presses the shutter button 1306, the CCD image pickup signal at that time is transferred and stored in the memory 1308. In the digital still camera 1300, a video signal output terminal 1312 and an input / output terminal 1314 for data communication are provided on the side surface of the case 1302. As shown in the figure, a television monitor 1330 is connected to the video signal output terminal 1312 and a personal computer 1340 is connected to the input / output terminal 1314 for data communication as necessary. Further, the imaging signal stored in the memory 1308 is output to the television monitor 1330 or the personal computer 1340 by a predetermined operation. Such a digital still camera 1300 incorporates, for example, a semiconductor device 1 used as an oscillator or a pressure sensor. Therefore, the digital still camera 1300 can exhibit higher performance and higher reliability.

  Note that an electronic apparatus including the semiconductor device of the present invention includes, for example, an ink jet type ejection device (for example, a personal computer (mobile personal computer) in FIG. 16, a mobile phone in FIG. 17, and a digital still camera in FIG. 18). Inkjet printers), laptop personal computers, televisions, video cameras, video tape recorders, car navigation devices, pagers, electronic notebooks (including those with communication functions), electronic dictionaries, calculators, electronic game devices, word processors, workstations, televisions Telephone, crime prevention TV monitor, electronic binoculars, POS terminal, medical equipment (for example, electronic thermometer, blood pressure monitor, blood glucose meter, electrocardiogram measuring device, ultrasonic diagnostic device, electronic endoscope), fish detector, various measuring devices, instruments Type (e.g., vehicle, Sky machine, gauges of a ship), can be applied to a flight simulator or the like.

[Moving object]
Next, a moving body provided with the semiconductor device of the present invention will be described.
FIG. 19 is a perspective view showing a moving body including the semiconductor device of the present invention.

  A semiconductor device 1 is mounted on an automobile (mobile body) 1500. The semiconductor device 1 is, for example, keyless entry, immobilizer, car navigation system, car air conditioner, anti-lock brake system (ABS), air bag, tire pressure monitoring system (TPMS), engine control, hybrid The present invention can be widely applied to electronic control units (ECUs) such as battery monitors for automobiles and electric vehicles, and vehicle body attitude control systems. Thus, since the automobile 1500 includes the semiconductor device 1, it can exhibit higher performance and higher reliability.

  As described above, the semiconductor device, the electronic apparatus, and the moving body of the present invention have been described based on the illustrated embodiment. It can be replaced with that of the configuration. In addition, any other component may be added to the present invention. Moreover, you may combine each embodiment suitably.

  In each of the embodiments described above, the configuration in which the cavity is formed between the substrate and the lid by forming the recess in the substrate has been described. It is not limited. For example, a cavity may be formed between the substrate and the lid by forming a recess on the lower surface (substrate side) of the lid without providing the recess in the substrate, or between the substrate and the lid. Alternatively, a recess may be formed by the inner peripheral surface of the frame-shaped concept and the upper surface of the substrate with a frame-shaped structure interposed therebetween. That is, the bottom surface and the wall surface of the recess are formed from different members, and these may not be formed integrally.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Base substrate 21 ... Semiconductor substrate 211 ... Upper surface 215 ... Diaphragm 215a ... Pressure-receiving surface 216 ... Recess 22 ... 1st insulating film 23 ... 2nd insulating film 24 ... Recessed 241 …… Bottom surface 242 …… Wall surface 242a …… Third curved surface 242a ′ …… Curved concave surface 242a ”…… Curved convex surface 243 …… First curved surface 244 …… Second curved surface 3 …… Vibrating element 31 …… Vibration Part electrode 311... Fixed part 312... Vibrating body 312 a... Base part 312 b, 312 c, 312 d, 312 e. ... Covering layer 41a ... Communication hole 411 ... Insulating layer 412 ... Conductive layer 412a ... Contact part 42 ... Sealing layer 421 ... Contact part 43 ... Structure 431 ... Layer Insulating film 432 ... Wiring layer 433 ... Interlayer insulating film 434 '... External connection terminal 434 ... Wiring layer 435 ... Surface protective layer 5 ... Cavity 6 ... Semiconductor circuit 61 ... MOS transistor 71 ... Wall Part 711, 712, 713, 714 ... Projection part 72, 72a, 72b, 72c, 72d ... Column part 73 ... Reinforcement part 8 ... Pressure sensor element 80 ... Bridge circuit 81, 82, 83, 84 ... Piezoresistive element 91 …… First sacrificial layer 92 …… Second sacrificial layer 95 …… Polysilicon film 950 …… Remaining etching 1100 …… Personal computer 1102 …… Keyboard 1104 …… Main body 1106 …… Display unit 1108 …… Display unit 1200 …… Cellular phone 1202 …… Operation buttons 1204 …… Earpiece 1206 …… Speaker 1208 …… Display unit 300 …… Digital still camera 1302 …… Case 1304 …… Light receiving unit 1306 …… Shutter button 1308 …… Memory 1310 …… Display unit 1312 …… Video signal output terminal 1314 …… Input / output terminal 1330 …… TV monitor 1340 …… Personal computer 1500 …… Automobile M1 …… Mask M11 …… Opening M2 …… Mask T1, T2 …… Thickness

Claims (13)

A functional element;
A bottom surface on which the functional element is disposed;
A wall surface disposed around the bottom surface;
A first curved surface disposed between the bottom surface and the wall surface and connecting the bottom surface and the wall surface;
A lid portion disposed to face the bottom surface;
A pillar portion that supports the lid portion;
A circuit for driving the functional element ,
The functional device is electrically connected to the circuit through the pillar portion .   The semiconductor device according to claim 1, wherein the first curved surface is a concave surface.   3. The semiconductor device according to claim 1, further comprising a second curved surface that is located on a side opposite to the bottom surface of the wall surface and is connected to the wall surface.   The semiconductor device according to claim 3, wherein the second curved surface is a convex surface.   The semiconductor device according to claim 3, wherein the wall surface is inclined so as to face the side opposite to the bottom surface.   The semiconductor device according to claim 5, wherein the wall surface has a third curved surface.   The semiconductor device according to claim 6, wherein the third curved surface has a curved concave surface located on the first curved surface side and a curved convex surface located on the second curved surface side.   The semiconductor device according to claim 1, further comprising a substrate including the bottom surface and the wall surface. The semiconductor device of claim 8, which is arranged before Kikai path on the substrate. The functional element is a semiconductor device according to any one of claims 1 to 9 which is a vibration element. The functional element is a semiconductor device according to any one of claims 1 to 10 is a pressure sensor element. An electronic apparatus characterized by having a semiconductor device according to any one of claims 1 to 11. Mobile, characterized in that it has a semiconductor device according to any one of claims 1 to 11.

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