JP6439284B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a manufacturing method and a configuration of a semiconductor device having a ferroelectric capacitor.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. In order to realize a nonvolatile random access memory (RAM) capable of high-speed write and read operations at a lower voltage, a technology using a ferroelectric film having spontaneous polarization characteristics as a capacitive insulating film has been developed. ing. Such a storage device is called a ferroelectric memory or “FeRAM”.

  In a ferroelectric memory, a ferroelectric film used for a capacitor is easily reduced in a reducing atmosphere generally used in a semiconductor process, resulting in a problem that the ferroelectricity deteriorates. As shown in FIG. 1, even when the ferroelectric capacitor 1015 including the lower electrode 1014, the ferroelectric film 1013, and the upper electrode 1012 is protected by the hydrogen barrier film 1016, the contact plugs 1033 and 1037 are formed. Then, hydrogen (H) and fluorine (F) generated in the process of forming tungsten (W) enter the ferroelectric capacitor 1015. The invading hydrogen and fluorine cause defects and voids in the crystal of the ferroelectric film 1013. When the upper electrode 1012 is formed of a metal oxide such as iridium oxide (IrO), the upper electrode 1012 is also eroded by hydrogen or fluorine and a damage layer D is generated.

  Various proposals have been made to suppress the reduction of the ferroelectric film 1013. After polishing the interlayer insulating film covering the capacitor to a certain thickness, etch back to the hydrogen barrier film on the upper surface of the capacitor, and then etch a part of the hydrogen barrier film on the upper electrode to form an opening, which is exposed in the opening A method is known in which titanium (Ti), titanium nitride (TiN), aluminum (Al), and TiN are laminated in this order directly on the upper electrode to form a four-layer wiring (for example, Patent Document 1). reference).

  As another method, the side surface of the capacitor is covered with a hydrogen barrier film, and the entire upper surface of the upper electrode is covered with no hydrogen barrier film disposed on the upper surface of the capacitor, and three layers of TiN, aluminum copper (AlCu), and TiN are covered. A method of forming a layer wiring is known (see, for example, Patent Document 2).

JP 2004-335536 A JP 2010-157560 A

  In the conventional configuration of FIG. 1, the interlayer insulating film 1011 is left above the ferroelectric capacitor 1015 with a thickness of about 300 to 500 nm, and the contact hole 1017 reaching the upper electrode 1012 in the interlayer insulating film 1011 and the lower electrode 1014 A reaching contact hole 1018 is formed. When the contact holes 1017 and 1018 are formed, a part of the hydrogen barrier film 1016 is removed to expose a part of the upper electrode 1012 and the lower electrode 1014, and the glue film 1031 is formed on the bottom and side walls of the contact holes 1017 and 1018. 1037 is formed. The glue films 1031 and 1037 cannot completely block hydrogen and fluorine generated when the tungsten films 1032 and 1037 are formed. The glue films 1031 and 1037 formed in the contact holes 1017 and 1018 having a large aspect ratio are not uniform, and the inner walls, particularly the bottom surfaces of the contact holes 1017 and 1018 cannot be completely covered, and hydrogen, fluorine, and the like penetrate through. It is. Further, the tungsten films 1032 and 1036 formed in the contact holes 1017 and 1018 are also non-uniform, and hydrogen and fluorine generated during the film formation enter the upper electrode 1012 of the ferroelectric capacitor 1015. Further, during the etching of the interlayer insulating film 1011, chlorine (Cl) and platinum (Pt) of the lower electrode 1014 remain in the hydrogen barrier film 1016 exposed in the contact holes 1017 and 1018, adsorb moisture and absorb hydrogen. Occurs and degrades the ferroelectricity.

  In the method of Patent Document 1, the number of steps is increased by performing etch back after polishing. In addition, there is a problem that hydrogen or water cannot be completely prevented from entering the ferroelectric film from the interlayer insulating film, and the contact hole to the transistor on the substrate is too deep to be completely buried.

  The method of Patent Document 2 polishes the surface of the upper electrode of the capacitor to reduce the unevenness, but damages the upper electrode itself. In addition, moisture and hydrogen in the interlayer insulating film after the layer in which the capacitor is disposed enter the upper electrode and damage the ferroelectric film.

  Accordingly, it is an object of the present invention to provide a method and a structure for manufacturing a semiconductor device that can prevent the entry of hydrogen, fluorine, or the like generated in a semiconductor process into a ferroelectric capacitor and maintain the ferroelectricity of a memory.

In one aspect, a method for manufacturing a semiconductor device includes:
A capacitor having a lower electrode, a ferroelectric film, and an upper electrode is formed on a semiconductor substrate,
Forming an insulating protective film covering the side surface and the upper surface of the capacitor;
Forming an interlayer insulating film on the insulating protective film;
Polishing the interlayer insulating film to the position of the insulating protective film covering the upper surface of the capacitor,
After the polishing, an opening exposing a part of the upper electrode of the capacitor and a contact hole above the transistor on the lower electrode or the semiconductor substrate are formed,
A first conductor film and a second conductor film electrically connected to the lower electrode or the transistor are sequentially formed in the opening and the contact hole,
Polishing the first conductor film and the second conductor film to the position of the insulating protective film remaining on the upper electrode to fill the opening; and a contact plug filling the contact hole; Form the
Forming wiring on the conductive protective film and on the contact plug;
It is characterized by that.

  It is possible to prevent the intrusion of ferroelectric capacitors such as hydrogen and fluorine generated in the semiconductor process, and maintain the ferroelectricity of the memory.

It is a figure which shows the conventional problem. It is a figure which shows the structure of the ferroelectric capacitor used by embodiment. FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; FIG. 6 is a manufacturing process diagram of the semiconductor device of Example 1; 6 is a schematic diagram of a semiconductor device of Example 2. FIG. 6 is a schematic diagram of a semiconductor device of Example 3. FIG. FIG. 6 is a schematic diagram of a semiconductor device of Example 4. 6 is a schematic diagram of a semiconductor device of Example 5. FIG.

  In the following embodiments, as an example of a semiconductor device, a configuration and a manufacturing method of a ferroelectric memory including a memory holding ferroelectric capacitor and a memory cell transistor on a semiconductor substrate will be described.

  In the process leading to the method and configuration of the embodiment, while maintaining the conventional configuration of FIG. 1, a uniform glue film and a plug conductive film are formed in the contact holes connected to the upper electrode and the lower electrode of the ferroelectric capacitor. An attempt was made to form. For example, an attempt was made to form a thick film on the bottom of the contact hole by forming a glue film and a conductive film for plug while applying a bias. However, in the actually produced contact plug, a uniform film thickness cannot be obtained at the bottom and side walls of the contact hole.

  Therefore, in the embodiment, there is provided a configuration and method for eliminating the contact plug that electrically connects the upper electrode of the ferroelectric capacitor and the upper layer wiring, and preventing the penetration of hydrogen and fluorine into the ferroelectric capacitor. provide.

  Briefly, the entire ferroelectric capacitor is protected with an insulating protective film, and the insulating protective film covering the upper surface of the ferroelectric capacitor is used as a polishing stopper, and the interlayer insulating film is almost the same as the ferroelectric capacitor. Polish to the same height. An opening is formed in the insulating protective film on the upper electrode exposed by polishing to expose a part of the upper electrode, and a contact hole reaching the lower electrode or the lower plug is formed in the interlayer insulating film whose film thickness is reduced. To do. After the opening and contact hole are filled with the conductive protective film and the conductive film for plug, the conductive protective film and the conductive film for plug are polished up to the position of the insulating protective film remaining on the upper electrode to fill the opening. A protective protective film and a contact plug are formed. A wiring is formed directly on the conductive protective film and the contact plug.

  The depth of the opening formed in the insulating protective film on the upper electrode is not more than the diameter of the opening, and the aspect ratio is not more than 1. Further, by polishing the interlayer insulating film to a position corresponding to the height of the ferroelectric capacitor, the size in the thickness direction of the device is reduced, and the aspect ratio of the contact hole formed in the interlayer insulating film is 1 or less. can do. A conductive protective film having a uniform film thickness and film quality is formed in the opening and contact hole with a small aspect ratio, and hydrogen and fluorine generated in the plug formation process can be blocked.

  FIG. 2 is a diagram showing the configuration of the ferroelectric capacitor 15 of the semiconductor device 1 and the vicinity thereof. The ferroelectric capacitor 15 has a lower electrode 14, a ferroelectric film 13, and an upper electrode 12. A side surface of the ferroelectric capacitor 15 and a part of the upper electrode 12 are covered with an insulating protective film 16.

  An outer peripheral portion of the upper electrode 12 is covered with an insulating protective film 16, and a central portion other than the outer periphery is covered with a conductive protective film 19. As will be described later, the conductive protective film 19 is disposed in an opening 17 formed in the insulating protective film 16 on the upper electrode 12. The wiring 25 is directly connected to the conductive protective film 19. The wiring 25 is, for example, a three-layer laminated wiring, and is a lamination of a titanium (Ti) film 21, an aluminum (Al) film 22, and a Ti film 23. Alternatively, as will be described later, a Ti / TiN film 21, an AlCu film 22, and a TiN / Ti film 23 may be laminated.

  Since the wiring 25 is connected through the conductive protective film 19 having a uniform and sufficient thickness that fills the opening 17 of the insulating protective film 16 without installing a contact plug on the upper electrode 12, the ferroelectric capacitor It is possible to prevent hydrogen and fluorine from entering 15 and to make reliable contact with the upper wiring.

  From the viewpoint of comparison with FIG. 1, a planar type ferroelectric capacitor 15 is used in FIG. The lower electrode 14 and the upper layer wiring 25 are electrically connected by a contact plug 37. Compared with the configuration of FIG. 1, the thickness of the interlayer insulating film 11 is small, and the aspect ratio of the contact plug 37 is 1 or less. For the convenience of illustration, the aspect ratio of the contact plug 37 seems to be larger than 1, but actually, the total thickness of the ferroelectric film 13 and the upper electrode 12 is about 180 to 280 nm, and the plug diameter is 300 to 400 nm. The aspect ratio is 1 or less. In the contact hole having an aspect ratio of 1 or less, the glue film 35 and the W film 36 are formed with a uniform film thickness and film quality to prevent hydrogen and fluorine from entering the ferroelectric film 13 from the interlayer insulating film 11. be able to.

  3A to 3L are manufacturing process diagrams of the semiconductor device 100A according to the first embodiment.

  In FIG. 3A, a well 114 is formed in a region partitioned by an element isolation region 112 of an n-type or p-type semiconductor substrate (for example, a silicon substrate) 111. In the active region on the surface of the well 114, a MOS (Metal Oxide Semiconductor) transistor Tr having a gate insulating film 115, a gate electrode 116, a source / drain region 117, and a source / drain extension 118 is formed. A refractory metal silicide layer (not shown) is formed on a necessary portion of the surface of the silicon substrate 111, and a cover insulating film 106 is formed. The cover insulating film 106 is a silicon oxynitride film (SiON) 116 formed to a thickness of about 200 nm by, for example, plasma CVD.

  A silicon oxide film 107 having a thickness of about 1000 nm is formed as a first interlayer insulating film 107 on the cover insulating film 106 by plasma CVD using TEOS gas, and the upper surface of the first interlayer insulating film 107 is chemically mechanically polished ( Polishing and flattening by a CMP method. As a result of CMP, the thickness of the first interlayer insulating film 107 is about 700 nm on the flat surface of the silicon substrate 111.

  The cover insulating film 106 and the first interlayer insulating film 107 are patterned by photolithography to form a first contact hole connected to the source / drain region 117 with a diameter of, for example, 0.25 μm. A TiN / Ti adhesion film (glue film) 108 in which a TiN film with a thickness of 20 nm is stacked on a Ti film with a thickness of 30 nm is formed in the contact hole, and a tungsten (W) film 119 is formed in the hole by a CVD method. To flatten the surface to form contact plugs 120a to 120c. Furthermore, a first anti-oxidation film 121 made of SiON is formed to a thickness of, for example, 130 nm on the entire surface of the planarized substrate by plasma CVD. A second interlayer insulating film 122 having a thickness of, for example, 300 nm is formed on the first antioxidant film 121 by plasma CVD using TEOS as a raw material. The first antioxidant film 121 is not limited to SiON, but may be a silicon nitride (SiN) film or an aluminum oxide (AlO) film.

  In FIG. 3B, a second contact plug 125 is formed through the second interlayer insulating film 122 and the first antioxidant film (SiON, AlO, etc.) 121 to be electrically connected to the first contact plugs 120a and 120b. . Similar to the first contact plugs 120a to 120c, the second contact plug 125 includes a glue film 123 and a plug conductive film 124. When the excess glue film 123 and the plug conductive film 124 on the second interlayer insulating film 122 are polished by CMP, the polishing rate of the glue film 123 and the plug conductive film 124 to be polished is the second speed of the base. A slurry that is faster than the interlayer insulating film 122, for example, SSW2000 manufactured by Cabot Microelectronics Corporation is used. In order not to leave a polishing residue on the second interlayer insulating film 122, the polishing amount of CMP is set to be thicker than the total film thickness of the glue film 122 and the W film 124, and as a result of overpolishing, the contact is not shown. A recess is generated on the surface of the plug 125.

  In FIG. 3C, a glue film 127 for improving crystallinity is formed on the entire surface. As the glue film 127, for example, a TiN film 127 is formed. First, a titanium (Ti) film having a thickness of 10 nm or less is formed by sputtering, and heat treatment is performed at 650 ° C. for 60 seconds in a nitrogen atmosphere by rapid thermal annealing (RTA). The film 127 is used. An oxygen diffusion barrier film 128 is formed on the TiN film 127. As the oxygen diffusion barrier film 128, for example, a titanium aluminum nitride (TiAlN) film 128 having a thickness of 40 nm is formed. The oxygen diffusion barrier film 128 is not limited to TiAlN, and can be polished titanium aluminum oxynitride (TiAlON), tantalum aluminum nitride (TaAlN), tantalum aluminum oxynitride (TaAlON), hafnium aluminum nitride (HfAlN), hafnium aluminum oxynitride (HfAlON) ), Iridium silicon nitride (IrSiN), iridium silicon oxynitride (IrSiON), iridium aluminum nitride (IrAlN), iridium aluminum oxynitride (IrAlON), ruthenium silicon nitride (RuSiN), ruthenium silicon oxynitride (RuSiON), iridium (Ir) ), Ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or hafnium nitride (HfN). There.

An iridium (Ir) film is formed as a lower electrode film 129m on the oxygen diffusion barrier film 128 to a thickness of 30 to 50 nm. The lower electrode film 129m may have a two-layer structure by laminating a conductive noble metal oxide film on the Ir film. On the lower electrode film 129m, a lead zirconate titanate (PZT) film 131m having a thickness of 80 nm is formed as the ferroelectric film 131m. PZT is formed by a sol-gel method, a CSD method, a sputtering method, or an MOCVD method. The ferroelectric film 131m may be a single layer or a laminated film. For example, a laminated ferroelectric film 131m of 70 nm and 10 nm is used. An upper electrode film 132m is formed on the ferroelectric film 131m. For example, an IrO _x film crystallized at the time of film formation as the first upper electrode film is formed by sputtering to a thickness of 25 nm, and by RTA, in an atmosphere of oxygen 20 sccm and argon (Ar) 2000 sccm, 725 ° C., 120 seconds. The heat treatment is performed. This heat treatment completely crystallizes the ferroelectric film 131m, and at the same time, can recover the plasma damage of the IrO _x film, and compensates for oxygen deficiency in PZT. Although not shown, an IrO _Y film may be formed on the upper electrode film 132m as a second upper electrode film having a thickness of 100 nm to 200 nm. In this case, it is desirable that the IrO _Y film has a composition close to the stoichiometric composition of IrO 2 in order to suppress process deterioration. By setting the composition close to the stoichiometric composition of IrO2, it is possible to suppress the catalytic action against hydrogen, prevent the ferroelectric film 131m from being reduced by hydrogen radicals, and improve the hydrogen resistance of the ferroelectric capacitor. . As the material of the upper electrode film 132m, Ir instead of _{IrO 2, Ru, Rh, Re} , Os, Pd, oxides thereof, and may be a conductive oxide or a stacked structure thereof, such as SrRuO3. When an IrO _Y film is formed as the second upper electrode film, an Ir film may be formed on the IrO _Y film by sputtering as a hydrogen barrier film and a conductivity improving film. For example, the film is deposited in an Ar atmosphere at a pressure of 1 Pa and a sputtering power of 1.0 kW to a thickness of 50 nm. In addition, a Ru film or a SrRuO3 film can be used as the hydrogen barrier film.

  In FIG. 3D, a hard mask (not shown) is formed, and the stack from the glue film 127 to the upper electrode film 132m for improving crystallinity is processed into a predetermined shape. For example, using a two-layer hard mask of metal and silicon oxide film, the upper electrode film 132m, the ferroelectric film 131m, and the lower electrode film 129m are processed by plasma etching to form the ferroelectric capacitor 135. The silicon oxide mask is removed by dry etching or wet etching. Subsequently, the portion of the oxygen diffusion barrier film 128 not covered with the ferroelectric capacitor 135, the glue film 127 for improving crystallinity, and the upper metal mask are removed by etch back. For example, the etch back is performed by supplying a mixed gas of 5% CF4 gas and 95% O2 gas as an etching gas into a down flow type plasma etching chamber and supplying a power of 2.45 GHz to the upper electrode of the chamber. Is performed at a substrate temperature of 200 ° C. by supplying high-frequency power of 1400 W.

  An insulating protective film 138 is formed to cover the multilayer structure processed into the capacitor shape and the entire surface of the substrate. In this example, the insulating protective film 138 is a laminate of a first alumina (Al 2 O 3) film 136 and a second Al 2 O 3 film 137. The first Al 2 O 3 film 136 is formed with a thickness of 10 to 20 nm by sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or the like. The insulating protective film 138 is not limited to alumina, but may be a single layer or a laminated film selected from the group consisting of titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon oxide, silicon oxynitride, and silicon nitride. Next, in order to recover the damage of the ferroelectric film 131, recovery annealing is performed in an oxygen-containing atmosphere. The conditions for this recovery annealing are not particularly limited, but in the embodiment, the recovery annealing is performed at a substrate temperature of 550 ° C. to 700 ° C. in the furnace. When the ferroelectric film 131 is PZT, it is desirable to perform annealing for 60 minutes in an atmosphere of 610 ° C. oxygen.

  In FIG. 3E, a third interlayer insulating film 139 having a thickness of, for example, 1300 nm is formed on the entire surface by, eg, plasma TEOSCVD. When the silicon oxide film 139 is formed as the third interlayer insulating film 139, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas. An inorganic insulating film may be formed instead of the TEOS film.

  In FIG. 3F, the surface of the third interlayer insulating film 139 is planarized by, eg, CMP. In this CMP process, the insulating protective film 138 (or the second Al 2 O 3 film 137) is used as a CMP stopper film. By the planarization, the insulating protective film 138 covering the surface of the upper electrode 132 of the ferroelectric capacitor 135 is exposed, and the thickness of the third interlayer insulating film 139 is such that the thickness of the ferroelectric capacitor 135 with respect to the second interlayer insulating film 122 is increased. It becomes almost the same as the height. This configuration is different from the conventional configuration of FIG.

  In FIG. 3G, the insulating protective film 138 (including the first Al 2 O 3 film 136 and the second Al 2 O 3 film 137) is patterned by photolithography and etching, and a first opening is formed in the insulating protective film 138 on the upper electrode 132. 141 is formed. An end portion of the upper electrode 132 is covered with an insulating protective film 138. A region excluding the end portion of the upper electrode 132 is exposed in the opening 141.

  In FIG. 3H, recovery annealing is performed at a substrate temperature of about 400 to 500 ° C. (eg, 450 ° C.) in an oxygen-containing atmosphere in order to recover the damage received by the ferroelectric film 131 in the previous step.

  In FIG. 3I, a contact hole 143 connected to the contact plug 120b is formed in the third interlayer insulating film 139 and the second interlayer insulating film 122.

  In FIG. 3J, the natural oxide film on the surface of the upper electrode 132 exposed in the opening 141 and the surface of the tungsten film 119 exposed in the contact hole 143 is removed by RF etching using argon plasma. Next, a conductive protective film 144 is formed on the entire surface of the substrate including the opening 141 and the contact hole 143. As the conductive protective film 144, for example, a TiN film 144 is formed with a thickness of about 100 nm by sputtering. The depth of the opening 141 corresponds to the thickness of the insulating protective film 138, and the conductive protective film 144 is formed in the shallow opening 141 with a uniform film thickness and film quality. The conductive protection film 144 filling the opening 141 covers the upper electrode 132 and prevents entry of hydrogen, fluorine, or the like into the ferroelectric capacitor 135. As a result, it is possible to prevent defects and voids from being formed in the ferroelectric capacitor 135 by elements such as hydrogen and fluorine. The contact hole 143 connected to the lower contact plug 120b has a relatively high aspect ratio exceeding 1, so that the conductive protective film 144 is formed by a sputtering method using SIP (Self-Ionized Plasma) technology. In addition, it is desirable to use a sputtering method capable of forming a film with good coverage. The conductive protective film 144 is not limited to TiN, but tantalum nitride (TaN), hafnium nitride (HfN), chromium nitride (CrN), zirconium nitride (ZrN), titanium aluminum nitride (TiAlN), titanium aluminum oxynitride (TiAlON) Tantalum aluminum nitride (TaAlN), tantalum aluminum oxynitride (TaAlON), hafnium aluminum nitride (HfAlN), hafnium aluminum oxynitride (HfAlON), chromium aluminum nitride (CrAlN), chromium aluminum oxynitride (CrAlON), zirconium aluminum nitride ( ZrAlN), zirconium aluminum oxynitride (ZeAlON), iridium silicon nitride (IrSiN), iridium silicon oxynitride (IrSiON), iridium aluminum nitride (IrAlN), iridium aluminum oxynitride (IrAlON), ruthenium silicon nitride (RuSiN), oxynitride Ruthenium silicon (RuSiON), titanium (Ti), tantalum (Ta), iri It may be a single layer or a laminated film selected from the group consisting of palladium (Ir) and ruthenium (Ru). The conductive protective film 144 may be formed using any one of a plating method, an organic metal decomposition method, a CSD (Chemical Solution Deposition) method, a chemical vapor deposition method, an epitaxial growth method, and an MOCVD method in addition to the sputtering method. Good.

  In FIG. 3K, a tungsten (W) film 145 having a thickness of about 300 nm is formed as a plug conductive film on the conductive protective film 144 by sputtering, and the contact hole 143 is buried. In the CVD method, for example, a mixed gas of tungsten hexafluoride gas and hydrogen gas is used. In FIG. 3J of the previous step, a uniform conductive protective film 144 without a cavity is formed in the shallow opening 141 on the upper electrode 132. Further, since the insulating protective film 138 exposed at the side wall of the contact hole 143 is also covered with the uniform conductive protective film 144, the ferroelectric capacitor 135 is made of hydrogen or fluorine generated when the tungsten film 145 is formed. Can be protected. The plug conductive film 145 is not limited to the tungsten film 145, and may be a copper film or a polysilicon film. As for the copper film, when the film is formed by the CVD method in which hydrogen is included in the film formation atmosphere, the practical benefit of the hydrogen barrier by the conductive protective film 144 on the upper electrode 132 is great. Further, since the polysilicon film formation atmosphere also contains hydrogen, the ferroelectric capacitor 135 can be protected from hydrogen by forming the conductive protective film 144 having a high hydrogen barrier property. By polishing the excess conductive film protective film 144 and the plug conductive film 145 on the substrate by CMP, the upper electrode 132 is placed in the contact plug 146 and the shallow opening 141 on the upper electrode 132 as shown in FIG. A conductive protective film 144 having the same thickness as that of the upper insulating protective film 138 is obtained.

  In FIG. 3L, the natural oxide film on the upper surface of the contact plug 146 is removed by etching using argon plasma, and a wiring pattern 151 is formed corresponding to the contact plug 146 and the conductive protection film 144. For example, by sputtering, a Ti film having a thickness of 60 nm and a TiN film having a thickness of 30 nm are laminated 147, an AlCu alloy film 148 having a thickness of 360 nm, a TiN film having a thickness of 70 nm, and a Ti film having a thickness of 5 nm. Stacks 149 are formed sequentially. By patterning the laminated film using a photolithography technique, a three-layer wiring pattern 151 of a TiN / Ti film 147, an AlCu alloy film 148, and a Ti / TiN film 149 is formed. The wiring pattern 151 is a first metal wiring layer. Thereafter, although not shown, an interlayer insulating film, a contact plug, and a second metal wiring are formed, and a cover film made of, for example, a TEOS oxide film and a SiN film is formed to form a ferroelectric capacitor 135. The ferroelectric memory 100A having the above is completed.

  As described above, the side surface of the ferroelectric capacitor 135 and a part (end portion) of the upper electrode 132 are covered with the insulating protective film 138, and the upper electrode 132 is exposed in the shallow opening 141 of the insulating protective film 138. A uniform conductive protective film is formed to protect the ferroelectric capacitor 135. Thereby, it is possible to prevent hydrogen and fluorine from entering the upper electrode 132 and the ferroelectric film 131 of the ferroelectric capacitor 135 when forming a contact plug such as tungsten or copper. In addition, since moisture and hydrogen from the wiring 151 are also barriered by the conductive protective film 144 and the insulating protective film 138, a decrease in ferroelectricity of the ferroelectric capacitor 135 can be suppressed. With this configuration and method, device yield is improved.

  FIG. 4 is a schematic cross-sectional view of the ferroelectric memory 100B according to the second embodiment. In the second embodiment, parts different from the first embodiment will be described.

  In Example 2, the third interlayer insulating film 139 is polished to the height of the ferroelectric capacitor 135 by CMP using the insulating protective film 138 as a stopper, and then a flat second insulating protective film 153 is formed. The second insulating protective film 153 has a thickness of 20 to 50 nm, for example, and is formed by sputtering, MOCVD, ALD, or the like. The second insulating protective film 153 uses one or more materials selected from the group consisting of aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon oxide, silicon oxynitride, and silicon nitride. It is a single layer or laminated film.

  Thereafter, the contact hole 143 is opened by the same method as FIG. 3I of the first embodiment, and the conductive protective film 144, the plug conductive film 145, and the upper metal wiring 151 are formed. Recovery annealing may be performed before the contact hole 143 is formed.

  In Example 2, when the third interlayer insulating film 139 is subjected to CMP polishing using the insulating protective film 138 as a stopper, the second insulating protective film 153 is formed even after over-polishing to some extent. Hydrogen and water generated in the formation of the contact plug 146 and the subsequent wiring formation process do not enter the capacitor. From Example 1, the ferroelectricity of the capacitor can be effectively maintained.

  FIG. 5 is a schematic cross-sectional view of the ferroelectric memory 100C according to the third embodiment. A difference between the third embodiment and the first embodiment will be described.

  In Example 3, after forming contact plugs 120a and 120c connected to one of the source or drain of the transistor Tr in the first interlayer insulating film 107 covering the transistor Tr, the antioxidant film 121 and the second interlayer insulating film 122 are formed. The capacitor stack is formed as it is. That is, a glue film 127 for improving crystallinity, an oxygen diffusion barrier film 128, a lower electrode film 129m, a ferroelectric film 131m, and an upper electrode film 132m are sequentially stacked on the first interlayer insulating film 107 (FIG. 3C) The ferroelectric capacitor 135 is formed by processing into a predetermined shape. After forming an insulating protective film 138 on the entire surface of the ferroelectric capacitor and the wafer, a third interlayer insulating film 139 is formed to cover the entire surface, and the third interlayer insulating film is formed using the insulating protective film 138 located on the upper electrode 132 as a stopper. The film 139 is planarized. Thereafter, an opening 141 is formed in the insulating protective film 138 located on the upper electrode 132, and recovery annealing is performed.

  In the third embodiment, since the second interlayer insulating film is excluded, after the recovery annealing, the third interlayer insulating film 139 and the first interlayer insulating film 107 are penetrated and connected to the other of the source or the drain of the transistor Tr. A contact hole is formed. A conductive protection film 144 is formed on the upper electrode 132 in the opening 141 and on the inner wall of the contact hole, and the contact hole is filled with the conductive film 154 to form a contact plug 156. The subsequent process is the same as in Example 1.

  In the third embodiment, the contact plug 156 connected to the other of the source and the drain of the transistor Tr can be formed by a single process. The effect of preventing hydrogen and fluorine from entering the ferroelectric capacitor 135 is the same as in the first and second embodiments.

  FIG. 6 is a schematic sectional view of a ferroelectric memory 100D according to the fourth embodiment. In the fourth embodiment, the configuration in which the opening 141 formed in the insulating protective film 138 is filled with the conductive protective film 144 to protect the upper electrode 132 is applied to a planar capacitor. Similarly to the third embodiment, the second interlayer insulating film 122 is omitted, and the glue film 127 for improving the crystallinity, the oxygen diffusion barrier film 128, the lower electrode film 169, and the ferroelectric film are directly formed on the CMOS bulk. 171 and the upper electrode film 172 are sequentially formed to form a capacitor stack.

  After the capacitor stack is processed into the shape of a planar ferroelectric capacitor 175, an insulating protective film 138 that covers the ferroelectric capacitor 175 and the entire wafer surface is formed. A third interlayer insulating film 139 is formed on the entire surface, and the third interlayer insulating film 139 is polished and planarized using the insulating protective film 138 positioned on the upper electrode 172 as a stopper. Thereafter, an opening 141 of the insulating protective film 138 located on the upper electrode 132 and a contact hole for connecting the lower electrode 169 are formed, and recovery annealing is performed. Further, a transistor connection contact hole for the plug 125 connected to the lower contact plug 120 is formed, and the conductive protective film 144 filling the opening 141 and the contact for connecting the lower electrode 169 are formed in the same manner as in the first embodiment. A glue film 161 on the inner wall of the hole and a glue film 123 on the inner wall of the contact hole for transistor connection are formed. Subsequently, plug conductive films 124 and 162 for filling the contact holes are formed, and the whole is planarized. Thereby, the conductive protective film 144 and the contact plugs 163 and 125 covering the upper electrode 172 are formed. Thereafter, the wiring 151 is formed as in the first embodiment.

  The contact plug 163 for connecting the lower electrode is formed on the third interlayer insulating film 139 having a thickness aligned with the height of the ferroelectric capacitor 173 and its aspect ratio is smaller than 1. The aspect ratio of the contact plug 125 for connecting transistors is about 1. Therefore, it is possible to form the conductive protective film 144 and the glue films 123 and 161 having a uniform film thickness and quality, and strong from the reducing atmosphere when the plug conductive films 124 and 161 such as tungsten and copper are formed. The dielectric capacitor 175 can be protected.

  FIG. 7 is a schematic sectional view of a ferroelectric memory 100E according to the fifth embodiment. In the fifth embodiment, a planar ferroelectric capacitor 175 is used as in the fourth embodiment, and a flat covering the insulating protective film 138 and the third interlayer insulating film 139 on the upper electrode 172 is performed as in the second embodiment. A second insulating protective film 153 is formed. This configuration can also maintain the ferroelectricity by preventing the entry of hydrogen and fluorine into the ferroelectric capacitor 175 as in the case of Example 1-4.

  Through Examples 1 to 5, two or more laminated films may be formed as the conductive protective film 144 that protects the upper electrodes 132 and 172 in the opening 141. As the lower electrodes 129 and 169, a single layer or a stacked film of a material selected from the group consisting of Ir, Ru, Pt, Pd, Os, Rh, IrOx, RuOx, PtOx, PdOx, OsOx, RhOx, and SrRuO3 may be used. it can.

Ferroelectrics 131 and 171 may be formed by sputtering, MOCVD, sol-gel, organometallic decomposition (MOD), CSD (Chemical Solution Deposition), or chemical vapor deposition (CVD). In addition, an epitaxial growth method or the like can be used. As the ferroelectrics 131 and 171, for example, a film whose crystal structure becomes a Bi layer structure or a perovskite structure can be formed by heat treatment. Examples of such a film include a film represented by the general formula ABO ₃ such as PZT, SBT, BLT, and Bi-based layered compound doped with a small amount of La, Ca, Sr, and / or Si, in addition to the PZT film. .

  When the upper electrodes 132 and 172 are formed, for example, sputtering using a target containing a noble metal element such as platinum, iridium, ruthenium, rhodium, rhenium, osmium and / or palladium causes oxidation of these noble metal elements. Under the conditions.

  In any case, the opening 141 formed in the insulating protective film that protects part of the side surfaces and the upper surface of the ferroelectric capacitors 135 and 175 is very shallow, and the conductive protective film 144 has a uniform film thickness and quality. The upper electrodes 132 and 172 can be protected. Also, in the case of forming a planar type ferroelectric capacitor, the aspect ratio of the contact plug connected to the lower electrode 169 is smaller than 1, and hydrogen or fluorine is removed from the contact plug 163 in the film forming process in a reducing atmosphere. Intrusion into the ferroelectric capacitor 175 from the interlayer insulating film 139 can be prevented.

  In the manufacturing process, the interlayer insulating film 139 is polished by using the insulating protective film 138 on the upper electrodes 132 and 172 of the ferroelectric capacitors 135 and 175 as a stopper, and the wiring 151 is formed thereon. The size of the device in the vertical direction (direction perpendicular to the substrate surface) can be reduced. At the same time, moisture, hydrogen, fluorine and the like are prevented from entering the ferroelectric films 131 and 171 from the interlayer insulating film 139, and damage to the upper electrodes 132 and 172 is also suppressed. The switching characteristics of the ferroelectric capacitors 135 and 175 are maintained well, and the device yield is improved.

The following notes are presented for the following explanation.
(Appendix 1)
A capacitor having a lower electrode, a ferroelectric film, and an upper electrode is formed on a semiconductor substrate,
Forming an insulating protective film covering the side surface and the upper surface of the capacitor;
Forming an interlayer insulating film on the insulating protective film;
Polishing the interlayer insulating film to the position of the insulating protective film covering the upper surface of the capacitor,
After the polishing, an opening exposing a part of the upper electrode of the capacitor and a contact hole above the transistor on the lower electrode or the semiconductor substrate,
A first conductor film and a second conductor film electrically connected to the lower electrode or the transistor are sequentially formed in the opening and the contact hole,
Polishing the first conductor film and the second conductor film to the position of the insulating protective film remaining on the upper electrode to fill the opening; and a contact plug filling the contact hole; Form the
Forming wiring on the conductive protective film and on the contact plug;
A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device.
(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein an aspect ratio of the opening and the contact hole is 1 or less.
(Appendix 3)
2. The semiconductor according to claim 1, wherein the conductive protective film having the same thickness as the insulating protective film is formed in the opening by the polishing of the first conductive film and the second conductive film. Device manufacturing method.
(Appendix 4)
The opening is completely filled with the first conductor film, and the conductive protective film is formed of the first conductor film by the polishing of the first conductor film and the second conductor film. A manufacturing method of a semiconductor device according to attachment 3.
(Appendix 5)
2. The method of manufacturing a semiconductor device according to claim 1, wherein after the opening is formed in the insulating protective film, the ferroelectric capacitor is heat-treated in an oxygen-containing atmosphere.
(Appendix 6)
After the polishing of the interlayer insulating film, a flat second insulating protective film is formed on the insulating protective film and on the interlayer insulating film in a portion covering the upper surface of the ferroelectric capacitor. A method for manufacturing a semiconductor device according to any one of appendices 1 to 5.
(Appendix 7)
The insulating protective film is a single layer or a laminated film selected from the group consisting of alumina, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon oxide, silicon oxynitride, and silicon nitride. A manufacturing method of a semiconductor device according to any one of appendices 1 to 6,
(Appendix 8)
The conductive protective film includes titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), chromium nitride (CrN), zirconium nitride (ZrN), titanium aluminum nitride (TiAlN), and titanium aluminum oxynitride (TiAlON). ), Tantalum aluminum nitride (TaAlN), tantalum aluminum oxynitride (TaAlON), hafnium aluminum nitride (HfAlN), hafnium aluminum oxynitride (HfAlON), chromium aluminum nitride (CrAlN), chromium aluminum oxynitride (CrAlON), zirconium aluminum nitride (ZrAlN), zirconium aluminum oxynitride (ZeAlON), iridium silicon nitride (IrSiN), iridium silicon oxynitride (IrSiON), iridium aluminum nitride (IrAlN), iridium aluminum oxynitride (IrAlON), ruthenium silicon nitride (RuSiN), acid Ruthenium silicon nitride (RuSiON), titanium (Ti), tantalum (Ta), iridium Beam (Ir), the method of manufacturing a semiconductor device according to any one of appendixes 1 to 7, characterized by forming a single layer or a laminated film selected from the group consisting of ruthenium (Ru).
(Appendix 9)
The lower electrode includes iridium (Ir), ruthenium (Ru), platinum (Pt), palladium (Pd), osmium (Os), rhodium (Rh), iridium oxide (IrOx), ruthenium oxide (RuOx), platinum oxide ( PtOx), palladium oxide (PdOx), osmium oxide (OsOx), rhodium oxide (RhOx) film, and a single layer or laminated film selected from the group consisting of strontium ruthenate (SrRuO3) A method for manufacturing a semiconductor device according to any one of appendices 1 to 8.
(Appendix 10)
10. The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the ferroelectric film is a compound film having a perovskite structure or a compound film having a bismuth layer structure.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, wherein the upper electrode is formed of a conductive film containing a noble metal oxide.
(Appendix 12)
The noble metal oxide is an oxide of one element selected from the group consisting of iridium (Ir), ruthenium (Ru), platinum (Pt), osmium (Os), rhodium (Rh), and palladium (Pd). The method for manufacturing a semiconductor device according to appendix 11, wherein:
(Appendix 13)
A semiconductor substrate;
A capacitor formed on the semiconductor substrate and having a lower electrode, a ferroelectric film, and an upper electrode;
An insulating protective film covering a part of the upper surface of the upper electrode and a side surface of the capacitor;
A conductive protective film covering a region of the upper electrode that is not covered by the insulating protective film, the conductive protective film having a surface position aligned with the insulating protective film;
Wiring connected to the conductive protective film;
A semiconductor device comprising:
(Appendix 14)
An interlayer insulating film that fills the capacitor up to the position of the insulating protective film located on the upper surface of the capacitor;
A contact plug formed on the interlayer insulating film and connected to the lower electrode of the capacitor or a plug electrode directly below the interlayer insulating film;
14. The semiconductor device according to appendix 13, wherein the contact plug has an aspect ratio of 1 or less.
(Appendix 15)
14. The semiconductor device according to appendix 13, wherein a bottom surface of the conductive protective film is in contact with the upper electrode, and an upper surface of the conductive protective film is in contact with the wiring.
(Appendix 16)
The wiring layer is a wiring in which a first metal film in contact with the conductive protective film, a second metal film on the first metal film, and a third metal film on the second metal film are laminated. 14. The semiconductor device according to appendix 13, characterized by:

1,100A-100E Ferroelectric memory (semiconductor device)
12, 132, 172 Upper electrode 13, 131, 171 Ferroelectric film 14, 129, 169 Lower electrode 15, 135, 175 Ferroelectric capacitor 138 Insulating protective film 141 Opening 144 Conductive protective film 151 Wiring

Claims (5)

A capacitor having a lower electrode, a ferroelectric film, and an upper electrode is formed on a semiconductor substrate,
Forming an insulating protective film covering the side surface and the upper surface of the capacitor;
Forming an interlayer insulating film on the insulating protective film;
Polishing the interlayer insulating film to the position of the insulating protective film covering the upper surface of the capacitor,
After the polishing, an opening exposing a part of the upper electrode of the capacitor and a contact hole above the transistor on the lower electrode or the semiconductor substrate,
A first conductor film and a second conductor film electrically connected to the lower electrode or the transistor are sequentially formed in the opening and the contact hole,
Polishing the first conductor film and the second conductor film to the position of the insulating protective film remaining on the upper electrode to fill the opening; and a contact plug filling the contact hole; Form the
Forming wiring on the conductive protective film and on the contact plug;
A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 1, wherein an aspect ratio of the opening and the contact hole is set to 1 or less.   2. The conductive protective film according to claim 1, wherein the conductive protective film having the same thickness as the insulating protective film is formed in the opening by the polishing of the first conductive film and the second conductive film. A method for manufacturing a semiconductor device.   The opening is completely filled with the first conductor film, and the conductive protective film is formed of the first conductor film by the polishing of the first conductor film and the second conductor film. A method of manufacturing a semiconductor device according to claim 3.   2. The method of manufacturing a semiconductor device according to claim 1, wherein after the opening is formed in the insulating protective film, the ferroelectric capacitor is subjected to a heat treatment in an oxygen-containing atmosphere.

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