JP2010212574A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device suitable for miniaturization, while deterioration in characteristics and a damage to an upper electrode due to hydrogen in a ferroelectric capacitor, are suppressed. <P>SOLUTION: The semiconductor memory device is provided with a first plug PLG1, a second plug PLG2, a ferroelectric capacitor FC, a hydrogen barrier film HB, a second interlayer film ILD 3, a local wiring LIC, and a through plug PPLG. The first plug PLG1 penetrates through a first interlayer film ILD 1 to be connected to one of a source and drain of a transistor. The second plug PLG2 penetrates through the first interlayer film to be connected to the other one of the source and the drain of the transistor. The ferroelectric capacitor FC contains a lower electrode LE arranged above the first plug and electrically connected to the first plug, a ferroelectric film FE, and an upper electrode UE. The hydrogen barrier film HB covers the ferroelectric capacitor. The second interlayer film ILD 3 is arranged on the hydrogen barrier film. The local wiring LIC is arranged on the second interlayer film and the hydrogen barrier film, and penetrates through the hydrogen barrier film to be connected to an upper electrode. The penetration plug PPLG penetrates through the local wiring, the second interlayer film, and the hydrogen barrier film so as to be connected to the second plug. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof.

  In recent years, a ferroelectric memory (FeRAM (ferro-electric random access memory)) including a ferroelectric capacitor has attracted attention as one of nonvolatile semiconductor memories. In general, a ferroelectric memory employs a so-called COP (capacitor on plug) structure for miniaturization. The COP structure is a structure in which the lower electrode of the ferroelectric capacitor is connected to the source or drain of the cell transistor by a conductive contact plug provided under the ferroelectric capacitor.

  Further, both ends of the capacitor (C) are connected between the source and drain of the cell transistor (T), and this is used as a unit cell, and a plurality of unit cells are connected in series, “TC parallel unit serial connection type ferroelectric memory ( Hereinafter, it is also referred to as a chain-type FeRAM) ”. The chain type FeRAM is suitable for increasing the signal amount and operating at high speed. In the chain type FeRAM, it is necessary to connect the upper electrodes of two adjacent ferroelectric capacitors and the source or drain of the cell transistor. Therefore, an electrode plug electrically connected to the source or drain of the cell transistor must be formed between the two ferroelectric capacitors between the two ferroelectric capacitors. Usually, the electrode plug is made of tungsten. MO-CVD (Metal Organic-Chemical Vapor Deposition) used to deposit tungsten generates hydrogen. Hydrogen deteriorates the polarization characteristics of the ferroelectric capacitor by its reducing action. In order to prevent this, the ferroelectric capacitor is covered with a hydrogen barrier film.

  Here, when polishing the tungsten embedded in the electrode plug, the interlayer film on the upper electrode is also shaved off at the same time. Therefore, the interlayer film covering the upper electrode needs to be formed thick beforehand. Since the interlayer film is thick, a plug is formed in the interlayer film on the upper electrode in order to connect the upper electrode to the local wiring. The plug on the upper electrode is made of tungsten or aluminum.

  However, in order to form the plug on the upper electrode by aluminum reflow, a dedicated device is required. For this reason, a manufacturing cost will rise. On the other hand, when the plug on the upper electrode is formed of tungsten, an apparatus used in another metallization process can be used. However, as described above, since a large amount of hydrogen is generated, there is a problem that the ferroelectric capacitor may be deteriorated.

  Furthermore, if the interlayer film on the upper electrode is thick, it is necessary to perform overetching for a long time when forming a via hole on the upper electrode. Prolonged overetching increases damage to the upper electrode and causes deterioration of the characteristics of the ferroelectric capacitor.

JP 2007-95898 A

  Provided is a semiconductor memory device suitable for miniaturization while suppressing deterioration of characteristics of a ferroelectric capacitor due to hydrogen and damage to an upper electrode.

  A semiconductor memory device according to an embodiment of the present invention includes a semiconductor substrate, a plurality of transistors provided on the semiconductor substrate, a first interlayer film covering the transistors, and the first interlayer film. A first plug passing through and connected to one of a source or a drain of the transistor; a second plug passing through the first interlayer film and connected to the other of the source or the drain of the transistor; A lower electrode provided above the first plug and electrically connected to the first plug, a ferroelectric film provided on the lower electrode, and an upper part provided on the ferroelectric film A ferroelectric capacitor including an electrode, a hydrogen barrier film covering the ferroelectric capacitor, a second interlayer film provided on the hydrogen barrier film, the second interlayer film, and the hydrogen barrier film A local wiring connected to the upper electrode through the hydrogen barrier film, and connected to the second plug through the local wiring, the second interlayer film, and the hydrogen barrier film. And a through-plug.

A method for manufacturing a semiconductor memory device according to an embodiment of the present invention includes:
Forming a plurality of transistors on a semiconductor substrate;
Forming a first interlayer film so as to cover the transistor;
A first plug passing through the first interlayer film and connected to one of the source and drain of the transistor and a first plug passing through the first interlayer film and connected to the other of the source and drain of the transistor 2 plugs and
Forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode above the first plug;
Forming a hydrogen barrier film so as to cover the ferroelectric capacitor;
Forming a second interlayer film on the hydrogen barrier film;
Forming a first via hole that penetrates the hydrogen barrier film and reaches the upper electrode;
Forming a local wiring on the upper electrode in the first via hole and on the second interlayer film;
Removing the local wiring on the second plug to provide a through hole in the local wiring;
Etching the second interlayer film and the hydrogen barrier film using the local wiring as a mask to form a second via hole,
Forming a through plug in the second via hole;

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes forming a plurality of transistors on a semiconductor substrate,
Forming a first interlayer film so as to cover the transistor;
A first plug passing through the first interlayer film and connected to one of the source and drain of the transistor and a first plug passing through the first interlayer film and connected to the other of the source and drain of the transistor 2 plugs and
Depositing a lower electrode material, a ferroelectric film material and an upper electrode material above the first plug;
Forming a hard mask in a region inside a plane pattern of a ferroelectric capacitor including the lower electrode, the ferroelectric film and the upper electrode;
Etching the upper part of the material of the upper electrode using the hard mask as a mask,
Forming a sidewall film on the upper side of the upper electrode material;
The ferroelectric including the inverted T-shaped upper electrode by etching the lower electrode material, the ferroelectric film material and the lower electrode material using the hard mask and the sidewall film as a mask. Forming a capacitor,
Forming a hydrogen barrier film so as to cover the ferroelectric capacitor;
Forming a second interlayer film on the hydrogen barrier film;
Polishing the second interlayer film to expose the upper surface of the upper electrode;
Forming a local wiring on the upper electrode and the second interlayer film;
Removing the local wiring on the second plug to provide a through hole in the local wiring;
Etching the second interlayer film and the hydrogen barrier film using the local wiring as a mask to form a second via hole reaching the second plug;
Forming a through plug in the second via hole;

  The semiconductor memory device according to the present invention is suitable for miniaturization while suppressing characteristic deterioration due to hydrogen of the ferroelectric capacitor and damage to the upper electrode.

1 is a circuit diagram showing a configuration of a ferroelectric memory according to a first embodiment of the present invention. FIG. 3 is a layout diagram illustrating a partial planar configuration of the first embodiment. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 2. Sectional drawing along line 4-4 in FIG. Sectional drawing which shows the manufacturing method of the ferroelectric memory by 1st Embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the ferroelectric memory following FIG. 5. FIG. 7 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 6. FIG. 8 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 7. FIG. 9 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 8. FIG. 10 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 9. FIG. 11 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 10. FIG. 12 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 11. FIG. 13 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 12. FIG. 14 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 13. FIG. 15 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 14. The top view which shows the structure of the ferroelectric memory according to 2nd Embodiment concerning this invention. Sectional drawing which shows the structure of the ferroelectric memory according to 3rd Embodiment concerning this invention. Sectional drawing which shows the manufacturing method of the ferroelectric memory by 3rd Embodiment. FIG. 19 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 18. FIG. 20 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 19. FIG. 21 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 20. FIG. 22 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 21. FIG. 23 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 22. FIG. 24 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 23. FIG. 25 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 24. FIG. 26 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 25. FIG. 27 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 26. FIG. 28 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 27. FIG. 29 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 28. FIG. 30 is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 29.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a ferroelectric memory according to the first embodiment of the present invention. Although not limited, the ferroelectric memory according to the present embodiment is, for example, a chain type FeRAM. In the chain type FeRAM, both ends of the ferroelectric capacitor FC are connected between the source and drain of the cell transistor CT, and this is used as a unit cell (memory cell MC), and a plurality of unit cells (memory cells MC) are connected in series. It is a connected ferroelectric memory.

  The ferroelectric memory according to the present embodiment includes a plurality of word lines WLi (i is an integer) extending in the row direction, a plurality of bit lines BL and bBL extending in the column direction orthogonal to the row direction, and the row direction. A plurality of plate lines PL extending to the right and a block selection unit BSP.

  One memory cell MC stores binary data or multi-bit data in a ferroelectric capacitor. The memory cell MC is provided corresponding to the intersection of the word line WLi and the bit lines BL, bBL. Each word line WLi is connected to the gate of the cell transistor CT arranged in the row direction or functions as a gate. Each bit line BL, bBL is connected to the source or drain of the cell transistor CT arranged in the column direction.

  The ferroelectric memory includes a plurality of cell blocks CB configured by connecting a plurality of memory cells MC including a ferroelectric capacitor FC and a cell transistor TC connected in parallel to each other in series. One end of the cell block CB is connected to one end of the block selection unit BSP. The other end of the cell block CB is connected to the plate line PL. The other end of the block selection unit BSP is connected to the bit line BL or bBL, respectively. That is, the bit lines BL and bBL are each connected to the cell block CB via the block selection unit BSP.

  The block selection unit BSP includes an enhancement type transistor TSE and a depletion type transistor TSD. The enhancement type transistor TSE and the depletion type transistor TSD are controlled by a block selection line BS0 or BS1. Thereby, the block selection unit BSP can selectively connect one of the bit line pair BL or bBL to the bit line BL or bBL.

  A sense amplifier SA is connected to the bit line pair BL, bBL. The sense amplifier SA detects data from the memory cell that propagates to the bit line pair BL, bBL when reading data. The sense amplifier SA can write data to the memory cell MC by applying a voltage to the bit line pair BL, bBL at the time of data writing. Note that this embodiment may operate in either the 1T1C mode or the 2T2C mode.

  FIG. 2 is a layout diagram illustrating a partial planar configuration of the first embodiment. A plurality of ferroelectric capacitors FC are arranged in the extending direction (column direction) of the bit lines BL and bBL to form a cell block. Two upper electrodes UE of the ferroelectric capacitors FC included in the cell block are connected to each other by the local wiring LIC. Furthermore, the local wiring LIC is connected to an electrode plug PLG2 provided in the Via hole VH.

  The word line WL also serves as the gate electrode G of the cell transistor CT and extends in the row direction. The word line WL is formed below the ferroelectric capacitor FC and insulated from the ferroelectric capacitor FC.

  A first electrode plug PLG1 is formed under the lower electrode LE between two local wirings LIC adjacent in the column direction. The first electrode plug PLG1 connects the lower electrode LE to the source or drain of the cell transistor CT. The two lower electrodes LE on both sides of the first electrode plug PLG1 are separated from each other in FIG. However, as shown in FIG. 3, these two lower electrodes LE may be connected.

  Since the side surface of the ferroelectric capacitor FC is formed in a forward tapered shape, the planar size of the upper electrode UE is smaller than the planar size of the lower electrode LE indicated by a broken line in FIG.

  Two cell blocks adjacent to each other in the row direction are shifted by a half pitch of the local wiring LIC in the column direction.

  FIG. 3 is a cross-sectional view taken along line 3-3 (column direction) of FIG. 4 is a cross-sectional view taken along line 4-4 (row direction) of FIG. Note that the scale of the drawings may be different in each drawing. A plurality of cell transistors CT are formed on the silicon substrate 10. A first interlayer insulating film ILD1 is provided on the source S or drain D of the cell transistor CT and on the side surface and upper surface of the gate electrode G. The first and second electrode plugs PLG1 and PLG2 pass through the first interlayer insulating film ILD1 and are connected to either the source S or the drain D of the cell transistor CT.

  A metal plug 20 is formed on the first electrode plug PLG1. A conductive barrier film 30 is provided on the metal plug 20. A lower electrode LE is provided on the barrier film 30. The lower electrode LE is electrically connected to the first electrode plug PLG1 through the barrier film 30 and the metal plug 20. A ferroelectric film FE is provided on the lower electrode LE. The upper electrode UE is provided on the ferroelectric film FE. The upper electrode UE, the ferroelectric film FE, and the lower electrode LE constitute the ferroelectric capacitor FC.

  A part of the upper surface and the side surface of the ferroelectric capacitor FC are covered with the hydrogen barrier film HB. The other part of the upper surface of the ferroelectric capacitor FC is not covered with the hydrogen barrier film HB and is connected to the local wiring LIC. The hydrogen barrier film HB may be only a hydrogen barrier film that covers the side surface of the ferroelectric capacitor FC, or may be a laminated film including a hydrogen barrier film and an insulating film.

  The bottom surface of the ferroelectric capacitor FC is covered with a barrier film 30, and a part of the upper surface and the entire side surface of the ferroelectric capacitor FC are covered with a hydrogen barrier film HB. The hydrogen barrier film HB is formed along the side surface of the ferroelectric capacitor FC formed in a forward tapered shape. Therefore, it is possible to prevent hydrogen from entering the ferroelectric capacitor FC to some extent after the manufacture of the ferroelectric capacitor FC.

  A second interlayer insulating film ILD2 is formed on the hydrogen barrier film HB. The local wiring LIC is provided on the second interlayer insulating film ILD2 and the hydrogen barrier film HB, and is connected to the upper electrode UE through the hydrogen barrier film HB. The local wiring LIC connects the upper electrodes UE of the two ferroelectric capacitors FC adjacent in the column direction on both sides of the second electrode plug PLG2. Further, the local wiring LIC is connected to the second electrode plug PLG2 through the through plug PPLG. As a result, the upper electrodes UE of the two ferroelectric capacitors FC are connected to the source S or drain D of the cell transistor CT via the through plug PPLG and the second electrode plug PLG2 provided therebetween. .

  The through plug PPG passes through the local wiring LIC, the second interlayer insulating film ILD2, and the hydrogen barrier film HB and is connected to the metal plug 20 and the second electrode plug PLG2. The through plug PPG is filled in a via hole formed in a self-aligning manner using the local wiring LIC as a mask. Therefore, the alignment misalignment of the photoresist mask or hard mask on the third interlayer insulating film is corrected by the local wiring LIC. As a result, a sufficient distance between the through plug PPG and the ferroelectric capacitor FC is maintained, and a short circuit between the through plug PPG and the ferroelectric capacitor FC is prevented.

  The local wiring LIC is electrically insulated from the ferroelectric film FE and the lower electrode LE by the second interlayer insulating film ILD2 and the hydrogen barrier film HB formed on the side surface of the ferroelectric capacitor FC. Further, as shown in FIG. 2, the central portion of the local wiring LIC protrudes in the row direction in the planar layout. That is, the width in the row direction at the center of the local wiring LIC is wider than the width in the row direction at the end of the local wiring LIC. The distance from the end of the via hole VH2 to the side end of the local wiring LIC is maintained at F or more. This is because the local wiring LIC having the via hole VH2 can be patterned by lithography and etching. Here, F (Feature Size) is the minimum line width that can be formed using a lithography technique and an etching technique.

  On the other hand, the lower electrodes LE of the two ferroelectric capacitors FC adjacent in the column direction on the first electrode plug PLG1 are both connected to the first electrode plug PLG1, and the cell transistor is connected via the first electrode plug PLG1. Connected to the drain D or source S of CT.

  As described above, the ferroelectric capacitor FC and the cell transistor CT are connected in parallel to form the memory cell MC. The plurality of memory cells MC arranged in the column direction are connected in series by the first electrode plug PLG1, the second electrode plug PLG2, and the local wiring LIC to form a cell block CB.

  A third interlayer insulating film ILD3 is deposited on the local wiring LIC. Further, a dummy metal layer DM is provided on the third interlayer insulating film ILD3. A fourth interlayer insulating film ILD4 is provided on the dummy metal layer DM.

  The dummy metal layer DM is provided to suppress dishing of the fourth interlayer insulating film ILD4 in the memory region when wiring necessary for the peripheral logic circuit in the memory region is formed. Therefore, the dummy metal layer DM may be in a floating state or grounded. The dummy metal layer DM is preferably formed of a metal having a resistance lower than that of the local wiring LIC. Alternatively, the planar pattern of the dummy metal layer DM is preferably laid out with a pattern having a lower resistance than that of the local wiring LIC. This is because the adjacent upper electrode UE and the adjacent second electrode plug PLG2 can be connected with low resistance.

  According to the present embodiment, the local wiring LIC is formed in a process prior to the process of forming the through plug PPLG connected to the second electrode plug PLG2. Therefore, the interlayer film (second interlayer insulating film ILD2) between the local wiring LIC and the upper electrode UE can be thinned. Thereby, the local wiring LIC can be formed of a metal sputtered film such as iridium. Since the sputtering process does not generate hydrogen unlike MO-CVD, the ferroelectric capacitor FC does not deteriorate. Furthermore, since there is no need to form a plug on the upper electrode UE, the number of buried electrode steps can be reduced. Thereby, the manufacturing cost can be reduced.

  Since the second interlayer insulating film ILD2 on the upper electrode UE is thinned, the overetching time when forming the via hole on the upper electrode UE is shortened. Therefore, damage to the upper electrode UE can be suppressed. The film thickness of the hydrogen barrier film HB provided on the upper electrode UE is preferably smaller than the film thickness of the hydrogen barrier film HB provided on the side surface of the ferroelectric capacitor FC. This is because the overetching time when forming the via hole on the upper electrode UE is further shortened, and damage to the upper electrode UE can be further suppressed.

  FIG. 5A to FIG. 15B are cross-sectional views illustrating a method for manufacturing a ferroelectric memory according to the first embodiment. (A) of these drawings corresponds to the cross section shown in FIG. 3, and (B) corresponds to the cross section shown in FIG. First, as shown in FIGS. 5A and 5B, the cell transistor CT is formed on the surface of the semiconductor substrate 10. At this time, a silicide layer 40 may be formed on the gate electrode G, the source S, and the drain D in order to reduce the wiring resistance. The semiconductor substrate 10 is a silicon substrate, for example.

  Next, a first interlayer insulating film ILD1 is deposited on the gate electrode G, the source S, and the drain D by using LP-CVD (Low Pressure-CVD) method or plasma CVD method. The first interlayer insulating film ILD1 is, for example, a PSG film, a BPSG film, a TEOS film, or a laminated film thereof. Next, the first interlayer insulating film ILD1 is planarized using CMP (Chemical Mechanical Polishing). Next, contact holes reaching the source S or the drain D are formed between the gate electrodes G adjacent in the column direction by using lithography and RIE (Reactive Ion Etching).

  Next, a metal laminated film of Ti (titanium) or TiN and W (tungsten) is deposited in the contact hole by using MO-CVD method or ALD (Atomic Layer Deposition) method. Further, the first electrode plug PLG1 and the second electrode plug PLG2 are formed by flattening the metal laminated film using the CMP method. Such a method of embedding a metal plug in the contact hole is called a damascene method. At this time, since the ferroelectric capacitor FC has not been formed yet, the MO-CVD method in which a large amount of hydrogen is generated may be used.

  Similarly, the damascene method is used to form the metal plug 20 on the first and second metal plugs PLG1 and PLG2. A conductive hydrogen barrier film 30 is formed on the second metal plug PLG2.

Next, the ferroelectric capacitor FC is formed on the barrier film 30. More specifically, a lower electrode material such as iridium is deposited on the barrier film 30 by sputtering. Sputtering, using MO-CVD method or a sol-gel _{method, PZT (Pb (Zr x Ti} (1-x)) O 3), SBT (Sr x Bi y Ta z O a), BLT (Bi x La y O _A ferroelectric film made of _z ) or the like is deposited on the lower electrode material. Further, an upper electrode material such as an IrO ₂ film is deposited on the ferroelectric film by sputtering. Using a plasma CVD method, a mask material such as a TEOS film is deposited on the upper electrode material. Note that the materials of the upper electrode UE and the lower electrode LE are not limited to the above materials.

  Next, as shown in FIGS. 6A and 6B, the mask material is processed into a pattern of the ferroelectric capacitor FC by using lithography and RIE. Further, the upper electrode material, the ferroelectric film, and the lower electrode material are sequentially etched by the RIE method using the mask material as a mask. At this time, the side surface of the ferroelectric capacitor FC is formed in a forward tapered shape. The forward taper refers to the inclination of the side in a trapezoid whose lower side is longer than the upper side in the cross section. In this way, by forming the side surface of the ferroelectric capacitor FC in a forward tapered shape, the second interlayer insulating film ILD2 can cover the ferroelectric capacitor FC with good coverage.

After the formation of the ferroelectric capacitor FC, as shown in FIGS. 7A and 7B, a hydrogen barrier film HB such as Al ₂ O ₃ is deposited by sputtering or ALD. The hydrogen barrier film HB covers the upper surface and side surfaces of the ferroelectric capacitor FC. The film thickness of the hydrogen barrier film HB on the upper surface of the upper electrode UE may be smaller than the film thickness of the hydrogen barrier film HB on the side surface of the ferroelectric capacitor FC. The hydrogen barrier film HB may be a multilayer film including a barrier film that does not allow hydrogen to permeate.

  As shown in FIGS. 8A and 8B, a second interlayer insulating film ILD2 is deposited on the hydrogen barrier film using plasma CVD or the like. The second interlayer insulating film ILD2 is planarized to the upper surface level of the hydrogen barrier film HB. At this time, the upper surface of the hydrogen barrier film HB may be exposed, or may be covered with the second interlayer insulating film ILD2.

  Next, as shown in FIGS. 9A and 9B, a first via hole VH1 is formed on the upper electrode UE. At this time, since it is sufficient to etch the thin hydrogen barrier film HB, the over-etching time is short. For this reason, the damage to the upper electrode UE is less than before. At this time, it is sufficient to use a normal resist, and it is not necessary to use a hard mask process.

Next, as shown in FIGS. 10A and 10B, using a sputtering method, a single layer film such as Ir, TiN, TiAlN, IrO ₂ , Ru, or SrRuO ₂ or _two or more of them is used. A laminated film made of is deposited on the second interlayer insulating film ILD2 and the upper electrode UE. This metal film is a material processed into the local wiring LIC. This metal film is also formed on the inner wall of the first via hole VH1. Here, since the material of the local wiring LIC is formed by sputtering, hydrogen is not generated. Therefore, even if the upper electrode UE is exposed at this time, the ferroelectric capacitor FC hardly deteriorates.

  In order to prevent hydrogen from entering the ferroelectric capacitor FC when the through plug PPLG is formed later, the material of the local wiring LIC is formed of a hydrogen barrier film that prevents permeation of hydrogen. May be. For example, the material of the local wiring LIC is TiAlN, a single layer film of TiN, or a laminated film of TiAlN or TiN and Ir. Alternatively, the second hydrogen barrier film HB2 may be provided under or on the local wiring LIC.

  Next, as shown in FIGS. 11A and 11B, the local wiring LIC is patterned using lithography and RIE. As a result, the local wiring LIC on the second electrode plug PLG2 is removed to provide the through hole PH. The through hole PH is provided above the second electrode plug PLG2 in FIG.

  Next, as shown in FIGS. 12A and 12B, the third interlayer insulating film ILD3 is formed on the local wiring LIC, the second interlayer insulating film ILD2, and the hydrogen barrier film HB by using the CVD method. To deposit. The third interlayer insulating film ILD3 is planarized using the CMP method.

  Next, as shown in FIGS. 13A and 13B, via holes VH2 are formed on second electrode plugs PLG2 and 20 using lithography and RIE. At this time, the third interlayer insulating film ILD3 is patterned according to a resist mask or a hard mask formed by lithography. However, after that, the second interlayer insulating film ILD2 and the hydrogen barrier film HB are etched by RIE using the local wiring LIC (end portion of the through hole PH) as a mask. As a result, a second via hole VH2 reaching the plug 20 on the second electrode plug PLG2 is formed.

  As shown in FIGS. 14A and 14B, the through-plug PPLG is filled in the second via hole VH2 using MO-CVD. The material of the through plug PPLG is, for example, tungsten. At this time, hydrogen is generated, but the hydrogen barrier films HB and 30 and the local wiring LIC (or the second hydrogen barrier film HB2) protect the ferroelectric capacitor FC from hydrogen. In this step, since it is not necessary to use an aluminum reflow process, the manufacturing cost does not increase.

  After planarizing the through plug PPLG by CMP or the like, a dummy wiring DM is formed on the through plug PPLG and the third interlayer insulating film ILD3 as shown in FIGS. 15A and 15B. Thereby, the ferroelectric memory according to the first embodiment is completed.

  According to the present embodiment, the second via hole VH2 is formed in a step after the local wiring LI. This eliminates the need for a plug between the local wiring LIC and the upper electrode UE. As a result, the local wiring LIC can be formed by a sputtering method in which hydrogen is not generated. Moreover, since the hydrogen barrier film HB can be formed thin, damage to the upper electrode UE can be suppressed.

  Even if the mask on the third interlayer insulating film ILD3 is slightly misaligned, the through hole PH of the local wiring LIC can correct this misalignment. In this case, the through plug PPLG is not in contact with the local wiring LIC at one end of the through hole PH, but is in contact with the top and side surfaces of the local wiring LIC at the other end of the through hole PH (see 99 in FIG. 13A). . Therefore, the contact resistance between the through plug PPLG and the local wiring LIC is not so high.

  As shown in FIG. 2, in adjacent columns, the memory cells of the ferroelectric capacitor FC are formed with a half pitch shift of the local wiring LIC. Similarly, the through plug PPLG is shifted by a half pitch. As a result, the space between adjacent columns can be kept narrow while making the planar layout of the central portion of the local wiring LIC wider than the end of the local wiring LIC. This leads to miniaturization of the memory chip.

  Furthermore, the number of lithography processes in the manufacturing method according to the present embodiment is the same as that of the conventional ferroelectric memory.

(Second Embodiment)
FIG. 16 is a plan view showing the configuration of the ferroelectric memory according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that a part of the through hole of the local wiring LIC is opened. Other configurations of the second embodiment may be the same as those of the first embodiment. In the planar layout, the through hole of the local wiring LIC is formed in a U shape, and one side is notched. Let this notch be H.

  In the second embodiment, when the second via hole VH2 is formed, the opening diameter of the second via hole VH2 is changed even if the mask on the third interlayer insulating film ILD3 is shifted to the notch H side. Absent. Of course, when the mask on the third interlayer insulating film ILD3 is shifted to the opposite side to the notch H side, or when the mask on the third interlayer insulating film ILD3 is shifted in the column direction, The opening diameter of the second via hole VH2 is reduced. Therefore, even if the mask on the third interlayer insulating film ILD3 is shifted to the side opposite to the notch H side, the mask on the third interlayer insulating film ILD3 is not reduced so that the opening diameter of the second via hole VH2 is not reduced. May be shifted to the notch H side in advance. Furthermore, the second embodiment can obtain the same effects as those of the first embodiment.

  The manufacturing method of the second embodiment may be the same as the manufacturing method of the first embodiment. However, the planar layout of the local wiring LIC according to the second embodiment is only different from that of the first embodiment.

(Third embodiment)
17 and 18 are cross-sectional views showing the structure of a ferroelectric memory according to the third embodiment of the present invention. Since the plan view is the same as FIG. 2 or FIG. 16, the illustration is omitted. 17 corresponds to a cross-sectional view taken along line 3-3 in FIG. 2, and FIG. 18 corresponds to a cross-sectional view taken along line 4-4 in FIG.

  The third embodiment is different from the first or second embodiment in that the upper electrode UE is formed in an inverted T shape in a cross section in the column direction. That is, the area of the upper surface of the upper electrode UE is narrower than the area of the bottom surface. The bottom surface of the upper electrode UE is in contact with the upper surface of the ferroelectric film FE, and the area of the bottom surface of the upper electrode UE is substantially equal to the area of the upper surface of the ferroelectric film FE. The entire upper surface of the upper electrode UE is in contact with the local wiring LIC. In other words, the upper electrode UE has a pillar at the top, and is connected to the local wiring LIC by the pillar.

  According to the third embodiment, the local wiring LIC is directly formed on the planarized upper electrode UE (pillar). That is, etching such as RIE is not used when forming the contact hole to the upper electrode UE. Therefore, the upper electrode UE does not receive etching damage due to RIE or the like. Further, since the area of the upper surface of the upper electrode UE (pillar) is smaller than the area of the bottom surface, the area of the ferroelectric film FE compressed by the pillar becomes relatively small. Since the ferroelectric film FE expands or contracts in the vertical direction due to polarization, it is preferable that the ferroelectric film FE is not subjected to compression between the upper electrode UE and the lower electrode LE. Therefore, the polarization characteristics of the ferroelectric capacitor FC can be improved by making the area of the upper surface of the upper electrode UE (pillar) narrower than the area of the bottom surface.

  Other configurations of the third embodiment may be the same as the configurations of the first or second embodiment. Therefore, the third embodiment can further obtain the effects of the first or second embodiment.

  FIG. 19A to FIG. 30B are cross-sectional views showing a method for manufacturing a ferroelectric memory according to the third embodiment. First, as described above, the structure shown in FIG. 5 is formed.

  As shown in FIGS. 19A and 19B, a TEOS film or the like as the mask material 60 is deposited on the upper electrode UE by plasma CVD. Next, the mask material 60 is processed using lithography and RIE. At this time, the mask material 60 is patterned so as to remain in the region inside the plane pattern of the ferroelectric capacitor FC.

  Next, as shown in FIGS. 20A and 20B, the upper portion of the upper electrode UE is etched by RIE using the mask material 60 as a mask.

  Next, as shown in FIGS. 21A and 21B, a sidewall film 70 is formed on the side surface of the mask material 60 and the upper side surface of the upper electrode UE. The material of the sidewall film 70 may be the same as the material of the mask material 60.

  Next, as shown in FIGS. 22A and 22B, using the mask material 60 and the sidewall film 70 as a mask, the lower part of the upper electrode UE, the material of the ferroelectric film FE, and the lower electrode LE The material and the hydrogen barrier film 30 are etched by RIE. Thereby, the ferroelectric capacitor FC is formed. At this time, the bottom surface of the upper electrode UE is formed wider than the top surface by the thickness of the sidewall film 70. Therefore, the upper electrode UE is formed in an inverted T shape having a pillar on the upper part.

Next, as shown in FIGS. 23A and 23B, the upper and side surfaces of the ferroelectric capacitor FC are covered with a hydrogen barrier film HB such as Al ₂ O ₃ by using a sputtering method or an ALD method. To do.

  Next, as shown in FIGS. 24A and 24B, a second interlayer insulating film ILD2 is deposited on the hydrogen barrier film HB using plasma CVD or the like. Subsequently, as shown in FIGS. 25A and 25B, the second interlayer insulating film ILD2 is planarized to the upper surface of the upper electrode UE using CPM. At this time, the upper surface of the upper electrode UE is exposed.

  Next, as shown in FIGS. 26A and 26B, the material of the local wiring LIC is deposited on the upper electrode UE and the second interlayer insulating film ILD2 by sputtering. The material of the local wiring LIC may be the same as the material of the local wiring in the first embodiment. At this time, since the upper surface of the upper electrode UE is exposed, the local wiring LIC can contact the entire upper surface of the upper electrode UE.

  Here, since the material of the local wiring LIC is formed by sputtering, hydrogen is not generated. Therefore, even if the upper electrode UE is exposed at this time, the ferroelectric capacitor FC hardly deteriorates.

  In order to prevent hydrogen from entering the ferroelectric capacitor FC when the through plug PPLG is formed later, the material of the local wiring LIC is formed of a hydrogen barrier film that prevents permeation of hydrogen. May be. For example, the material of the local wiring LIC is TiAlN, a single layer film of TiN, or a laminated film of TiAlN or TiN and Ir. Alternatively, the second hydrogen barrier film HB2 may be provided under or on the local wiring LIC.

  Next, as shown in FIGS. 27A and 27B, the material of the local wiring LIC is patterned using lithography and RIE. As a result, the local wiring LIC on the second electrode plug PLG2 is removed to provide the through hole PH. The through hole PH is provided at the position of the via hole VH2 in FIG. 2 or FIG.

  Since the process after the formation of the local wiring LIC may be the same as the manufacturing process of the first embodiment, its detailed description is omitted. As shown in FIGS. 28A and 28B, a third interlayer insulating film ILD3 is deposited on the local wiring LIC and the second interlayer insulating film ILD2 by using the CVD method. The third interlayer insulating film ILD3 is planarized using the CMP method.

  Next, as shown in FIGS. 29A and 29B, via holes VH2 are formed on the second electrode plugs PLG2 and 20 using lithography and RIE. Since the method for forming the via hole VH2 may be the same as that in the first embodiment, a detailed description thereof is omitted.

  Next, as shown in FIGS. 30A and 30B, the through-plug PPLG is filled in the second via hole VH2 using MO-CVD. The material of the through plug PPLG is, for example, tungsten. At this time, hydrogen is generated, but the hydrogen barrier films HB and 30 and the local wiring LIC (or the second hydrogen barrier film HB2) protect the ferroelectric capacitor FC from hydrogen.

  After planarizing the through plug PPLG by CMP or the like, a dummy wiring DM is formed on the through plug PPLG and the third interlayer insulating film ILD3 as shown in FIGS. Thereby, the ferroelectric memory according to the third embodiment is completed.

  The third embodiment can obtain the effects of the first or second embodiment in addition to the effects described above.

10 Semiconductor Substrate ILD1, ILD2, ILD3 ... Interlayer Insulating Film, PLG1, PLG2 ... Electrode Plug, Lower Electrode ... LE, Ferroelectric Film ... FE, Upper Electrode ... UE, Electric Capacitor ... FC, Hydrogen Barrier Film ... HB, Local Wiring ... LIC, through plug ... PPLG

Claims (5)

A semiconductor substrate;
A plurality of transistors provided on the semiconductor substrate;
A first interlayer film covering the transistor;
A first plug penetrating through the first interlayer film and connected to one of a source or a drain of the transistor;
A second plug penetrating the first interlayer film and connected to the other of the source and drain of the transistor;
A lower electrode provided above the first plug and electrically connected to the first plug, a ferroelectric film provided on the lower electrode, and provided on the ferroelectric film A ferroelectric capacitor including an upper electrode;
A hydrogen barrier film covering the ferroelectric capacitor;
A second interlayer film provided on the hydrogen barrier film;
A local wiring provided on the second interlayer film and the hydrogen barrier film, penetrating the hydrogen barrier film and connected to the upper electrode;
A semiconductor memory device comprising: the local wiring, the second interlayer film, and a through plug connected to the second plug through the hydrogen barrier film.   The semiconductor memory device according to claim 1, wherein a part of the through hole of the local wiring provided with the through plug is open. The upper electrode is formed to have an upper surface with a smaller area than the bottom surface,
The ferroelectric film faces a bottom surface of the upper electrode;
3. The semiconductor memory device according to claim 1, wherein the local wiring is in contact with an upper surface of the upper electrode. Forming a plurality of transistors on a semiconductor substrate;
Forming a first interlayer film so as to cover the transistor;
A first plug passing through the first interlayer film and connected to one of the source and drain of the transistor and a first plug passing through the first interlayer film and connected to the other of the source and drain of the transistor 2 plugs and
Forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode above the first plug;
Forming a hydrogen barrier film so as to cover the ferroelectric capacitor;
Forming a second interlayer film on the hydrogen barrier film;
Forming a first via hole that penetrates the hydrogen barrier film and reaches the upper electrode;
Forming a local wiring on the upper electrode in the first via hole and on the second interlayer film;
Removing the local wiring on the second plug to provide a through hole in the local wiring;
Etching the second interlayer film and the hydrogen barrier film using the local wiring as a mask to form a second via hole,
A method of manufacturing a semiconductor memory device, comprising forming a through plug in the second via hole. Forming a plurality of transistors on a semiconductor substrate;
Forming a first interlayer film so as to cover the transistor;
A first plug passing through the first interlayer film and connected to one of the source and drain of the transistor and a first plug passing through the first interlayer film and connected to the other of the source and drain of the transistor 2 plugs and
Depositing a lower electrode material, a ferroelectric film material and an upper electrode material above the first plug;
Forming a hard mask in a region inside a plane pattern of a ferroelectric capacitor including the lower electrode, the ferroelectric film and the upper electrode;
Etching the upper part of the material of the upper electrode using the hard mask as a mask,
Forming a sidewall film on the upper side of the upper electrode material;
The ferroelectric including the inverted T-shaped upper electrode by etching the lower part of the material of the upper electrode, the material of the ferroelectric film, and the material of the lower electrode using the hard mask and the sidewall film as a mask. Forming a capacitor,
Forming a hydrogen barrier film so as to cover the ferroelectric capacitor;
Forming a second interlayer film on the hydrogen barrier film;
Polishing the second interlayer film to expose the upper surface of the upper electrode;
Forming a local wiring on the upper electrode and the second interlayer film;
Removing the local wiring on the second plug to provide a through hole in the local wiring;
Etching the second interlayer film and the hydrogen barrier film using the local wiring as a mask to form a second via hole reaching the second plug;
A method of manufacturing a semiconductor memory device, comprising forming a through plug in the second via hole.

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