JP6435683B2 - PLL circuit and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a PLL circuit and a semiconductor integrated circuit.

  A semiconductor integrated circuit such as SoC (System on Chip) has, for example, a PLL (Phase Locked Loop) circuit that supplies a clock to each circuit block. The output clock of the PLL circuit is used for, for example, an AD converter, HDMI (High-Definition Multimedia Interface: registered trademark), USB (Universal Serial Bus), and the like.

  The PLL circuit has, for example, a frequency divider that divides the output clock in order to generate an output clock obtained by multiplying the frequency of the input clock. For example, the PLL circuit performs feedback control so that the phase difference between the feedback clock obtained by dividing the output clock and the input clock match (for example, refer to Patent Documents 1 and 2).

  For example, power for the PLL circuit is supplied from a dedicated analog power source in order to reduce jitter due to noise from other circuit blocks. Note that noise generated by the frequency divider causes a jitter increase, and therefore, the power source of the frequency divider may be supplied from a digital power source different from the analog power source dedicated to the PLL circuit.

  Here, in the PLL circuit that divides the input clock and the output clock using a counter, a phase detector that compares the phase of the input clock with the phase of the output clock instead of comparing the phase of the output signal of the counter is proposed. (For example, see Patent Document 3). For example, the phase detector uses the output signal of the counter as a control signal and compares the phase of the input clock with the phase of the output clock.

JP 2011-135381 A JP 2001-76439 A JP 2007-124699 A

  The power supply noise of a digital power supply is often larger than the power supply noise of an analog power supply. For example, when the power supply noise of the digital power supply supplied to the frequency divider is large, the delay time of the frequency divider may vary. Since the phase of the input clock is compared with the phase of the feedback clock output from the frequency divider, fluctuations in the delay time of the frequency divider appear as jitter in the output clock.

  In the method of comparing the phase of the input clock with the phase of the output clock using the output signal of the frequency divider as a control signal, for example, the fluctuation of the delay time of the frequency divider exceeds one cycle of the output clock. In this case, the fluctuation of the delay time of the frequency divider appears as jitter of the output clock.

  In one aspect, a PLL circuit and a semiconductor integrated circuit disclosed herein are intended to reduce jitter of an output clock of the PLL circuit.

  According to one aspect, the PLL circuit generates an output clock having a frequency according to a control voltage adjusted by a control signal, and receives the output clock and divides the output clock to generate a divided clock. A delay adjusting circuit that receives the divided clock, adjusts a delay amount with respect to the divided clock, and generates a feedback clock obtained by delaying the divided clock, and receives the input clock, the output clock, and the feedback clock. And a phase comparator that detects a phase difference between the output clock detected at the timing based on the feedback clock and the input clock and generates a control signal in accordance with the phase difference between the output clock and the input clock.

  According to another aspect, the semiconductor integrated circuit includes a PLL circuit, and the PLL circuit receives an output clock, a clock generation unit that generates an output clock having a frequency according to a control voltage adjusted by a control signal, A divider that divides the output clock to generate a divided clock, and a delay adjustment circuit that receives the divided clock, adjusts the amount of delay with respect to the divided clock, and generates a feedback clock by delaying the divided clock The input clock, output clock and feedback clock are received, the phase difference between the input clock and the output clock detected at the timing based on the feedback clock is detected, and the control signal is sent according to the phase difference between the output clock and the input clock. And a phase comparator to be generated.

  The PLL circuit and the semiconductor integrated circuit of the present disclosure can reduce the jitter of the output clock of the PLL circuit.

It is a figure which shows one Embodiment of a PLL circuit and a semiconductor integrated circuit. FIG. 2 is a diagram illustrating an example of a phase comparator illustrated in FIG. 1. FIG. 2 is a diagram illustrating an example of a delay adjustment circuit illustrated in FIG. 1. It is a figure which shows an example of the delay detection part shown in FIG. FIG. 4 is a diagram illustrating an example of a variable delay unit illustrated in FIG. 3. FIG. 3 is a diagram illustrating an example of the operation of the phase comparator illustrated in FIG. 2. FIG. 5 is a diagram illustrating an example of an operation of a delay detection unit illustrated in FIG. 4. It is a figure which shows an example of operation | movement of the variable delay part shown in FIG. FIG. 2 is a diagram illustrating an example of the operation of the PLL circuit illustrated in FIG. 1. It is a figure which shows another example of the delay detection part shown in FIG. It is a figure which shows an example of operation | movement of the delay detection part shown in FIG. It is a figure which shows an example of operation | movement of the PLL circuit containing the delay detection part shown in FIG. It is a figure which shows another embodiment of a PLL circuit and a semiconductor integrated circuit. It is a figure which shows an example of the phase comparator shown in FIG. It is a figure which shows an example of operation | movement of the phase comparator shown in FIG. It is a figure which shows an example of operation | movement of the PLL circuit shown in FIG. It is a figure which shows another example of operation | movement of the PLL circuit shown in FIG. It is a figure which shows another embodiment of a PLL circuit and a semiconductor integrated circuit. It is a figure which shows an example of the control circuit shown in FIG. It is a figure which shows another embodiment of a PLL circuit and a semiconductor integrated circuit. It is a figure which shows an example of the phase comparator shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings. The broken arrows in the figure show an example of the flow of signals such as clocks. In addition, reference sign PLL (Phase Locked Loop) in the figure indicates a phase synchronization circuit. Hereinafter, the phase synchronization circuit PLL is also referred to as a PLL circuit.

  FIG. 1 shows an embodiment of a PLL circuit and a semiconductor integrated circuit. The PLL circuit of this embodiment is mounted on a semiconductor integrated circuit SEM such as SoC (System on Chip). That is, the semiconductor integrated circuit SEM of this embodiment has a PLL circuit. In addition to the PLL circuit, the semiconductor integrated circuit SEM has a logic circuit such as an image processing circuit. Note that the logic circuit in the semiconductor integrated circuit SEM is not limited to the image processing circuit. The logic circuit in the semiconductor integrated circuit SEM outputs, for example, a reset signal SRST for resetting the operation of the PLL circuit and control signals EN and STR for controlling the operation of the delay adjustment circuit DLY in the PLL circuit to the PLL circuit. . Note that the control signals EN and STR may be generated in the PLL circuit.

  The PLL circuit receives, for example, an input clock CKI (hereinafter also referred to as clock CKI), control signals EN and STR, and a reset signal SRST, and outputs an output clock CKO (hereinafter also referred to as clock CKO) to a logic circuit or the like in the semiconductor integrated circuit SEM. ). The output clock CKO of the PLL circuit is used for an AD converter, HDMI (High-Definition Multimedia Interface), USB (Universal Serial Bus), etc., for example. The input clock CKI is supplied to the PLL circuit from a crystal oscillator connected to the semiconductor integrated circuit SEM, for example. Note that the PLL circuit may receive a clock (for example, clock CKID1 in FIG. 20) obtained by dividing the clock of the crystal oscillator as an input clock CKI from an input frequency divider or the like. In this case, the PLL circuit may be defined including the input frequency divider, or may be defined excluding the input frequency divider.

  For example, the PLL circuit includes a phase comparator PFD, a clock generation unit CGEN, a frequency divider DIV, and a delay adjustment circuit DLY. The power of the phase comparator PFD, the clock generation unit CGEN, and the delay adjustment circuit DLY is supplied from, for example, analog power supplies AVD and AVS dedicated to the PLL circuit. For example, the voltage of the analog power supply AVS corresponds to the ground voltage.

  Further, the power supply of the frequency divider DIV is supplied from digital power supplies VDD and VSS different from the analog power supplies AVD and AVS. For example, the voltage of the digital power supply VSS corresponds to the ground voltage. Here, for example, the power supply of the logic circuit in the semiconductor integrated circuit SEM is also supplied from the digital power supplies VDD and VSS. That is, the power supply of the frequency divider DIV is supplied from the digital power supplies VDD and VSS common to the logic circuit.

  Reference sign PLLa in the figure indicates a circuit block to which power is supplied from analog power supplies AVD and AVS among circuit blocks in the PLL circuit. Reference sign PLLd in the figure indicates a circuit block to which power is supplied from the digital power supplies VDD and VSS among circuit blocks in the PLL circuit.

  The phase comparator PFD is an example of a phase comparator that detects a phase difference between an output clock CKO detected at a timing based on a feedback clock CKFB (hereinafter also referred to as a clock CKFB) and an input clock CKI. For example, the phase comparator PFD receives the reset signal SRST, the input clock CKI, the output clock CKO output from the clock generation unit CGEN, and the feedback clock CKFB output from the delay adjustment circuit DLY. Then, the phase comparator PFD generates the up signal UP and the down signal DN based on the phase difference between the input clock CKI and the output clock CKO, and outputs the up signal UP and the down signal DN to the clock generation unit CGEN.

  For example, the phase comparator PFD compares the first rising edge of the output clock CKO after the feedback clock CKFB rises with the rising edge of the input clock CKI, and compares the phase difference between the output clock CKO and the input clock CKI. To detect. The phase comparator PFD outputs, for example, an up signal UP when the phase of the output clock CKO is behind the input clock CKI, and the down signal DN when the phase of the output clock CKO is ahead of the input clock CKI. Is output. Thus, since the phase comparator PFD compares the output clock CKO and the input clock CKI, it is possible to reduce the influence of delay variation of the feedback clock CKFB. For example, the PLL circuit can suppress an increase in jitter of the output clock CKO even when delay variation occurs in the feedback path (frequency divider DIV).

  The clock generation unit CGEN is an example of a clock generation unit that generates an output clock CKO having a frequency corresponding to a control voltage adjusted by a control signal (for example, an up signal UP or a down signal DN). For example, the clock generation unit CGEN includes a charge pump circuit CP, a low-pass filter LPF, and a voltage control oscillator VCO.

  Charge pump circuit CP receives up signal UP and down signal DN from phase comparator PFD. Then, the charge pump circuit CP executes current flow or current draw according to the up signal UP and the down signal DN. For example, the charge pump circuit CP flows current into the low-pass filter LPF when the up signal UP is asserted. For example, the charge pump circuit CP draws current from the low-pass filter LPF when the down signal DN is asserted. As described above, the charge pump circuit CP executes the flow of current and the extraction of current according to the phase difference with respect to the low-pass filter LPF.

  The low-pass filter LPF smoothes the output of the charge pump circuit CP and generates a control voltage for the voltage-controlled oscillator VCO. The control voltage generated by the low pass filter LPF is supplied to the voltage control oscillator VCO. In this way, the control voltage is adjusted by the up signal UP and the down signal DN.

  The voltage control oscillator VCO generates an output clock CKO having a frequency corresponding to the control voltage received from the low-pass filter LPF, and generates the generated output clock CKO from the outside of the PLL circuit, the frequency divider DIV, the delay adjustment circuit DLY, and the phase. Output to the comparator PFD. For example, the output clock CKO output from the voltage control oscillator VCO to the outside of the PLL circuit is supplied to a logic circuit or the like in the semiconductor integrated circuit SEM.

  The frequency divider DIV is an example of a frequency divider that divides the output clock CKO to generate a frequency-divided clock CKDIV (hereinafter also referred to as clock CKDIV). For example, the frequency divider DIV divides the output clock CKO received from the voltage control oscillator VCO by a predetermined frequency division ratio to generate the frequency divided clock CKDIV. Then, the frequency divider DIV outputs the frequency-divided clock CKDIV obtained by frequency-dividing the output clock CKO to the delay adjustment circuit DLY. For example, the frequency divider DIV generates the frequency-divided clock CKDIV so that the pulse width (high level period) of the frequency-divided clock CKDIV is equal to one cycle of the output clock CKO. The frequency dividing ratio may be fixed or may be set variably from the outside of the frequency divider DIV.

  The delay adjustment circuit DLY is an example of a delay adjustment circuit that adjusts a delay amount with respect to the divided clock CKDIV and generates a feedback clock CKFB obtained by delaying the divided clock CKDIV. For example, the delay adjustment circuit DLY receives the output clock CKO, the divided clock CKDIV, the control signals EN, STR, and the reset signal SRST, and outputs the feedback clock CKFB to the phase comparator PFD. The control signal STR is a signal for setting the initial value of the delay adjustment circuit DLY, and the control signal EN is a signal for starting the delay adjustment circuit DLY. The feedback clock CKFB is a clock obtained by delaying the frequency-divided clock CKDIV, for example.

  For example, the delay adjustment circuit DLY adjusts the delay amount of the feedback clock CKFB with respect to the divided clock CKDIV so that the delay variation of the feedback clock CKFB is less than one cycle of the output clock CKO. As a result, the PLL circuit can keep the delay variation of the feedback clock CKFB below one cycle of the output clock CKO even when the delay variation of the divided clock CKDIV exceeds one cycle of the output clock CKO. As a result, the PLL circuit can suppress an increase in jitter of the output clock CKO even when the delay variation of the frequency divider DIV exceeds one cycle of the output clock CKO, for example.

  Note that the configurations of the PLL circuit and the semiconductor integrated circuit SEM are not limited to this example. For example, the PLL circuit and the semiconductor integrated circuit SEM may be configured by a DDC (Deeply Depleted Channel) transistor operating at a low voltage, which has been attracting attention in recent years. For example, the DDC transistor can be operated at a low voltage while suppressing a leakage current by controlling the back bias voltage by a back bias voltage generation circuit built in the semiconductor integrated circuit SEM. However, there is a concern that the amount of jitter increases due to noise included in the back bias voltage. Therefore, conventionally, it has been difficult to apply a back bias voltage to the frequency divider DIV in applications where low jitter is required. On the other hand, by applying the circuit of this embodiment, for example, the back bias voltage of a P-type MOS (Metal Oxide Semiconductor) transistor or the back bias voltage of an N-type MOS transistor is applied to the divider DIV. Also good. In this case, the leakage current of the frequency divider DIV can be reduced and the power consumption can be reduced. Further, since it is not necessary to separate the power supply of the logic circuit to which the back bias voltage is applied and the frequency divider DIV, it is possible to prevent the power supply system from being complicated.

  Even when the delay variation of the divider DIV increases due to the noise of the back bias voltage, for example, the delay adjustment circuit DLY adjusts the delay amount so that the delay variation of the feedback clock CKFB is less than one cycle of the output clock CKO. To do. For this reason, even when a back bias voltage is applied to the frequency divider DIV, the PLL circuit can suppress an increase in jitter of the output clock CKO.

  FIG. 2 shows an example of the phase comparator PFD shown in FIG. The phase comparator PFD includes, for example, flip-flops DFF10, DFF11, DFF12, and an AND circuit AND10. The flip-flops DFF10 to DFF12 are, for example, D-type flip-flop circuits that operate in synchronization with a clock received at a clock terminal. The flip-flops DFF10 to DFF12 reset the signal at the output terminal Q when the signal received at the reset terminal RST is asserted. For example, each reset terminal RST of the flip-flops DFF10 to DFF12 is connected to the output of the AND circuit AND10.

  The input terminal D of the flip-flop DFF10 is connected to the analog power supply AVD, and the output terminal Q of the flip-flop DFF10 is connected to the input of the AND circuit AND10. For example, the flip-flop DFF10 receives the voltage (high level voltage) of the analog power supply AVD at the input terminal D, and receives the input clock CKI at the clock terminal. Then, the flip-flop DFF10 outputs the up signal UP from the output terminal Q in synchronization with the input clock CKI.

  The input terminal D of the flip-flop DFF11 is connected to the analog power supply AVD, and the output terminal Q of the flip-flop DFF11 is connected to the input terminal D of the flip-flop DFF12. For example, the flip-flop DFF11 receives the voltage (high level voltage) of the analog power supply AVD at the input terminal D, and receives the feedback clock CKFB at the clock terminal. The flip-flop DFF11 outputs the signal CKFB2 from the output terminal Q in synchronization with the feedback clock CKFB.

  The output terminal Q of the flip-flop DFF12 is connected to the input of the AND circuit AND10. For example, the flip-flop DFF12 receives the signal CKFB2 at the input terminal D and the output clock CKO at the clock terminal. Then, the flip-flop DFF12 outputs the down signal DN from the output terminal Q in synchronization with the output clock CKO.

  The AND circuit AND10 calculates a logical product of the up signal UP and the down signal DN, and outputs the calculation result to each reset terminal RST of the flip-flops DFF10 to DFF12. That is, the AND circuit AND10 outputs a high level signal to each reset terminal RST of the flip-flops DFF10 to DFF12 when both the up signal UP and the down signal DN become high level. As a result, the signals at the output terminals Q of the flip-flops DFF10 to DFF12 are reset to a low level. Note that the configuration of the phase comparator PFD is not limited to this example.

  FIG. 3 shows an example of the delay adjustment circuit DLY shown in FIG. The delay adjustment circuit DLY includes a delay detection unit DDET, a variable delay unit VDLY, and a selector SEL10. The delay detection unit DDET receives the control signal EN, the output clock CKO, and the feedback clock CKFB, and outputs an increase signal INC and a decrease signal DEC to the variable delay unit VDLY. For example, the delay detection unit DDET detects the delay amount of the feedback clock CKFB with respect to a clock (for example, the clock CKOD shown in FIG. 4) obtained by delaying the output clock CKO by a predetermined amount (for example, about one half of one cycle of the output clock CKO). To do. Then, the delay detection unit DDET generates an increase signal INC and a decrease signal DEC based on the detected delay amount.

  The variable delay unit VDLY receives the control signal STR, the increase signal INC, the decrease signal DEC, and the divided clock CKDIV, and outputs a clock CKDL obtained by delaying the divided clock CKDIV to the terminal I1 of the selector SEL10. For example, the variable delay unit VDLY delays the divided clock CKDIV based on the increase signal INC and the decrease signal DEC, and generates the clock CKDL.

  The selector SEL10 receives the divided clock CKDIV, the clock CKDL, and the control signal EN, and outputs a feedback clock CKFB. For example, when the control signal EN is at a high level, the selector SEL10 outputs the clock CKDL received at the terminal I1 as the feedback clock CKFB. For example, when the control signal EN is at a low level, the selector SEL10 outputs the divided clock CKDIV received at the terminal I0 as the feedback clock CKFB.

  That is, when the control signal EN is negated, the delay adjustment circuit DLY outputs the divided clock CKDIV received from the frequency divider DIV to the phase comparator PFD as the feedback clock CKFB. Note that the configuration of the delay adjustment circuit DLY is not limited to this example.

  FIG. 4 shows an example of the delay detection unit DDET shown in FIG. In FIG. 4 and subsequent figures, the output clock CKO, the feedback clock CKFB, the control signal EN, the increase signal INC, and the decrease signal DEC are also referred to as signals CKO, CKFB, EN, INC, and DEC, respectively.

  The delay detection unit DDET includes a delay element DE10, inverters INV10-INV14, a negative logical product circuit NAND10-NAND17, and a negative logical sum circuit NOR10, NOR11. The delay element DE10 receives the output clock CKO and outputs a clock CKOD (hereinafter also referred to as a signal CKOD) obtained by delaying the output clock CKO to the inverters INV11, INV13, INV14, and the NAND circuits NAND10, NAND16. For example, the delay amount of the delay element DE10 (the delay amount of the clock CKOD with respect to the output clock CKO) is set to about half of one cycle of the output clock CKO.

  The NAND circuit NAND10 receives the control signal EN, the clock CKOD, and the signal I2 that is the output of the NAND circuit NAND11. Then, the NAND circuit NAND10 outputs a signal I1 indicating the result of the NAND of the signals EN, CKOD, and I2 to the NAND circuit NAND11.

  The NAND circuit NAND11 receives the control signal EN, the signal I1, the feedback clock CKFB, and the signal D2 that is the output of the NAND circuit NAND15. Then, the NAND circuit NAND11 outputs a signal I2 indicating the result of NAND of the signals EN, I1, CKFB, and D2 to the NAND circuit NAND10, NAND15, and the NOR circuit NOR10.

  The inverter INV11 outputs an inverted signal of the signal CKOD to the NAND circuit NAND12. The NAND circuit NAND12 receives the control signal EN, the inverted signal of the signal CKOD, and the signal I4 that is the output of the NAND circuit NAND13. Then, the NAND circuit NAND12 outputs a signal I3 indicating the result of the NAND operation of the signal EN, the inverted signal of the signal CKOD, and the signal I4 to the NAND circuit NAND13.

  The NAND circuit NAND13 receives the control signal EN, the signal I3, and the feedback clock CKFB. Then, the NAND circuit NAND13 outputs a signal I4 indicating the result of NAND of the signals EN, I3, and CKFB to the inverter INV12 and the NAND circuit NAND12.

  The inverter INV12 outputs an inverted signal of the signal I4 to the NOR circuit NOR10. The inverter INV10 receives the control signal EN and outputs an inverted signal of the control signal EN to the negative OR circuit NOR10. The NOR circuit NOR10 receives the inverted signal of the control signal EN, the signal I2, and the inverted signal of the signal I4. Then, the negative OR circuit NOR10 calculates the negative logical sum of the inverted signal of the control signal EN, the signal I2, and the inverted signal of the signal I4, and outputs the calculation result as an increase signal INC.

  The inverter INV13 outputs an inverted signal of the signal CKOD to the NAND circuit NAND14. The NAND circuit NAND14 receives the control signal EN, the inverted signal of the signal CKOD, and the signal D2 that is the output of the NAND circuit NAND15. Then, the NAND circuit NAND14 outputs a signal D1 indicating the result of the NAND operation of the signal EN, the inverted signal of the signal CKOD, and the signal D2 to the NAND circuit NAND15.

  The NAND circuit NAND15 receives the control signal EN, the signal D1, the feedback clock CKFB, and the signal I2 that is the output of the NAND circuit NAND11. Then, the NAND circuit NAND15 outputs a signal D2 indicating the result of NAND of the signals EN, D1, CKFB, and I2 to the NAND circuit NAND11, NAND14, and the NOR circuit NOR11.

  The NAND circuit NAND16 receives the control signal EN, the signal CKOD, and the signal D4 that is the output of the NAND circuit NAND17. Then, the negative logical product circuit NAND16 outputs a signal D3 indicating the result of the negative logical product of the signals EN, CKOD, and D4 to the negative logical product circuit NAND17.

  The NAND circuit NAND17 receives the control signal EN, the signal D3, and the feedback clock CKFB. Then, the NAND circuit NAND17 outputs a signal D4 indicating the result of NAND of the signals EN, D3 and CKFB to the NOR circuit NOR11 and the NAND circuit NAND16.

  The inverter INV14 outputs an inverted signal of the signal CKOD to the negative OR circuit NOR11. The NOR circuit NOR11 receives the signal D2, the inverted signal of the signal CKOD, and the signal D4. Then, the negative OR circuit NOR11 calculates a negative logical sum of the signal D2, the inverted signal of the signal CKOD, and the signal D4, and outputs the calculation result as a decrease signal DEC. Note that the configuration of the delay detection unit DDET is not limited to this example.

  FIG. 5 shows an example of the variable delay unit VDLY shown in FIG. The variable delay unit VDLY includes, for example, current sources IS1, IS2, switches SW1, SW2, SW3, SW4, resistors R1, R2, a capacitor C1, and a voltage control delay element VCD.

  Current source IS1, switch SW1, switch SW2, and current source IS2 are connected in series between analog power supply AVD and analog power supply AVS. The switch SW1 is controlled to be turned on / off based on, for example, an increase signal INC received at the control terminal. The switch SW2 is controlled to be turned on / off based on a decrease signal DEC received at the control terminal, for example.

  The resistor R1, the switch SW3, the switch SW4, and the resistor R2 are connected in series between the analog power supply AVD and the analog power supply AVS. The switches SW3 and SW4 are controlled to be turned on / off based on a control signal STR received at the control terminal, for example.

  The capacitor C1 is arranged between a node DCNT, which is a connection node between the switch SW1 and the switch SW2, and the analog power supply AVS. For example, the two terminals of the capacitor C1 are connected to the node DCNT and the analog power supply AVS, respectively. Further, the node DCNT is connected to a connection node between the switch SW3 and the switch SW4 and the control terminal PN3 of the voltage control delay element VCD.

  The voltage control delay element VCD receives the divided clock CKDIV at the terminal PN1, and outputs the clock CKDL obtained by delaying the divided clock CKDIV from the terminal PN4. The terminal PN2 of the voltage control delay element VCD is connected to the analog power supply AVS. For example, the delay amount of the voltage control delay element VCD increases as the voltage of the node DCNT connected to the control terminal PN3 increases.

  For example, the voltage controlled delay element VCD has a variable resistor RV1 and a capacitor C2 connected in series between the terminals PN1 and PN2. For example, the resistance value of the variable resistor RV1 changes according to the voltage of the node DCNT connected to the control terminal PN3. A connection node between the variable resistor RV1 and the capacitor C2 is connected to the terminal PN4.

  Here, for example, in a period in which the control signal STR is at a high level, the switches SW3 and SW4 are in an on state (conductive state). For this reason, during a period when the control signal STR is at a high level, the voltage of the node DCNT is set to a voltage corresponding to the resistance division by the resistors R1 and R2. Further, for example, during the period in which the increase signal INC is at a high level, the switch SW1 is in an on state (conductive state). For this reason, during a period in which the increase signal INC is at a high level, the current source IS1 charges the capacitor C1 via the switch SW1. As a result, the voltage of the node DCNT increases.

  Further, for example, during a period in which the decrease signal DEC is at a high level, the switch SW2 is in an on state (conductive state). For this reason, during a period in which the decrease signal DEC is at a high level, the current source IS2 discharges the capacitor C1 via the switch SW2. As a result, the voltage at the node DCNT decreases.

  Thus, the delay amount of the voltage control delay element VCD is adjusted by the increase signal INC and the decrease signal DEC. For example, the delay amount of the voltage control delay element VCD is adjusted so that the rising edge of the feedback clock CKFB matches the rising edge of the clock CKOD. Thereby, for example, when the delay amount of the clock CKOD with respect to the output clock CKO is about a half cycle of the output clock CKO, the phase comparator PFD detects the rising edge of the output clock CKO next to the rising edge of the feedback clock CKFB. False detection can be reduced. Note that the configuration of the variable delay unit VDLY is not limited to this example.

  FIG. 6 shows an example of the operation of the phase comparator PFD shown in FIG. First, an operation when the rising edge of the input clock CKI is earlier than the rising edge of the feedback clock CKFB will be described.

  As the input clock CKI rises, the up signal UP changes to a high level ((a) in FIG. 6). As the feedback clock CKFB rises, the signal CKFB2 changes to a high level ((b) in FIG. 6). Then, when the output clock CKO rises while the signal CKFB2 is maintained at a high level, the down signal DN changes to a high level ((c) in FIG. 6). Since both the up signal UP and the down signal DN are at a high level, the output of the AND circuit AND10 (reset terminals RST of the flip-flops DFF10 to DFF12) changes to a high level. As a result, the flip-flops DFF10 to DFF12 are reset, and the signal CKFB2, the up signal UP, and the down signal DN change to a low level ((d) in FIG. 6).

  Next, an operation when the rising edge of the input clock CKI is later than the rising edge of the feedback clock CKFB will be described.

  As the feedback clock CKFB rises, the signal CKFB2 changes to a high level ((e) in FIG. 6). When the output clock CKO rises while the signal CKFB2 is maintained at a high level, the down signal DN changes to a high level ((f) in FIG. 6). Then, when the input clock CKI rises, the up signal UP changes to a high level ((g) in FIG. 6). Since both the up signal UP and the down signal DN are at a high level, the output of the AND circuit AND10 (reset terminals RST of the flip-flops DFF10 to DFF12) changes to a high level. As a result, the flip-flops DFF10 to DFF12 are reset, and the signal CKFB2, the up signal UP, and the down signal DN change to a low level ((e) in FIG. 6).

  As described above, the phase comparator PFD detects the output clock CKO at the timing based on the feedback clock CKFB (in the example of FIG. 6, the first rising edge of the output clock CKO after the feedback clock CKFB rises is detected. ) Thereby, the phase comparator PFD can perform phase comparison between the input clock CKI and the output clock CKO.

  Note that the PLL circuit operates so as to align the phases of the input clock CKI and the output clock CKO even when the feedback clock CKFB includes jitter due to delay variation. Therefore, in this embodiment, it is possible to suppress an increase in the phase difference (phase jitter) between the input clock CKI and the output clock CKO even when the feedback clock CKFB includes jitter due to delay variation. For example, in a PLL circuit that operates so as to align the phases of the input clock CKI and the feedback clock CKFB, the phase jitter increases if the feedback clock CKFB includes jitter due to delay variation.

  In addition, in the phase comparator that does not use the feedback clock CKFB to detect the output clock CKO, there are a plurality of rising edges of the output clock CKO in one cycle of the input clock CKI, so the phase comparison between the input clock CKI and the output clock CKO is performed. It is difficult to do. In contrast, in the example of FIG. 6, the phase comparator PFD compares the rising edge of the first output clock CKO with the rising edge of the input clock CKI after the feedback clock CKFB rises. Therefore, the phase comparator PFD can perform phase comparison between the input clock CKI and the output clock CKO.

  FIG. 7 shows an example of the operation of the delay detection unit DDET shown in FIG. The delay time TD1 in FIG. 7 corresponds to the delay time of the delay element DE10 shown in FIG.

  When the rising edge of the feedback clock CKFB is earlier than the rising edge of the clock CKOD, the increase signal INC is maintained at a high level for the time T10 from the rising edge of the feedback clock CKFB to the rising edge of the clock CKOD. When the rising edge of the feedback clock CKFB is later than the rising edge of the clock CKOD, the time T20 corresponding to the time T21 from the rising edge of the clock CKOD to the rising edge of the feedback clock CKFB and the decrease signal DEC are maintained at a high level. .

  For example, the signal I2 (output of the NAND circuit NAND11) and the signal D2 (output of the NAND circuit NAND15) are signals that detect whether the rising edge of the clock CKOD is later or earlier than the rising edge of the feedback clock CKFB. . For example, the signals I2 and D2 are maintained at a high level during a period when the feedback clock CKFB is at a low level.

  For example, when the feedback clock CKFB rises and the clock CKOD is at a low level, the signal I2 changes to a low level ((a) in FIG. 7). When the signal I2 is at a low level, the increase signal INC is maintained at a high level for a time T10 from the rising edge of the feedback clock CKFB to the rising edge of the clock CKOD ((b) in FIG. 7).

  On the other hand, when the clock CKOD is at a high level when the feedback clock CKFB rises, the signal D2 changes to a low level ((c) in FIG. 7). When the signal D2 is at a low level, the decrease signal DEC is maintained at a high level for a time T20 from the rising edge of the clock CKOD to the falling edge of the feedback clock CKFB ((d) in FIG. 7).

  When the pulse width (high-level period) of the divided clock CKDIV is equal to or substantially equal to one period of the output clock CKO, the pulse width (high-level period) of the feedback clock CKFB is equal to one period of the clock CKOD. Or nearly equal. In this case, the time T20 from the rising edge of the clock CKOD to the falling edge of the feedback clock CKFB is equal to or substantially equal to the time T21 from the rising edge of the clock CKOD to the rising edge of the feedback clock CKFB.

  FIG. 8 shows an example of the operation of the variable delay unit VDLY shown in FIG. The DCNT voltage in FIG. 8 indicates the voltage of the node DCNT (control terminal PN3 of the voltage control delay element VCD) shown in FIG. Further, the delay time between CKDIV and CKDL in FIG. 8 indicates the delay time of the clock CKDL with respect to the divided clock CKDIV. Note that the delay time of the clock CKDL with respect to the divided clock CKDIV corresponds to, for example, the delay time of the feedback clock CKFB with respect to the divided clock CKDIV when the control signal EN is at a high level.

  First, the control signal STR is maintained at a high level for a time T30 (for example, a time equal to or approximately equal to one period of the input clock CKI). As a result, the switches SW3 and SW4 are turned on (conductive state), and the voltage of the node DCNT increases. For example, the voltage of the node DCNT rises to a voltage corresponding to resistance division by the resistors R1 and R2 (hereinafter also referred to as initial voltage). The delay in the voltage controlled delay element VCD (the delay time of the clock CKDL with respect to the divided clock CKDIV) increases as the voltage of the node DCNT increases. For this reason, the delay time of the clock CKDL with respect to the divided clock CKDIV increases to a delay amount corresponding to the initial voltage. Thereby, the initial value of the voltage controlled delay element VCD is set.

  After the initial value of the voltage control delay element VCD is set, the control signal STR is maintained at a low level, so that the switches SW3 and SW4 are maintained in the off state (non-conduction state). For this reason, the voltage of the node DCNT increases or decreases according to the levels of the increase signal INC and the decrease signal DEC.

  For example, in the period T31 in which the increase signal INC is low and the decrease signal DEC is high, the switch SW1 is maintained in the off state (non-conduction state), and the switch SW2 is maintained in the on state (conduction state). The voltage at node DCNT falls. For this reason, the delay time of the clock CKDL with respect to the divided clock CKDIV decreases. Further, for example, in the period T32 in which the decrease signal DEC is at a low level and the increase signal INC is at a high level, the switch SW2 is maintained in an off state (non-conduction state), and the switch SW1 is maintained in an on state (conduction state). Therefore, the voltage at the node DCNT increases. For this reason, the delay time of the clock CKDL with respect to the divided clock CKDIV increases.

  Note that the amount of change in the delay of the voltage control delay element VCD is set to be, for example, about the same as or slightly larger than the time during which the increase signal INC and the decrease signal DEC are at a high level. For example, if the amount of change in the delay of the voltage control delay element VCD is too large compared to the time when the increase signal INC or the decrease signal DEC is at a high level, the clock CKDL is shifted by one cycle of the output clock CKO, and the PLL circuit malfunctions. There is a risk. Alternatively, when the amount of change in the delay of the voltage control delay element VCD is smaller than the time during which the increase signal INC and the decrease signal DEC are at a high level, the adjustment of the delay amount by the voltage control delay element VCD is performed by the divided clock CKDIV. There is a possibility that the delay variation cannot be followed.

  For this reason, the voltage controlled delay element VCD has, for example, a delay change amount (adjustment amount) of about 1 to 1.5 times the high level time of the increase signal INC or the decrease signal DEC due to the increase signal INC or the decrease signal DEC. Designed to be

  FIG. 9 shows an example of the operation of the PLL circuit shown in FIG. Times TD2, TD3, TD4, and TD5 in FIG. 9 indicate the delay time of the frequency divider DIV (the delay time between the output clock CKO and the frequency-divided clock CKDIV). A time TD10 indicates a delay time between the output clock CKO and the input clock CKI.

  First, in the period T100, the reset signal SRST changes to a high level while the control signals EN and STR are maintained at a low level. As a result, the PLL circuit is activated. Since the control signals EN and STR are maintained at a low level, the delay adjustment circuit DLY is not operating. For example, the divided clock CKDIV is transmitted to the phase comparator PFD as the feedback clock CKFB.

  For example, the phase comparator PFD detects the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB. At the start of the operation of the PLL circuit, the frequency of the output clock CKO is low. Therefore, even when the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB is compared with the rising edge of the input clock CKI from the start of the operation of the PLL circuit, the possibility that the PLL circuit malfunctions is low. For example, it is unlikely that the phase comparator PFD erroneously detects the rising edge adjacent to the rising edge to be detected among the rising edges of the output clock CKO.

  In the period T200, the operation of the delay adjustment circuit DLY starts after the PLL circuit locks up (after the output clock CKO is synchronized with the input clock CKI). For example, the control signal STR is set to a high level for a predetermined time (for example, a time equal to or approximately equal to one cycle of the input clock CKI) when a time period sufficient to lock up the PLL circuit has elapsed since the PLL circuit started. Maintained. Thereby, the initial value of the voltage control delay element VCD (the initial voltage of the node DCNT) is set. Further, after the initial value of the voltage control delay element VCD is set, the control signal EN changes to a high level. As a result, the delay detection unit DDET is activated.

  Note that the clock CKDL shown in FIG. 5 is delayed with respect to the divided clock CKDIV during a period in which the control signal STR is at a high level, but the clock CKDL is selected as the feedback clock CKFB because the control signal EN is at a low level. It has not been. For example, the delay adjustment circuit DLY selects the divided clock CKDIV as the feedback clock CKFB.

  In the periods T300 and T400, since the control signal STR is maintained at a low level and the control signal EN is maintained at a high level, the delay adjustment circuit DLY includes an increase signal INC and a decrease signal as illustrated in FIG. The delay amount is adjusted based on DEC. For example, the delay adjustment circuit DLY is arranged between the frequency-divided clock CKDIV and the feedback clock CKFB so that the rising edge of the clock CKOD and the rising edge of the feedback clock CKFB are aligned (portion surrounded by a dashed ellipse in FIG. 9). Adjust the delay time.

  With the rising edge of the clock CKOD and the rising edge of the feedback clock CKFB aligned or substantially aligned, the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB is compared with the rising edge of the input clock CKI. The PLL circuit operates so that the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB is aligned with the rising edge of the input clock CKI.

  Thus, the delay time TD10 between the output clock CKO and the input clock CKI is maintained at a constant or substantially constant delay amount even when a delay variation occurs in the frequency divider DIV. For example, the delay time TD5 of the frequency divider DIV in the period T400 is smaller than the delay time TD4 of the frequency divider DIV in the period T300. Even in this case, the delay time TD10 of the period T400 is adjusted to the same or substantially the same delay amount as the delay time TD10 of the period T300.

  In this manner, the PLL circuit can suppress an increase in jitter of the output clock even when delay variation occurs in the frequency divider DIV. In this embodiment, since the phase of the feedback clock CKFB is not directly compared with the phase of the input clock CKI, the delay adjustment accuracy by the delay adjustment circuit DLY may be low.

  FIG. 10 shows another example of the delay detection unit DDET shown in FIG. In the delay detection unit DDET shown in FIG. 10, the delay element DE10 and the inverters INV11, INV13, and INV14 are deleted from the delay detection unit DDET shown in FIG. 4, and the inverters INV15 and INV16 are added to the delay detection unit DDET shown in FIG. Have been added. Other configurations of the delay detection unit DDET illustrated in FIG. 10 are the same as or similar to the delay detection unit DDET illustrated in FIG. The same or similar elements as those described in FIG. 4 are denoted by the same or similar reference numerals, and detailed description thereof will be omitted.

  The delay detection unit DDET includes inverters INV10, INV12, INV15, INV16, a negative logical product circuit NAND10-NAND17, and a negative logical sum circuit NOR10, NOR11. The inverter INV15 receives the output clock CKO and outputs an inverted signal of the output clock CKO to the NAND circuit NAND10. For example, when the duty ratio of the output clock CKO is 50%, the output of the inverter INV15 corresponds to a clock obtained by delaying the output clock CKO by about a half cycle of the output clock CKO.

  The NAND circuit NAND10 receives the control signal EN, the inverted signal of the output clock CKO, and the signal I2. Then, the NAND circuit NAND10 outputs to the NAND circuit NAND11 a signal I1 indicating the result of the NAND operation of the signal EN, the inverted signal of the output clock CKO, and the signal I2.

  The NAND circuit NAND12 receives the control signal EN, the output clock CKO, and the signal I4. Then, the negative logical product circuit NAND12 outputs a signal I3 indicating the result of the negative logical product of the signals EN, CKO, and I4 to the negative logical product circuit NAND13.

  The NAND circuit NAND14 receives the control signal EN, the output clock CKO, and the signal D2. Then, the NAND circuit NAND14 outputs a signal D1 indicating the result of NAND of the signals EN, CKO, and D2 to the NAND circuit NAND15.

  The inverter INV16 receives the output clock CKO, and outputs an inverted signal of the output clock CKO to the NAND circuit NAND16. The NAND circuit NAND16 receives the control signal EN, the inverted signal of the output clock CKO, and the signal D4. Then, the NAND circuit NAND16 outputs a signal D3 indicating the result of the NAND operation of the signal EN, the inverted signal of the output clock CKO, and the signal D4 to the NAND circuit NAND17.

  The NOR circuit NOR11 receives the signal D2, the output clock CKO, and the signal D4. Then, the negative OR circuit NOR11 calculates the negative logical sum of the signals D2, CKO, and D4 and outputs the calculation result as a decrease signal DEC. In the delay detection unit DDET of FIG. 10, the delay element DE10 is omitted from the delay detection unit DDET of FIG. 4, so that the circuit design is compared with the case where the delay time of the delay element DE10 varies depending on the sample and operating conditions. Easy to do. Further, in the delay detection unit DDET of FIG. 10, the delay element DE10 and the like are omitted from the delay detection unit DDET of FIG. 4, so that the circuit scale (number of elements) of the delay detection unit DDET can be reduced. Note that the configuration of the delay detection unit DDET is not limited to this example.

  FIG. 11 shows an example of the operation of the delay detection unit DDET shown in FIG. When the rising edge of the feedback clock CKFB is earlier than the falling edge of the output clock CKO, the time T12 from the rising edge of the feedback clock CKFB to the falling edge of the output clock CKO, the increase signal INC is maintained at a high level. When the rising edge of the feedback clock CKFB is later than the falling edge of the output clock CKO, the time T22 corresponding to the time T23 from the falling edge of the output clock CKO to the rising edge of the feedback clock CKFB, the decrease signal DEC is at a high level. Maintained.

  For example, the signal I2 (output of the NAND circuit NAND11) and the signal D2 (output of the NAND circuit NAND15) detect whether the falling edge of the output clock CKO is later or earlier than the rising edge of the feedback clock CKFB. It is. For example, the signals I2 and D2 are maintained at a high level during a period when the feedback clock CKFB is at a low level.

  For example, when the feedback clock CKFB rises and the output clock CKO is at a high level, the signal I2 changes to a low level ((a) in FIG. 11). When the signal I2 is at the low level, the increase signal INC is maintained at the high level during the time T12 from the rising edge of the feedback clock CKFB to the falling edge of the output clock CKO ((b) in FIG. 11).

  On the other hand, when the output clock CKO is at a low level when the feedback clock CKFB rises, the signal D2 changes to a low level ((c) in FIG. 11). When the signal D2 is at a low level, the decrease signal DEC is maintained at a high level for a time T22 from the falling edge of the output clock CKO to the falling edge of the feedback clock CKFB ((d) in FIG. 11).

  When the pulse width (high level period) of the divided clock CKDIV is equal to or approximately equal to one cycle of the output clock CKO, the time T22 is equal to or approximately equal to the time T23. That is, the time T22 from the falling edge of the output clock CKO to the falling edge of the feedback clock CKFB is equal to or substantially equal to the time T23 from the falling edge of the output clock CKO to the rising edge of the feedback clock CKFB.

  FIG. 12 shows an example of the operation of the PLL circuit including the delay detection unit DDET shown in FIG. The meanings of times TD2, TD3, TD4, TD5, and TD10 in FIG. 12 are the same as or similar to those in FIG. Detailed description of the same or similar operations as those described in FIG. 9 is omitted.

  For example, the delay adjustment circuit DLY includes the divided clock CKDIV and the feedback clock CKFB so that the falling edge of the output clock CKO and the rising edge of the feedback clock CKFB are aligned (portion surrounded by a dashed ellipse in FIG. 12). Adjust the delay time between. Other operations are the same as or similar to the operations in FIG.

  For example, the operations in the periods T100 and T200 in which the control signal EN is maintained at the low level are the same as or similar to the operations in the periods T100 and T200 in FIG.

  In the periods T300 and T400, since the control signal STR is maintained at a low level and the control signal EN is maintained at a high level, the delay adjustment circuit DLY includes an increase signal INC and a decrease signal as illustrated in FIG. The delay amount is adjusted based on DEC. For example, the delay adjustment circuit DLY is configured so that the falling edge of the output clock CKO and the rising edge of the feedback clock CKFB are aligned (portion surrounded by a broken line ellipse in FIG. 9) and the divided clock CKDIV and the feedback clock CKFB. Adjust the delay time between.

  With the falling edge of the output clock CKO and the rising edge of the feedback clock CKFB aligned or nearly aligned, the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB is compared with the rising edge of the input clock CKI. The The PLL circuit operates so that the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB is aligned with the rising edge of the input clock CKI.

  Thus, the delay time TD10 between the output clock CKO and the input clock CKI is maintained at a constant or substantially constant delay amount even when a delay variation occurs in the frequency divider DIV. In this manner, the PLL circuit can suppress an increase in jitter of the output clock even when delay variation occurs in the frequency divider DIV. In this embodiment, since the phase of the feedback clock CKFB is not directly compared with the phase of the input clock CKI, the delay adjustment accuracy by the delay adjustment circuit DLY may be low.

  As described above, in the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. 1 to 12, the PLL circuit includes the clock generation unit CGEN, the frequency divider DIV, the delay adjustment circuit DLY, and the phase comparator PFD. Have. For example, the clock generation unit CGEN generates an output clock CKO having a frequency corresponding to a control voltage adjusted by a control signal such as an up signal UP or a down signal DN. The frequency divider DIV divides the output clock CKO to generate a divided clock CKDIV. The delay adjustment circuit DLY adjusts the delay amount of the divided clock CKDIV to generate the feedback clock CKFB. The phase comparator PFD detects the phase difference between the output clock CKO detected at the timing based on the feedback clock CKFB and the input clock CKI. Then, the phase comparator PFD generates a control signal according to the phase difference.

  For example, the phase comparator PFD detects the phase difference between the input clock CKI and the output clock CKO by comparing the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB with the rising edge of the input clock CKI. To do. Thus, in this embodiment, since the phase difference between the output clock CKO and the input clock CKI is detected, the influence of delay variation of the feedback clock CKFB can be reduced. For example, in this embodiment, it is possible to suppress an increase in jitter of the output clock CKO even when delay variation occurs in the feedback path (frequency divider DIV). That is, in this embodiment, the jitter of the output clock of the PLL circuit can be reduced.

  In this embodiment, since the influence of delay variation of the frequency divider DIV can be reduced, the back bias voltage of the P-type MOS transistor and the back bias voltage of the N-type MOS transistor can be applied to the frequency divider DIV. Thereby, in this embodiment, the leakage current of the frequency divider DIV can be reduced, and the power consumption can be reduced. In this embodiment, the logic circuit to which the back bias voltage is applied and the frequency divider DIV do not have to be separated from each other in power supply, so that the configuration of the power supply system can be prevented from becoming complicated. Thus, in this embodiment, both low power consumption and low jitter can be realized.

  FIG. 13 shows another embodiment of the PLL circuit and the semiconductor integrated circuit. The PLL circuit of this embodiment has a phase comparator PFD2 instead of the phase comparator PFD shown in FIG. The other configuration of the PLL circuit shown in FIG. 13 is the same as or similar to that of the PLL circuit shown in FIG.

  Further, the semiconductor integrated circuit SEM of this embodiment is the same as the semiconductor integrated circuit SEM shown in FIG. 1 except that it has the PLL circuit shown in FIG. 13 instead of the PLL circuit shown in FIG. Or the same. Elements that are the same as or similar to those described in FIGS. 1 to 12 are given the same or similar reference numerals, and detailed descriptions thereof are omitted. The meanings of the symbols PLLa and PLLd in FIG. 13 are the same as or similar to those in FIG. For example, power for the phase comparator PFD2, the clock generation unit CGEN, and the delay adjustment circuit DLY is supplied from analog power supplies AVD and AVS. Further, for example, the power source of the frequency divider DIV is supplied from the digital power sources VDD and VSS.

  The PLL circuit includes, for example, a phase comparator PFD2, a clock generation unit CGEN, a frequency divider DIV, and a delay adjustment circuit DLY. The phase comparator PFD2 is an example of a phase comparator that detects a phase difference between the output clock CKO detected at the timing based on the feedback clock CKFB and the input clock CKI. For example, the phase comparator PFD2 includes control signals EN and STR, a reset signal SRST, an input clock CKI, an output clock CKO output from the clock generation unit CGEN, and a feedback clock CKFB output from the delay adjustment circuit DLY. Receive. Then, the phase comparator PFD2 outputs the up signal UP and the down signal DN to the clock generation unit CGEN.

  For example, during a period when the control signal EN is at a high level, the phase comparator PFD2 generates the up signal UP and the down signal DN based on the phase difference between the input clock CKI and the output clock CKO. That is, the operation of the phase comparator PFD2 when the control signal EN is at a high level is the same as or similar to the phase comparator PFD shown in FIG. Thus, since the phase comparator PFD2 detects the phase difference between the output clock CKO and the input clock CKI, it is possible to reduce the influence of delay variation of the feedback clock CKFB. For example, the PLL circuit can suppress an increase in jitter of the output clock CKO even when delay variation occurs in the feedback path (frequency divider DIV).

  Further, for example, during the period when the control signal EN is at a low level, the phase comparator PFD2 generates the up signal UP and the down signal DN based on the phase difference between the input clock CKI and the feedback clock CKFB. Before the PLL circuit locks up, the control signal EN is maintained at a low level. Therefore, the PLL circuit detects the phase difference between the input clock CKI and the feedback clock CKFB in the lockup process. Therefore, the PLL circuit can lock up normally even when the frequency of the output clock CKO in the lockup process temporarily becomes higher than a predetermined frequency (for example, the frequency after lockup).

  The clock generation unit CGEN, the frequency divider DIV, and the delay adjustment circuit DLY are the same as or similar to the clock generation unit CGEN, the frequency divider DIV, and the delay adjustment circuit DLY shown in FIG. For example, the delay detection unit DDET of the delay adjustment circuit DLY may be the delay detection unit DDET illustrated in FIG. 4 or the delay detection unit DDET illustrated in FIG. Note that the configurations of the PLL circuit and the semiconductor integrated circuit are not limited to this example. For example, the phase comparator PFD2 may receive only the control signal EN among the control signals EN and STR.

  FIG. 14 shows an example of the phase comparator PFD2 shown in FIG. In the phase comparator PFD2, selectors SEL20 and SEL21 are added to the phase comparator PFD shown in FIG. The other configuration of the phase comparator PFD2 is the same as or similar to that of the phase comparator PFD shown in FIG. The same or similar elements as those described in FIG. 2 are denoted by the same or similar reference numerals, and detailed description thereof will be omitted.

  The output terminal Q of the flip-flop DFF10 is connected to the terminal I1 of the selector SEL20. The terminal I0 and the control terminal of the selector SEL20 are connected to the analog power supply AVD. Therefore, selector SEL20 outputs signal SUP (output of flip-flop DFF10) received at terminal I1 as up signal UP to AND circuit AND10 and charge pump circuit CP shown in FIG. The selector SEL20 is provided, for example, to adjust the timing of the up signal UP and the down signal DN.

  The output terminal Q of the flip-flop DFF11 is connected to the input terminal D of the flip-flop DFF12 and the terminal I0 of the selector SEL21. The terminal I1 of the selector SEL21 is connected to the output terminal Q of the flip-flop DFF12. The selector SEL21 receives the control signal EN at the control terminal.

  For example, when the control signal EN is at a high level, the selector SEL21 sets the signal SDN (output of the flip-flop DFF12) received at the terminal I1 as the down signal DN to the AND circuit AND10 and the charge pump circuit CP shown in FIG. Output. Further, for example, when the control signal EN is at a low level, the selector SEL21 uses the signal CKFB2 (output of the flip-flop DFF11) received at the terminal I0 as the down signal DN, and the AND circuit AND10 and the charge pump circuit shown in FIG. Output to CP. The configuration of the phase comparator PFD2 is not limited to this example.

  FIG. 15 shows an example of the operation of the phase comparator PFD2 shown in FIG. When the control signal EN is at a high level (EN = 1 in FIG. 15), the operation of the phase comparator PFD2 is the same as or similar to the operation of the phase comparator PFD shown in FIG. Therefore, in FIG. 15, the operation when the control signal EN is at a low level (EN = 0 in FIG. 15) will be described. First, an operation when the rising edge of the input clock CKI is earlier than the rising edge of the feedback clock CKFB will be described.

  When the input clock CKI rises, the up signal UP changes to a high level ((a) in FIG. 15). As the feedback clock CKFB rises, the output (signal CKFB2) of the flip-flop DFF11 changes to a high level. When the control signal EN is at a low level, the output (signal CKFB2) of the flip-flop DFF11 is selected as the down signal DN. Accordingly, when the feedback clock CKFB rises, the down signal DN changes to a high level ((b) in FIG. 15). Since both the up signal UP and the down signal DN are at a high level, the output of the AND circuit AND10 (reset terminals RST of the flip-flops DFF10 to DFF12) changes to a high level. As a result, the flip-flops DFF10 to DFF12 are reset, and the up signal UP and the down signal DN change to a low level ((c) in FIG. 15).

  Next, an operation when the rising edge of the input clock CKI is later than the rising edge of the feedback clock CKFB will be described.

  As the feedback clock CKFB rises, the output (signal CKFB2) of the flip-flop DFF11 changes to a high level. When the control signal EN is at a low level, the output (signal CKFB2) of the flip-flop DFF11 is selected as the down signal DN. Therefore, when the feedback clock CKFB rises, the down signal DN changes to a high level ((d) in FIG. 15). Then, when the input clock CKI rises, the up signal UP changes to a high level ((e) in FIG. 15). Since both the up signal UP and the down signal DN are at a high level, the output of the AND circuit AND10 (reset terminals RST of the flip-flops DFF10 to DFF12) changes to a high level. As a result, the flip-flops DFF10 to DFF12 are reset, and the up signal UP and the down signal DN change to a low level ((f) in FIG. 15).

  Thus, when the control signal EN is at a low level (EN = 0 in FIG. 15), the phase comparator PFD outputs the up signal UP and the down signal DN based on the phase difference between the input clock CKI and the feedback clock CKFB. Generate. When the control signal EN is at a high level (EN = 1 in FIG. 15), the phase comparator PFD generates a phase difference between the input clock CKI and the output clock CKO as in the phase comparator PFD shown in FIG. Based on this, an up signal UP and a down signal DN are generated.

  FIG. 16 shows an example of the operation of the PLL circuit shown in FIG. Note that the delay detection unit DDET of the delay adjustment circuit DLY is, for example, the delay detection unit DDET illustrated in FIG. The meanings of times TD2, TD3, TD4, TD5, and TD10 in FIG. 16 are the same as or similar to those in FIG. Detailed description of the same or similar operations as those described in FIG. 9 is omitted.

  In the period T100, the reset signal SRST changes to a high level while the control signals EN and STR are maintained at a low level. As a result, the PLL circuit is activated. Since the control signals EN and STR are maintained at a low level, the delay adjustment circuit DLY is not operating. For example, the divided clock CKDIV is transmitted to the phase comparator PFD2 as the feedback clock CKFB.

  Further, the phase comparator PFD2 detects the phase difference between the feedback clock CKFB and the input clock CKI, for example, because the control signal EN is maintained at a low level. For example, the phase comparator PFD2 compares the rising edge of the feedback clock CKFB with the rising edge of the input clock CKI. For this reason, for example, even when the frequency of the output clock CKO in the lockup process temporarily becomes higher than the frequency after the lockup, the PLL circuit is normal based on the phase difference between the feedback clock CKFB and the input clock CKI. Can lock up.

  In the period T200, after the PLL circuit locks up, the operation of the delay adjustment circuit DLY starts. For example, the control signal STR is set to a high level for a predetermined time (for example, a time equal to or approximately equal to one cycle of the input clock CKI) when a time period sufficient to lock up the PLL circuit has elapsed since the PLL circuit started. Maintained. Thereby, the initial value of the voltage control delay element VCD (the initial voltage of the node DCNT) is set. Further, after the initial value of the voltage control delay element VCD is set, the control signal EN changes to a high level. As a result, the delay detection unit DDET is activated.

  Further, the operation of the phase comparator PFD2 is switched by the change of the control signal EN to the high level. For example, the operation of the phase comparator PFD2 is an operation of detecting the phase difference between the output clock CKO and the input clock CKI from the operation of detecting the phase difference between the feedback clock CKFB and the input clock CKI (EN = 0 in FIG. 15). (EN = 1 in FIG. 15). Therefore, the operations in the periods T300 and T400 are the same as or similar to the operations in the periods T300 and T400 in FIG.

  FIG. 17 shows another example of the operation of the PLL circuit shown in FIG. Note that the delay detection unit DDET of the delay adjustment circuit DLY is, for example, the delay detection unit DDET illustrated in FIG. The meanings of times TD2, TD3, TD4, TD5, and TD10 in FIG. 16 are the same as or similar to those in FIG. Detailed description of the same or similar operations as those described in FIGS. 9, 12, and 16 is omitted.

  The operations in the periods T100 and T200 are the same as or similar to the operations in the periods T100 and T200 in FIG. 16 because the delay detection unit DDET is not activated. The operations in the periods T300 and T400 are the same as or similar to the operations in the periods T300 and T400 in FIG.

  As described above, the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. 13 to 17 can obtain the same effects as those of the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. . For example, the phase comparator PFD compares the rising edge of the output clock CKO with the rising edge of the input clock CKI immediately after the rising edge of the feedback clock CKFB during the period when the control signal EN is at a high level (after lockup).

  As described above, after the lockup, the PLL circuit detects the phase difference between the output clock CKO and the input clock CKI, so that the influence of the delay variation of the feedback clock CKFB can be reduced. For example, in this embodiment, it is possible to suppress an increase in jitter of the output clock CKO even when delay variation occurs in the feedback path (frequency divider DIV). That is, in this embodiment, the jitter of the output clock of the PLL circuit can be reduced.

  Further, for example, the phase comparator PFD compares the rising edge of the feedback clock CKFB with the rising edge of the input clock CKI during a period when the control signal EN is at a low level (lock-up process). Therefore, the PLL circuit can normally lock up even when the frequency of the output clock CKO in the lockup process temporarily becomes higher than a predetermined frequency (for example, the frequency after the lockup).

  FIG. 18 shows another embodiment of the PLL circuit and the semiconductor integrated circuit. In the PLL circuit of this embodiment, a lock detection circuit LDET and a control circuit CLC are added to the PLL circuit shown in FIG. The other configuration of the PLL circuit shown in FIG. 18 is the same as or similar to that of the PLL circuit shown in FIG.

  The semiconductor integrated circuit SEM of this embodiment is the same as the semiconductor integrated circuit SEM shown in FIG. 1 except that it has the PLL circuit shown in FIG. 18 instead of the PLL circuit shown in FIG. Or the same. The same or similar elements as those described in FIGS. 1 to 17 are denoted by the same or similar reference numerals, and detailed description thereof will be omitted. The meanings of the symbols PLLa and PLLd in FIG. 18 are the same as or similar to those in FIG. For example, the power of the phase comparator PFD, the clock generation unit CGEN, the delay adjustment circuit DLY, the lock detection circuit LDET, and the control circuit CLC is supplied from analog power supplies AVD and AVS. Further, for example, the power source of the frequency divider DIV is supplied from the digital power sources VDD and VSS.

  The PLL circuit includes, for example, a phase comparator PFD, a clock generation unit CGEN, a frequency divider DIV, a delay adjustment circuit DLY, a lock detection circuit LDET, and a control circuit CLC. Phase comparator PFD, clock generation unit CGEN, frequency divider DIV and delay adjustment circuit DLY are the same as or similar to phase comparator PFD, clock generation unit CGEN, frequency divider DIV and delay adjustment circuit DLY shown in FIG. is there.

  The lock detection circuit LDET is an example of a lock detection circuit that determines whether the output clock CKO is in a locked state within a predetermined frequency range based on a control signal. For example, the lock detection circuit LDET receives the reset signal SRST, the up signal UP, and the down signal DN, and outputs the lock signal LSIG to the outside of the PLL circuit and the control circuit CLC.

  For example, when the PLL circuit is activated, the lock detection circuit LDET outputs a low level lock signal LSIG. Then, the lock detection circuit LDET determines whether or not the frequency of the output clock CKO has been locked up to a predetermined value. Note that the fact that the frequency of the output clock CKO is locked up to a predetermined value corresponds to the locked state where the output clock CKO falls within a predetermined frequency range.

  For example, the lock detection circuit LDET determines that the frequency of the output clock CKO has been locked up to a predetermined value when the pulse widths of the up signal UP and the down signal DN have fallen below a predetermined value. The lock detection circuit LDET outputs a high level lock signal LSIG when the frequency of the output clock CKO is locked up to a predetermined value.

  The control circuit CLC is an example of a control circuit that receives a detection result (for example, a high-level lock signal LSIG) indicating a lock state from the lock detection circuit LDET and controls activation of the delay adjustment circuit DLY based on the detection result. For example, the control circuit CLC receives the input clock CKI, the output clock CKO, the reset signal SRST, and the lock signal LSIG, and outputs the control signals EN and STR to the delay adjustment circuit DLY. For example, the control circuit CLC outputs the control signals EN and STR to the delay adjustment circuit DLY in response to the high level lock signal LSIG.

  For example, the control circuit CLC has a pulse width (high level period) equal to or substantially equal to one period of the input clock CKI in synchronization with the falling edge of the input clock CKI immediately after receiving the high level lock signal LSIG. A control signal STR is output. The control circuit CLC changes the control signal EN to a high level in synchronization with the falling edge of the input clock CKI immediately after changing the control signal STR to a high level. Then, the control circuit CLC maintains the control signal EN at a high level.

  Thereby, for example, the control signals EN and STR having the same or similar waveforms as the control signals EN and STR shown in FIG. 9 are output from the control circuit CLC to the delay adjustment circuit DLY. That is, the control circuit CLC activates the delay adjustment circuit DLY using the control signals EN and STR. Since the control circuit CLC operates at the frequency of the input clock CKI, the control circuit CLC can operate with less power than the frequency divider DIV that operates at the frequency of the output clock CKO.

  Here, the operation of the PLL circuit shown in FIG. 18 is the same as that of the PLL circuit shown in FIG. 1 (for example, FIG. 9 and FIG. 12), except that the control signals EN and STR are generated in the PLL circuit. The same or similar operation as shown).

  Note that the configurations of the PLL circuit and the semiconductor integrated circuit SEM are not limited to this example. For example, the PLL circuit may include a phase comparator PFD2 instead of the phase comparator PFD. In this case, for example, the control circuit CLC outputs the control signals EN and STR to the delay adjustment circuit DLY and the phase comparator PFD2. The operation of the PLL circuit having the phase comparator PFD2 instead of the phase comparator PFD is the same as that of the PLL circuit shown in FIG. 13 except that the control signals EN and STR are generated in the PLL circuit (for example, FIG. 16 and the operation shown in FIG.

  FIG. 19 shows an example of the control circuit CLC shown in FIG. For example, the control circuit CLC includes inverters INV20 to INV22, a NOR circuit NOR20, and flip-flops DFF20 and DFF21.

  The inverter INV20 receives the input clock CKI and outputs an inverted signal of the input clock CKI to each clock terminal of the flip-flops DFF20 and DFF21. The inverter INV21 receives the reset signal SRST and outputs an inverted signal of the reset signal SRST to each reset terminal RST of the flip-flops DFF20 and DFF21.

  The flip-flop DFF20 receives the lock signal LSIG at the input terminal D. The output terminal Q of the flip-flop DFF20 is connected to the input terminal D of the flip-flop DFF21 and the input of the inverter INV22. For example, the flip-flop DFF20 outputs the lock signal LSIG received at the input terminal D from the output terminal Q in synchronization with the rising edge of the inverted signal of the input clock CKI.

  Also, for example, the flip-flop DFF21 outputs the signal received at the input terminal D (output of the flip-flop DFF20) from the output terminal Q in synchronization with the rising edge of the inverted signal of the input clock CKI as the control signal EN. Note that the output terminal Q of the flip-flop DFF21 is connected to, for example, the input of the NOR circuit NOR20 and the delay adjustment circuit DLY shown in FIG.

  The inverter INV22 outputs an inverted signal of the signal output from the flip-flop DFF20 to the input of the NOR circuit NOR20. The negative logical sum circuit NOR20 calculates a negative logical sum of the signal received from the inverter INV22 and the control signal EN, and outputs the calculation result to the delay adjustment circuit DLY shown in FIG. 18 as the control signal STR. Note that the configuration of the control circuit CLC is not limited to this example.

  As described above, the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. 18 to 19 can obtain the same effects as those of the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. . For example, the phase comparator PFD detects the phase difference between the output clock CKO and the input clock CKI by comparing the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB with the rising edge of the input clock CKI. .

  Thus, in this embodiment, since the phase difference between the output clock CKO and the input clock CKI is detected, the influence of delay variation of the feedback clock CKFB can be reduced. For example, in this embodiment, it is possible to suppress an increase in jitter of the output clock CKO even when delay variation occurs in the feedback path (frequency divider DIV). That is, in this embodiment, the jitter of the output clock of the PLL circuit can be reduced.

  Further, the PLL circuit includes, for example, a lock detection circuit LDET that determines whether or not the lock state is set, and a control circuit CLC that activates the delay adjustment circuit DLY in response to the lock signal LSIG indicating the lock state. . Thereby, for example, the PLL circuit can detect that the output clock CKO is within a predetermined frequency range and activate the delay adjustment circuit DLY. Further, for example, the PLL circuit can omit a terminal for receiving the control signals EN and STR from the outside of the PLL circuit. Therefore, in this embodiment, the interface of the PLL circuit can be simplified.

  FIG. 20 shows another embodiment of the PLL circuit and the semiconductor integrated circuit. In the PLL circuit of this embodiment, frequency dividers DIV2 and DIV3, delay adjustment circuits DLY2 and DLY3, and a flip-flop DFF30 are added to the PLL circuit shown in FIG. The PLL circuit shown in FIG. 20 includes a phase comparator PFD3 instead of the phase comparator PFD shown in FIG. The other configuration of the PLL circuit shown in FIG. 20 is the same as or similar to that of the PLL circuit shown in FIG.

  Further, the semiconductor integrated circuit SEM of this embodiment is the same as the semiconductor integrated circuit SEM shown in FIG. 1 except that it has the PLL circuit shown in FIG. 20 instead of the PLL circuit shown in FIG. Or the same. Elements that are the same as or similar to those described in FIGS. 1 to 19 are given the same or similar reference numerals, and detailed descriptions thereof are omitted. The meanings of symbols PLLa and PLLd in FIG. 20 are the same as or similar to those in FIG.

  For example, the phase comparator PFD3, clock generator CGEN, frequency divider DIV3, delay adjustment circuits DLY, DLY2, DLY3, and flip-flop DFF30 are supplied with power from analog power sources AVD and AVS. Further, for example, the power supplies of the frequency dividers DIV and DIV2 are supplied from digital power supplies VDD and VSS. In FIG. 20, the power supply line between the frequency divider DIV and the digital power supplies VDD and VSS is omitted for easy understanding of the drawing.

  The PLL circuit includes, for example, a phase comparator PFD3, a clock generation unit CGEN, frequency dividers DIV, DIV2, DIV3, delay adjustment circuits DLY, DLY2, DLY3, and a flip-flop DFF30. The clock generation unit CGEN, the frequency divider DIV, and the delay adjustment circuit DLY are the same as or similar to the clock generation unit CGEN, the frequency divider DIV, and the delay adjustment circuit DLY shown in FIG.

  The frequency divider DIV2 is an example of an input frequency divider that divides the input clock CKI1 (hereinafter also referred to as clock CKI1). For example, frequency divider DIV2 receives input clock CKI1 and reset signal SRST. Then, the frequency divider DIV2 divides the input clock CKI1 by a predetermined frequency division ratio to generate the clock CKID1. The input clock CKI1 is supplied to the PLL circuit from a crystal oscillator connected to the semiconductor integrated circuit SEM, for example. Further, the frequency division ratio may be fixed, or may be variably set from outside the frequency divider DIV2.

  The clock CKID1 obtained by dividing the input clock CKI1 is transmitted to the delay adjustment circuit DLY2. For example, the frequency divider DIV2 outputs a clock CKID1 obtained by dividing the input clock CKI1 to the delay adjustment circuit DLY2.

  The delay adjustment circuit DLY2 is an example of an input delay adjustment circuit that adjusts a delay amount with respect to a clock obtained by dividing the input clock CKI1 and generates a second input clock CKID2 obtained by delaying the clock CKID1 obtained by dividing the input clock CKI1. is there. Hereinafter, the second input clock CKID2 is also referred to as clock CKID2. For example, the delay adjustment circuit DLY2 receives the input clock CKI1, the clock CKID1, the control signals EN, STR, and the reset signal SRST, and outputs the second input clock CKID2 to the phase comparator PFD3. The second input clock CKID2 is a clock obtained by delaying the clock CKID1, for example.

  The configuration and operation of the delay adjustment circuit DLY2 are the same as or similar to, for example, the delay adjustment circuit DLY. For example, in the delay adjustment circuit DLY2, the clocks CKI1, CKID1, and CKID2 correspond to the clocks CKO, CKDIV, and CKFB in the delay adjustment circuit DLY, respectively.

  For example, the delay adjustment circuit DLY2 adjusts the delay amount of the second input clock CKID2 with respect to the clock CKID1 so that the delay variation of the second input clock CKID2 is less than one cycle of the input clock CKI1. Thereby, for example, even when the delay variation of the frequency divider DIV2 exceeds one cycle of the input clock CKI1, the PLL circuit can keep the delay variation of the second input clock CKID2 less than one cycle of the input clock CKI1.

  The phase comparator PFD3 is an example of a phase comparator that compares the phases of the input clock CKI1 detected at the timing based on the second input clock CKID2 and the output clock CKO detected at the timing based on the feedback clock CKFB. For example, the phase comparator PFD3 receives the reset signal SRST, the input clock CKI1, the second input clock CKID2, the output clock CKO of the clock generation unit CGEN, and the feedback clock CKFB. Then, the phase comparator PFD3 generates the up signal UP and the down signal DN based on the phase difference between the input clock CKI1 and the output clock CKO, and outputs the up signal UP and the down signal DN to the clock generation unit CGEN.

  For example, the phase comparator PFD3 compares the first rising edge of the output clock CKO after the feedback clock CKFB rises with the first rising edge of the input clock CKI1 after the second input clock CKID2 rises. Thereby, the phase comparator PFD3 detects the phase difference between the output clock CKO and the input clock CKI1. The phase comparator PFD3 outputs, for example, an up signal UP when the phase of the output clock CKO is behind the input clock CKI1, and the down signal DN when the phase of the output clock CKO is ahead of the input clock CKI1. Is output. Thus, since the phase comparator PFD3 compares the output clock CKO with the input clock CKI1, it is possible to reduce the influence of delay variation of the frequency dividers DIV and DIV2. For example, the PLL circuit can suppress an increase in jitter of the output clock CKO even when delay variation occurs in the feedback path (frequency divider DIV) or the input path (frequency divider DIV2).

  The frequency divider DIV3 is an example of an output frequency divider that divides the output clock CKO. For example, frequency divider DIV3 receives output clock CKO and reset signal SRST. Then, the frequency divider DIV3 divides the output clock CKO by a predetermined frequency division ratio to generate the clock CKOD1. The frequency dividing ratio may be fixed or may be variably set from the outside of the frequency divider DIV3.

  The clock CKOD1 obtained by dividing the output clock CKO is transmitted to the delay adjustment circuit DLY3. For example, the frequency divider DIV3 outputs a clock CKOD1 obtained by dividing the output clock CKO to the delay adjustment circuit DLY3.

  The delay adjustment circuit DLY3 is an example of an output delay adjustment circuit that adjusts a delay amount with respect to the clock CKOD1 obtained by dividing the output clock CKO, and generates a second output clock CKOD2 obtained by delaying the clock CKOD1 obtained by dividing the output clock CKO. It is. Hereinafter, the second output clock CKOD2 is also referred to as clock CKOD2. For example, the delay adjustment circuit DLY3 receives the output clock CKO, the clock CKOD1, the control signals EN, STR, and the reset signal SRST, and outputs the second output clock CKOD2 to the input terminal D of the flip-flop DFF30. The second output clock CKOD2 is a clock obtained by delaying the clock CKOD1, for example.

  The configuration and operation of the delay adjustment circuit DLY3 are the same as or similar to, for example, the delay adjustment circuit DLY. For example, in the delay adjustment circuit DLY3, the clocks CKO, CKOD1, and CKOD2 correspond to the clocks CKO, CKDIV, and CKFB in the delay adjustment circuit DLY, respectively.

  For example, the delay adjustment circuit DLY3 adjusts the delay amount of the second output clock CKOD2 with respect to the clock CKOD1 so that the delay variation of the second output clock CKOD2 is less than one cycle of the output clock CKO. As a result, the PLL circuit can keep the delay variation of the second output clock CKOD2 within one cycle of the output clock CKO even when the delay variation of the frequency divider DIV3 exceeds one cycle of the output clock CKO.

  The flip-flop DFF30 is an example of an output unit that adjusts the output timing of the second output clock CKOD2 based on the output clock CKO. For example, the flip-flop DFF30 receives the second output clock CKOD2 at the input terminal D, the output clock CKO at the clock terminal, and the reset signal SRST at the reset terminal RST. For example, the flip-flop DFF30 outputs the second output clock CKOD2 received at the input terminal D as the clock CKOT from the output terminal Q in synchronization with the rising edge of the output clock CKO.

  Note that the configurations of the PLL circuit and the semiconductor integrated circuit SEM are not limited to this example. For example, the delay adjustment circuit DLY2 may be omitted when the frequency of the input clock CKI1 is low and the delay variation of the divider DIV2 is unlikely to exceed one period of the input clock CKI1. Further, for example, when the delay of the frequency divider DIV3 is small and it is unlikely that the delay variation of the frequency divider DIV3 exceeds one cycle of the output clock CKO, the delay adjustment circuit DLY3 may be omitted. Alternatively, when the output clock CKO of the clock generation unit CGEN is distributed to the logic circuit in the semiconductor integrated circuit SEM, the frequency divider DIV3, the delay adjustment circuit DLY3, and the flip-flop DFF30 may be omitted.

  Further, as described in FIG. 13 and the like, the phase comparator PFD3 may switch the operation according to the control signal EN. For example, until the PLL circuit locks up, the phase comparator PFD3 may detect the phase difference between the feedback clock CKFB and the second input clock CKID2.

  FIG. 21 shows an example of the phase comparator PFD3 shown in FIG. In the phase comparator PFD3, a flip-flop DFF13 is added to the phase comparator PFD shown in FIG. The other configuration of the phase comparator PFD3 is the same as or similar to that of the phase comparator PFD shown in FIG. The same or similar elements as those described in FIG. 2 are denoted by the same or similar reference numerals, and detailed description thereof will be omitted.

  The input terminal D of the flip-flop DFF13 is connected to the analog power supply AVD, and the output terminal Q of the flip-flop DFF13 is connected to the input terminal D of the flip-flop DFF10. The reset terminal RST of the flip-flop DFF13 is connected to each reset terminal RST of the flip-flops DFF10 to DFF12 and the output of the AND circuit AND10.

  For example, the flip-flop DFF13 receives the voltage (high level voltage) of the analog power supply AVD at the input terminal D, and receives the second input clock CKID2 at the clock terminal. Then, the flip-flop DFF13 outputs the signal CKID3 from the output terminal Q in synchronization with the second input clock CKID2.

  The output terminal Q of the flip-flop DFF10 is connected to the input of the AND circuit AND10. For example, the flip-flop DFF10 receives the signal CKID3 at the input terminal D and receives the input clock CKI1 at the clock terminal. Then, the flip-flop DFF10 outputs the up signal UP from the output terminal Q in synchronization with the input clock CKI1.

  The flip-flops DFF11 and DFF12 and the AND circuit AND10 are the same as or similar to the flip-flops DFF11 and DFF12 and the AND circuit AND10 shown in FIG.

  Note that the configuration of the phase comparator PFD3 is not limited to this example. For example, the phase comparator PFD3 may include selectors SEL20 and SEL21, similarly to the phase comparator PFD2 illustrated in FIG. In this case, for example, the terminal I0 of the selector SEL20 is connected to the output terminal Q of the flip-flop DFF13, and the control terminal of the selector SEL20 receives the control signal EN. For example, the PLL circuit may include the lock detection unit LDET and the control circuit CLC illustrated in FIG.

  As described above, also in the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. 20 to 21, the same effects as those of the PLL circuit and the semiconductor integrated circuit SEM of the embodiment shown in FIGS. . For example, the phase comparator PFD3 compares the rising edge of the output clock CKO immediately after the rising edge of the feedback clock CKFB with the rising edge of the input clock CKI1 immediately after the rising edge of the second input clock CKID2. Thereby, the phase comparator PFD3 detects the phase difference between the output clock CKO and the input clock CKI1.

  Thus, in this embodiment, since the phase difference between the output clock CKO and the input clock CKI1 is detected, it is possible to reduce the influence of delay variation of the feedback clock CKFB and the second input clock CKID2. For example, in this embodiment, even when delay variation occurs in the feedback path (frequency divider DIV) or the input path (frequency divider DIV2), an increase in jitter of the output clock CKO can be suppressed. That is, in this embodiment, the jitter of the output clock of the PLL circuit can be reduced.

  Further, for example, the PLL circuit outputs the second output clock CKOD2 obtained by delaying the clock CKOD1 divided by the frequency divider DIV3 as the clock CKOT and outputs it to the outside of the PLL circuit in synchronization with the output clock CKO. For example, the delay adjustment circuit DLY3 adjusts the delay amount of the second output clock CKOD2 with respect to the clock CKOD1 so that the delay variation of the second output clock CKOD2 is less than one cycle of the output clock CKO. For this reason, in this embodiment, even when delay variation occurs in the frequency divider DIV3, it is possible to suppress an increase in jitter of the clock CKOT. That is, in this embodiment, the jitter of the clock CKOT output to the outside of the PLL circuit can be reduced.

  In this embodiment, even when the frequency divider DIV3, the delay adjustment circuit DLY3, and the flip-flop DFF30 are omitted, the output clock CKO of the clock generation unit CGEN is output to the outside of the PLL circuit, so that the output clock of the PLL circuit Jitter can be reduced.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A clock generation unit that generates an output clock having a frequency according to a control voltage adjusted by a control signal;
A frequency divider that receives the output clock and divides the output clock to generate a divided clock;
A delay adjustment circuit that receives the divided clock, adjusts a delay amount with respect to the divided clock, and generates a feedback clock obtained by delaying the divided clock;
The input clock, the output clock and the feedback clock are received, the phase difference between the output clock detected at the timing based on the feedback clock and the input clock is detected, and the phase difference between the output clock and the input clock is detected. And a phase comparator for generating the control signal according to the PLL circuit.
(Appendix 2)
In the PLL circuit according to attachment 1,
A lock detection circuit that receives the control signal and determines whether the output clock is in a locked state within a predetermined frequency range based on the control signal;
A control circuit that receives a detection result indicating the lock state from the lock detection circuit and controls activation of the delay adjustment circuit based on the detection result;
The phase comparator receives the frequency-divided clock as the feedback clock in a period before the delay adjustment circuit is activated.
(Appendix 3)
In the PLL circuit according to Supplementary Note 1 or Supplementary Note 2,
The delay adjustment circuit delays the feedback clock with respect to the divided clock so that one of the rising edge and the falling edge of the output clock is aligned with one edge of the feedback clock. Adjust the amount,
The phase comparator detects the other edge of the rising edge and the falling edge of the output clock detected after detecting the one edge of the feedback clock, and one of the rising edge and the falling edge of the input clock. A PLL circuit that compares edges and detects a phase difference between the output clock and the input clock.
(Appendix 4)
In the PLL circuit according to Supplementary Note 1 or Supplementary Note 2,
The delay adjustment circuit is configured so that one of a rising edge and a falling edge of the feedback clock is aligned with one edge of a rising edge and a falling edge of the clock obtained by delaying the output clock by a predetermined amount. Adjust the delay amount of the feedback clock with respect to the clock,
The phase comparator detects the edge of the output clock corresponding to the one edge of the delayed clock, the rising edge and the rising edge of the input clock, which are detected after detecting the one edge of the feedback clock. A phase difference between the output clock and the input clock is detected by comparing with one edge of the falling edge.
(Appendix 5)
In the PLL circuit according to any one of appendix 1 to appendix 4,
An input divider for receiving the input clock and dividing the input clock;
A second input clock obtained by receiving a clock obtained by dividing the input clock from the input divider, adjusting a delay amount with respect to the clock obtained by dividing the input clock, and delaying the clock obtained by dividing the input clock. And an input delay adjusting circuit for generating
The phase comparator receives the input clock, the second input clock, the output clock, and the feedback clock, and detects the input clock detected at a timing based on the second input clock and a timing based on the feedback clock. A phase difference between the output clock and the input clock is detected, and a phase difference between the output clock and the input clock is detected.
(Appendix 6)
In the PLL circuit according to appendix 5,
The phase comparator receives the frequency-divided clock as the feedback clock and receives the frequency-divided input clock as the second input clock before the delay adjustment circuit is activated. PLL circuit.
(Appendix 7)
In the PLL circuit according to attachment 6,
The phase comparator detects a phase difference between the second input clock and the feedback clock as a phase difference used for generation of the control signal in a period before the delay adjustment circuit is activated, and the delay adjustment circuit A PLL circuit that detects a phase difference between the input clock and the output clock as a phase difference used for generation of the control signal in a period after the activation.
(Appendix 8)
In the PLL circuit according to any one of appendices 1 to 7,
An output divider that receives the output clock and divides the output clock;
A second output clock obtained by receiving a clock obtained by dividing the output clock from the output divider, adjusting a delay amount with respect to the clock obtained by dividing the output clock, and delaying the clock obtained by dividing the output clock. An output delay adjusting circuit for generating
An output unit that receives the output clock and the second output clock and adjusts an output timing of the second output clock based on the output clock.
(Appendix 9)
In the PLL circuit according to any one of appendix 1 to appendix 4,
The phase comparator receives the frequency-divided clock as the feedback clock and uses a phase difference between the input clock and the feedback clock for generating the control signal in a period before the delay adjustment circuit is activated. A PLL circuit, wherein a phase difference between the input clock and the output clock is detected as a phase difference used for generation of the control signal in a period after detection as a phase difference and activation of the delay adjustment circuit.
(Appendix 10)
In the PLL circuit according to any one of appendix 1 to appendix 4,
The phase comparator receives the frequency-divided clock as the feedback clock in a period before the delay adjustment circuit is activated, and the output clock detected at a timing based on the frequency-divided clock received as the feedback clock; A PLL circuit that detects a phase difference from the input clock.
(Appendix 11)
A semiconductor integrated circuit including a PLL circuit,
The PLL circuit includes:
A clock generation unit that generates an output clock having a frequency according to a control voltage adjusted by a control signal;
A frequency divider that receives the output clock and divides the output clock to generate a divided clock;
A delay adjustment circuit that receives the divided clock, adjusts a delay amount with respect to the divided clock, and generates a feedback clock obtained by delaying the divided clock;
The input clock, the output clock and the feedback clock are received, the phase difference between the output clock detected at the timing based on the feedback clock and the input clock is detected, and the phase difference between the output clock and the input clock is detected. And a phase comparator for generating the control signal in response.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  AND10 ... AND circuit; C1, C2 ... capacity; CGEN ... clock generation unit; CLC ... control circuit; CP ... charge pump circuit; DDET ... delay detection part; DE10 ... delay element; DFF10, DFF11, DFF12, DFF13, DFF20 DFF21, DFF30 ... flip-flop; DIV, DIV2, DIV3 ... frequency divider; DLY, DLY2, DLY3 ... delay adjustment circuit; INV10-INV16, INV20-INV22 ... inverter; IS1, IS2 ... current source; LDET ... lock detector; LPF: low pass filter; NAND10-NAND15: NAND circuit; NOR10, NOR11, NOR20: NOR circuit; PFD, PFD2, PFD3 ... phase comparator; PLL ... PLL circuit; R1, R2 ... resistance; RV1 ... variable resistance SEL 0, SEL20, SEL21 ‥ selector; SW1, SW2, SW3, SW4 ‥ switch; VCD ‥ voltage controlled delay element; VCO ‥ voltage controlled oscillator; VDLY ‥ variable delay unit

Claims (9)

A clock generation unit that generates an output clock having a frequency according to a control voltage adjusted by a control signal;
A frequency divider that receives the output clock and divides the output clock to generate a divided clock;
A delay adjusting circuit that receives the divided clock and the output clock, delays the divided clock, and generates a feedback clock having a predetermined delay amount with the output clock ;
The input clock, the output clock and the feedback clock are received, the phase difference between the output clock detected at the timing based on the feedback clock and the input clock is detected, and the phase difference between the output clock and the input clock is detected. And a phase comparator for generating the control signal according to the PLL circuit. The PLL circuit according to claim 1,
A lock detection circuit that receives the control signal and determines whether the output clock is in a locked state within a predetermined frequency range based on the control signal;
A control circuit that receives a detection result indicating the lock state from the lock detection circuit and controls activation of the delay adjustment circuit based on the detection result;
The phase comparator receives the frequency-divided clock as the feedback clock in a period before the delay adjustment circuit is activated. In the PLL circuit according to claim 1 or 2,
The delay adjustment circuit delays the feedback clock with respect to the divided clock so that one of the rising edge and the falling edge of the output clock is aligned with one edge of the feedback clock. Adjust the amount,
The phase comparator detects the other edge of the rising edge and the falling edge of the output clock detected after detecting the one edge of the feedback clock, and one of the rising edge and the falling edge of the input clock. A PLL circuit that compares edges and detects a phase difference between the output clock and the input clock. In the PLL circuit according to claim 1 or 2,
The delay adjustment circuit is configured so that one of a rising edge and a falling edge of the feedback clock is aligned with one edge of a rising edge and a falling edge of the clock obtained by delaying the output clock by a predetermined amount. Adjust the delay amount of the feedback clock with respect to the clock,
The phase comparator detects the edge of the output clock corresponding to the one edge of the delayed clock, the rising edge and the rising edge of the input clock, which are detected after detecting the one edge of the feedback clock. A phase difference between the output clock and the input clock is detected by comparing with one edge of the falling edge. The PLL circuit according to any one of claims 1 to 4, wherein
An input divider for receiving the input clock and dividing the input clock;
A second input clock obtained by receiving a clock obtained by dividing the input clock from the input divider, adjusting a delay amount with respect to the clock obtained by dividing the input clock, and delaying the clock obtained by dividing the input clock. And an input delay adjusting circuit for generating
The phase comparator receives the input clock, the second input clock, the output clock, and the feedback clock, and detects the input clock detected at a timing based on the second input clock and a timing based on the feedback clock. A phase difference between the output clock and the input clock is detected, and a phase difference between the output clock and the input clock is detected. The PLL circuit according to any one of claims 1 to 5,
An output divider that receives the output clock and divides the output clock;
A second output clock obtained by receiving a clock obtained by dividing the output clock from the output divider, adjusting a delay amount with respect to the clock obtained by dividing the output clock, and delaying the clock obtained by dividing the output clock. An output delay adjusting circuit for generating
An output unit that receives the output clock and the second output clock and adjusts an output timing of the second output clock based on the output clock. The PLL circuit according to any one of claims 1 to 4, wherein
The phase comparator receives the frequency-divided clock as the feedback clock and uses a phase difference between the input clock and the feedback clock for generating the control signal in a period before the delay adjustment circuit is activated. A PLL circuit, wherein a phase difference between the input clock and the output clock is detected as a phase difference used for generation of the control signal in a period after detection as a phase difference and activation of the delay adjustment circuit. The PLL circuit according to any one of claims 1 to 4, wherein
The phase comparator receives the frequency-divided clock as the feedback clock in a period before the delay adjustment circuit is activated, and the output clock detected at a timing based on the frequency-divided clock received as the feedback clock; A PLL circuit that detects a phase difference from the input clock. A semiconductor integrated circuit including a PLL circuit,
The PLL circuit includes:
A clock generation unit that generates an output clock having a frequency according to a control voltage adjusted by a control signal;
A frequency divider that receives the output clock and divides the output clock to generate a divided clock;
A delay adjusting circuit that receives the divided clock and the output clock, delays the divided clock, and generates a feedback clock having a predetermined delay amount with the output clock ;
The input clock, the output clock and the feedback clock are received, the phase difference between the output clock detected at the timing based on the feedback clock and the input clock is detected, and the phase difference between the output clock and the input clock is detected. And a phase comparator for generating the control signal in response.

Images