JP2011139285A - Jitter removing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem with a conventional circuit, wherein jitter is generated in a clock which is generated by a reference clock generation circuit. <P>SOLUTION: A jitter removing circuit removes the jitter of a reference clock 51, and includes: a latch circuit 12 which detects edges of the reference clock 51 in synchronism with a sampling clock 52; a counter 13 which counts edge intervals of the reference clock 51; and a phase adjustment circuit 14 which adjusts a phase of the reference clock 51 on the basis of the number of counts of the respective edge intervals. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a jitter removal circuit suitable for removing clock jitter.

  A reference clock generation circuit is known as a circuit that generates a reference clock used for a PLL. The PLL generates an output clock having a desired frequency based on a reference clock (reference clock). The reference clock generation circuit is disclosed as a discrete time oscillator in Patent Document 1 and Patent Document 2, for example.

JP-A-1-36184 JP 2002-1000096 A

  Here, in order for the PLL to generate a highly accurate output clock, the jitter of the reference clock is required to be less than an allowable value. However, in the case of the reference clock generation circuit described in Patent Document 1 and Patent Document 2, there is a problem that the PLL cannot generate an output clock with high accuracy because jitter components are mixed in the reference clock.

  A jitter removal circuit according to the present invention is a jitter removal circuit that removes clock jitter, a latch circuit that detects an edge of the clock in synchronization with a sampling clock, a counter that counts the edge interval, A phase adjustment circuit that adjusts the phase of the clock based on a count number of edge intervals.

  With the above circuit configuration, it is possible to suppress clock jitter.

  According to the present invention, it is possible to provide a jitter removing circuit capable of suppressing clock jitter.

It is a figure which shows the clock generation circuit using the jitter removal circuit concerning Embodiment 1 of this invention. It is a figure which shows the jitter removal circuit concerning Embodiment 1 of this invention. It is a figure which shows the jitter removal circuit concerning Embodiment 1 of this invention. 3 is a timing chart showing an operation of the jitter removal circuit according to the first exemplary embodiment of the present invention; 3 is a flowchart showing an operation of the jitter removal circuit according to the first exemplary embodiment of the present invention; 3 is a timing chart showing an operation of the jitter removal circuit according to the first exemplary embodiment of the present invention;

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. For clarity of explanation, duplicate explanation is omitted as necessary.

Embodiment 1
FIG. 1 shows a clock generation circuit according to the first exemplary embodiment of the present invention. The circuit shown in FIG. 1 includes a reference clock generation circuit 10, a jitter removal circuit 11, and a PLL 20.

  A clock source 50 is input to the reference clock generation circuit 10. Then, the reference clock generation circuit 10 outputs the reference clock 51 to the jitter removal circuit 11. In addition to the reference clock 51, a sampling clock 52 is further input to the jitter removal circuit 11. Then, the jitter removal circuit 11 outputs the reference clock 53 to the PLL 20. The PLL 20 outputs an output clock 54.

  The reference clock generation circuit 10 generates a reference clock 51 having a predetermined frequency based on the clock source 50. The jitter removal circuit 11 removes the jitter of the reference clock 51 and generates the reference clock 53. The PLL 20 generates an output clock 54 having a desired frequency based on the reference clock 53.

  FIG. 2 is a diagram showing the jitter removal circuit 11 according to the present embodiment in more detail. The jitter removal circuit 11 shown in FIG. 2 includes a latch circuit 12, a counter 13, and a phase adjustment circuit 14.

  First, the circuit configuration of the jitter removal circuit 11 will be described. In the jitter removal circuit 11, the reference clock input terminal 41 and the sampling clock input terminal 42 are connected to each input terminal of the latch circuit. The output terminal of the latch circuit 12 is connected to one input terminal of the phase adjustment circuit 14 and the input terminal of the counter 13. The output terminal of the counter 13 is connected to the other input terminal of the phase adjustment circuit 14. The output terminal of the phase adjustment circuit 14 is connected to the clock output terminal 43.

  Next, the operation of the jitter removal circuit 11 will be described. A reference clock 51 is supplied to the latch circuit 12 from the outside via a reference clock input terminal 41. A sampling clock 52 is supplied to the latch circuit 12 from the outside via the sampling clock input terminal 42. The latch circuit 12 detects the edge of the reference clock 51 in synchronization with the sampling clock 52. That is, the latch circuit 12 refers to the logical value of the reference clock 51 using the detection edge (for example, rising edge) of the sampling clock 52 as a trigger. The latch circuit 12 outputs a pulse signal to the phase adjustment circuit 14 and the counter 13 when the logical value of the reference clock 51 changes. For example, the latch circuit 12 outputs an L level signal in the initial state, and outputs an H level pulse signal when the logical value of the reference clock 51 changes.

  The frequency of the sampling clock 52 is set based on the jitter (variation width) allowed for the reference clock 53. For example, a case where the jitter of the reference clock 53 is set to 1.5 ns or less will be described. In this case, the frequency of the sampling clock 52 is set to be 655.36 MHz or higher. That is, the period of the sampling clock 52 is set to be equal to or less than the jitter allowed for the reference clock 53.

  The counter 13 counts a period from when the latch circuit 12 detects the edge of the reference clock 51 until the next edge is detected (hereinafter simply referred to as an edge interval). In other words, the counter 13 counts a period from when the latch circuit 12 outputs a pulse signal until it outputs the next pulse signal. The counter 13 then outputs the count number of each edge interval of the reference clock 51 to the phase adjustment circuit 14. The counter 13 performs a count operation in synchronization with the sampling clock 52 (not shown), for example. The bit length of the counter 13 is set by an external control signal (not shown). The phase adjustment circuit 14 adjusts the phase of the reference clock 53 based on the count number of each edge interval of the reference clock 51. More specifically, the phase adjustment circuit 14 adds a delay value calculated based on the count number of each edge interval of the reference clock 51 to the corresponding edge of the reference clock 51 and outputs it as the reference clock 53.

  Next, the phase adjustment circuit 14 will be described in detail with reference to FIG. The phase adjustment circuit 14 includes a difference detection unit 15, a count number storage unit 16, and a delay control unit 17.

  First, the circuit configuration of the phase adjustment circuit 14 will be described. The output terminal of the counter 13 is connected to one input terminal of the difference detection unit 15, the input terminal of the count number storage unit 16, and the first input of the delay control unit 17 via the other input terminal of the phase adjustment circuit 14. Terminal. The output terminal of the latch circuit 12 is connected to the second input terminal of the delay control unit 17 via one input terminal of the phase adjustment circuit 14 in addition to the input terminal of the counter 13.

  The output terminal of the count number storage unit 16 is connected to the other input terminal of the difference detection unit 15. The output terminal of the difference detection unit 15 is connected to the third input terminal of the delay control unit 17. The output terminal of the delay control unit 17 is connected to the clock output terminal 43 via the output terminal of the phase adjustment circuit 14.

  Next, the operation of the phase adjustment circuit 14 will be described. The count number storage unit 16 stores the count number of each edge interval output from the counter 13 as needed, and calculates the average count number. The count number storage unit 16 outputs the average count number to the difference detection unit 15. The difference detection unit 15 detects the difference (hereinafter simply referred to as the difference count number) between the count number of the latest edge interval (hereinafter simply referred to as the latest edge interval) counted by the counter 13 and the average count number. And output to the delay control unit 17.

  The delay control unit 17 adds a delay value calculated based on the count number of the latest edge interval output from the latch circuit 12 and the corresponding difference count number to the corresponding edge of the reference clock 51, and Output as clock 53.

  FIG. 4 is a timing chart showing the relationship between the reference clock 51 and the reference clock 53. In the example of FIG. 4, the count numbers of the edge intervals in the reference clock 51 are 8, 10, 12, 8, 10, 12 in order. In the example of FIG. 4, the average count number is 10.

  Here, in the latest edge interval of the reference clock 51, the first edge is referred to as a first edge and the subsequent edge is referred to as a second edge. In the reference clock 53, an edge corresponding to the first edge is referred to as a third edge, and an edge corresponding to the second edge is referred to as a fourth edge. In the example of FIG. 4, the first and third edges are rising edges, and the second and fourth edges are falling edges. At this time, after the third edge rises, the fourth edge falls after the count of the latest edge interval (12 counts) and the difference count number (10-12 = -2 counts) have elapsed. Such an operation is repeated at each edge interval. Thereby, the count number of the edge interval in the reference clock 53 indicates 10, 10, 10, 10, 10 in order.

  The period from the first edge rising to the third edge rising is not only the delay time by the delay element or the time required for the arithmetic processing, but also the accumulated difference count number (hereinafter simply referred to as the accumulated difference count). Number). For example, the cumulative difference count number when the third edge rises is (+ 2 + 0−2 + 2 + 0) = + 2. Therefore, after the first edge rises, the third edge rises after the cumulative difference count number (2 counts) has elapsed in addition to the delay time by the delay element and the time required for the arithmetic processing.

  Next, the operation of the jitter removal circuit 11 shown in FIG. 2 will be described in more detail with reference to FIGS. FIG. 5 is a flowchart showing the operation of the jitter removal circuit 11 according to this embodiment. FIG. 6 is a timing chart showing the operation of the jitter removal circuit 11 according to the present embodiment.

  First, the reference clock 51 is input to the jitter removal circuit 11 (S101 in FIG. 5; a in FIG. 6). The latch circuit 12 detects the edge of the reference clock 51 in synchronization with the sampling clock 52 and outputs a pulse signal (S102 in FIG. 5; b in FIG. 6). The counter 13 counts each edge interval of the reference clock 51 and outputs the count number (S103 in FIG. 5; c in FIG. 6).

  The count number storage unit 16 stores the count numbers of the plurality of edge intervals counted by the counter 13, and calculates the average count number (S104 in FIG. 5; d in FIG. 6). The difference detection unit 15 detects a difference (difference count number) between the count number of the latest edge interval counted by the counter 13 and the average count number (S105 in FIG. 5; e in FIG. 6).

  The delay control unit 17 adds a delay value calculated based on the count number of the latest edge interval and the corresponding difference count number to the corresponding edge of the reference clock 51 (S106 in FIG. 5; FIG. 6). f, g). More specifically, the delay control unit 17 includes, for example, a counter inside. The delay control unit 17 counts the total count number of the latest edge interval count and the corresponding difference count number in synchronization with the sampling clock (f in FIG. 6). Then, the delay control unit 17 outputs a reference clock 53 with an edge interval corresponding to the total count (g in FIG. 6).

  As described above, the jitter removal circuit 11 according to this embodiment can generate the reference clock 53 in which the jitter of the reference clock 51 is suppressed. As a result, the post-stage PLL 20 can generate the output clock 54 with high accuracy using the reference clock (reference clock 53) in which jitter is suppressed.

  The reference clock generation circuit 10 is often used as a macro. An example will be described in which the reference clock generation circuit 10 includes a counter that operates in synchronization with an internal clock. When the count by the counter reaches a predetermined count number, the reference clock generation circuit 10 resets the count number to 0 and changes the logical value of the reference clock 51. Thereby, the reference clock generation circuit 10 generates a reference clock 51 having a predetermined frequency.

  At this time, the reference clock 51 has a jitter corresponding to the period of the internal clock. That is, the reference clock 51 has a larger jitter as the period of the internal clock is larger. However, when the reference clock generation circuit 10 is made into a macro, the period of the internal clock cannot be adjusted. Therefore, it is difficult to suppress the jitter of the reference clock 51 in the reference clock generation circuit 10.

  Even in such a case, the problem can be solved by using the jitter removing circuit 11 according to the present embodiment. That is, the jitter removal circuit 11 according to the present embodiment can generate the reference clock 53 in which the jitter of the reference clock 51 is suppressed.

  As described above, the jitter removal circuit 11 according to the above embodiment can generate the reference clock 53 in which the jitter of the reference clock 51 is suppressed. As a result, the post-stage PLL 20 can generate the output clock 54 with high accuracy using the reference clock (reference clock 53) in which jitter is suppressed. Note that the jitter removal circuit 11 according to the above embodiment is particularly effectively used when the reference clock generation circuit 10 cannot suppress the jitter of the reference clock 51.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the above embodiment, the case where the count number storage unit 16 stores the count number output from the counter 13 as needed and calculates the average count number corresponding to the count number has been described as an example. For example, the count number storage unit 16 can appropriately change to a circuit configuration that stores the count number output from the counter 13 and calculates the average count number in the sampling period before the actual operation starts. In this case, the count number storage unit 16 can determine the average count number before starting the actual operation.

DESCRIPTION OF SYMBOLS 10 Reference clock generation circuit 11 Jitter removal circuit 12 Latch circuit 13 Counter 14 Phase adjustment circuit 15 Difference detection part 16 Count number storage part 17 Delay control part 20 PLL
50 clock source 51 reference clock 41 reference clock input terminal 52 sampling clock 42 sampling clock input terminal 53 reference clock 43 clock output terminal 54 output clock

Claims (4)

A jitter removal circuit for removing clock jitter,
A latch circuit for detecting an edge of the clock in synchronization with a sampling clock;
A counter for counting the edge interval;
And a phase adjusting circuit for adjusting a phase of the clock based on a count number of each edge interval. The phase adjustment circuit includes:
The jitter removal circuit according to claim 1, wherein the phase of the clock is adjusted based on a difference between an average count number of the plurality of edge intervals and a count number of the edge intervals. The phase adjustment circuit includes:
A count number storage unit for storing a plurality of count numbers of the edge intervals;
A difference detection unit for detecting a difference between an average count number of the edge intervals stored in the count number storage unit and a count number of the edge intervals;
And a delay adjustment unit that adds a delay value based on the count number counted by the counter and the corresponding difference detected by the difference detection unit to a corresponding edge of the clock. Item 3. The jitter elimination circuit according to Item 1 or 2. The sampling clock is
The jitter removal circuit according to claim 1, wherein the cycle is smaller than a predetermined fluctuation range of the clock.

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