JP2010124102A - Deadlock detection circuit and deadlock restoration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a deadlock detection circuit for accurately detecting a deadlock state without erroneous detection. <P>SOLUTION: The deadlock detection circuit detects the deadlock state of a PLL circuit and includes: a PLL incorporated frequency divider for frequency-dividing the output signals of the voltage controlled oscillator of the PLL circuit and outputting a first frequency division clock; a feedback frequency divider for frequency-dividing the output signals of the voltage controlled oscillator and outputting a second frequency division clock to be a feedback clock to the phase comparator of the PLL circuit; and an erroneous lock detection circuit for outputting a determination signal indicating whether or not it is in the deadlock state on the basis of the clock number of the second frequency division clock included in a prescribed period determined by the cycle of the first frequency division clock. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a deadlock detection circuit that detects a deadlock state of a PLL circuit (phase synchronization circuit), and a deadlock recovery circuit that detects a deadlock state and returns the PLL circuit to a normal lock state.

  The PLL circuit generates an output clock that is phase-synchronized with a reference clock, and is generally a phase comparison circuit (PFD), a charge pump circuit (CP), a loop filter (LF), a voltage controlled oscillator (VCO), and the like. Consists of.

  In order to realize the multiplication function which is one characteristic of the PLL circuit, a feedback frequency divider (FB frequency divider) is provided in the feedback path (FB path) in order to generate a feedback clock to the PFD. The FB frequency divider is desirably operable in the entire range of the oscillation frequency of the VCO in the PLL circuit. However, in many cases, the FB frequency divider is configured by a logic circuit, so that the operation speed is limited.

  Therefore, even if the FB frequency divider operates without any problem in the normal lock state, for example, when a pulse having a frequency component higher than expected is temporarily input to the reference clock, the oscillation frequency of the VCO increases. , May not work properly. Usually, when a frequency exceeding the upper limit of operation is input, the FB frequency divider first enters a frequency-divided state with a longer period than normal. Specifically, for example, the 2 frequency divider apparently operates like a 4 frequency divider.

  When the input frequency to the FB divider is further increased, the feedback clock output from the FB divider is stacked at a high level (H) or a low level (L). However, depending on the configuration of the FB frequency divider, there is a case where the frequency division state having a longer period than that in the normal state does not occur, and the output suddenly becomes a stack state. When the feedback clock is divided or stacked with a longer period than normal, the PLL circuit determines that the feedback clock is slower than the reference clock, that is, the oscillation frequency of the VCO is low, and further increases the oscillation frequency. Finally, the upper limit of the oscillation frequency of the VCO is reached.

  In this case, even if the reference clock returns to normal after that, it does not exit from that state, and the PLL circuit enters a deadlock state.

  There have been various proposals for an automatic recovery method from a deadlock state.

  For example, in Patent Document 1, as a method for returning from a deadlock state, as shown in FIG. 9B, the VCO frequency is returned to the initial state by returning the control voltage of the VCO (the maximum operation). Frequency) to 0 in the initial state. However, in this method, a long time is required until the PLL circuit returns to the normal lock state (the VCO frequency returns to the frequency of the normal lock state). Depending on the application of the system in which the PLL circuit is incorporated, a quick return as much as possible is required.

  Patent Document 2 is a proposal that pays attention to the return time. However, this method requires a large-scale analog circuit, and it is not easy to find the optimum analog voltage value on the actual circuit when considering the analog voltage fluctuation range depending on the operating conditions and process conditions. The applicable frequency range may be limited.

  Patent Documents 3 and 4 also focus on recovery from deadlock or prevention, but both require analog voltage detection.

  As described above, there has been proposed a method that can automatically recover from a deadlock and achieve the fastest possible relock time (recovery time). However, the detection method using an analog circuit is based on operating conditions. It is susceptible to fluctuations depending on the process conditions and the area increases. On the other hand, in an example composed only of digital circuits, it cannot be said that the time reduction until re-locking is an optimum value.

  In addition, many proposals do not mention in detail the erroneous detection of deadlock that erroneously detects the deadlock state after the power is turned on or during the operation from the normal reset state to the initial lock.

JP-A-11-122102 JP 2003-18004 A JP 2006-174358 A JP 2007-104585 A

A first object of the present invention is to provide a deadlock detection circuit capable of accurately detecting a deadlock state without erroneous detection.
A second object of the present invention is to provide a deadlock recovery circuit capable of returning to a normal lock state in the shortest possible time after detecting a deadlock state.

In order to achieve the above object, the present invention is a deadlock detection circuit for detecting a deadlock state of a PLL circuit,
A PLL built-in frequency divider that divides the output signal of the voltage controlled oscillator of the PLL circuit and outputs a first frequency-divided clock;
A feedback frequency divider that divides the output signal of the voltage controlled oscillator and outputs a second frequency-divided clock as a feedback clock to the phase comparator of the PLL circuit;
An error that outputs a determination signal indicating whether or not a deadlock state is present based on the number of clocks of the second divided clock included in a predetermined period determined by the period of the first divided clock. A deadlock detection circuit comprising a lock detection circuit is provided.

Here, the erroneous lock detection circuit divides the first frequency-divided clock by 2m (m is a positive integer), and outputs a third frequency-divided clock.
A counter that resets the pulse of the third divided clock during one level, counts the number of clocks of the second divided clock during the other level, and outputs the counted number When,
The number of counts is equal to or less than the decimal point of a value determined by the frequency division number of the PLL built-in frequency divider × 1/2 of the frequency division number of the third frequency divider ÷ frequency division number of the feedback frequency divider. A determination circuit that outputs the determination signal indicating a deadlock state when the value is not an integer value obtained by rounding down the value or a value in a range of ± 1 of the integer value;
The integer value is preferably 2 or more.

Further, the present invention is a deadlock recovery circuit that detects a deadlock state of a PLL circuit and returns the PLL circuit to a normal lock state.
A deadlock detection circuit according to any of the above,
A dummy pulse generation circuit that generates a dummy pulse including a frequency component higher than the reference clock based on a reference clock input to the PLL circuit;
A deadlock recovery circuit comprising: a multiplexer that switches between the second frequency-divided clock and the dummy pulse based on the determination signal and inputs the clock to the phase comparator.

  Here, the dummy pulse generation circuit includes a double clock generation circuit that generates a double clock from the reference clock, and the number of double clock pulses output from the double clock generation circuit n times (n is an integer of 3 or more) And a pulse thinning circuit that thins out once.

Further, the present invention is a deadlock recovery circuit that detects a deadlock state of a PLL circuit and returns the PLL circuit to a normal lock state.
A deadlock detection circuit according to any of the above,
A dummy pulse generation circuit that generates a dummy pulse including a frequency component lower than the reference clock based on a reference clock input to the PLL circuit;
A first multiplexer that switches between the reference clock and the dummy pulse based on the determination signal and inputs the reference clock to the phase comparator;
A deadlock recovery circuit comprising: a second multiplexer that switches between the second divided clock and the reference clock based on the determination signal and inputs the clock to the phase comparator To do.

  Here, the dummy pulse generation circuit is preferably a pulse thinning circuit that thins out the number of pulses of the reference clock once every n times (n is an integer of 2 or more).

  In the present invention, the output of the voltage controlled oscillator itself is used as a reference for detecting an abnormal operation state. Therefore, according to the present invention, there is almost no risk of erroneous detection during the initial lock operation after power-on or the like, and the deadlock state can be accurately detected.

  In the present invention, when an abnormal operation state of the PLL circuit is detected, the feedback clock is switched to a dummy pulse having a frequency higher than that of the reference clock, or the feedback clock is switched to the reference clock, and the reference clock is switched to the reference clock. By switching to a lower frequency dummy pulse and gradually decreasing the frequency of the voltage controlled oscillator, the frequency controlled oscillator frequency is prevented from dropping too much, and when the feedback divider returns to normal operation, the feedback clock is Return to the frequency divider clock of the feedback divider. Thereby, according to this invention, the time to re-lock can be shortened.

  Hereinafter, a deadlock detection circuit and a deadlock recovery circuit according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block diagram of an embodiment showing a configuration of a semiconductor integrated circuit to which the present invention is applied. The semiconductor integrated circuit 10 shown in the figure has a deadlock recovery circuit that detects a deadlock state of the PLL circuit and automatically returns it to a normal lock state. The semiconductor integrated circuit 10 includes a PLL circuit 12 and a feedback frequency divider (FBDIV). ) 14, an erroneous lock detection circuit 16, a dummy pulse generation circuit 18, and a multiplexer (MUX) 20.

  The PLL circuit 12 incorporates a PLL built-in frequency divider (ADIV) 30 that divides the output clock of the VCO 28 in addition to the normal components PFD22, CP24, LF26, and VCO28. The elements are connected in series in this order. A reference clock REFCLK and a feedback clock FBCLK output from the MUX 20 are input to the PFD 22, and an output clock OUTCLK is output from the VCO 28.

  The ADIV 30 is designed (guaranteed) so as to operate normally up to the maximum operating frequency of the VCO 28 when the PLL circuit 12 is designed. Normally, in order for the VCO 28 to oscillate stably up to a high frequency, it is not a circuit that fully amplifies between the power supply voltage VDD indicating the logic H level and the ground voltage GND indicating the L level, but operates with an amplitude smaller than that. Analog type oscillators are often used. ADIV30 directly receives the small-amplitude output of this analog type oscillator, and ADIV30 itself is also composed of an analog circuit, so that it is possible to divide at a much higher frequency than the frequency divider designed by the logic circuit. It becomes. The ADIV 30 does not have to be limited to an analog divider, but with the above-described devices, it is possible to build a high-speed divider that guarantees operation up to the maximum operating frequency of the VCO 28 in the PLL circuit 12. is there. The ADIV 30 is configured so that even when the VCO 28 operates (oscillates) at the maximum operating frequency, the external logic including the erroneous lock detection circuit 16 (digital circuit outside the PLL circuit 12) can operate normally with sufficient margin. The frequency division number is set. The ADIV 30 outputs a frequency-divided clock VDCLK.

  For example, even when the maximum operating frequency of the VCO 28 is 2 GHz and the external logic cannot operate at 2 GHz, the frequency becomes 250 MHz if it is divided by 8 and becomes a sufficiently operable frequency in recent semiconductor processes. .

  Regarding the output clock OUTCLK, the output signal of the VCO 28 may be output as it is (without frequency division), or the output signal of the VCO 28 may be divided and output (with frequency division) inside the PLL circuit 12. There is no particular limitation.

  Subsequently, the FBDIV 14 divides the output clock OUTCLK and outputs a divided clock OUTDIV that becomes the feedback clock FBCLK to the PFD 22. Here, in a general-purpose PLL circuit, in general, the frequency division number of the feedback clock FBCLK with respect to the output clock OUTCLK (that is, the frequency division number of the FBDIV 14) can be arbitrarily selected within a certain range. For this reason, the frequency division number of the FBDIV 14 may be different from the frequency division number of the ADIV 30 or may be accidentally the same fraction number. The same applies to the present embodiment.

  Subsequently, the erroneous lock detection circuit 16 determines whether or not it is in a deadlock state based on the number of clocks of the divided clock OUTDIV included in a predetermined period determined by the cycle of the divided clock VDCLK. ERJDG is output. Details will be described later.

  Based on the reference clock REFCLK, the dummy pulse generation circuit 18 generates a dummy pulse DUMPLS including a frequency component slightly higher than the reference clock REFCLK (a pulse frequency slightly higher than that of the reference clock REFCLK). Here, the fact that the dummy pulse DUMPLS includes a frequency component slightly higher than the reference clock REFCLK means that the pulsed down signal DN is output from the PFD 22, but does not continue to be output. Details will be described later.

  The frequency division clock OUTDIV is input to the input terminal A0 of the MUX 20, the dummy pulse DUMPLS is input to the A1, and the determination signal ERJDG is input to the selection input terminal. Therefore, the route selection of the MUX 20 is controlled based on the determination signal ERJDG, and switching between the divided clock OUTDIV and the dummy pulse DUMPLS is performed. That is, the MUX 20 outputs the divided clock OUTDIV as the feedback clock FBCLK when the determination signal ERJDG is L, and outputs the dummy pulse DUMPLS when the determination signal ERJDG is H and is input to the PFD 22.

  Here, the ADIV 30, the FBDIV 14, and the erroneous lock detection circuit 16 built in the PLL circuit 12 constitute a deadlock detection circuit of the present invention. The FBDIV 14 is mounted in order to realize the multiplication function of the PLL circuit 12. The deadlock detection circuit, dummy pulse generation circuit 18 and MUX 20 of the present invention constitute a deadlock recovery circuit of the present invention.

  Next, the erroneous lock detection circuit 16 will be described.

  FIG. 2 is a block diagram showing the configuration of the erroneous lock detection circuit shown in FIG. The erroneous lock detection circuit 16 shown in FIG. 1 includes a frequency divider VDDIV32, a counter 34, and a determination circuit 36.

  Here, the erroneous lock state represents an abnormal operation state including a deadlock state. That is, it is a state that is not a normal operation state including a normal lock state.

  The VDDIV 32 divides the frequency-divided clock VDCLK by 2 m (m is a positive integer) and outputs a frequency-divided clock ERCHK in which the H period and the L period are 50:50. The frequency-divided clock ERCHK is a signal for controlling the counting and resetting of the counter 34.

  The counter 34 is reset during the period of one level of the pulse of the divided clock ERCK, for example, the period of L, and counts the number of clocks of the divided clock OUTDIV during the period of the other level, for example, the period H. The counted number (count value) is output.

  For example, consider a case where the frequency division number of VDDIV32 is twice the frequency division number of FBDIV and the counter 34 counts while the frequency division clock ERCHK is H. In this case, the count number in the normal lock state should be the same as the frequency division number of ADIV30. This relationship is valid regardless of the oscillation frequency of the VCO 28. That is, even if the PLL circuit 12 is on the way to the normal lock state after the system is turned on.

  The determination circuit 36 is an integer value obtained by rounding off the value after the decimal point of the value determined by the division number of the ADIV30 × 1/2 of the division number of the VDDIV32 ÷ the division number of the FBDIV14. When the value is not in the range of ± 1 of the integer value, the determination signal ERJDG indicating the deadlock state is output. Here, the aforementioned integer value is a value of 2 or more (that is, the count number is 1 or more).

  Note that the frequency division numbers of ADIV30, VDDIV32, and FBDIV14 need to satisfy the condition that the integer value is 2 or more as described above.

  In the case of the present embodiment, the determination signal ERJDG is output as L when in a normal operation state, and the MUX 20 selects the route A0. On the other hand, in the abnormal operation state, H is output as the determination signal ERJDG, and the MUX 20 selects the route A1.

  Here, the divided clock ERCK and the divided clock OUTDIV have different paths until these signals are generated. Further, a large delay (not shown in FIG. 1) may be inserted into the FB path of the PLL circuit 12 in order to cancel the delay due to CTS (clock tree synthesis) in the semiconductor chip. Therefore, it can be said that the timing (phase relationship) between the divided clock ERCK and the divided clock OUTDIV is not in a fixed relationship (asynchronous).

  Also, since the frequency-divided clock ERCK and the frequency-divided clock OUTDIV are asynchronous, the number of counts by the counter 34 may not always be constant. Therefore, as described above, the configuration is regarded as normal operation even within the range of ± 1. It is desirable to do. This is because when the FBDIV 14 is in an abnormal operation state, the operation is not performed such that the number of pulses of the divided clock OUTDIV is slightly reduced, and the number of pulses is significantly reduced.

  Also, for resetting the counter 34 of the erroneous lock detection circuit 16 and reading the count number, a gray code counter (decoder) is used, or a circuit (two-stage shift register) for changing the clock to prevent metastable is provided. It is desirable to take measures against asynchronous signals. The asynchronous signal countermeasure circuit itself has various configurations, and may be general in the present invention, and the configuration is not limited.

  Next, the dummy pulse generation circuit 18 will be described.

  FIG. 3 is a block diagram showing the configuration of the dummy pulse generation circuit shown in FIG. The dummy pulse generation circuit 18 shown in FIG. 1 includes a double clock generation circuit 38 and a pulse thinning circuit 40.

  The double clock generation circuit 38 generates a double clock (a clock having a pulse number twice that of the reference clock REFCLK) REFX2 from the reference clock REFCLK. The double clock generation circuit 38 includes a delay circuit 38a and an EOR gate 38b. The EOR gate 38b receives the reference clock REFCLK and the reference clock REFCLK delayed by the delay circuit 38a. The EOR gate 38b outputs a double clock REFX2 having a pulse width corresponding to the delay time of the delay circuit 38a from the rise and fall of the reference clock REFCLK.

  The configuration of the double clock generation circuit 38 is general. It is ideal that the dummy pulse DUMPLS has a frequency component higher than the reference clock REFCLK, preferably a slightly higher frequency component. For example, the dummy pulse DUMPLS may have a frequency twice as high (without the pulse thinning circuit 40). .

  The pulse thinning circuit 40 thins out the number of pulses of the double clock REFX2 once every n times (n is an integer of 3 or more), and in the case of the specific example of this embodiment described later, once every four times, Sometimes, a dummy pulse DUMPLS used as a feedback clock FBCLK instead of the divided clock OUTDIV is generated.

  In order to reduce the pulse frequency of the double clock REFX2, a dummy pulse DUMPLS having a pulse number 1.5 times that of the reference clock REFCLK can be generated by thinning out the number of pulses of the double clock REFX2 once every four times. The 1.5-fold dummy pulse DUMPLS generated in this way has an average period that is 1 / 1.5 of the reference clock REFCLK, but does not have a regular clock shape (clock waveform). However, that shape is sufficient for the purposes of the present invention.

  By increasing the pulse frequency of the dummy pulse DUMPLS with respect to the reference clock REFCLK, the oscillation frequency of the VCO 28 can be decreased during an abnormal operation state. However, if the pulse frequency of the dummy pulse DUMPLS is increased too much, the down signal DN continues to be output, and since the oscillation frequency of the VCO 28 decreases rapidly, it is too low, and a long time is required until a normal lock state is achieved. Therefore, the pulse frequency of the dummy pulse DUMPLS is desirably about 1 to 2 times the reference clock REFCLK.

  Next, the operation of the semiconductor integrated circuit 10 shown in FIG. 1 will be described.

  When the erroneous lock detection circuit 16 is in a normal operation state, the determination signal ERJDG is L, and the route of the MUX 20 is selected on the A0 side.

  In the normal operation state, in the PLL circuit 12, the phase difference between the reference clock REFCLK and the feedback clock FBCLK is detected by the PFD 22, and the up signal UP or the down signal DN that is the detection result is output. For example, the PFD 22 compares the rising phases of the reference clock REFCLK and the feedback clock FBCLK, and outputs the up signal UP when the phase of the reference clock REFCLK is earlier than the phase of the feedback clock FBCLK, and vice versa. Outputs a down signal DN.

  Subsequently, the pulse width of the output signal is changed according to the up signal UP or the down signal DN by the CP 24, and further converted into a control voltage (analog voltage) according to the pulse width of the output signal of the CP 24 by the LP 26. The In the VCO 28, the oscillation frequency of the output clock OUTCLK is changed according to the control voltage, and is output as the output clock of the PLL circuit 12 and also input to the FBDIV 14.

  In the FBDIV 14, the output clock OUTCLK is divided according to the set multiplication number. The divided clock OUTDIV is input as a feedback clock FBCLK to the PFD 22 via the MUX 20 when the determination signal ERJDG is L (in a normal operation state). Thereafter, similarly, the phase difference between the reference clock REFCLK and the feedback clock FBCLK is synchronized (locked) by repeatedly detecting the phase difference between the reference clock REFCLK and the feedback clock FBCLK and changing the oscillation frequency of the output clock OUTCLK. The

  In the erroneous lock detection circuit 16, the divided clock VDCLK is divided by VDDIV32 and the divided clock ERCHK is output. The counter 34 counts the number of clocks of the frequency-divided clock OUTDIV while the frequency-divided clock ERCK is H, and the counted number is determined by the determination circuit 36. In the normal operation state, the count number is in the range of the above-described integer value ± 1, and the determination signal ERJDG becomes L, and A0 is selected as the path of the MUX 20 as described above.

  On the other hand, for example, when the frequency of the VCO 28 becomes high and the FBDIV 14 cannot operate normally, the erroneous lock detection circuit 16 assumes that it is in an abnormal operation state, that is, an erroneous lock state, the determination signal ERJDG becomes H, and the path of the MUX 20 is A1. Can be switched.

  In this case, the dummy pulse DUMPLS is output as the feedback clock FBCLK, and the frequency of the feedback clock FBCLK becomes higher than that of the reference clock REFCLK. Therefore, the PLL circuit 12 considers that the oscillation frequency of the VCO 28 is high and reduces the frequency to reduce the frequency. DN is output. When the frequency of the output clock OUTCLK decreases and the FBDIV 14 returns to the normal operation state, the erroneous lock detection circuit 16 detects this and the determination signal ERJDG becomes L, and the MUX path returns to the A0 side. Thereafter, the normal lock operation is performed in a normal PLL operation.

  Hereinafter, a specific example will be described.

  FIG. 4 is a block diagram showing a specific example of the semiconductor integrated circuit shown in FIG. The semiconductor integrated circuit 50 shown in the figure basically includes the erroneous lock detection circuit 16 having the configuration shown in FIG. 2 and the dummy pulse generating circuit 18 having the configuration shown in FIG. 3 in the semiconductor integrated circuit 10 shown in FIG. It has a configuration. In the semiconductor integrated circuit 50, the frequency division number of the ADIV 30 of the PLL circuit 12 is divided by 8, and the frequency division number of the FBDIV 14 is divided by 5.

  In the erroneous lock detection circuit 16, the VDDIV 32 includes two frequency dividers 32a and 32b. Here, in order to facilitate understanding, the frequency divider is divided into two frequency dividers, but needless to say, it can be realized with one frequency divider.

  As shown in the timing chart of FIG. 5, the frequency-divided clock VDCLK is divided by 5 by the frequency divider 32a and output as the frequency-divided clock VDCLK5. In this example, the divided clock VDCLK5 has a period of 3 clocks of the divided clock VDCLK as H and a period of 2 clocks as L (H: L = 3: 2). The distribution of H and L of the divided clock VDCLK5 is not limited at all. For example, it may be 2: 3, 1: 4 or 4: 1, or 2 using the falling edge of the divided clock VDCLK. .5: 2.5.

  The frequency-divided clock VDCLK5 is frequency-divided by 2 by the frequency divider 32b and output as the frequency-divided clock ERCK. By dividing the divided clock VDCLK5 by 2 by the frequency divider 32b, the distribution of H and L of the divided clock ERCK becomes 5: 5.

  As shown in Table 1, the counter 34 is in a reset state (counter output = 0) regardless of the state of the divided clock OUTDIV (the divided clock OUTDIV = X) while the pulse of the divided clock ERCK is L. And wait. On the other hand, while the frequency-divided clock ERCHK is H, it counts up from 0 at the timing of the rising edge (↑) of the frequency-divided clock OUTDIV, and outputs the counted number (counter output). In the example of Table 1, the counter 34 stops counting up when the count number reaches 10, and holds 10 even when the rising edge of the divided clock OUTDIV comes thereafter.

  The reason why the count up of the counter 34 is stopped when the count number is 10 is that when the count number becomes 10 or more, the determination circuit 36 indicates that the normal operation state is not reached no matter how much the count number thereafter increases. This is because it can be determined. However, the present invention is not limited to this, and the count-up may be continued without stopping the count number at 10.

  As described above, the frequency division number of ADIV30 (= 8) × the frequency division number of VDDIV32 (= 5 × 2 = 10) × 1/2 ÷ the frequency division number of FBDIV14 (= 5) = 8. In the state, the count number of the counter 34 is always in the range of 8 ± 1 (7-9).

  As shown in Table 2, the determination circuit 36 determines whether or not the count number of the counter 34 is in the range of 8 ± 1, and outputs a determination signal ERJDG. The determination signal ERJDG becomes L when the count number (counter output) is in the range of 8 ± 1, and becomes H when not in the range of 8 ± 1.

  Subsequently, in the dummy pulse generation circuit 18, the configuration of the double clock generation circuit 38 is the same as that shown in FIG.

  As shown in Table 3, the pulse decimation circuit 40 decimates the H pulse of the double clock REFX2 generated by the double clock generation circuit 38 once every four times, and outputs it as a dummy pulse DUMPLS.

  In this example, the pulse thinning circuit 40 includes a counter that repeatedly counts from 0 to 3 inside. As shown in the timing chart of FIG. 6, this internal counter counts up at the falling edge (↓) timing of the double clock REFX2. In the pulse thinning circuit 40, when the count value of the internal counter is 0, 1, 3, the double clock REFX2 is output as a dummy pulse DUMPLS as it is, but when the count value is 2, the H pulse of the double clock REFX2 is masked. L is output. As a result, it is possible to perform pulse thinning only once every four times of the double clock REFX2.

  Note that the internal counter is counted up at the falling edge timing of the double clock REFX2, because in this example, the specification is such that the H pulse (H section) of the double clock REFX2 is masked, as shown in the timing chart of FIG. This is because the timing design for masking is facilitated. However, the internal counter can be counted up at the rising edge of the double clock REFX2 by appropriately adjusting the masking timing. Further, the L pulse (L section) of the double clock REFX2 is masked and H is output. It is good also as a structure.

  The specific circuit configurations of the counter 34, the determination circuit 36, and the pulse thinning circuit 40 are not limited at all. These circuits can be easily realized by describing them in a circuit description language based on Tables 1 to 3 (truth table) and logically synthesizing them.

  The circuits and specifications shown here (settings such as the frequency division number and decimation) are merely examples. For example, the specific specifications of the method of generating the frequency division clock ERCHK, the counter 34, the determination circuit 36, and the pulse decimation circuit 40 are shown. It is not limited. Furthermore, the idea to avoid the infinite loop entry of the state machine is generally considered in digital circuit design and has nothing to do with the gist of the present invention. Not.

  Specifically, the operation of the semiconductor integrated circuit 50 is such that the frequency-divided clock OUTDIV or the dummy pulse DUMPLS is output as the feedback clock FBCLK depending on whether or not the count number of the counter 34 is in the range of 8 ± 1. Except for this, it is the same as the semiconductor integrated circuit 10. That is, when the count number is in the range of 8 ± 1, the normal operation state is obtained, and when the count number is any other value, the abnormal operation state is obtained. When an abnormal operation state is detected (determination signal ERJDG = H), a dummy pulse DUMPLS in which the H pulse of the double clock REFX2 is masked once every four times is output as the feedback clock FBCLK.

  Here, a widely adopted PFD system is assumed as the PFD 22. As shown in the timing chart of FIG. 7, when the reference clock REFCLK rises earlier than the feedback clock FBCLK (dummy pulse DUMPLS) from the reset state (the state where the reference clock REFCLK and the feedback clock FBCLK are L). The up signal UP is set to H, and is returned to L at the rise of the next feedback clock FBCLK. While the up signal UP is H, the control voltage of the VCO 28 is charged up by the CP 24 and the frequency of the VCO 28 is increased.

  Conversely, the PFD 22 sets the down signal DN to H when the feedback clock FBCLK (dummy pulse DUMPLS) rises earlier than the reference clock REFCLK from the reset state, and returns it to L at the next rise of the reference clock REFCLK. While the down signal DN is H, the control voltage is discharged at CP24, and the frequency of the VCO 28 is lowered.

  As shown in the timing chart of FIG. 7, since the down signal DN is intermittently generated in the semiconductor integrated circuit 50, the frequency of the VCO 28 can be gradually lowered. Although not shown in the figure, in the case of the semiconductor integrated circuit 50, if the dummy pulse DUMPLS is used without being thinned out and left as it is, the down signal DN is maintained in the almost H state, and the frequency of the VCO 28 is drastically lowered and excessively lowered. There is a case. Therefore, it is desirable to select an appropriate pulse thinning according to the characteristics of the PLL circuit 12.

  Subsequently, a further idea of the erroneous lock detection circuit 16 will be described. In particular, the timing for detecting that the FBDIV 14 has returned to the normal operating state is preferably as early as possible after returning to the normal operating state. In the example of FIG. 4, it is detected after a time corresponding to 80 clocks of the output clock OUTCLK. However, if this is late, the frequency division number of the frequency division clock VDCLK in the erroneous lock detection circuit 16 may be appropriately reduced while taking into account the number of counts in the counter 34 in the normal operation state.

  For example, consider a case where the frequency division number of VDDIV32 is 6. Detection by the erroneous lock detection circuit 16 is performed at a frequency of every 8 × 6 = 48 clocks with the output clock OUTCLK. The count number at this timing is 48 × 1/2 ÷ 5 = 4.8, but the count number is 4 because it is an integer value obtained by rounding down values after the decimal point. Alternatively, the timing may be 3 or 5, but there is no problem in detection accuracy even if any of the range of 4 ± 1 (3 to 5) is regarded as a normal operation.

  Furthermore, another feature of the erroneous lock detection circuit 16 will be described. Conventional digital erroneous lock detection circuits often use the reference clock REFCLK as a reference for detecting malfunction. In some cases, this may work, but in the first place, most of the causes of the erroneous lock state are temporary disturbances of the reference clock REFCLK. Since the disturbance operation is generally unknown and cannot be defined, it is impossible to predict the state of the erroneous lock detection circuit during that time.

  Another problem is false detection when going to the initial lock after power-on. Naturally, the oscillation frequency of the VCO 28 is low until the PLL circuit 12 is locked, and the number of feedback clock FBCLK pulses is smaller than that of the reference clock REFCLK. However, this is the same appearance as when the FBDIV 14 cannot operate normally and the predetermined number of pulses does not return, and it is necessary to devise how to distinguish between the two.

  In the present invention, the output clock of the VCO 28 itself is used as a reference for detecting a malfunction state. Therefore, the deadlock detection circuit and the deadlock recovery circuit according to the present invention all solve the above problems.

  The deadlock detection circuit detects a deadlock state of the PLL circuit 12 and outputs a determination signal ERJDG. The circuit for returning the PLL circuit 12 to a normal lock state using the determination signal ERJDG. (For example, the dummy pulse generation circuit 18 and the MUX 20 shown in FIG. 1) having various configurations can be used.

  FIG. 8 is a block diagram showing another configuration of the dummy pulse generation circuit shown in FIG. The dummy pulse generation circuit 18 shown in the figure generates a dummy pulse including a frequency component lower than the reference clock REFCLK based on the reference clock REFCLK input to the PLL circuit 12. The dummy pulse generation circuit 18 shown in the figure is constituted by a pulse thinning circuit 42 and a MUX 44.

  The pulse thinning circuit 42 thins out the H pulse of the reference clock REFCLK once every four times and outputs it as a thinning clock.

  The reference clock REFCLK is input to the input terminal A0 of the MUX 44, the decimation clock output from the pulse decimation circuit 42 is input to A1, and the determination signal ERJDG is input to the selection input terminal. The route selection of the MUX 44 is controlled based on the determination signal ERJDG. The reference clock REFCLK is output from the MUX 44 when the determination signal ERJDG is L. On the other hand, when the determination signal ERJDG is H, a decimation clock is output. Is input to the input terminal of the reference clock REFCLK as the reference clock of the PLL circuit 12.

  The reference clock REFCLK is input to the input terminal A1 of the MUX 20.

  In the dummy pulse generation circuit 18 shown in the figure, in the abnormal operation state (determination signal ERJDG = H), the thinning clock is input as the reference clock, and the reference clock itself is input as the feedback clock. Therefore, since the reference clock (= decimation clock) has a frequency component slightly lower than the feedback clock (= REFCLK), the dummy pulse generation circuit 18 shown in FIG. 8 has the same effect as that shown in FIG. Can be obtained.

  Incidentally, one of the objects of the present invention is to relock as soon as possible. The purpose of increasing the detection frequency of the erroneous lock detection circuit 16 is to prevent the DN command from being issued and the frequency being lowered excessively even though the FBDIV 14 has returned to the normal operation state. The reason why the VCO frequency is gradually lowered by slightly increasing the period during which the down signal DN is output by the dummy pulse generation circuit 18 is also to prevent the frequency of the VCO 28 from being lowered too much.

  If the VCO 28 is in a PLL condition that is stable at a very low frequency within the operating frequency range, rather than gradually lowering the frequency of the VCO 28 as described above, the VCO 28 may be lowered to the initial state (= 0) at once. It may be faster to lock. As described above, when the PLL condition is known (determined) in advance, it is desirable to adopt a configuration according to the PLL condition.

  In order to return the PLL circuit 12 that has entered the abnormal operation state to the normal operation state and to return to the normal lock state, it is necessary to eventually converge naturally through the normal FB path. Therefore, the present invention aims to switch to that state as soon as possible (switch the divided clock OUTDIV and the dummy pulse DUMPLS). Therefore, the present invention is not limited, but is effective when the locking frequency is relatively high.

  FIGS. 9A and 9B are timing charts showing transition states up to relocking of the deadlock recovery circuit according to the present invention and the conventional deadlock recovery circuit, respectively. As shown in FIG. 4A, in the deadlock recovery circuit according to the present invention, the frequency of the VCO gradually decreases from the frequency of the VCO in the deadlock state (maximum operating frequency) to the frequency of the VCO in the normal lock state, Compared with the conventional deadlock recovery circuit shown in FIG. 4B, the normal lock state can be recovered in a short time without the VCO frequency being excessively lowered.

  As described above, in the present invention, when the abnormal operation state of the PLL circuit is detected, the feedback clock FBCLK is switched to the dummy pulse DUMPLS, and the VCO frequency is not lowered too much, but gradually lowered, so that the VCO frequency is lowered too much. When the FBDIV returns to the normal operation state, the feedback clock FBCLK is quickly returned to the divided clock OUTDIV. Thereby, the time until re-locking can be shortened. Further, since the false lock detection method uses the output of the VCO itself as a reference, there is almost no risk of false detection during the initial lock operation such as after power-on.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

It is a block diagram of one embodiment showing the composition of the semiconductor integrated circuit to which the present invention is applied. FIG. 2 is a block diagram illustrating a configuration of an erroneous lock detection circuit illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a dummy pulse generation circuit illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a specific example of the semiconductor integrated circuit illustrated in FIG. 1. It is a timing chart showing the relationship between the divided clock VDCLK, the divided clock VDCLK5, and the divided clock ERCK. 3 is a timing chart showing an internal state of a thinning circuit 40. 6 is a timing chart showing a relationship among a reference clock REFCLK, a double clock REFX2, a dummy pulse DUMPLS, an up signal UP, and a down signal DN. FIG. 6 is a block diagram illustrating another configuration of the dummy pulse generation circuit illustrated in FIG. 1. (A) And (B) is a timing chart showing the transition state until the relock of the deadlock return circuit concerning this invention and the conventional deadlock return circuit, respectively.

Explanation of symbols

10, 50 Semiconductor integrated circuit 12 PLL circuit 14 Feedback frequency divider (FBDIV)
16 False lock detection circuit 18 Dummy pulse generation circuit 20, 44 Multiplexer (MUX)
22 Phase comparison circuit (PFD)
24 Charge pump circuit (CP)
26 Loop filter (LF)
28 Voltage controlled oscillator (VCO)
30 Analog divider (ADIV)
32, 32a, 32b Frequency divider 34 Counter 36 Determination circuit 38 Double clock generation circuit 38a Delay circuit 38b EOR gate 40, 42 Pulse decimation circuit

Claims (6)

A deadlock detection circuit for detecting a deadlock state of a PLL circuit,
A PLL built-in frequency divider that divides the output signal of the voltage controlled oscillator of the PLL circuit and outputs a first frequency-divided clock;
A feedback frequency divider that divides the output signal of the voltage controlled oscillator and outputs a second frequency-divided clock as a feedback clock to the phase comparator of the PLL circuit;
An error that outputs a determination signal indicating whether or not a deadlock state is present based on the number of clocks of the second divided clock included in a predetermined period determined by the period of the first divided clock. A deadlock detection circuit comprising a lock detection circuit. The erroneous lock detection circuit divides the first frequency-divided clock by 2 m (m is a positive integer), and outputs a third frequency-divided clock.
A counter that resets the pulse of the third divided clock during one level, counts the number of clocks of the second divided clock during the other level, and outputs the counted number When,
The number of counts is equal to or less than the decimal point of a value determined by the frequency division number of the PLL built-in frequency divider × 1/2 of the frequency division number of the third frequency divider ÷ frequency division number of the feedback frequency divider. A determination circuit that outputs the determination signal indicating a deadlock state when the value is not an integer value obtained by rounding down the value or a value in a range of ± 1 of the integer value;
The deadlock detection circuit according to claim 1, wherein the integer value is 2 or more. A deadlock return circuit for detecting a deadlock state of the PLL circuit and returning the PLL circuit to a normal lock state;
A deadlock detection circuit according to claim 1 or 2,
A dummy pulse generation circuit that generates a dummy pulse including a frequency component higher than the reference clock based on a reference clock input to the PLL circuit;
A deadlock recovery circuit, comprising: a multiplexer that switches between the second frequency-divided clock and the dummy pulse based on the determination signal and inputs the clock to the phase comparator.   The dummy pulse generation circuit includes a double clock generation circuit that generates a double clock from the reference clock, and a double clock pulse output from the double clock generation circuit once every n times (n is an integer of 3 or more). The deadlock recovery circuit according to claim 3, further comprising a thinning-out pulse thinning circuit. A deadlock return circuit for detecting a deadlock state of the PLL circuit and returning the PLL circuit to a normal lock state;
A deadlock detection circuit according to claim 1 or 2,
A dummy pulse generation circuit that generates a dummy pulse including a frequency component lower than the reference clock based on a reference clock input to the PLL circuit;
A first multiplexer that switches between the reference clock and the dummy pulse based on the determination signal and inputs the reference clock to the phase comparator;
A deadlock recovery circuit comprising: a second multiplexer that switches between the second frequency-divided clock and the reference clock based on the determination signal and inputs the clock to the phase comparator.   6. The deadlock recovery circuit according to claim 5, wherein the dummy pulse generation circuit is a pulse thinning circuit that thins out the number of pulses of the reference clock once every n times (n is an integer of 2 or more).

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