JP6435624B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

In an electronic apparatus having a display function, a transmissive electro-optical device or a reflective electro-optical device is used. Light is irradiated to these electro-optical devices, and transmitted light or reflected light modulated by the electro-optical device becomes a display image, or is projected on a screen to become a projection image. A liquid crystal device is known as an electro-optical device used in such an electronic device, which forms an image using the dielectric anisotropy of the liquid crystal and the optical rotation of the light in the liquid crystal. is there. In the liquid crystal device, scanning lines and signal lines are arranged in a display area, and pixels are arranged in a matrix at intersections thereof. Each pixel is provided with a pixel transistor and a pixel capacitor. An image signal is supplied to each pixel via the pixel transistor, and an image is formed by holding the image signal in the pixel capacitor.

An example of a pixel layout of a liquid crystal device is described in Patent Document 1. As described in FIG. 7 of Patent Document 1, the pixel transistor is formed such that a straight strip-shaped gate electrode intersects a straight strip-shaped semiconductor film via a gate insulating film.

JP 2006-3920 A

However, the liquid crystal device described in Patent Document 1 has a problem that miniaturization is difficult. In order to display a high-quality image, it is necessary to miniaturize pixels. On the other hand, it is difficult to reduce the transistor size to a certain extent due to restrictions on electrical characteristics such as pressure resistance. Therefore, in the conventional liquid crystal device, the transistor size determines the limit of pixel miniaturization. In other words, the conventional electro-optical device has a problem that it is difficult to ensure both electrical reliability and high-quality image display.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

Application Example 1 An electro-optical device according to this application example includes a first transistor and a second transistor, and the first transistor includes a first portion of the first semiconductor film and a first gate that intersects the first portion. An electrode, and the second transistor includes a second portion of the second semiconductor film,
A second gate electrode intersecting with the second portion, the first portion extending along the first direction, and the first semiconductor film including a third portion extending along the second direction intersecting with the first direction. The sum of the length of the first portion and the length of the third portion is greater than the sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode.
The sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode is the pixel pitch. Therefore, according to this configuration, the length of the first semiconductor film can be made longer than the pixel pitch. That is, the pixel length can be made shorter than the length of the first semiconductor film constituting the first transistor, and miniaturization can be promoted. In other words, it is possible to ensure electrical reliability with a relatively large first transistor and display a high-quality image with fine pixels.

Application Example 2 In the electro-optical device according to Application Example 1, the second portion extends along the first direction, and the second semiconductor film includes a fourth portion extending along the second direction. The sum of the length of the second portion and the length of the fourth portion is preferably larger than the sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode.
The sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode is the pixel pitch. Therefore, according to this configuration, the length of the second semiconductor film can be made longer than the pixel pitch. That is, the length of the pixel can be made shorter than the length of the second semiconductor film constituting the second transistor, and miniaturization can be promoted. In other words, it is possible to ensure electrical reliability with a relatively large second transistor and display a high-quality image with fine pixels.

Application Example 3 In the electro-optical device according to Application Example 2, the sum of the length of the first portion and the length of the third portion is approximately equal to the sum of the length of the second portion and the length of the fourth portion. It is preferable that they are equal.
According to this structure, the 1st semiconductor film which comprises a 1st transistor, and the 2nd semiconductor film which comprises a 2nd transistor can be made the same size.

Application Example 4 In the electro-optical device according to any one of Application Examples 1 to 3, the first pixel electrode electrically connected to one of the source and drain of the first transistor, and the second transistor It is preferable to further include a second pixel electrode electrically connected to one of the source and drain.
According to this configuration, the first semiconductor film constituting the first transistor and the second semiconductor film constituting the second transistor can be used as the pixel switching element.

Application Example 5 In the electro-optical device according to any one of Application Examples 1 to 4, the other of the source drain of the first transistor and the other of the source drain of the second transistor are electrically connected. A signal line is further provided, and the signal line preferably extends along the first direction.
According to this configuration, the first transistor and the second transistor can control the passage and blocking of the information supplied to the signal line.

Application Example 6 An electro-optical device according to this application example includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the first transistor is a first portion of the first semiconductor film. And a first gate electrode that intersects the first portion, and the second transistor includes a second portion of the second semiconductor film, a second gate electrode that intersects the second portion,
The third transistor includes a fifth portion of the first semiconductor film and a third gate electrode intersecting the fifth portion, and the fourth transistor includes a sixth portion of the second semiconductor film and a sixth gate electrode. A fourth gate electrode intersecting the portion, the first portion and the fifth portion extending along the first direction, and the first semiconductor film extending along the second direction intersecting the first direction Including a part and a seventh part,
The sum of the length of the first part, the length of the third part, the length of the fifth part and the length of the seventh part is obtained by summing the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode. It is also characterized by being large.
The sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode is the length of two rows of pixels. On the other hand, the sum of the length of the first portion, the length of the third portion, the length of the fifth portion, and the length of the seventh portion is the length of the first semiconductor film over two rows. Therefore, according to this configuration, the length of the first semiconductor film can be made longer than twice the pixel pitch. That is, the pixel length can be made shorter than the length of the first semiconductor film constituting the first transistor, and miniaturization can be promoted. In other words, it is possible to ensure electrical reliability with a relatively large first transistor and display a high-quality image with fine pixels.

Application Example 7 In the electro-optical device according to Application Example 6, the second portion and the sixth portion extend in the first direction, and the second semiconductor film extends in the second direction. Including the fourth part and the eighth part, the sum of the length of the second part, the length of the fourth part, the length of the sixth part and the length of the eighth part,
It is preferably larger than the sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode.
The sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode is the length of two rows of pixels. On the other hand, the sum of the length of the second portion, the length of the fourth portion, the length of the sixth portion, and the length of the eighth portion is the length of the second semiconductor film over two rows. Therefore, according to this configuration, the length of the second semiconductor film can be made longer than twice the pixel pitch. That is, the length of the pixel can be made shorter than the length of the second semiconductor film constituting the second transistor, and miniaturization can be promoted. In other words, it is possible to ensure electrical reliability with a relatively large second transistor and display a high-quality image with fine pixels.

Application Example 8 In the electro-optical device according to Application Example 7, the sum of the length of the first portion and the length of the third portion is substantially equal to the sum of the length of the second portion and the length of the fourth portion. It is preferable that they are equal.
According to this structure, the 1st semiconductor film which comprises a 1st transistor, and the 2nd semiconductor film which comprises a 2nd transistor can be made the same size.

Application Example 9 In the electro-optical device according to any one of Application Examples 6 to 8, the sum of the length of the first portion and the length of the third portion is the length of the fifth portion and the seventh portion. It is preferable to be approximately equal to the sum of
According to this configuration, the first transistor and the third transistor can have the same size.

Application Example 10 In the electro-optical device according to any one of Application Examples 6 to 9,
A first pixel electrode electrically connected to one of the source and drain of the first transistor; a second pixel electrode electrically connected to one of the source and drain of the second transistor; It is preferable to further include a third pixel electrode that is electrically connected and a fourth pixel electrode that is electrically connected to one of the source and drain of the fourth transistor.
According to this configuration, the first transistor, the second transistor, the third transistor, and the fourth transistor can be used as pixel switching elements.

Application Example 11 In the electro-optical device according to any one of Application Examples 6 to 10, the other of the source / drain of the first transistor, the other of the source / drain of the second transistor, and the source / drain of the third transistor. And a signal line electrically connected to the other of the fourth transistor and the other of the source and drain of the fourth transistor, and the signal line preferably extends in the first direction.
According to this configuration, the first transistor, the second transistor, the third transistor, and the fourth transistor can control the passage and blocking of the information supplied to the signal line.

Application Example 12 An electronic apparatus including the electro-optical device according to any one of Application Examples 1 to 11.
According to this configuration, it is possible to realize an electronic apparatus including an electro-optical device that achieves both electrical reliability and high-quality image display.

FIG. 2 is a block diagram illustrating an electrical configuration of the electro-optical device according to the first embodiment. FIG. 3 illustrates a structure of a liquid crystal device according to Embodiment 1. 2 is a plan view illustrating pixels of the liquid crystal device according to Embodiment 1. FIG. 4 is a cross-sectional view illustrating a pixel of the liquid crystal device according to Embodiment 1. FIG. FIG. 3 is a diagram illustrating a pixel transistor of the electro-optical device according to the first embodiment. The top view which shows the structure of the three-plate-type projector as an electronic device. FIG. 6 is a plan view illustrating pixels of a liquid crystal device according to Embodiment 2. FIG. 6 illustrates a pixel transistor of an electro-optical device according to a second embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the scale of each layer and each member is made different from the actual scale so that each layer and each member can be recognized.

(Embodiment 1)
"Outline of electro-optical device"
FIG. 1 is a block diagram illustrating an electrical configuration of the electro-optical device according to the first embodiment. Hereinafter, the electrical configuration of the electro-optical device will be described with reference to FIG. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member can be recognized in the drawing. In describing the layers formed on the element substrate, the upper layer side or the surface side means the side opposite to the side where the substrate body of the element substrate is located (the side where the counter substrate is located), and the lower layer side is It means the side where the substrate body of the element substrate is located. Further, when describing the layer formed on the counter substrate, the upper layer side or the surface side is opposite to the side of the counter substrate where the substrate body is located (
Means the side where the element substrate is located), and the lower layer side means the side where the substrate body of the counter substrate is located.

As shown in FIG. 1, in this embodiment, the electro-optical device is a TN (Twisted Nema).
tic) mode or VA (Vertical Alignment) mode liquid crystal device 10
0. Such a liquid crystal device 100 includes a display region 10a in which a plurality of pixels 100a are arranged in a matrix in the central region. The liquid crystal device 100 includes an element substrate 10 (see FIG. 2). In the element substrate 10, a plurality of signal lines 6a and a plurality of scanning lines 3a intersecting with these signal lines 6a extend vertically and horizontally inside the display region 10a, and a pixel is located at a position corresponding to the intersecting portion. 100a is configured. Each of the pixels 100a is provided with a pixel switching element and a pixel electrode 9a provided so as to correspond to each pixel switching element.

The pixel switching element is a pixel transistor 30 formed of a field effect transistor.
Is used. The signal line 6 a is electrically connected to the source of the pixel transistor 30, the scanning line 3 a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30. Has been. Note that the source and the drain in the field effect transistor can be switched depending on the potential, but here, for convenience of explanation, the side to which the pixel electrode 9a is connected is the drain and the signal line 6a is connected. The side is the source. In this way, in the liquid crystal device 100, a plurality of pixels 10
A plurality of pixel electrodes 9a and a plurality of pixel transistors 30 are formed corresponding to each of 0a. The element formed in each pixel is not limited to a field effect transistor, and may be a bipolar transistor. In the following description, a field effect transistor is taken as an example, but when a bipolar transistor is used as a pixel switching element, in the following description, a source may be read as an emitter, a drain as a collector, and a gate as a base.

In the element substrate 10, a scanning line driving circuit 104 and a signal line driving circuit 101 are provided on the outer peripheral side of the display region 10a. The signal line driving circuit 101 is electrically connected to each signal line 6a, and sequentially supplies image signals supplied from an image processing circuit (not shown) to each signal line 6a. The scanning line driving circuit 104 is electrically connected to each scanning line 3a, and sequentially supplies a scanning signal to each scanning line 3a.

In each pixel 100a, the pixel electrode 9a faces a common electrode 21 (see FIG. 2) formed on a counter substrate 20 (see FIG. 2), which will be described later, via a liquid crystal 50 (see FIG. 2).
a. Each pixel 100a is provided with a holding capacitor 55 in parallel with the liquid crystal capacitor 50a in order to prevent fluctuation of the image signal held in the liquid crystal capacitor 50a. In the present embodiment, in order to form the storage capacitor 55, the element substrate 10 is formed with a capacitor line 5b extending across the plurality of pixels 100a, and the capacitor line 5b is applied with a common potential Vcom. It is electrically connected to the constant potential wiring 7r.

"Configuration of the liquid crystal device"
2A and 2B are diagrams for explaining the structure of the liquid crystal device according to the first embodiment. FIG. 2A is a plan view of the liquid crystal device viewed from the side of the counter substrate together with each component, and FIG. It is sectional drawing in -H '. Next, the structure of the electro-optical device will be described with reference to FIG. In addition, in the following forms, when it is described as “on XX” or “on the upper layer of XX”, it is arranged so as to be in contact with XX or so as to be in contact with the upper layer of XX. In the case of being arranged, or in the case of being arranged on the upper side of XX, or in the case of being arranged on the upper layer side of XX, or on the upper side of XX, When parts are placed in contact with each other and partly placed via other components, or partly placed on the upper layer side of XX and partly placed via other components ,
.

As shown in FIG. 2, in the liquid crystal device 100, the element substrate 10 (electro-optical device substrate) and the counter substrate 20 are bonded to each other with a sealing material 107 through a predetermined gap.
07 is provided in a frame shape along the outer edge of the counter substrate 20. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material 107a such as glass fiber or glass beads for setting the distance between the two substrates to a predetermined value. Liquid crystal device 1
In 00, a liquid crystal 50 (electro-optical material) made of various liquid crystal materials (electro-optical materials) is provided in a region surrounded by the sealing material 107 between the element substrate 10 and the counter substrate 20. . In this embodiment, the sealing material 107 is formed with a discontinuous portion used as the liquid crystal injection port 107c. The liquid crystal injection port 107c is sealed by the sealing material 108 after the liquid crystal material is injected. .

In the liquid crystal device 100, both the element substrate 10 and the counter substrate 20 are square, and the display region 10 a described with reference to FIG. 1 is provided as a square region in the approximate center of the liquid crystal device 100. Corresponding to the shape of the display area 10a, the sealing material 107 is also provided in a substantially square shape, and the outer side of the display area 10a is a rectangular frame-shaped outer peripheral area 10c.

In the element substrate 10, the signal line driving circuit 101 and the plurality of terminal electrodes 102 are formed along one side of the element substrate 10 in the outer peripheral region 10 c, and the scanning line driving circuit is formed along another side adjacent to the one side. 104 is formed. The terminal electrode 102 is connected to a flexible wiring board (not shown), and various potentials and various signals are input to the element substrate 10 through the flexible wiring board.

As will be described later in detail with reference to FIG. 4, the display region 10 a on the side of the one surface 10 s facing the counter substrate 20 out of the one surface 10 s and the other surface 10 t of the element substrate 10 is referred to FIG. 1. The pixel transistors 30 described above and the pixel electrodes 9a electrically connected to the pixel transistors 30 are formed in a matrix, and the alignment film 16 is formed on the upper layer side of the pixel electrodes 9a.

On the side of the one surface 10s of the element substrate 10, the outer peripheral area 10c outside the display area 10a.
Among them, in the peripheral area 10b having a square frame shape sandwiched between the display area 10a and the sealing material 107,
A dummy pixel electrode 9b formed simultaneously with the pixel electrode 9a is formed. Dummy pixel electrode 9
As for b, the adjacent dummy pixel electrodes 9b are connected by the connection part (not shown) narrower than the dummy pixel electrode 9b. The dummy pixel electrode 9b is applied with a common potential Vcom,
The disorder of the alignment of the liquid crystal molecules at the outer peripheral side end of the display region 10a is prevented. The dummy pixel electrode 9b reduces the difference in height between the display region 10a and the peripheral region 10b when the surface on which the alignment film 16 is formed on the element substrate 10 is flattened by polishing. This contributes to flattening the surface to be formed. In some cases, no potential is applied to the dummy pixel electrode 9b, and the dummy pixel electrode 9b is floated in terms of potential. In this case as well, the dummy pixel electrode 9b has a height between the display region 10a and the peripheral region 10b. This contributes to reducing the position difference and making the surface on which the alignment film 16 is formed flat.

A common electrode 21 is formed on the side of the one surface 20 s facing the element substrate 10 out of the one surface 20 s and the other surface 20 t of the counter substrate 20. The common electrode 21 is formed across the plurality of pixels 100a as substantially the entire surface of the counter substrate 20 or a plurality of strip electrodes. In the present embodiment, the common electrode 21 is formed on substantially the entire surface of the counter substrate 20.

A light shielding layer 29 is formed on the lower layer side of the common electrode 21 on the one surface 20 s side of the counter substrate 20, and an alignment film 26 is laminated on the upper layer side of the common electrode 21. The light shielding layer 29 is the display area 10.
It is formed as a frame portion 29 a extending along the outer peripheral edge of a, and the display area 10 a is defined by the inner peripheral edge of the light shielding layer 29. The light shielding layer 29 is also formed as a black matrix portion 29b that overlaps the inter-pixel region 10f sandwiched between the adjacent pixel electrodes 9a. Here, the frame portion 29a is formed at a position overlapping the dummy pixel electrode 9b,
The outer peripheral edge of the frame portion 29 a is in a position with a gap between it and the inner peripheral edge of the sealing material 107.
Therefore, the frame portion 29a and the sealing material 107 do not overlap.

In the liquid crystal device 100, the one surface 20 s of the counter substrate 20 is located outside the sealing material 107.
The inter-substrate conduction electrodes 25 are formed at the four corners on the side of the element substrate 10, and the one surface 1 of the element substrate 10.
On the 0s side, inter-substrate conduction electrodes 19 are formed at positions facing the four corners of the counter substrate 20 (inter-substrate conduction electrodes 25). The inter-substrate conduction electrode 25 is composed of a part of the common electrode 21. The inter-substrate conduction electrode 19 is electrically connected to the constant potential wiring 7 r to which the common potential Vcom is applied. The constant potential wiring 7 r is the terminal electrode 10 for applying the common potential among the terminal electrodes 102.
It is conducting to 2a. An inter-substrate conducting material 109 containing conductive particles is disposed between the inter-substrate conducting electrode 19 and the inter-substrate conducting electrode 25, and the common electrode 21 of the counter substrate 20 is connected to the inter-substrate conducting electrode 19. The element substrate 1 through the inter-substrate conductive material 109 and the inter-substrate conductive electrode 25.
It is electrically connected to the 0 side. Thus, the common potential Vcom is applied to the common electrode 21 from the element substrate 10. The sealing material 107 is provided along the outer peripheral edge of the counter substrate 20 with substantially the same width dimension. That is, the arrangement shape of the sealing material 107 in a plan view is a substantially square shape. However, the sealing material 107 is provided so as to pass through the inside avoiding the inter-substrate conducting electrodes 19 and 25 in a region overlapping with the corner portion of the counter substrate 20, and the corner portion of the sealing material 107 is substantially arc-shaped. .

The liquid crystal device 100 is a reflective electro-optical device, and the common electrode 21 is an indium tin oxide (ITO) film or an indium zinc tin oxide (Indi).
um Zinc Oxide (IZO) film or the like, and a pixel electrode 9
a is formed of a reflective conductive film such as an aluminum film. In such a reflective liquid crystal device (the liquid crystal device 100), light incident from the counter substrate 20 side of the element substrate 10 and the counter substrate 20 is reflected by the element substrate 10 and emitted according to an image signal. The image is displayed after being modulated.

The liquid crystal device 100 can be used as a color display device of an electronic device such as a mobile computer or a mobile phone. In this case, a color filter (not shown) is formed on the counter substrate 20 or the element substrate 10. The liquid crystal device 100 can be used as electronic paper. In the liquid crystal device 100, the polarizing film, the retardation film, the polarizing plate, etc. are in a predetermined direction with respect to the liquid crystal device 100 according to the type of the liquid crystal 50 to be used and the normally white mode / normally black mode. Be placed. Furthermore, the liquid crystal device 100 can be used as a light valve for RGB in a projection display device (liquid crystal projector) described later. In this case, the color filters are not formed on each of the RGB liquid crystal devices 100 because the light of each color separated through the RGB color separation dichroic mirror is incident as projection light.

In the present embodiment, the case where the liquid crystal device 100 is an RGB reflective light valve of a projection display device will be mainly described. Further, in the liquid crystal device 100, a case where a nematic liquid crystal compound having a negative dielectric anisotropy is used as the liquid crystal 50 and a VA mode display is performed will be mainly described.

"Pixel configuration"
FIG. 3 is a plan view illustrating pixels of the liquid crystal device according to the first embodiment. 4 is a cross-sectional view illustrating a pixel of the liquid crystal device according to the first embodiment, and corresponds to a cross section taken along line FF ′ of FIG. Next, the structure of the pixel 100a will be described with reference to FIGS. In FIG. 3, for the sake of easy understanding, only the portions related to the present invention are shown, and other portions are omitted. Four pixels 10
0a is named pixel (1,1), pixel (1,2), pixel (2,1), pixel (2,2), and semiconductor film 1a includes pixel (1,1) and pixel (2). , 2) using solid lines and hatching, and the other pixels 100a are drawn with broken lines. The scanning line 3a is a pixel (1, 1).
The pixel (1, 2) is drawn using a solid line, and the other pixel 100a is drawn using a broken line. The drain electrode 4a is drawn using a solid line and hatching in the pixel (1,1) and the pixel (2,1), and is drawn in a broken line in the other pixels 100a. The capacitor line 5b is a pixel (1,
1) and pixels (1, 2) are drawn using solid lines and hatching, and other pixels 100a are drawn with broken lines. The signal line 6a is drawn using a solid line in the pixel (1, 1) and the pixel (2, 1), and is drawn in a broken line in the other pixels 100a. Contact hole 41a, contact hole 42a, and contact hole 42b are pixel (1,1) and pixel (2,1).
The other pixels 100a are drawn with broken lines. Pixel electrode 9
a is drawn using a solid line and hatching in the pixel (1, 1) and the pixel (2, 2), and is drawn in a broken line in the other pixels 100a.

As shown in FIG. 3, a pixel electrode 9 a is formed on each of the plurality of pixels 100 a on one surface 10 s of the element substrate 10 facing the counter substrate 20. The signal line 6a extends linearly in the first direction (Y direction in the present embodiment), and the scanning line 3a extends in the second direction intersecting the first direction (
In this embodiment, it extends linearly in the X direction). In the present embodiment, the first direction and the second direction are substantially orthogonal, but the angle at which they intersect may be other than 90 °. A pixel transistor 30 is formed corresponding to the intersection of the signal line 6a and the scanning line 3a, and the pixel transistor 30 is formed by utilizing the intersection region of the signal line 6a and the scanning line 3a and its vicinity. ing. Capacitor lines 5b are formed on the element substrate 10, and such capacitor lines 5b are formed.
A common potential Vcom is applied to b. In the present embodiment, the capacitor line 5b is formed to extend so as to substantially overlap the scanning line 3a. An upper light shielding layer 7a (see FIG. 4) is formed on the upper layer side of the pixel transistor 30, and the upper light shielding layer 7a extends so as to overlap the signal line 6a. A lower light-shielding layer 8a (see FIG. 4) is formed on the lower layer side of the pixel transistor 30, and the lower light-shielding layer 8a includes a main line portion linearly extending so as to overlap the scanning line 3a and a signal line 6a. And a sub-line portion extending so as to overlap the signal line 6a at the intersection of the scanning line 3a.

As shown in FIG. 4, the element substrate 10 includes a light-transmitting substrate body 10w such as a quartz substrate or a glass substrate.
The pixel electrode 9a formed on the substrate surface on the liquid crystal 50 side (one surface 10s side facing the counter substrate 20), the pixel transistor 30 as a pixel switching element, and the alignment film 16 are mainly configured. An insulating film such as a fourth interlayer insulating film 45 is provided between the pixel electrode 9a that is a reflective film and the pixel transistor 30 that is a pixel switching element. Counter substrate 2
Reference numeral 0 denotes a translucent substrate body 20w such as a quartz substrate or a glass substrate, a light shielding layer 29 formed on the surface of the liquid crystal 50 (one surface 20s facing the element substrate 10), the common electrode 21, and an alignment film 26 is the main component.

In the element substrate 10, a lower-side light-shielding layer 8 a made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film is formed on the one surface 10 s side of the substrate body 10 w. ing. The lower light-shielding layer 8a is made of a light-shielding film such as tungsten silicide (WSi), and when the light that has passed through the liquid crystal device 100 is reflected by another member, such reflected light is incident on the semiconductor film 1a and the pixel transistor. 30 prevents a malfunction caused by the photocurrent. In some cases, the lower light shielding layer 8a may be configured as a scanning line.
A gate electrode 3c, which will be described later, and the lower light shielding layer 8a are electrically connected.

A light-transmitting base insulating film 12 is formed on the upper surface side of the lower light shielding layer 8a on the one surface 10s side of the substrate body 10w, and the semiconductor film 1a is provided on the surface side of the base insulating film 12. A pixel transistor 30 is formed. The base insulating film 12 is a silicon oxide film (Non-doped silicate glass, NSG film) into which impurities are not intentionally introduced, or a silicon oxide film containing phosphorous (phospho silicate gl).
ass, PSG film), silicon oxide film containing boron (Boro silicate g)
glass, a silicon oxide film containing boron and phosphorus (Boro-phospho)
a silicon oxide film (including silicate glass) such as a silicon glass (referred to as silicate glass or BPSG film), or a silicon nitride film. Such a base insulating film 12 is made of silane gas (S
iH ₄ ), dichloride silane (SiCl ₂ H ₂ ), TEOS (tetraethoxysilane / tetra ·
Atmospheric pressure CVD method or reduced pressure CVD method using ethyl ortho silicate / Si (OC ₂ H ₅ ) ₄ ), TEB (tetraethyl boatrate), TMOP (tetramethyloxyphosphate), Alternatively, it is formed by a plasma CVD method or the like.

The pixel transistor 30 includes a semiconductor film 1a having a long side direction in the extending direction of the signal line 6a, and a central portion in the length direction of the semiconductor film 1a extending in a direction orthogonal to the length direction of the semiconductor film 1a. And a gate electrode 3c overlapping with the gate electrode 3c. The gate electrode 3c is a part of the scanning line 3a,
This is the portion of the scanning line 3a that overlaps the semiconductor film 1a in plan view. The pixel transistor 30
A translucent gate insulating film 2 is provided between the semiconductor film 1a and the gate electrode 3c. The semiconductor film 1a has a channel formation region 1 facing the gate electrode 3c through the gate insulating film 2.
g, and a source 1b and a drain 1c on both sides of the channel forming region 1g.
It has. The pixel transistor 30 has an LDD structure. Therefore, source 1
Each of b and the drain 1c includes a low concentration region on both sides of the channel formation region 1g, and a high concentration region in a region adjacent to the low concentration region on the opposite side to the channel formation region 1g.

The semiconductor film 1a is composed of a polysilicon film (polycrystalline silicon film) or the like. The gate insulating film 2 includes a first gate insulating film 2a made of a silicon oxide film obtained by thermally oxidizing the semiconductor film 1a and a silicon oxide film formed by a low pressure CVD method under a high temperature condition of 700 to 900 ° C. It has a two-layer structure with a two-gate insulating film 2b. The gate electrode 3c and the scanning line 3a are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the gate electrode 3c has a two-layer structure of a conductive polysilicon film and a tungsten silicide film.

A translucent first interlayer insulating film 41 made of a silicon oxide film such as an NSG film, a PSG film, a BSG film, or a BPSG film is formed on the upper layer side of the gate electrode 3c. A drain electrode 4a extends on the upper layer side. The drain electrode 4a is a conductive polysilicon film,
It is made of a conductive film such as a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the drain electrode 4a is made of a titanium nitride film. The drain electrode 4a is formed so as to partially overlap the drain 1c (drain on the pixel electrode side) of the semiconductor film 1a, and through the first interlayer insulating film 41 and the contact hole 41a penetrating the gate insulating film 2. Is electrically connected to the drain 1c.

A translucent etching stopper layer 49 made of a silicon oxide film or the like and a translucent dielectric layer 40 are formed on the upper layer side of the drain electrode 4a, and a capacitance is formed on the upper layer side of the dielectric layer 40. A line 5b is formed. As the dielectric layer 40, a silicon compound such as a silicon oxide film or a silicon nitride film can be used, and an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, zirconium A dielectric layer having a high dielectric constant such as an oxide film can be used. The capacitor line 5b is made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the capacitor line 5b has a three-layer structure of a titanium nitride film, an aluminum film, and a titanium nitride film. The capacitor line 5b overlaps the drain electrode 4a through the dielectric layer 40, and the storage capacitor 55
Is configured.

A second interlayer insulating film 42 is formed on the upper layer side of the capacitor line 5b. On the upper layer side of the second interlayer insulating film 42, the signal line 6a and the relay electrode 6b are formed of the same conductive film. . The second interlayer insulating film 42 is made of a silicon oxide film. The signal line 6a and the relay electrode 6b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the signal line 6a and the relay electrode 6b are made of an aluminum alloy film or a film in which a titanium nitride film and an aluminum film are laminated in two to four layers. The signal line 6a is connected to the second interlayer insulating film 4
2. Conductive to the source 1b (signal line side source / drain) through the contact hole 42a penetrating the etching stopper layer 49, the first interlayer insulating film 41 and the gate insulating film 2.
The relay electrode 6 b is electrically connected to the drain electrode 4 a through a contact hole 42 b that penetrates the second interlayer insulating film 42 and the etching stopper layer 49.

A translucent third interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the signal line 6a and the relay electrode 6b. The upper light shielding layer is formed on the upper layer side of the third interlayer insulating film 44. 7a and relay electrode 7b are formed of the same conductive film. The third interlayer insulating film 44 is made of, for example, a silicon oxide film formed by a plasma CVD method using tetraethoxysilane and oxygen gas, a plasma CVD method using silane gas and nitrous oxide gas, or the like. Is flattened. The upper light shielding layer 7a and the relay electrode 7b are made of a conductive film such as a conductive polysilicon film, a metal silicide film, a metal film, or a metal compound film. In the present embodiment, the upper light shielding layer 7a and the relay electrode 7b are made of an aluminum alloy film or a film in which a titanium nitride film and an aluminum film are laminated in two to four layers. The relay electrode 7 b is electrically connected to the relay electrode 6 b through a contact hole 44 a that penetrates the third interlayer insulating film 44. The upper light shielding layer 7a extends so as to overlap the signal line 6a and functions as a light shielding layer. The upper light shielding layer 7
a may be electrically connected to the capacitor line 5b and used as a shield layer.

A translucent fourth interlayer insulating film 45 made of a silicon oxide film or the like is formed on the upper layer side of the upper light shielding layer 7a and the relay electrode 7b, and aluminum is formed on the upper layer side of the fourth interlayer insulating film 45. A pixel electrode 9a (reflective film) of a reflective metal film including a film, an aluminum alloy film or the like is formed. A contact hole 45a is formed in the fourth interlayer insulating film 45 so as to penetrate the fourth interlayer insulating film 45 and reach the relay electrode 7b. The pixel electrode 9a is electrically connected to the relay electrode 7b through the contact hole 45a. Connected. As a result, the pixel electrode 9a is connected to the relay electrode 7b,
It is electrically connected to the drain 1c through the relay electrode 6b and the drain electrode 4a. An enhanced reflection film 18 is provided on the pixel electrode 9a. The increased reflection film 18 includes at least a first light transmissive film 181 having a first refractive index and a second light transmissive film 182 having a second refractive index. As a result, the reflective reflection film 18 increases the reflectance on the surface of the pixel electrode 9a and also serves as a moisture-proof film. The fourth interlayer insulating film 45, the pixel electrode 9a, and the reflective reflection film 18 will be described in detail later.

An alignment film 16 made of polyimide or an inorganic alignment film is formed on the upper surface of the increased reflection film 18. In the present embodiment, the alignment film 16 is made of SiO _x (x <2), SiO ₂ , TiO ₂ , Mg.
It consists of oblique vapor deposition films (gradient vertical alignment film / inorganic alignment film) such as O, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ .

"Configuration of counter substrate"
In the counter substrate 20, a translucent substrate body 20w (translucent substrate) such as a quartz substrate or a glass substrate.
The liquid crystal 50 side surface (one surface 20s facing the element substrate 10) is provided with a light shielding layer 29, an insulating film 28 made of a silicon oxide film, and a common electrode 21 made of a translucent conductive film such as an ITO film. An alignment film 26 made of polyimide or an inorganic alignment film is formed so as to cover the common electrode 21. In this embodiment, the common electrode 21 is made of an ITO film, and the alignment film 26 is
Similar to the alignment film 16, SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂
It consists of an oblique vapor deposition film (tilted vertical alignment film / inorganic alignment film) such as O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ . The alignment film 16 and the alignment film 26 cause the nematic liquid crystal compound having negative dielectric anisotropy used for the liquid crystal 50 to be tilted and vertically aligned, and the liquid crystal device 100 operates as a normally black VA mode.
In the present embodiment, as the alignment film 16 and the alignment film 26, among various inorganic alignment films, a silicon oxide film (
An obliquely deposited film of SiO _x ) is used.

Note that the signal line driver circuit 101 and the scanning line driver circuit 104 described with reference to FIGS.
A complementary transistor circuit including an n-channel type driving transistor and a p-channel type driving transistor is configured. Here, the driving transistor is formed by utilizing a part of the manufacturing process of the pixel transistor 30. Therefore, the region where the signal line driver circuit 101 and the scanning line driver circuit 104 are formed in the element substrate 10 also has a cross-sectional configuration substantially similar to the cross-sectional configuration shown in FIG.

"Pixel transistor"
FIG. 5 is a diagram illustrating a pixel transistor of the electro-optical device according to the first embodiment.
Next, the pixel and the pixel transistor will be described with reference to FIGS.

As shown in FIG. 3, the electro-optical device according to the present embodiment includes a first transistor Tr <b> 1 and a second transistor Tr <b> 2 as the pixel transistor 30. The first transistor Tr1 includes a first portion P1 of the first semiconductor film 1a and a first gate electrode 3c intersecting the first portion P1, and the second transistor Tr2 is in a first direction with respect to the first semiconductor film 1a. The second portion P2 of the second semiconductor film 1a adjacent in the present embodiment (Y direction, row direction) and the second gate electrode 3c intersecting the second portion P2 are included. The first pixel electrode 9a is electrically connected to one of the source / drain of the first transistor Tr1 (referred to as a drain in this embodiment), and the other of the source / drain of the first transistor Tr1 (referred to as a source in this embodiment). Is electrically connected to a signal line 6a. Similarly, the second transistor Tr2
The second pixel electrode 9a is electrically connected to one of the source drains (referred to as a drain in this embodiment), and the other of the source drains of the second transistor Tr2 (referred to as a source in this embodiment) is connected to a signal line. 6a is electrically connected.

In short, the first transistor Tr1 and the second transistor Tr2 are any two pixel transistors 30 adjacent in the first direction, and the first gate electrode 3c and the second gate electrode 3c are adjacent two scanning lines 3a. Respectively. The portion of the scanning line 3a that intersects the first semiconductor film 1a is the first gate electrode 3c constituting the first transistor Tr1, and the portion of the scanning line 3a that intersects the second semiconductor film 1a is the second transistor Tr2. Is the second gate electrode 3c.

The signal line extends along the first direction, the first portion P1 of the first semiconductor film 1a, and the second semiconductor film 1
The second part P2 of a, a part of the third part P3 of the first semiconductor film 1a, and a part of the fourth part P4 of the second semiconductor film 1a are covered. The signal line 6a is electrically connected to the source of the first transistor Tr1 and the source of the second transistor Tr2 through the contact hole 42a, and the first transistor Tr1 and the second transistor Tr2 supply the signal line 6a. Control is made to pass and block the information (image signal) that has passed through the pixel electrode 9a. The first transistor Tr1 and the second transistor Tr2 are used as pixel switching elements.

The first portion P1 of the first semiconductor film 1a extends along the first direction, and the first semiconductor film 1a includes a third portion P3 extending along the second direction intersecting the first direction. The sum (L1 + L3) of the length L1 of the first portion P1 and the length L3 of the third portion P3 is the distance DG between the first gate electrode 3c and the second gate electrode 3c and the width GW of the first gate electrode 3c. It is larger than the sum (DG + GW). The distance DG between the first gate electrode 3c and the second gate electrode 3c and the width G of the first gate electrode 3c
The sum (DG + GW) with W is the pixel pitch in the first direction. Therefore, by doing so,
The length (L1 + L3) of the first semiconductor film 1a is longer than the pixel pitch. That is, the length of the pixel 100a can be made shorter than the length of the first semiconductor film 1a constituting the first transistor Tr1, and miniaturization can be promoted.

Similarly, the second portion P2 of the second semiconductor film 1a extends along the first direction, and the second semiconductor film 1a
Includes a fourth portion P4 extending along a second direction intersecting the first direction. Second part P
The sum (L2 + L4) of the length L2 of 2 and the length L4 of the fourth portion P4 is the sum of the distance DG between the first gate electrode 3c and the second gate electrode 3c and the width GW of the first gate electrode 3c ( DG + GW). Therefore, by doing so, the length (L2 + L4) of the second semiconductor film 1a becomes longer than the pixel pitch. That is, the length of the pixel 100a can be made shorter than the length of the second semiconductor film 1a constituting the second transistor Tr2, and miniaturization can be promoted. In other words, the electrical reliability is ensured by the relatively large first transistor Tr1 and second transistor Tr2, and the display region 10 is formed using the fine pixel 100a with a reduced pixel pitch.
A high-quality image can be displayed on a.

In general, the sum (L1 + L3) of the length L1 of the first portion P1 and the length L3 of the third portion P3 is the sum of the length L2 of the second portion P2 and the length L4 of the fourth portion P4 (L2 + L4). Is preferably approximately equal to This is because the first semiconductor film 1a constituting the first transistor Tr1 and the second semiconductor film 1a constituting the second transistor Tr2 have the same size, and the same transistor is repeated for each row.

As described above, in the present embodiment, the first transistor Tr1 and the second transistor Tr2 have the same configuration. Hereinafter, the configuration of these transistors will be described in detail by taking the first transistor Tr1 as an example. In the following description, the first transistor Tr1 is read as the second transistor Tr2, the first semiconductor film 1a is read as the second semiconductor film 1a, the first part P1 is read as the second part P2, and the third part P3 is read as the second part. If it is read as the four portions P4, the same configuration holds for the second transistor Tr2 and the second semiconductor film 1a.

As shown in FIG. 5, the first portion P of the first semiconductor film 1a constituting the first transistor Tr1.
Reference numeral 1 denotes a source pad region SP, a source region S, a source side LDD region SLDD, a channel formation region 1g, a drain side LDD region DLDD, and a part of the drain region (first drain region D
1) is included. On the other hand, the third portion P3 of the first semiconductor film 1a constituting the first transistor Tr1 has another drain region (second drain region D2) and the drain pad region D.
P is included. Source pad region SP, source region S, and source side LDD region SLDD
Are the source 1b of the first transistor Tr1, and the drain side LDD region DLDD, the drain region, and the drain pad region DP are the drain 1c of the first transistor Tr1. The first semiconductor film 1a is bent in the drain region and is L-shaped as a whole.

Next, the effect of this embodiment will be verified. As an example, the length of the source pad region SP is 1.5.
Micrometer (μm), the length of the source region S is 1.5 μm (μm), the length of the source side LDD region SLDD is 1.0 μm (μm), and the length of the channel forming region 1 g is 2. 0 micrometer (μm), the length of the drain side LDD region DLDD is 1.0 micrometer (μm), the length of the drain region is 1.5 micrometers (μ
m), the length of the drain pad region DP is 1.5 micrometers (μm), and the semiconductor film 1a
The interval DS (see FIG. 3, the interval between the first semiconductor film 1a and the second semiconductor film 1a) is set to 0.5 micrometers (μm). In the present embodiment, the first semiconductor film 1a is bent in the drain region, the length of the first drain region D1 is 0.75 micrometers (μm), and the length of the second drain region D2 is 0.75 micrometers (μm). ). Therefore, the length (L1 + L3) of the first semiconductor film 1a is 10 micrometers (μm), but the length LS along the first direction of the first semiconductor film 1a is 8.5 micrometers (μm). . Since the distance DS between the semiconductor films 1a is 0.5 micrometers (μm), the pixel pitch (DG + GW = LS + DS) in the first direction is 9.0 micrometers (μ) in the present embodiment.
m). Assuming a full high-definition electro-optical device with 1080 rows × 1920 columns, the display area 10a is 10 mm long, 17 mm wide, and 0.78 inches diagonal.

On the other hand, when the same dimension is applied to a conventional liquid crystal device, the length of the semiconductor film is equal to the length along the first direction of the semiconductor film, and is 10 micrometers (μm), so the pixel pitch is 10.5 micrometers. (Μm). In this case, the size of the display area of the electro-optical device for full high vision is 11 mm long, 20 mm wide, and 0.91 inch diagonal, and it has been impossible to further reduce the size. On the other hand, in the electro-optical device of this embodiment, since the semiconductor film 1a is bent in an L shape, miniaturization can be promoted as described above.

"Electronics"
FIG. 6 is a plan view showing a configuration of a three-plate projector as an electronic apparatus. Next, FIG.
With reference to FIG. 1, a projection display apparatus 1000 will be described as an example of the electronic apparatus according to the present embodiment.

As shown in FIG. 6, the projection display apparatus 1000 includes a light source unit 1021 that generates light source light, and light source light emitted from the light source unit 1021 in three colors of red light R, green light G, and blue light B. It has a color separation light guide optical system 1023 that separates into color light, and a light modulator 1025 that is illuminated by the light source light of each color emitted from the color separation light guide optical system 1023. In addition, the projection display device 100
Reference numeral 0 denotes a cross dichroic prism 1027 (combining optical system) that synthesizes image light of each color emitted from the light modulation unit 1025 and a projection optical system 1029 that projects image light that has passed through the cross dichroic prism 1027 onto a screen (not shown). And.

In the projection display apparatus 1000, the light source unit 1021 includes a light source 1021a, a pair of fly-eye optical systems 1021d and 1021e, a polarization conversion member 1021g, and a superimposing lens 102.
1i. In the present embodiment, the light source unit 1021 is a reflector 1 having a parabolic surface.
021f, and emits parallel light. The fly-eye optical systems 1021d and 1021e are composed of a plurality of element lenses arranged in a matrix in a plane orthogonal to the system optical axis, and the light source light is divided by these element lenses and individually condensed and diverges. Polarization conversion member 1021
g converts light source light emitted from the fly-eye optical system 1021e into, for example, only a p-polarized component parallel to the drawing and supplies it to the optical path downstream optical system. The superimposing lens 1021i allows the plurality of electro-optical devices provided in the light modulation unit 1025 to uniformly illuminate each other by appropriately converging the light source light that has passed through the polarization conversion member 1021g as a whole.

The color separation light guide optical system 1023 includes a cross dichroic mirror 1023a, a dichroic mirror 1023b, and reflection mirrors 1023j and 1023k. In the color separation light guide optical system 1023, the substantially white light source light from the light source unit 1021 enters the cross dichroic mirror 1023a. The red light R reflected by one of the first dichroic mirrors 1031a constituting the cross dichroic mirror 1023a is reflected by the reflecting mirror 1023j, passes through the dichroic mirror 1023b, and transmits the incident side polarizing plate 1037r and p-polarized light. The light enters the electro-optical device (red liquid crystal device 100R) as p-polarized light through the wire grid polarizer 1032r that reflects s-polarized light and the optical compensation plate 1039r.

The green light G reflected by the first dichroic mirror 1031a is reflected by the reflection mirror 102.
3j, and then reflected by the dichroic mirror 1023b to transmit the incident-side polarizing plate 1037g and transmit the p-polarized light while reflecting the s-polarized light.
The light is incident on the electro-optical device (green liquid crystal device 100G) as p-polarized light through 32g and the optical compensator 1039g.

On the other hand, the blue light B reflected by the other second dichroic mirror 1031b constituting the cross dichroic mirror 1023a is reflected by the reflection mirror 1023k,
Incident-side polarizing plate 1037b transmits the p-polarized light, while reflecting the s-polarized light, and enters the electro-optical device (blue liquid crystal device 100B) as the p-polarized light through the optical grid 1039b and the optical compensation plate 1039b. To do. Optical compensation plates 1039r, 1039g, 1039
In b, the characteristics of the liquid crystal are optically compensated by adjusting the polarization states of incident light and outgoing light to the electro-optical device.

In the projection type display apparatus 1000 configured as described above, the optical compensation plates 1039r, 1039g,
Each of the three color lights incident through 1039b is modulated in each electro-optical device. At this time, of the modulated light emitted from the electro-optical device, the s-polarized component light is reflected by the wire grid polarizing plates 1032r, 1032g, and 1032b, and the outgoing side polarizing plates 1038r and 1038g.
Then, the light enters the cross dichroic prism 1027 through 1038b. The cross dichroic prism 1027 includes a first dielectric multilayer film 1027a and a second dielectric film that intersect in an X shape.
A dielectric multilayer film 1027b is formed. One of the first dielectric multilayer films 1027a reflects the red light R, and the other second dielectric multilayer film 1027b reflects the blue light B. Therefore, the three colors of light are combined by the cross dichroic prism 1027 and emitted to the projection optical system 1029. The projection optical system 1029 projects the color image light combined by the cross dichroic prism 1027 onto a screen (not shown) at a desired magnification.

(Other projection display devices)
In addition, about a projection type display apparatus, you may comprise so that the light source etc. which radiate | emit the light of each color may be used as a light source part, and each color light radiate | emitted from the LED light source may be supplied to another liquid crystal device.

(Other electronic devices)
As for the electro-optical device described in detail in the present embodiment, in addition to the above electronic devices, mobile phones, personal digital assistants (PDAs), digital cameras, liquid crystal televisions, car navigation devices, video phones, You may use as a direct view type | mold display apparatus in electronic devices, such as an apparatus provided with the POS terminal and the touch panel.

As described above, the electro-optical device according to this embodiment achieves both electrical reliability and high-quality image display. In addition, an electronic apparatus including such an excellent electro-optical device can be realized.

(Embodiment 2)
"Forms with different semiconductor film shapes"
FIG. 7 is a plan view illustrating pixels of the liquid crystal device according to the second embodiment. FIG. 8 is a diagram illustrating a pixel transistor of the electro-optical device according to the second embodiment. Next, the electro-optical device according to the second embodiment will be described with reference to FIGS. In addition, about the component same as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted. 7 corresponds to a cross-sectional view of a pixel of the liquid crystal device according to Embodiment 1 shown in FIG. Furthermore, in FIG.
For the sake of clarity, only the parts related to the present invention are shown, and other parts are omitted. Also, 16 pixels are named from pixel (1,1) to pixel (4,4), and the semiconductor film 1a uses solid lines and hatching from pixel (1,1) to pixel (4,4). It is drawn. Scan line 3
a is also drawn from the pixel (1, 1) to the pixel (4, 4) using a solid line. Drain electrode 4a
Is drawn using a solid line and hatching for the pixel (3, 2) and the pixel (4, 2), and is drawn with a broken line for the other pixels 100a. The capacitor line 5b is drawn using a solid line and hatching in the pixel (3, 3) and the pixel (4, 3), and is drawn in a broken line in the other pixels 100a. As in the first embodiment, the capacitor line 5b is formed in the second direction (
In the present embodiment, it extends in the X direction and the row direction, and overlaps the scanning line 3a in plan view. The signal line 6a is drawn with a solid line at the pixel (1,1), the pixel (2,1), the pixel (3,1), and the pixel (4,1), and drawn with a broken line at the other pixels 100a. It is. Contact hole 4
1a and contact hole 42a are drawn from pixel (1,1) to pixel (4,4) using solid lines. The contact hole 42b is drawn using a solid line in the pixel (3, 2) and the pixel (4, 2), and is drawn in a broken line in the other pixels 100a. The pixel electrode 9a is a pixel (1,
It is drawn using solid lines and hatching in 1), and is drawn with broken lines in the other pixels 100a.

In the first embodiment, the repetitive pattern in the row direction is every one row. However, as shown in FIG. 7, in the electro-optical device of this embodiment, the repetitive pattern in the row direction is every two rows. Accordingly, the source pad region SP (see FIG. 8) is shared by two transistors. Other configurations are almost the same as those of the first embodiment.

As shown in FIG. 7, in the electro-optical device of the present embodiment, the first transistor Tr1, the second transistor Tr2, the third transistor Tr3,
And a fourth transistor Tr4. The first transistor Tr1 includes a first portion P1 of the first semiconductor film 1a and a first gate electrode 3c intersecting the first portion P1, and the second transistor Tr2 is in a first direction with respect to the first semiconductor film 1a. (Y direction in this embodiment,
The second portion P2 of the second semiconductor film 1a adjacent in the row direction) and the second gate electrode 3c intersecting the second portion P2 are included. The third transistor Tr3 includes a fifth portion P5 of the first semiconductor film 1a and a third gate electrode 3c intersecting the fifth portion P5, and the fourth transistor Tr4 is a sixth portion of the second semiconductor film 1a. P6 and a fourth gate electrode 3c intersecting with the sixth portion P6 are included. The first pixel electrode 9a is electrically connected to one of the source / drain of the first transistor Tr1 (referred to as a drain in this embodiment), and the other of the source / drain of the first transistor Tr1 (referred to as a source in this embodiment). Is electrically connected to a signal line 6a. Similarly, the second pixel electrode 9a is electrically connected to one of source and drain of the second transistor Tr2 (referred to as a drain in this embodiment), and the other of the source and drain of the second transistor Tr2 (source in the present embodiment). The signal line 6a is electrically connected. Similarly, the third pixel electrode 9a is electrically connected to one of the source and drain of the third transistor Tr3 (referred to as a drain in this embodiment), and the other of the source and drain of the third transistor Tr3 (in the present embodiment, the source drain). The signal line 6a is electrically connected. Further, the fourth pixel electrode 9a is electrically connected to one of the source and drain of the fourth transistor Tr4 (referred to as a drain in the present embodiment), and the other of the source and drain of the fourth transistor Tr4 (the source and drain in the present embodiment). The signal line 6a is electrically connected to the signal line.

In short, the first transistor Tr1, the third transistor Tr3, the second transistor Tr2, and the fourth transistor Tr4 are any four pixel transistors 30 adjacent in this order in the first direction, and the first gate electrode 3c and the first transistor Tr4. The three gate electrodes 3c, the second gate electrode 3c, and the fourth gate electrode 3c are a part of the four scanning lines 3a adjacent in this order. The portion of the scanning line 3a that intersects the first semiconductor film 1a is the first gate electrode 3c constituting the first transistor Tr1, and the portion of the scanning line 3a that intersects the first semiconductor film 1a is the third transistor Tr3. Is a third gate electrode 3c. Furthermore, the adjacent scanning line 3a
The portion intersecting with the second semiconductor film 1a is the second gate electrode 3c constituting the second transistor Tr2. Further, the portion of the scanning line 3a adjacent to the second semiconductor film 1a intersects with the fourth gate electrode 3c constituting the fourth transistor Tr4.

The signal line extends along the first direction, and the source pad of the first semiconductor film 1a (part of the third portion P3 and part of the seventh portion P7) and the source pad of the second semiconductor film 1a (fourth portion). Part of P4 and part of eighth part P8). The signal line 6a is connected via the contact hole 42a.
Are electrically connected to the source of the first transistor Tr1, the source of the second transistor Tr2, the source of the third transistor Tr3, the source of the fourth transistor Tr4, and the first transistor Tr1, the second transistor Tr2, and the third transistor Tr4. Transistor Tr3
The fourth transistor Tr4 controls passage and blocking of information (image signal) supplied to the signal line 6a to the pixel electrode 9a. The first transistor Tr1, the second transistor Tr2, the third transistor Tr3, and the fourth transistor Tr4 are used as pixel switching elements.

The first portion P1 and the fifth portion P5 of the first semiconductor film 1a extend along the first direction, and the first semiconductor film 1a includes the third portion P3 and the second portion extending along the second direction intersecting the first direction. Seven parts P7 are included. The sum (L1 + L3 + L5 + L7) of the length L1 of the first portion P1, the length L3 of the third portion P3, the length L5 of the fifth portion P5, and the length L7 of the seventh portion P7 is the first gate electrode 3.
The sum of the distance DG between c and the second gate electrode 3c and the width GW of the first gate electrode 3c (DG + GW
Bigger than). The sum (DG + GW) of the distance DG between the first gate electrode 3c and the second gate electrode 3c and the width GW of the first gate electrode 3c is the length of two rows in the first direction (twice the pixel pitch). ) Therefore, by doing so, the length of the first semiconductor film 1a (L1 + L3 + L5 +
L7) is longer than twice the pixel pitch. That is, the length of the pixel 100a can be made shorter than the length of the portion used as the first transistor Tr1 in the first semiconductor film 1a, and the portion used as the third transistor Tr3 in the first semiconductor film 1a. The length of the pixel 100a can be made shorter than the length of the pixel 100a, and miniaturization can be promoted.

Similarly, the second portion P2 and the sixth portion P6 of the second semiconductor film 1a extend along the first direction,
The second semiconductor film 1a includes a fourth portion P4 and an eighth portion P8 extending along a second direction intersecting the first direction. The length L2 of the second part P2, the length L4 of the fourth part P4 and the sixth part P
6 (L2 + L4 + L6 + L8) is the sum of the distance DG between the first gate electrode 3c and the second gate electrode 3c and the width GW of the first gate electrode 3c (L2 + L4 + L6 + L8). D
G + GW). Therefore, by doing so, the length of the second semiconductor film 1a (L2 + L4
+ L6 + L8) is longer than twice the pixel pitch. That is, the length of the pixel 100a can be made shorter than the length of the portion used as the second transistor Tr2 in the second semiconductor film 1a, and the length of the portion used as the fourth transistor Tr4 in the second semiconductor film 1a. In addition, the length of the pixel 100a can be shortened, and miniaturization can be promoted. In other words,
A relatively large first transistor Tr1, second transistor Tr2, third transistor Tr3, and fourth transistor Tr4 ensure electrical reliability and use a fine pixel 100a with a reduced pixel pitch to display the region 10a. It is possible to display a high-quality image.

In general, the sum (L1 + L3) of the length L1 of the first portion P1 and the length L3 of the third portion P3 is the sum of the length L2 of the second portion P2 and the length L4 of the fourth portion P4 (L2 + L4). Is preferably approximately equal to Furthermore, the sum of the length L5 of the fifth portion P5 and the length L7 of the seventh portion P7 (L
5 + L7) is the sum of the length L6 of the sixth portion P6 and the length L8 of the eighth portion P8 (L6 + L8)
Is preferably approximately equal to First transistor Tr1 and third transistor Tr3
A first semiconductor film 1a, a second transistor Tr2, and a fourth transistor Tr
This is because the second semiconductor film 1a forming 4 is the same size and the same transistor is repeated every two rows.

The sum (L1 + L3) of the length L1 of the first portion P1 and the length L3 of the third portion P3 is the sum (L5 + L7) of the length L5 of the fifth portion P5 and the length L7 of the seventh portion P7. It is preferable that they are almost equal. Furthermore, the sum of the length L2 of the second portion P2 and the length L4 of the fourth portion P4 (L2 + L4)
) Is preferably substantially equal to the sum (L6 + L8) of the length L6 of the sixth portion P6 and the length L8 of the eighth portion P8. In short, the first semiconductor film 1a is 18 with respect to the center of the source pad.
Preferably, the second semiconductor film 1a has a rotational symmetry of 180 ° with respect to the center of the source pad. Thus, the first transistor Tr1 and the third transistor T
r3 is the same size and symmetrical, and the second transistor Tr2 and the fourth transistor Tr4
This is because the pixel transistors 30 in the display area 10a are all equal in size.

As described above, in the present embodiment, the first transistor Tr1 and the second transistor Tr2 have the same configuration, and the third transistor Tr3 and the fourth transistor Tr4 have the same configuration. Hereinafter, the configuration of these transistors will be described in detail by taking the first transistor Tr1 and the third transistor Tr3 as examples. In the following description, the first transistor Tr1 is read as the second transistor Tr2, the third transistor Tr3 is read as the fourth transistor Tr4, the first semiconductor film 1a is read as the second semiconductor film 1a, and the first portion P1 is read as the first part P1. The second part P2 is read, the third part P3 is read as the fourth part P4, the fifth part P5
Is replaced with the sixth portion P6, and the seventh portion P7 is replaced with the eighth portion P8, the same configuration is established for the second transistor Tr2, the fourth transistor Tr4, and the second semiconductor film 1a.

As shown in FIG. 8, the first portion P of the first semiconductor film 1a constituting the first transistor Tr1.
1 includes a drain pad region DP1, a drain region D1, a drain side LDD region DLDD1, a channel formation region 1g1, a source side LDD region SLDD1, and a part of the source region (first source region S11). On the other hand, the third portion P3 of the first semiconductor film 1a constituting the first transistor Tr1 includes another part of the source region (second source region S21) and the source pad region SP. The source region of the first transistor Tr1 is the first source region S.
11 and the second source region S21. Source pad region SP and second source region S21
And the first source region S11 and the source side LDD region SLDD1 are the first transistor Tr1.
The drain side LDD region DLDD1, the drain region D1, and the drain pad region DP1 are the drain 1c of the first transistor Tr1.

The fifth portion P5 of the first semiconductor film 1a constituting the third transistor Tr3 includes a drain pad region DP3, a drain region D3, a drain side LDD region DLDD3, a channel formation region 1g3, a source side LDD region SLDD3, and a part of the source region ( First source region S13)
Including. On the other hand, the seventh portion P7 of the first semiconductor film 1a constituting the third transistor Tr3 includes another part of the source region (second source region S23) and the source pad region SP. The source region of the third transistor Tr3 includes a first source region S13 and a second source region S23. The source pad region SP, the second source region S23, the first source region S13, and the source side LDD region SLDD3 are the source 1b of the third transistor Tr3, and the drain side LDD region DLDD3, the drain region D3, and the drain pad region DP3. This is the drain 1c of the third transistor Tr3.

Thus, the source pad region SP is shared by the first transistor Tr1 and the third transistor Tr3. The first semiconductor film 1a is bent at the source region of the first transistor Tr1 and the source region of the third transistor Tr3, and has a crank shape as a whole.

Next, the effect of this embodiment will be verified. As in the first embodiment, as an example, the length of the source pad region SP is 1.5 micrometers (μm), the length of the source region is 1.5 micrometers (μm), and the length of the source side LDD region SLDD 1.0 micrometer (μm)
The length of the channel formation region 1g is 2.0 micrometers (μm), and the drain side LDD
The length of the region DLDD is 1.0 micrometers (μm), and the length of the drain region D is 1.5.
Micrometer (μm), the length of the drain pad region DP is 1.5 micrometers (
μm), and the distance DS between the semiconductor films 1a (see FIG. 7, the distance between the first semiconductor film 1a and the second semiconductor film 1a) is 0.5 micrometers (μm). In the present embodiment, the first semiconductor film 1a
Are bent twice in the source region of the first transistor Tr1 and the source region of the third transistor Tr3, and the length of the first source region S11 of the first transistor Tr1 is 0.75.
Micrometer (μm), the length of the second source region S21 of the first transistor Tr1 is 0.75 micrometer (μm), the first source region S13 of the third transistor Tr3
And the length of the second source region S23 of the third transistor Tr3 is 0.75 micrometers (μm), and the source pad region SP is shared. Accordingly, the length L1 of the first portion P1 is 7.75 micrometers (μm).
The length L3 of the third part P3 is 1.5 micrometers (μm), and the fifth part P3
The length L5 of 5 is 7.75 micrometers (μm), and the length L7 of the seventh portion P7 is 1
. 5 micrometers (μm). The length LS along the first direction of the first semiconductor film 1a is L1 + L5, which is 15.5 micrometers (μm). Since the distance DS between the semiconductor films 1a is 0.5 micrometers (μm), in this embodiment, the pixel pitch (DG + GW = (LS + DS) / 2) in the first direction is 8.0 micrometers (μm). .
Assuming an electro-optical device for full high-definition with 1080 rows × 1920 columns, the display area 10a is 9 mm long, 15 mm wide, and 0.69 inch diagonal.
It is possible to further miniaturize.

The present invention is not limited to the above-described embodiment, and various changes and improvements can be added to the above-described embodiment. A modification will be described below.

(Modification 1)
"Form adapted to the drive circuit"
An electro-optical device according to this modification will be described with reference to FIG. In addition, about the component same as Embodiment 1 thru | or 2, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

In the first embodiment, the first transistor Tr1 and the second transistor Tr2 are the pixel transistors 30. In the second embodiment, the first transistor Tr1 to the fourth transistor Tr4 are the pixel transistors 30. The first transistor Tr1 to the fourth transistor Tr4 are not limited to this, and the scanning line driving circuit 104 and the signal line driving circuit 10 are not limited thereto.
1 may be used.

When the first transistor Tr1 and the second transistor Tr2 are used in the scanning line driving circuit 104, the arrangement pitch of the first transistor Tr1 and the second transistor Tr2 is equal to the pixel pitch in the row direction. When the first transistor Tr1 and the second transistor Tr2 are used in the signal line driver circuit 101, the arrangement pitch of the first transistor Tr1 and the second transistor Tr2 is equal to the pixel pitch in the column direction. Even in such a configuration, an effect of arranging a large transistor in a narrow region is recognized.

P1 ... first part, P2 ... second part, P3 ... third part, P4 ... fourth part, P5 ... fifth part, P6 ... sixth part, P7 ... seventh part, P8 ... eighth part, Tr1 ... first One transistor, T
r2 ... second transistor, Tr3 ... third transistor, Tr4 ... fourth transistor, 1a ... semiconductor film, 1b ... source, 1c ... drain, 1g ... channel formation region, 2 ... gate insulating film, 3a ... scanning line, 3c ... Gate electrode, 4a ... drain electrode, 5b ... capacitance line, 6
a ... signal line, 6b ... relay electrode, 7a ... upper light shielding layer, 7b ... relay electrode, 7r ... constant potential wiring,
8a ... lower light shielding layer, 9a ... pixel electrode, 9b ... dummy pixel electrode, 10 ... element substrate, 10a ...
Display region, 10b ... peripheral region, 10c ... outer peripheral region, 10f ... inter-pixel region, 10w ... substrate body, 12 ... base insulating film, 16 ... alignment film, 18 ... reflection enhancing film, 19 ... inter-substrate conduction electrode, 20
... counter substrate, 20w ... substrate body, 21 ... common electrode, 25 ... inter-substrate conduction electrode, 26 ... alignment film, 28 ... insulating film, 29 ... light shielding layer, 29a ... frame portion, 29b ... black matrix portion, 30 ... Pixel transistor, 40 ... dielectric layer, 41 ... first interlayer insulating film, 41a ... contact hole, 42 ... second interlayer insulating film, 42a ... contact hole, 42b ... contact hole, 44 ... third interlayer insulating film, 44a ... Contact hole, 45 ... Fourth interlayer insulating film, 45
a ... contact hole, 49 ... etching stopper layer, 50 ... liquid crystal, 50a ... liquid crystal capacitor, 55 ... holding capacitor, 100 ... liquid crystal device, 100a ... pixel, 101 ... signal line drive circuit, 10
DESCRIPTION OF SYMBOLS 2 ... Terminal electrode, 104 ... Scanning line drive circuit, 107 ... Sealing material, 181 ... 1st light transmission film, 18
2 ... 2nd translucent film | membrane, 1000 ... Projection type display apparatus, 1021 ... Light source part, 1021a ... Light source, 1
021d ... Fly-eye optical system, 1021e ... Fly-eye optical system, 1021f ... Reflector, 1021g ... Polarization conversion member, 1021i ... Superimposing lens, 1023 ... Color separation light guide optical system,
1023a: Cross dichroic mirror, 1023b: Dichroic mirror, 102
3j: Reflection mirror, 1023k: Reflection mirror, 1025 ... Light modulation section, 1027 ... Cross dichroic prism, 1027a ... First dielectric multilayer film, 1027b ... Second dielectric multilayer film, 1029 ... Projection optical system, 1031a ... First Dichroic mirror, 1031b ... second dichroic mirror, 1032b ... wire grid polarizer, 1032g ... wire grid polarizer, 1032r ... wire grid polarizer, 1037b ... incident side polarizer, 103
7g: Incident side polarizing plate, 1037r: Incident side polarizing plate, 1038r: Outgoing side polarizing plate, 1039
b: Optical compensator, 1039 g: Optical compensator, 1039 r: Optical compensator.

Claims (11)

The first transistor,
A second transistor disposed adjacent to the first transistor along a first direction;
A signal line electrically connected to one of the source and drain of the first transistor and one of the source and drain of the second transistor;
With
The first transistor includes a first portion of a first semiconductor film and a first gate electrode intersecting the first portion,
The second transistor includes a second portion of a second semiconductor film, and a second gate electrode intersecting the second portion,
Wherein the first portion extends along the first direction, the first semiconductor film includes a third portion extending along a second direction crossing the first direction,
The signal line extends along the first direction;
The sum of the length of the first portion and the length of the third portion is greater than the sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode. Electro-optic device. The second portion extends along the first direction, the second semiconductor film includes a fourth portion extending along the second direction;
The sum of the length of the second portion and the length of the fourth portion is larger than the sum of the distance between the first gate electrode and the second gate electrode and the width of the first gate electrode. The electro-optical device according to claim 1.   3. The electro-optical device according to claim 2, wherein the sum of the length of the first portion and the length of the third portion is substantially equal to the sum of the length of the second portion and the length of the fourth portion. . A first pixel electrode electrically connected to the other of the source and drain of the first transistor;
A second pixel electrode electrically connected to the other of the source and drain of the second transistor;
The electro-optical device according to claim 1, further comprising: The first transistor,
The second transistor,
With a third transistor,
The fourth transistor,
With
Arranged in the order of the first transistor, the third transistor, the second transistor, the fourth transistor in the first direction,
The first transistor includes a first portion of a first semiconductor film and a first gate electrode intersecting the first portion,
The second transistor includes a second portion of a second semiconductor film, and a second gate electrode intersecting the second portion,
The third transistor includes a fifth portion of the first semiconductor film, and a third gate electrode intersecting with the fifth portion,
The fourth transistor includes a sixth portion of a second semiconductor film, and a fourth gate electrode intersecting the sixth portion,
From said first portion and said fifth portion extends along the first direction, the first semiconductor film, and a third portion and a seventh portion extending along a second direction crossing the first direction ,
The sum of the length of the first portion, the length of the third portion, the length of the fifth portion, and the length of the seventh portion is the distance between the first gate electrode and the second gate electrode and the first gate. An electro-optical device characterized by being larger than the sum of the electrode widths. The second portion and the sixth portion extend along the first direction, and the second semiconductor film includes a fourth portion and an eighth portion extending along the second direction,
The sum of the length of the second portion, the length of the fourth portion, the length of the sixth portion, and the length of the eighth portion is the distance between the first gate electrode and the second gate electrode and the first gate. 6. The electro-optical device according to claim 5, wherein the electro-optical device is larger than a sum of the width of the electrodes.   The electro-optical device according to claim 6, wherein the sum of the length of the first portion and the length of the third portion is substantially equal to the sum of the length of the second portion and the length of the fourth portion. .   8. The sum of the length of the first part and the length of the third part is substantially equal to the sum of the length of the fifth part and the length of the seventh part. The electro-optical device according to Item. A first pixel electrode electrically connected to one of the source and drain of the first transistor;
A second pixel electrode electrically connected to one of the source and drain of the second transistor;
A third pixel electrode electrically connected to one of the source and drain of the third transistor;
A fourth pixel electrode electrically connected to one of the source and drain of the fourth transistor;
The electro-optical device according to claim 5, further comprising: A signal line electrically connected to the other of the source and drain of the first transistor, the other of the source and drain of the second transistor, the other of the source and drain of the third transistor, and the other of the source and drain of the fourth transistor; Prepared,
The electro-optical device according to claim 5, wherein the signal line extends along the first direction.   An electronic apparatus comprising the electro-optical device according to claim 1.

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