JP6424473B2 - Arithmetic device, arithmetic method, and arithmetic processing program - Google Patents

Description

  The present invention relates to the technical field of an arithmetic device that includes multiple cores and can perform parallel processing.

  For control devices that may lose safety if they fail, measures have been taken to monitor the main core by a monitoring unit such as a sub core and detect an abnormality in the main core to guarantee the safe operation of the control device. . As one example, as disclosed in Patent Document 1, a technique called lock step is in widespread use. The lock step is a technology in which a plurality of cores execute the same processing in parallel and compare the execution results to determine that each core is operating normally. For example, as disclosed in Patent Document 2, there is known a technology that guarantees safe operation by authenticating an opposite device using encryption technology while lock step aims to detect a failure. .

JP, 2010-128627, A JP, 2013-138304, A

  However, side channel attacks are known in fields such as smart cards and TPMs (Trusted Platform Module) known as authentication devices. Side channel attack is a threat that has existed for a long time in the controller for cryptographic computation, and the content of computation using power consumed during computation and secondary information (side channel information) represented by generated electromagnetic waves Attack method to estimate In the case where lock step and authentication processing are to be realized by a single arithmetic device, the lock step causes the multiple cores to simultaneously execute the same processing, and power consumption and electromagnetic waves are increased. It becomes a problem that it becomes easy to become a target of side channel attack.

  Therefore, the present invention has been made in view of the above problems and the like, and an arithmetic device capable of realizing high tamper resistance without increasing side channel information even when lock step and authentication processing are simultaneously executed. , An arithmetic method, and an arithmetic processing program.

In order to solve the above problems, the invention according to claim 1 acquires a non-volatile memory storing an instruction code, and an instruction code output from the non-volatile memory, interprets the acquired instruction code, and interprets the acquired instruction code. Processing according to the specified instruction code, and the first operation unit storing the first result data indicating the result of the processing in the internal memory, and inverting the binary logic representing the instruction code output from the non-volatile memory Obtaining an instruction code obtained by inverting the binary logic by the first inverting means and the first inverting means, and interpreting and interpreting the acquired instruction code by binary logic opposite to the first operation unit A second operation unit that executes processing in binary logic opposite to the first operation unit according to an instruction code, and stores second result data indicating the result of the processing in the internal memory And wherein the Rukoto. The invention described in claim 2 is the arithmetic device according to claim 1, wherein the non-volatile memory stores one program composed of a plurality of instruction codes, and the first arithmetic unit stores the one program. Any one instruction code included in the program is acquired from the nonvolatile memory, the acquired one instruction code is interpreted, and processing is executed according to the interpreted one instruction code, and the second operation unit is An instruction code obtained by binary logic of the one instruction code acquired and interpreted by the first operation unit is acquired by the first inverting means, and the acquired instruction code is the first operation unit. According to the instruction code interpreted and interpreted by the opposite binary logic, the processing is performed by the binary logic opposite to the first operation unit.

The invention according to claim 3 comprises: a non-volatile memory for storing an instruction code; acquiring an instruction code output from the non-volatile memory; interpreting the acquired instruction code; and executing processing according to the interpreted instruction code A first operation unit for storing, in an internal memory, first result data indicating the result of the process; first inverting means for inverting binary logic representing the instruction code output from the non-volatile memory; An instruction code obtained by inverting the binary logic is acquired by the first inverting means, and the acquired instruction code is interpreted by the binary logic opposite to the first arithmetic unit, and the first arithmetic unit according to the interpreted instruction code run the process in the opposite binary logic and, of outputting the second result data indicating the result of the processing and the second processing units to be stored in an internal memory, from the second arithmetic unit And and a second inverting means for inverting the binary logic representing said second result data, the nonvolatile memory, the second result data binary logic is inverted by the second inverting means, It is characterized in that it is stored in a predetermined storage area.

The invention according to claim 4 acquires a non-volatile memory for storing an instruction code and an instruction code output from the non-volatile memory, interprets the acquired instruction code, and executes processing according to the interpreted instruction code. A first operation unit for storing, in an internal memory, first result data indicating the result of the process; first inverting means for inverting binary logic representing the instruction code output from the non-volatile memory; An instruction code obtained by inverting the binary logic is acquired by the first inverting means, and the acquired instruction code is interpreted by the binary logic opposite to the first arithmetic unit, and the first arithmetic unit according to the interpreted instruction code run the process in the opposite binary logic and the second result data indicating the result of the processing a computing device comprising a second arithmetic unit that stored in the internal memory, the said One operation unit writes the first result data to a predetermined storage area in the non-volatile memory, and the operation device inverts binary logic representing the first result data output from the non-volatile memory The second operation unit further includes a third inverting unit, and the second operation unit acquires the first result data whose binary logic is inverted by the third inverting unit, and acquires the first result data and the second result data. And comparing with.

The invention according to claim 5 is an arithmetic method in an arithmetic device including a non-volatile memory for storing an instruction code, wherein the instruction code output from the non-volatile memory is acquired, and the acquired instruction code is interpreted. A first operation step of executing processing according to the interpreted instruction code and storing first result data indicating the result of the processing in the internal memory; and binary logic representing the instruction code output from the non-volatile memory The step of inverting, acquiring the instruction code obtained by inverting the binary logic, interpreting the acquired instruction code by binary logic opposite to the first operation step, and performing the first operation according to the interpreted instruction code Performing a process with binary logic opposite to the step, and storing a second result data indicating the result of the process in the internal memory; To. The invention according to claim 6 is an arithmetic method in an arithmetic device including a non-volatile memory for storing an instruction code, which acquires an instruction code output from the non-volatile memory, and interprets the acquired instruction code. A first operation step of executing processing according to the interpreted instruction code and storing first result data indicating the result of the processing in the internal memory; and binary logic representing the instruction code output from the non-volatile memory The step of inverting, acquiring the instruction code obtained by inverting the binary logic, interpreting the acquired instruction code by binary logic opposite to the first operation step, and performing the first operation according to the interpreted instruction code A second operation step of executing processing with binary logic opposite to that of the step and storing second result data indicating the result of the processing in the internal memory; Inverting the binary logic representing the data, and storing the second result data obtained by inverting the binary logic in a predetermined storage area of the non-volatile memory. . The invention according to claim 7 is an arithmetic method in an arithmetic device including a non-volatile memory for storing an instruction code, which acquires an instruction code output from the non-volatile memory, and interprets the acquired instruction code. A first operation step of executing processing according to the interpreted instruction code and storing first result data indicating the result of the processing in the internal memory; and binary logic representing the instruction code output from the non-volatile memory The step of inverting, acquiring the instruction code obtained by inverting the binary logic, interpreting the acquired instruction code by binary logic opposite to the first operation step, and performing the first operation according to the interpreted instruction code A second operation step of executing processing with binary logic opposite to that of the step and storing second result data indicating the result of the processing in the internal memory; Writing the data into a predetermined storage area in the non-volatile memory, inverting the binary logic representing the first result data output from the non-volatile memory, and inverting the binary logic And acquiring the first result data, and comparing the acquired first result data with the second result data.

The invention according to claim 8 is a computer having a non-volatile memory for storing an instruction code, acquiring an instruction code output from the non-volatile memory, interpreting the acquired instruction code, and processing according to the interpreted instruction code Calculating a first result data indicating the result of the process in an internal memory, inverting the binary logic representing the instruction code output from the non-volatile memory, and The instruction code is obtained by inverting the binary logic, and the obtained instruction code is interpreted by the binary logic opposite to the first operation step, and the opposite 2 to the first operation step according to the interpreted instruction code. Performing a process according to value logic, and storing a second result data indicating a result of the process in an internal memory. The invention according to claim 9 is that according to an instruction code obtained by obtaining a command code output from the non-volatile memory, interpreting the obtained command code, and interpreting the obtained command code in a computer having a nonvolatile memory storing the command code. Calculating a first result data indicating the result of the process in an internal memory, inverting the binary logic representing the instruction code output from the non-volatile memory, and The instruction code is obtained by inverting the binary logic, and the obtained instruction code is interpreted by the binary logic opposite to the first operation step, and the opposite 2 to the first operation step according to the interpreted instruction code. A second operation step of executing processing with value logic and storing second result data indicating the result of the processing in an internal memory; and binary values representing the second result data A step of inverting the sense, the said binary logic is inverted the second result data, characterized in that to execute the steps of storing in a predetermined storage area in the nonvolatile memory. The invention according to claim 10 is that according to the instruction code obtained by acquiring the instruction code output from the non-volatile memory, interpreting the acquired instruction code, and processing the instruction code output from the non-volatile memory to a computer including the nonvolatile memory storing the instruction code. Calculating a first result data indicating the result of the process in an internal memory, inverting the binary logic representing the instruction code output from the non-volatile memory, and The instruction code is obtained by inverting the binary logic, and the obtained instruction code is interpreted by the binary logic opposite to the first operation step, and the opposite 2 to the first operation step according to the interpreted instruction code. A second operation step of executing processing with value logic and storing second result data indicating the result of the processing in an internal memory; and non-volatileally processing the first result data The steps of writing in a predetermined storage area in a memory, inverting the binary logic representing the first result data output from the non-volatile memory, and converting the first result data obtained by inverting the binary logic And acquiring the acquired first result data and comparing the acquired second result data with each other.

According to the present invention, the first operation unit acquires the instruction code output from the non-volatile memory, interprets the acquired instruction code, and executes processing in accordance with the interpreted instruction code, while the second operation unit get the instruction code binary logic is reversed by the reversing means, the instruction code obtained, the first arithmetic unit interprets the opposite binary logic, as opposed to the first arithmetic unit in accordance with instruction codes of interpreting Since the processing is executed by the binary logic, for example, even if lock step and authentication processing are executed simultaneously, side channel information is not increased, and high tamper resistance can be realized.

FIG. 6 is a diagram showing an example of a schematic configuration of an IC chip C. FIG. 7 is a diagram showing how an instruction code is fetched from a program memory PM and processing is executed according to the instruction code in the first embodiment. FIG. 7 is a diagram showing how an instruction code is fetched from a program memory PM and processing is executed according to the instruction code in the first embodiment. FIG. 7 is a diagram showing how an instruction code is fetched from a program memory PM and processing is executed according to the instruction code in the first embodiment. FIG. 7 is a diagram showing how an instruction code is fetched from a program memory PM and processing is executed according to the instruction code in the first embodiment. FIG. 7 is a diagram showing how an instruction code is fetched from a program memory PM and processing is executed according to the instruction code in the first embodiment. In Example 2, it is a figure which shows a mode that an instruction code is fetched from program memory PM and processing is performed according to an instruction code. In Example 2, it is a figure which shows a mode that an instruction code is fetched from program memory PM and processing is performed according to an instruction code. In Example 2, it is a figure which shows a mode that an instruction code is fetched from program memory PM and processing is performed according to an instruction code.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment described below is an embodiment in the case where the present invention is applied to an IC chip.

  First, with reference to FIG. 1, a schematic configuration of an IC chip according to the present embodiment will be described. FIG. 1 is a view showing a schematic configuration example of an IC chip C. As shown in FIG. The IC chip C is an example of the arithmetic device of the present invention. The IC chip C is mounted on a cash card, a credit card, an employee card or the like and used. Alternatively, the IC chip C is incorporated in a communication device such as a smartphone or a mobile phone. The IC chip C may be built directly on the circuit board of the communication device.

  As shown in FIG. 1, the IC chip C includes a core 1, a core 2, an inverter 3, a random access memory (RAM) 4, a non-volatile memory 5, a read only memory (ROM) 6, and an I / O circuit 7. It comprises and is constituted. The core 1 is an example of a first arithmetic unit. The core 2 is an example of a second operation unit. The cores 1 and 2 are configured to be capable of parallel processing. The core 1, the inverter 3, the RAM 4, the non-volatile memory 5, the ROM 6, and the I / O circuit 7 are connected to the bus 8. On the other hand, the core 2 is connected to the inverter 3. The inverter 3 is an example of first to third inverting means for inverting (in other words, inverting a low potential state and a high potential state) binary logic (logic 0 and logic 1) representing an instruction code, various data, etc. And is configured by a NOT circuit or the like. The bus 8 comprises an address bus and a data bus.

  The RAM 4 is a work memory and includes a stack memory. The stack memory is used to store return addresses and the like associated with subroutine calls and interrupts. The nonvolatile memory 5 includes a program memory PM and a data memory DM. The program memory PM stores (stores) a plurality of instruction codes constituting a program. Various data are stored in the data memory DM. The ROM 6 may store a part of the program stored in the non-volatile memory 5.

  The I / O circuit 7 interfaces with an external terminal. In the case of the contact type IC chip C, the I / O circuit 7 is provided with eight terminals C1 to C8, for example. For example, terminal C1 is a power supply terminal, terminal C2 is a reset terminal, terminal C3 is a clock terminal, terminal C5 is a ground terminal, and terminal C7 is a terminal for communication with an external terminal. On the other hand, in the case of the non-contact type IC chip C, the I / O circuit 7 is provided with, for example, an antenna and a modulation / demodulation circuit. In addition, as an example of an external terminal, an IC card issuing machine, an ATM, a ticket gate, an authentication gate, etc. may be mentioned. Alternatively, when the IC card 1 is incorporated into a communication device, the external terminal corresponds to a control unit that takes on the function of the communication device.

  The core 1 includes an arithmetic unit 11, an internal memory 12, a program counter 13, and an interrupt controller 14. The core 2 includes an arithmetic unit 21, an internal memory 22, a program counter 23, and an interrupt controller 24. The computing units 11 and 21 each include an instruction register and a decoder. The internal memories 12 and 22 each include a data register. The program counters 13 and 23 hold an address (address) on the program memory PM in which an instruction code to be executed next is stored. The interrupt controller 14 and the interrupt controller 24 are configured to be able to transmit and receive data without passing through the bus 8. Here, in the core 2, binary logic (in other words, identification criteria) of logic 0 and logic 1 in the core 1 is inverted. When core 1 represents logic 0 by a low potential state, core 2 represents logic 0 by a high potential state, and when core 1 represents logic 1 by a high potential state, core 2 represents logic 1 in a low potential state Expressed by For example, “9 (decimal number)” is described as “1001 (binary number)”, but “1001 (binary number)” is the core when expressed as low potential state = L and high potential state = H. In 1, it is expressed as "HLLH", and in core 2, it is expressed as "LHHL". Similarly, when the ADD instruction is written as "000111 (binary)", it is displayed as "LLLHHH" in core 1 and is expressed as "HHHLLL" in core 2.

  Arithmetic unit 11 fetches (acquires) the instruction code stored at the address indicated by program counter 13 from program memory PM to the instruction register. That is, the instruction code output from the program memory PM of the non-volatile memory 5 is fetched by the operation unit 11. Then, the arithmetic unit 11 interprets (decodes) the acquired instruction code by the decoder and executes processing according to the interpreted instruction code (for example, executes arithmetic processing such as four arithmetic operations and logical operations), and the result of the processing Are stored in the data register of the internal memory 12.

  On the other hand, the arithmetic unit 21 fetches (acquires) the instruction code stored at the address indicated by the program counter 23 from the program memory PM via the inverter 3 to the instruction register. That is, the instruction code output from the program memory PM of the non-volatile memory 5 and having the binary logic inverted by the inverter 3 is fetched. Here, the address (address indicated by the program counter 23) output from the core 2 is sent to the address bus after the binary logic is inverted by the inverter 3, and accordingly, from the program memory PM to the data bus The issued instruction code is input to the core 2 after the binary logic is inverted by the inverter 3. Then, the arithmetic unit 21 interprets the obtained instruction code by the decoder with binary logic opposite to that of the arithmetic unit 11, executes processing according to the interpreted instruction code, and internally stores the second result data indicating the result of the processing. It is stored in the data register of the memory 22.

  Next, an operation example of the IC chip according to the present embodiment will be described by dividing it into Example 1 and Example 2.

Example 1
First, Embodiment 1 will be described with reference to FIGS. 2 to 6. The first embodiment is an operation example in the case where the data memory is shared by the core 1 and the core 2. 2 to 6 are diagrams showing how an instruction code is fetched from the program memory PM and the process is executed according to the instruction code in the first embodiment. In FIGS. 2 to 6, although the address bus 81 and the address bus 83 are separated, they may be a single address bus. Similarly, data bus 82 and data bus 84 may be a single data bus. Moreover, in the example of FIGS. 2-6, the structural unit of an instruction code is 3 bytes. The state of FIG. 2A shows the state before the instruction code is fetched. In the state of FIG. 2 (A), while the initial value “00... (H)” is stored in the instruction register of the arithmetic unit 11 in the core 1, the instruction register of the arithmetic unit 21 in the core 2 is stored. , And an initial value "FF (h)" is stored. Here, "h" indicates a hexadecimal number. Further, in the state of FIG. 2A, while the initial value “ 00 (h) ” is stored in the data register of the internal memory 12 in the core 1, the data register of the internal memory 22 in the core 2 is: The initial value " FF (h) " is stored. In the example of FIG. 2A, two data registers of the data register R1 and the data register R2 are shown in the internal memory 12 and the internal memory 22, respectively. A data register is provided. Further, in the state of FIG. 2A, the program counter 13 in the core 1 indicates the address "0000 (h)" while the program counter 23 in the core 2 indicates the inverted value of the address "0000 (h)""FFFF(h)" is shown. Note that, thereafter, the arithmetic unit 11 and the arithmetic unit 21 execute processing in parallel.

  Arithmetic unit 11 in core 1 has the instruction code "08 01 09" stored in the address "0000 (h)" (that is, the value of program counter 13) pointed to by program counter 13 as shown in FIG. 2 (B). (H) "is fetched from the program memory PM to the instruction register via the data bus 82. That is, the address "0000 (h)" indicated by the program counter 13 is sent to the address bus 81, and in response, the instruction code sent from the program memory PM to the data bus 82 is fetched into the instruction register. Then, the arithmetic unit 11 in the core 1 interprets the fetched instruction code by the decoder (interprets it as a load (LOAD) instruction), and according to the interpreted instruction code (in this example, a load instruction), data in the internal memory 12 Load data into a register. In the example of FIG. 2B, “08” included in the instruction code is interpreted by the decoder of the arithmetic unit 11 as a load (LOAD) instruction, and “09” included in the instruction code is the operation target. The data is loaded as data into a data register R1 (= 01) in the internal memory 12.

On the other hand, as shown in FIG. 2 (B), the arithmetic unit 21 in the core 2 has an address (ie, the program counter) in which “FFFF (h)” indicated by the program counter 23 is inverted (ie, inverted by the inverter 31). The instruction code "0801 09 (h)" stored in the inverted value "0000 (h)" of 23 is fetched from the program memory PM into the instruction register through the data bus 82 and the inverter 32. That is, the program counter 2 3 pointed address "FFF F (h)" is sent to the address bus 81 after the inverter 31 is binary logic is inverted, accordingly, transmitted from the program memory PM into the data bus 82 The inverted instruction code is fetched into the instruction register after the binary logic is inverted by the inverter 32. Then, the arithmetic unit 21 in the core 2 interprets the fetched instruction code by the decoder (interprets it as a load (LOAD) instruction with binary logic opposite to the arithmetic unit 11), and internally executes the interpreted instruction code. Data is loaded into data register R1 in memory 22. In the example of FIG. 2B, “F7” included in the instruction code (that is, the inverted value of the instruction code) whose binary logic is inverted by the inverter 32 is a load (LOAD) instruction by the decoder of the arithmetic unit 21. The data “F6” included in the inverted instruction code, which is interpreted as being, is loaded to the data register R1 (= FE) in the internal memory 22 as data to be calculated.

  Next, as shown in FIG. 3A, the interrupt controller 14 in the core 1 acquires data from at least the data register R1 and the data register R2 in the internal memory 12 and outputs the data to the interrupt controller 24. On the other hand, the interrupt controller 24 in the core 2 acquires data from the interrupt controller 14 and acquires data from at least the data register R1 and the data register R2 in the internal memory 22. Then, the interrupt controller 24 compares the inverted value of the data acquired from the interrupt controller 14 with the value of the data acquired from the internal memory 22 (data comparison). Then, if the result of the data comparison shows that the data of the two do not match, the interrupt controllers 14 and 24 determine that they are abnormal and execute the internal reset of the cores 1 and 2. On the other hand, as a result of the above data comparison, when the values match each other, as shown in FIG. 3B, the program counter 13 in the core 1 sets the value (“0000 (h)”) of the program counter 13 The program counter 23 in the core 2 advances the value ("FFFF (h)") of the program counter 13 to the third address (an instruction code in this example). Of the unit of 3 bytes) (ie, advance to "FFFC (h)").

Next, the arithmetic unit 11 in the core 1 is not shown, but the instruction code "0802 1 1 (h)" stored in the address "0003 (h)" pointed to by the program counter 13 is transmitted from the program memory PM to the data bus Data is fetched into the instruction register via 82, the instruction code is interpreted by the decoder (interpreted as a load (LOAD) instruction), and data is loaded into the data register R2 in the internal memory 12 in accordance with the interpreted instruction code. On the other hand, the operation unit 21 in the core 2 is not shown, but the instruction code "0802 1 1 (h)" stored in the address "0003 (h)" obtained by inverting the "FFFC (h)" indicated by the program counter 23 Is fetched from the program memory PM into the instruction register via the data bus 82 and the inverter 32, and the instruction code is interpreted by the decoder (interpreted as a load (LOAD) instruction), and internally interpreted according to the interpreted instruction code. Load data into data register R2 in memory 22. Then, the interrupt controller 24 compares the data in the internal memories 12 and 22 in the same manner as in the case of the instruction code "0801 09 (h)", and when the values match each other, the program counter 13 in the core 1 The value of the program counter 13 ("0003 (h)") is advanced to the third address (that is, it advances to "0006 (h)"), and the program counter 23 in the core 2 calculates the value of the program counter 23 ("FFFC ( h) ") is advanced to the 3rd address (that is, it is advanced to" FFF 9 (h) ").

  Next, the arithmetic unit 11 in the core 1 is not shown, but the instruction code “300 01 02 (h)” stored in the address “0006 (h)” pointed to by the program counter 13 is transmitted from the program memory PM to the data bus Then, the instruction code is fetched by the decoder via the instruction register 82 (interpreted as an add (ADD) instruction). Then, operation unit 11 sets data “09 (h)” in data register R1 in internal memory 12 to data “11 (data register R2 in internal memory 12” according to the interpreted instruction code (in this example, the addition instruction). h) The process of adding “” is executed, and data (an example of the first result data) indicating the result of the process is stored in the data register R1 in the internal memory 12. That is, the data of the data register R1 in the internal memory 12 is rewritten to "1A (h)". On the other hand, the operation unit 21 in the core 2 is not shown, but the instruction code "30 01 02 (h)" stored in the address "0006 (h)" obtained by inverting the "FFF 9 (h)" indicated by the program counter 23 Is fetched from the program memory PM into the instruction register via the data bus 82 and the inverter 32, and the instruction code is interpreted by the decoder (interpreted as an add (ADD) instruction). Then, operation unit 21 adds data “EE (h)” in data register R 2 in internal memory 22 to data “F 6 (h)” in data register R 1 in internal memory 22 according to the interpreted instruction code A process of adding with binary logic opposite to 11 is executed, and data (an example of second result data) indicating the result of the process is stored in the internal memory 22. That is, the data of the data register R1 in the internal memory 12 is rewritten to "E5 (h)".

  Next, the interrupt controller 24 compares data in the internal memories 12 and 22 in the same manner as in the case of the instruction code “08 01 09 (h)”, and if the values match, the program counter in core 1 13 advances the value ("0006 (h)") of the program counter 13 to the third address as shown in FIG. 4A (that is, advances to "0009 (h)"), and the program counter 23 in the core 2 The value of the program counter 23 ("FFF 9 (h)") advances to the third address as shown in FIG. 4A (that is, advances to "FFF 6 (h)").

  Next, as shown in FIG. 4B, the arithmetic unit 11 in the core 1 has the instruction code “52 01 00 (h)” stored in the address “0009 (h)” indicated by the program counter 13 as follows: The instruction code is fetched from the program memory PM to the instruction register via the data bus 82, and the instruction code is interpreted (interpreted as a STORE instruction) by the decoder. On the other hand, as shown in FIG. 4B, the arithmetic unit 21 in the core 2 stores the instruction code "" stored in the address "0009 (h)" obtained by inverting the "FFF 6 (h)" indicated by the program counter 23. 52 01 00 (h) is fetched from the program memory PM to the instruction register via the data bus 82 and the inverter 32, and the instruction code is interpreted by the decoder (interpreted as a STORE confirmation instruction).

  Next, when the arithmetic unit 11 in the core 1 recognizes that the code system of the interpreted STORE instruction is double-length, the program counter 13 in the core 1 calculates the value ("0009 (h)") of the program counter 13 As shown in FIG. 5 (A), it advances to the third address (that is, it advances to "000C (h)"). On the other hand, when the arithmetic unit 21 in the core 2 recognizes that the code system of the interpreted store confirmation instruction is double-length, the program counter 23 in the core 2 calculates the value ("FFF6 (h)") of the program counter 23 As shown in FIG. 5A, the process proceeds to the third address (that is, the process proceeds to "FFF 3 (h)").

Next, as shown in FIG. 5 (B), the arithmetic unit 11 in the core 1 programs the code “ 10 00 00 (h)” stored in the address “000 C (h)” indicated by the program counter 13 It fetches from the memory PM to the instruction register (after the instruction code "5201 00 (h)" already stored) via the data bus 82. On the other hand, as shown in FIG. 5B, the arithmetic unit 21 in the core 2 stores the code " 10 " stored in the address "000C (h)" obtained by inverting the "FFF3 (h)" indicated by the program counter 23. 00 00 (h) is fetched from the program memory PM via the data bus 82 and the inverter 32 into the instruction register (after the instruction code “ AD FE FF (h)” already stored).

Next, as shown in FIG. 6A, the interrupt controller 14 in the core 1 follows the interpreted instruction code (in this example, a store instruction), the data “1A (h)” in the data register R1 in the internal memory 12 Is executed via the data bus 84 in a predetermined storage area (address "0010 00 00 (h)" included in the instruction code) in the data memory DM in the non-volatile memory 5. Then, the interrupt controller 24 in the core 2 executes the confirmation processing of the data written in the data memory DM according to the interpreted instruction code (in this example, the store confirmation instruction). Specifically, as shown in FIG. 6B, the interrupt controller 24 writes the data written by the core 1 to the storage area (address “0010 00 00 (h)” included in the instruction code) of the data memory DM. “1A (h)” is obtained via the data bus 84 and the inverter 34, and data “E5 (h)” is obtained from the data register R1 in the internal memory 22. That is, as shown in FIG. 6B, “FFEF FF FF (h)” stored in the instruction register is sent to the address bus 83 after the binary logic is inverted by the inverter 33, and accordingly Then, the data sent from the data memory DM to the data bus 84 is acquired after the binary logic is inverted by the inverter 34 (in this example, the data "E5 (h)" is acquired). Then, the interrupt controller 24 compares the values of the acquired data with each other (data comparison), and as a result of the data comparison, if the data do not match each other, it determines that it is abnormal and executes the internal reset of the core 2 And informs the interrupt controller 14 that their data do not match. Thereby, the interrupt controller 14 executes an internal reset of the core 1. On the other hand, as a result of the data comparison, when the values match each other, the program counter 13 in the core 1 advances the value of the program counter 13 to the third address (that is, advances to "000F (h)"), The program counter 23 in the core 2 advances the value of the program counter 13 to the third address (that is, advances to "FFF 0 (h)"). Thereafter, the process proceeds in the same manner as described above.

(Example 2)
A second embodiment will now be described with reference to FIGS. 7 to 9. The second embodiment is an operation example when the data memory is not shared between the core 1 and the core 2. FIGS. 7 to 9 are diagrams showing how an instruction code is fetched from the program memory PM and the process is executed according to the instruction code in the second embodiment. In the examples of FIGS. 7 to 9, the data memory DM is divided into a data memory DM1 for the core 1 and a data memory DM2 for the core 2. Also in the second embodiment, the same processing as the processing described with reference to FIG. 2 and FIG. 3 in the first embodiment is performed, and thus redundant description will be omitted.

  The state of FIG. 7 (A) is the same as the state of FIG. 4 (A). As shown in FIG. 7B, the computing unit 11 in the core 1 is configured to use the program memory PM for the instruction code “52 01 00 (h)” stored at the address “0009 (h)” indicated by the program counter 13. To the instruction register via the data bus 82, and the instruction code is interpreted (interpreted as a STORE instruction) by the decoder. On the other hand, as shown in FIG. 7B, the arithmetic unit 21 in the core 2 stores the instruction code "" stored in the address "0009 (h)" obtained by inverting the "FFF 6 (h)" indicated by the program counter 23. 52 01 00 (h) ′ ′ is fetched from the program memory PM to the instruction register via the data bus 82 and the inverter 32, and the instruction code is interpreted by the decoder. In this case, unlike the first embodiment, “AD FE FF (h)” which is the inverted value of the instruction code “52 01 00 (h)” is interpreted as a store (STORE) instruction.

  Next, when the arithmetic unit 11 in the core 1 recognizes that the code system of the interpreted STORE instruction is double-length, the program counter 13 in the core 1 calculates the value ("0009 (h)") of the program counter 13 As shown in FIG. 8A, advance to the third address. On the other hand, when the arithmetic unit 21 in the core 2 recognizes that the code system of the interpreted store confirmation instruction is double-length, the program counter 23 in the core 2 calculates the value ("FFF6 (h)") of the program counter 23 As shown in FIG. 8A, the process proceeds to the third address.

  Next, as shown in FIG. 8 (B), the arithmetic unit 11 in the core 1 programs the code “10 00 00 (h)” stored in the address “000 C (h)” indicated by the program counter 13 The data is fetched from the memory PM to the instruction register via the data bus 82. On the other hand, as shown in FIG. 8B, the arithmetic unit 21 in the core 2 stores the code "10" stored in the address "000C (h)" obtained by inverting the "FFF3 (h)" indicated by the program counter 23. 00 00 (h) is fetched from the program memory PM into the instruction register via the data bus 82 and the inverter 32.

  Next, as shown in FIG. 9A, the interrupt controller 14 in the core 1 uses the data “1A (h)” in the data register R1 in the internal memory 12 according to the interpreted instruction code (store instruction in this example). Is executed via the data bus 84 in a predetermined storage area (address "00 10 00 00 (h)" included in the instruction code) in the data memory DM1 of the non-volatile memory 5. On the other hand, interrupt controller 24 in core 2 transmits data "E5 (h)" in data register R1 in internal memory 22 through data bus 84 and inverter 34 according to the interpreted instruction code (store instruction in this example). Then, a process of writing in a predetermined storage area (address "00 10 00 00 (h)") in the data memory DM2 in the non-volatile memory 5 is executed. As a result, as shown in FIG. 9A, data “1A (h)” whose binary logic is inverted by the inverter 34 is stored in a predetermined storage area.

Next, as shown in FIG. 9A, the interrupt controller 14 in the core 1 acquires data (data “1A (h)” written according to the store instruction) from the data memory DM1 and outputs it to the interrupt controller 24. Do. On the other hand, the interrupt controller 24 in the core 2 acquires data from the interrupt controller 14 and converts data (data "1A (h)" written according to the store instruction) from the data memory DM2 into the data bus 84 and the inverter. Get through 34. Then, the interrupt controller 24 compares the inverted value of the data acquired from the interrupt controller 14 with the value of the data acquired from the data memory DM2 (data comparison). Then, if the result of the data comparison shows that the data of the two do not match, the interrupt controllers 14 and 24 determine that they are abnormal and execute the internal reset of the cores 1 and 2. On the other hand, the result of the data comparison, if the mutual values match, the program counter 13 in the core 1 advances the value of the program counter 13 to address 3 destination, the program counter 23 in the core 2, the program counter 23 Advance the value to address 3 forward. Thereafter, the process proceeds in the same manner as described above.

  As described above, according to the above embodiment, in the IC chip C including the cores 1 and 2 capable of parallel processing, the core 1 acquires an instruction code output from the non-volatile memory 5, The core 2 interprets the acquired instruction code and executes processing according to the interpreted instruction code, while the core 2 acquires the instruction code whose binary logic is inverted by the inverter 32, and the acquired instruction code is core 1 Since the processing is performed by the binary logic opposite to that of the core 1 according to the interpreted binary code and interpreted by the opposite binary logic, for example, even if lock step and authentication processing are simultaneously executed, the side channel information remains It is possible to realize high tamper resistance without increasing the length. That is, in the core 2, since the binary logic (in other words, the identification reference) of the logic 0 and the logic 1 in the core 1 is inverted, the Hamming weight is equalized in parallel processing of the core 1 and the core 2. It is possible to prevent side channel information from being collected as much as possible.

  Further, in the first embodiment, the core 2 acquires the first result data written to the data memory DM by the core 1 after the binary logic is inverted by the inverter 34, and the acquired first result data, As compared with the second result data stored in the internal memory 22, as a result, when the mutual data do not match, the internal reset of the cores 1 and 2 is performed, so that the IC chip C is generated. It is possible to properly detect anomalies due to internal failures or external attacks.

  Further, in the second embodiment, the core 2 acquires the second result data written in the data memory DM2 via the inverter 34, and the core 1 generates the first result data written in the data memory DM1. , And the obtained mutual data are compared, and as a result, when the mutual data do not match, the internal reset of the cores 1 and 2 is performed so that the IC An abnormality due to a failure in the chip C or an attack from the outside can be appropriately detected.

  In the above embodiment, an IC chip having two cores has been described as an example, but the present invention is also applicable to a multi-core processor having three or more cores.

1, 2 core 3 inverter 4 RAM
5 Nonvolatile memory 6 ROM
7 I / O circuit 8 bus C IC chip

Claims (10)

Non-volatile memory for storing instruction code,
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. An arithmetic unit,
First inverting means for inverting binary logic representing the instruction code output from the non-volatile memory;
An instruction code obtained by inverting the binary logic is acquired by the first inverting means, the acquired instruction code is interpreted by the binary logic opposite to the first arithmetic unit, and the first operation is performed according to the interpreted instruction code. A second operation unit that executes processing with binary logic opposite to the unit and stores second result data indicating the result of the processing in the internal memory;
A computing device comprising: The non-volatile memory stores one program composed of a plurality of instruction codes,
The first operation unit acquires any one instruction code included in the one program from the nonvolatile memory, interprets the acquired one instruction code, and processes according to the one instruction code interpreted. Run
The second operation unit acquires an instruction code obtained by the first inverting means by binary logic of the one instruction code acquired and interpreted by the first operation unit, and acquires the acquired instruction code. The operation according to claim 1, characterized in that processing is performed according to an instruction code interpreted according to the interpreted binary code opposite to the first operation unit according to the interpreted instruction code. apparatus. Non-volatile memory for storing instruction code,
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. An arithmetic unit,
First inverting means for inverting binary logic representing the instruction code output from the non-volatile memory;
An instruction code obtained by inverting the binary logic is acquired by the first inverting means, the acquired instruction code is interpreted by the binary logic opposite to the first arithmetic unit, and the first operation is performed according to the interpreted instruction code. A second operation unit that executes processing with binary logic opposite to the unit and stores second result data indicating the result of the processing in the internal memory;
Second inverting means for inverting binary logic representing the second result data output from the second operation unit;
Equipped with
The nonvolatile memory, the said second result data binary logic is inverted by the second inverting means, arithmetic device you characterized in that a predetermined storage area. Non-volatile memory for storing instruction code,
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. An arithmetic unit,
First inverting means for inverting binary logic representing the instruction code output from the non-volatile memory;
An instruction code obtained by inverting the binary logic is acquired by the first inverting means, the acquired instruction code is interpreted by the binary logic opposite to the first arithmetic unit, and the first operation is performed according to the interpreted instruction code. A second operation unit that executes processing with binary logic opposite to the unit and stores second result data indicating the result of the processing in the internal memory;
A computing device comprising
The first operation unit writes the first result data to a predetermined storage area in the non-volatile memory,
The arithmetic unit further comprises third inverting means for inverting binary logic representing the first result data output from the non-volatile memory,
The second operation unit is characterized in that it acquires the first result data whose binary logic is inverted by the third inverting means, and compares the acquired first result data with the second result data. It is that arithmetic unit. An arithmetic method in an arithmetic device provided with a non-volatile memory storing an instruction code, the arithmetic method comprising:
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. Operation step,
Inverting binary logic representing the instruction code output from the non-volatile memory;
The instruction code obtained by inverting the binary logic is acquired, and the acquired instruction code is interpreted by binary logic opposite to the first operation step, and the operation code is inverted according to the interpreted instruction code. A second operation step of executing processing in binary logic and storing second result data indicating the result of the processing in the internal memory;
A computing method characterized by including. An arithmetic method in an arithmetic device provided with a non-volatile memory storing an instruction code, the arithmetic method comprising:
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. Operation step,
Inverting binary logic representing the instruction code output from the non-volatile memory;
The instruction code obtained by inverting the binary logic is acquired, and the acquired instruction code is interpreted by binary logic opposite to the first operation step, and the operation code is inverted according to the interpreted instruction code. A second operation step of executing processing in binary logic and storing second result data indicating the result of the processing in the internal memory;
Inverting the binary logic representing the second result data;
Storing the second result data obtained by inverting the binary logic in a predetermined storage area of the non-volatile memory;
A computing method characterized by including. An arithmetic method in an arithmetic device provided with a non-volatile memory storing an instruction code, the arithmetic method comprising:
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. Operation step,
Inverting binary logic representing the instruction code output from the non-volatile memory;
The instruction code obtained by inverting the binary logic is acquired, and the acquired instruction code is interpreted by binary logic opposite to the first operation step, and the operation code is inverted according to the interpreted instruction code. A second operation step of executing processing in binary logic and storing second result data indicating the result of the processing in the internal memory;
Writing the first result data to a predetermined storage area in the non-volatile memory;
Inverting binary logic representing the first result data output from the non-volatile memory;
Acquiring the first result data obtained by inverting the binary logic, and comparing the acquired first result data with the second result data;
A computing method characterized by including. To a computer comprising a non-volatile memory storing instruction codes;
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. Operation step,
Inverting binary logic representing the instruction code output from the non-volatile memory;
The instruction code obtained by inverting the binary logic is acquired, and the acquired instruction code is interpreted by binary logic opposite to the first operation step, and the operation code is inverted according to the interpreted instruction code. A second operation step of executing processing in binary logic and storing second result data indicating the result of the processing in the internal memory;
An arithmetic processing program characterized by performing. To a computer comprising a non-volatile memory storing instruction codes;
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. Operation step,
Inverting binary logic representing the instruction code output from the non-volatile memory;
The instruction code obtained by inverting the binary logic is acquired, and the acquired instruction code is interpreted by binary logic opposite to the first operation step, and the operation code is inverted according to the interpreted instruction code. A second operation step of executing processing in binary logic and storing second result data indicating the result of the processing in the internal memory;
Inverting the binary logic representing the second result data;
Storing the second result data obtained by inverting the binary logic in a predetermined storage area of the non-volatile memory;
An arithmetic processing program characterized by performing. To a computer comprising a non-volatile memory storing instruction codes;
The instruction code output from the non-volatile memory is acquired, the acquired instruction code is interpreted, processing is executed according to the interpreted instruction code, and the first result data indicating the result of the processing is stored in the internal memory. Operation step,
Inverting binary logic representing the instruction code output from the non-volatile memory;
The instruction code obtained by inverting the binary logic is acquired, and the acquired instruction code is interpreted by binary logic opposite to the first operation step, and the operation code is inverted according to the interpreted instruction code. A second operation step of executing processing in binary logic and storing second result data indicating the result of the processing in the internal memory;
Writing the first result data to a predetermined storage area in the non-volatile memory;
Inverting binary logic representing the first result data output from the non-volatile memory;
Acquiring the first result data obtained by inverting the binary logic, and comparing the acquired first result data with the second result data;
An arithmetic processing program characterized by performing.

Images