JP6417903B2 - Signal modulation circuit - Google Patents

Description

  The present invention relates to a signal modulation circuit, and more particularly to a circuit that performs delta-sigma modulation.

  Conventionally, delta-sigma modulation (ΔΣ modulation) is used in switching amplifiers and the like. The delta-sigma modulator includes a subtracter, an integrator, a quantizer, and a quantization error feedback circuit. The subtractor calculates a difference between the input signal and the quantized feedback signal. The integrator integrates the difference signal. The integral signal is quantized by a quantizer and is output as a signal of 1 bit = 2 values, for example.

  The following Patent Document 1 discloses a delta-sigma modulation circuit composed of an integrator group, an adder group, a quantizer, and a pulse width round-up circuit, which is converted into a 1-bit signal synchronized with a sampling clock and output. Is disclosed. Further, it is disclosed that a D-type flip-flop is used as a quantizer. Patent Document 2 also discloses a delta-sigma modulation circuit.

  Patent Document 3 describes that a feedback signal is generated by reducing the switching signal by resistance division on a feedback loop that feeds back a switching signal obtained by pulse amplification of a quantized output signal to a delta-sigma modulation unit.

JP 2007-31258 A Special table 2012-527187 gazette Japanese Patent No. 3369503

  On the feedback loop that feeds back the switching signal to the delta-sigma modulation unit, generating the feedback signal by reducing the switching signal by resistance division is caused by ripple or external noise included in the constant voltage applied to the power amplification unit This is effective in that the waveform deformation of the switching signal is fed back as it is, but on the other hand, another problem may occur.

  That is, when the resistance value when dividing resistance is small, there is a problem that power consumption increases when the speaker output voltage driven by the switching signal is large, resulting in a heat generation problem and an increase in the size of the component. When the resistance value is large, there is a problem that the switching speed is lowered and the performance is deteriorated. In particular, since the printed circuit board pattern on the feedback loop tends to be relatively longer than the other lines, there is a problem that the signal attenuation of the high-frequency signal in the feedback loop cannot be ignored, and the performance tends to deteriorate.

  An object of the present invention is to provide a signal modulation circuit capable of generating a feedback signal to a delta-sigma modulation unit without suppressing an increase in power consumption and reducing a switching speed when generating a feedback signal. It is in.

The present invention is a signal modulation circuit that delta-sigma-modulates and outputs an input signal, a subtractor that calculates a difference between the input signal and a feedback signal, an integrator that integrates an output from the subtractor, A quantizer that delays and quantizes the signal integrated by the integrator, a driver circuit that generates a drive signal for driving a load based on the signal from the quantizer, and the drive from the driver circuit A feedback circuit that generates a feedback signal that feeds back a signal to the input signal, the feedback circuit including at least a first resistor and a second resistor connected in series to each other, and a capacitor connected in parallel to the first resistor The feedback signal is generated from a connection point between the first resistor and the second resistor.

In one embodiment of the present invention, the feedback circuit further includes a third resistor connected in series to the capacitor.
In another embodiment of the present invention, a resistance value of the third resistor is smaller than a resistance value of the first resistor.

In still another embodiment of the present invention, the resistance value of the first resistor is R1, the rated power consumption is P1, the resistance value of the second resistor is R2, the rated power consumption is P2, the drive voltage of the load is Vsp, When the voltage at the connection point between the first resistor and the second resistor is Vmid, R1> (Vsp−Vmid) ² / P1
R2> Vmid ² / P2
When the parasitic capacitance of the feedback circuit is Cfb and the capacitance of the capacitor is C1,
R1: R2≈Cfb: C1
It is characterized by being.

  According to the present invention, when generating a feedback signal, an increase in power consumption can be suppressed and a feedback signal can be generated without reducing the switching speed. Therefore, according to the present invention, the load can be driven with higher efficiency and higher performance than before.

It is a circuit block diagram of an embodiment. FIG. 2 is a circuit configuration diagram of a monovalent ternary waveform generation circuit and a driver circuit in FIG. 1. FIG. 2 is a circuit configuration diagram of the pulse synthesis circuit of FIG. 1. It is capacity setting explanatory drawing of capacitor C1. It is signal waveform explanatory drawing of embodiment. It is harmonic distortion explanatory drawing of embodiment. It is a circuit block diagram of the pulse synthesizing circuit of other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit configuration diagram of a signal modulation circuit according to the present embodiment. The signal modulation circuit includes a subtractor 10, an integrator 12, a phase inversion circuit 14, a monovalent ternary waveform generation circuit 16, a driver circuit 18, and a pulse synthesis circuit 22. The signal modulation circuit is connected to the speaker 20 as a load and drives the speaker 20.

  The subtractor 10 calculates the difference between the input signal and the feedback signal and outputs the difference to the integrator 12.

  The integrator 12 integrates the difference signal and outputs it to the phase inversion circuit 14 and the monovalent ternary waveform generation circuit 16. When outputting to the monovalent ternary waveform generating circuit 16, it is converted into a 1-bit digital signal by the DFF and output. The quantization function is realized by this DFF. However, in the DFF, the output can be made zero by supplying a signal to the reset terminal. Therefore, by supplying the clock signal to the reset terminal, the clock signal is converted to the clock signal. Zero level can be inserted at synchronized timing.

  The phase inversion circuit 14 inverts the phase of the output of the integrator 12 and outputs it to the monovalent ternary waveform generation circuit 16. When outputting to the monovalent ternary waveform generating circuit 16, it is converted into a 1-bit digital signal by the DFF and output. Similarly to the above, the quantization function is realized by this DFF, and a zero level can be inserted at a timing synchronized with the clock signal by supplying the clock signal to the reset terminal.

  By always inserting a zero level at a timing synchronized with the clock signal, the output of the DFF is a 1-bit digital signal and the pulse width is always a fixed digital signal. That is, the DFF outputs a signal at the rising edge of the input clock signal. For example, when a clock signal is supplied after being delayed and inverted by a delay circuit, the signal is output at the falling edge of the clock signal and the next clock signal rises. The output is reset to zero level at the edge, and this process is repeated, whereby the pulse width of the 1-bit digital signal becomes equal to the pulse width of the clock signal. Therefore, the magnitude of the input signal can be expressed by the number of pulses having a fixed pulse width.

  The monovalent ternary waveform generation circuit 16 includes a 1-bit digital signal from the integrator 12 and the DFF, that is, a binary signal of +1, 0, and a 1-bit digital signal from the phase inversion circuit 14 and the DFF, that is, −1, 0. A monovalent ternary waveform signal is generated from the binary signal (indicating that the phase is inverted by -1). Here, “monovalent ternary” means realizing three driving states of a load such as a speaker driven by a single power source, a state driven by a positive current, a state driven by a negative current, and an off state. Means. The positive current and the negative current mean that the directions of the currents flowing through the load are opposite to each other.

  The driver circuit 18 drives the speaker 20 as a load by using the monovalent ternary waveform signal from the monovalent ternary waveform generation circuit 16. The drive signal from the driver circuit 18 is supplied to the speaker 20 and also to the pulse synthesis circuit 22.

  The pulse synthesis circuit 22 functions as a feedback circuit, synthesizes the drive signals from the driver circuit 18 to generate a feedback signal, and feeds it back to the subtractor 10.

  One characteristic point in FIG. 1 is that the driver circuit 18 is included in the feedback loop. That is, the drive signal from the driver circuit 18 is not only supplied to the speaker 20 but also fed back to the subtractor 10 as a feedback signal through the pulse synthesis circuit 22. Therefore, when the driver circuit 18 is provided outside the feedback loop, the distortion of the driver circuit 18 is supplied as it is to the speaker 20 as a drive signal. In this embodiment, the distortion of the driver circuit 18 is also fed back and reduced. Can be done.

  FIG. 2 is a circuit configuration diagram of the monovalent ternary waveform generating circuit 16 and the driver circuit 18. The monovalent ternary waveform generation circuit 16 includes NOR gates 33a and 33b and four NOT gates 40a to 40d. These NOT gates 40a to 40d are referred to as G11, G12, G13, and G14 in order from the top in the figure, that is, the NOT gate 40a is referred to as G11, the NOT gate 40b is referred to as G12, the NOT gate 40c is referred to as G13, and the NOT gate 40d is referred to as G14. , G11 and G12 are supplied with the output signal of the NOR gate 33a, and G13 and G14 are supplied with the output signal of the NOR gate 33b. G11 to G14 invert respective input signals and supply output signals to the driver circuit 18, respectively.

  The NOR gate 33a is a signal from the inverting output terminal (Q bar) of the DFF 32 that converts the output of the integrator 12 into a 1-bit digital signal, and an output of the DFF 33 that converts the output from the phase inverting circuit 14 into a 1-bit digital signal. A logical operation is performed on the signal from the terminal (Q). The NOR gate 33b performs a logical operation on the signal from the output terminal (Q) of the DFF 32 and the signal from the inverting output terminal (Q bar) of the DFF 33, and outputs the result.

  The driver circuit 18 includes level shift circuits 42a1 and 42a2, gate drive circuits 42b1 to 42b4, and switching FETs 42c1 to 42c4. The switching FETs 42c1 and 42c3 are P-channel FETs, and the switching FETs 42c2 and 42c4 are N-channel FETs.

  The speaker 20 as a load has one end connected to the connection node of the switching FET 42c1 and the switching FET 42c2 connected in series with each other, and the other end connected to the connection node of the switching FET 42c3 and the switching FET 42c4 connected in series.

The switching FET 42c1 and the switching FET 42c3 are connected to the positive side of the single power source, and the switching FET 42c2 and the switching FET 42c4 are connected to the negative side of the single power source. Therefore, when the switching FET 42c1 is turned on and the switching FET 42c2 is turned off, and the switching FET 42c3 is turned off and the switching FET 42c4 is turned on,
Switching FET 42c1 → speaker 44 → switching FET 42c4
A current flows as shown in FIG.
When the switching FET 42c1 is turned off and the switching FET 42c2 is turned on, and the switching FET 42c3 is turned on and the switching FET 42c4 is turned off,
Switching FET 42c3 → Speaker → Switching FET 42c2
A current flows as shown in FIG.

  Further, when the switching FETs 42c1 and 42c3 are turned off and the switching FETs 42c2 and 42c4 are turned on, no current flows through the speaker 44, and the speaker 44 is turned off (off state due to a short circuit).

  The output signals of the four logic gates G11 to G14 of the monovalent ternary waveform generation circuit 16 are supplied to the respective gate drive circuits 42b1 to 42b4 for driving the four switching FETs 42c1 to 42c4. That is, the output signal of G11 is supplied to the gate drive circuit 42b1 via the level shift circuit 42a1, and drives the switching FET 42c1. The output signal of G12 is supplied to the gate drive circuit 42b2, and drives the switching FET 42c2. The output signal of G14 is supplied to the gate drive circuit 42b3 via the level shift circuit 42a2, and drives the switching FET 42c3. The output signal of G13 is supplied to the gate drive circuit 42b4 and drives the switching FET 42c4.

When the outputs of the NOR gates 33a and 33b are “1” and “0”, respectively, the outputs of G11 and G12 are “0” obtained by inverting “1”, and the outputs of G13 and G14 are “0” obtained by inverting “0”. 1 ". Then, the switching FET 42c1 is on, the switching FET 42c2 is off, the switching FET 42c3 is off, the switching FET c4 is on, and the current is
Switching FET 42c1 → speaker 44 → switching FET 42c4
(+ ON state).

When the outputs of the NOR gates 33a and 33b are “0” and “1”, respectively, the outputs of G11 and G12 are “1” obtained by inverting “0”, and the outputs of G13 and G14 are “1” obtained by inverting “1”. 0 ". Then, the switching FET 42c1 is turned off, the switching FET 42c2 is turned on, the switching FET 42c3 is turned on, the switching FET 42c4 is turned off, and the current is switched from the switching FET 42c3 to the speaker 44 to the switching FET 42c2.
(-ON state).

  When the outputs of the NOR gates 33b and 33a are “1”, the outputs of G11 to G14 are “0” obtained by inverting “1”. Then, the switching FET 42c1 is turned on, the switching FET 42c2 is turned off, the switching FET 42c3 is turned on, the switching FET c4 is turned off, and no current flows through the speaker 44 (off state).

  Further, when the outputs of the NOR gates 33b and 33a are “0”, the outputs of G11 to G14 are “1” obtained by inverting “0”. Then, the switching FET 42c1 is turned off, the switching FET 42c2 is turned on, the switching FET 42c3 is turned off, the switching FET c4 is turned on, and no current flows through the speaker 44 (off state).

  As described above, the monovalent ternary waveform generation circuit 16 generates the signal for driving the single power source tri-state speaker from the ternary pulse density modulation signal, thereby driving the speaker 20 without increasing the circuit scale. can do.

  The pulse synthesizing circuit 22 synthesizes the drive signal of the driver circuit 18 to generate a feedback signal. For example, in the circuit configuration of FIG. 2, a plurality of resistors are connected in parallel to the switching FET 42 c 2, And a plurality of resistors connected in parallel to the switching FET 42c4, a signal is output from the connection point, and both signals are combined to generate a feedback signal.

  FIG. 3 is a circuit configuration diagram of the pulse synthesis circuit 22. The pulse synthesizing circuit 22 includes resistors R1 and R2, a capacitor C1, a NOR gate 50, and a switch 52 as a first resistor and a second resistor.

  Resistors R1 and R2 are connected in series with the switching FET 42c2 in parallel, and resistors R1 and R2 are connected in series with the switching FET 42c4 in parallel. More specifically, resistors R1 and R2 are connected in series between the potential Vsp1 of the connection node of the switching FET 42c1 and the switching FET 42c2 and the ground potential. Similarly, the potential Vsp2 of the connection node of the switching FET 42c3 and the switching FET 42c4 and the ground potential The resistors R1 and R2 are connected in series. The resistors R1 and R2 lower the output voltage 20V to 100V of the speaker 20 to about 5V, for example.

  The connection points P and Q of R1 and R2 are connected to the input terminal of the NOR gate 50, respectively. The NOR gate 50 performs a logical calculation of the voltage signal at the connection points P and Q, and outputs the calculation result to the switch 52 to control on / off of the switch 52. The connection points P and Q of R1 and R2 are combined at the connection point R via a three-state buffer.

  One end of the switch 52 is connected to the reference voltage Vref, and the other end is connected to the connection point R. The other end of the switch 52, that is, the connection point R is also connected to the subtracter 10 and outputs a feedback signal Vfb to the subtractor 10. Therefore, when the switch 52 is turned on, the connection point R becomes the reference voltage Vref. On the other hand, when the switch 52 is turned off, a combined output of the output of the connection point P and the output of the connection point Q is output as the feedback signal Vfb.

  When the output at the connection point P and the output at the connection point Q are both “0” (that is, when both the switching FETs 42 c 2 and 42 c 4 are off), the output of the NOR gate 50 becomes “1” and the switch 52 is turned on. In this case, the reference voltage Vref signal is output to the subtracter 10 as the feedback signal Vfb.

  On the other hand, when either the output of the connection point P or the output of the connection point Q is “1” (that is, when one of the switching FETs 42c2 and 42c4 is on), the output of the NOR gate 50 becomes “0”. Switch 52 is turned off. In this case, the output from the connection point P and the output from the connection point Q are combined at the connection point R, and the combined voltage signal is output to the subtractor 10 as the feedback signal Vfb. Therefore, when the speaker 20 is in either the + ON state or the −ON state, the combined signal of the drive signals is output to the subtracter 10 as the feedback signal Vfb.

  Note that when both the output of the connection point P and the output of the connection point Q are “1”, the output of the NOR gate 50 is logically “0” and the switch 52 is turned off. The monovalent ternary waveform generation circuit 16 or the driver circuit 18 may be configured so as to exclude the condition that both the output of P and the output of the connection point Q are “1”.

  By the way, when the resistors R1 and R2 are simply connected, as described above, when the resistance values of R1 and R2 are small, the power consumption increases when the speaker output voltage driven by the switching signal is large, There is a problem that leads to an increase in the size of the component, and conversely, when the resistance value is large, there is a problem that the switching speed is lowered and the performance deteriorates.

  Therefore, in the pulse synthesizing circuit according to the present embodiment, as shown in FIG. 3, by connecting the capacitor C1 in parallel with the resistor R1, even if the resistance value is relatively increased, the switching speed is lowered, particularly the transient response. The deterioration of characteristics can be suppressed.

Specifically, when the capacitor C1 is not provided, assuming that the rated power consumption of the resistor R1 is P1, the rated power consumption of the resistor R2 is P2, and the voltage at the connection points P and Q is Vmid, R1 and R2 satisfy the following conditions: It is necessary to use in.
R1> (Vsp−Vmid) ² / P1
R2> Vmid ² / P2 (1)

  On the other hand, when R1 and R2 are determined under this condition, the output waveform may be “rounded” by the parasitic capacitances Cfb, R1, and R2 of the feedback loop, and a normal feedback signal cannot be generated, resulting in performance degradation.

Therefore, as shown in FIG. 4, when the parasitic capacitance of the feedback loop is represented by Cfb, the capacitor C1 is connected in parallel to the resistor R1, and the ratio of the capacitance C1 and the parasitic capacitance Cfb is determined by the ratio of the resistors R1 and R2. For the ratio
R1: R2 = Cfb: C1 (2)
Impedance matching is performed by

In the present embodiment, the expression (2) is not necessarily strictly satisfied,
R1: R2≈Cfb: C1 (3)
Of course, it will be understood.

  FIG. 5 shows an example of transient response characteristics when the capacitor C1 is not connected and when the capacitor C1 is connected. FIG. 5A shows the characteristics when the capacitor C1 is not connected, and FIG. 5B shows the characteristics when the capacitor C1 is connected.

  In FIG. 5A, a waveform 100 is an output signal waveform from the driver circuit 18, and a waveform 200 is a signal waveform of a feedback signal that is fed back to the subtractor 10. When the capacitor C1 is not connected, it can be seen that the output waveform is “rounded”.

  On the other hand, in FIG. 5B, a waveform 100 is similarly an output signal waveform from the driver circuit 18, and a waveform 300 is a signal waveform of a feedback signal fed back to the subtractor 10. By connecting the capacitor C1, there is almost no “round” in the output waveform, and a normal feedback signal can be generated.

  As described above, in this embodiment, the resistors R1 and R2 can be set sufficiently large so as to satisfy the equation (1) to prevent the parts from being damaged, and the resistor so as to satisfy the equation (2) or (3). By connecting the capacitor C1 in parallel with R1, it is possible to suppress a decrease in responsiveness and generate a normal feedback signal to improve performance. The pulse synthesizing circuit 22 of the present embodiment generates a feedback signal by setting the ratio of the parasitic capacitances Cfb and C1 in terms of AC, and generates a feedback signal by setting the ratio of the resistors R1 and R2 in terms of DC. I can say that.

  FIG. 6 shows the total harmonic distortion characteristics in this embodiment. In the figure, the horizontal axis is power, and the vertical axis is distortion rate + noise (%). For comparison, the case where the capacitor C1 is not connected and the resistance value is relatively increased, and the case where the capacitor C1 is not connected and the resistance value is relatively reduced are also shown. When the capacitor C1 is connected and the resistance value is relatively increased as in the present embodiment, harmonic distortion is suppressed in all power regions, and the performance is improved.

Second Embodiment
FIG. 7 is a circuit configuration diagram of the pulse synthesis circuit 22 of the present embodiment. A difference from FIG. 3 is that a resistor R3 is connected as a third resistor in series with the capacitor C1.

  As described in the first embodiment, the capacitor C1 is connected in parallel to the resistor R1, and the capacitance is adjusted to generate a normal feedback signal while using the resistors R1 and R2 within the rated power. It is possible to feed back to the subtracter 10. However, since the signal of the speaker 20 is instantaneously short-circuited by the parasitic capacitances Cfb and C1 by connecting the capacitor C1, a steep large current flows and inherently unnecessary radiation is generated. There may be cases. There is a concern that such radiation may affect sound quality as electromagnetic noise.

  Therefore, by connecting a resistor R3 in series with the capacitor C1, as shown in FIG. 7, it is possible to prevent a steep large current from flowing and to prevent unnecessary radiation.

Note that the resistance value of the resistor R3 is desirably smaller than the resistance value of the resistor R1 so that the feedback signal does not deteriorate. That is,
0 <R3 <R1 (4)
It is.

  In the present embodiment, the speaker 20 can be driven with higher performance by satisfying the expressions (1), (2), (2), and (4).

  As mentioned above, although embodiment of this invention was described, this invention is not limited to this, A various deformation | transformation is possible.

  For example, in this embodiment, a DFF is provided as a quantizer. However, instead of this, a quantizer may be configured by a chopper circuit and a DFF. By controlling on / off of switching of the chopper circuit with the clock signal, it is possible to generate a 1-bit digital signal while inserting a zero level at a timing synchronized with the clock signal.

  In the present embodiment, the pulse synthesizing circuit 22 as shown in FIG. 3 or FIG. 7 is shown, but this is only an example, and an arbitrary feedback signal is generated from the driving signal (driving voltage signal) of the speaker 20. It can be applied to a circuit configuration.

10 subtractor, 12 integrator, 14 phase inversion circuit, 16 monovalent ternary waveform generation circuit, 18 driver circuit, 20 speaker, 22 pulse synthesis circuit.

Claims (4)

A signal modulation circuit that outputs a delta-sigma modulated input signal,
A subtractor that calculates the difference between the input signal and the feedback signal;
An integrator for integrating the output from the subtractor;
A quantizer for quantizing the signal integrated by the integrator;
A driver circuit for generating a drive signal for driving a load based on a signal from the quantizer;
A feedback circuit that generates a feedback signal that feeds back the drive signal from the driver circuit to the input signal;
With
The feedback circuit includes at least a first resistor and a second resistor connected in series to each other, and a capacitor connected in parallel to the first resistor, from the connection point of the first resistor and the second resistor. A signal modulation circuit for generating a feedback signal. The signal modulation circuit according to claim 1,
The feedback circuit further includes a third resistor connected in series to the capacitor. The signal modulation circuit according to claim 2,
The signal modulation circuit, wherein a resistance value of the third resistor is smaller than a resistance value of the first resistor. In the signal modulation circuit according to any one of claims 1 to 3,
The resistance value of the first resistor is R1, the rated power consumption is P1, the resistance value of the second resistor is R2, the rated power consumption is P2, the drive voltage of the load is Vsp, and the first resistance and the second resistance are When the voltage at the connection point is Vmid, R1> (Vsp−Vmid) ² / P1
R2> Vmid ² / P2
When the parasitic capacitance of the feedback circuit is Cfb and the capacitance of the capacitor is C1,
R1: R2≈Cfb: C1
A signal modulation circuit.