JP2009303133A - Digital amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital amplifier for preventing use efficiency of an output signal from being reduced. <P>SOLUTION: A digital amplifier includes: a delta-sigma modulator which quantizes an input signal through delta-sigma modulation to produce a quantized output signal; a power amplifier which produces a pulse-amplified output signal by switching a constant voltage in accordance with the quantized output signal produced by the delta-sigma modulator; and an attenuator 15c which is provided on a feedback loop feeding the output signal produced by the power amplifier back to the delta-sigma modulator for producing a feedback signal by attenuating the output signal through a capacitor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital amplifier that performs amplification by generating a PWM (Pulse Width Modulation) signal based on an input signal and switching a high voltage.

  As a digital amplifier, a digital input type class D amplifier that generates a 1-bit PWM signal by delta-sigma modulation (ΔΣ modulation) of an input signal (for example, an audio signal) and amplifies the input signal based on the generated PWM signal is known. It has been. In this digital switching amplifier, a technique is known in which the amplified output is decompressed and fed back to a delta-sigma calculator in order to suppress distortion in the time axis direction caused by amplification (see, for example, Patent Document 1). .

  FIG. 11 is a block diagram showing an electrical configuration of a typical conventional digital switching amplifier.

  The digital switching amplifier includes a difference unit 11, an integrator / adder group 12, a quantizer 13, a constant voltage switch (power amplification unit) 14, an attenuator (decompression unit) 15, and an arithmetic unit 16. When the digital switching amplifier is used as an audio signal reproducing device, a low-pass filter (LPF) 17 and a low-pass filter (LPF) 18 are connected to the output side of the constant voltage switch 14, and the output signals of the LPF 17 and LPF 18 are connected to the speaker. 19 is supplied. Note that the delta-sigma modulation unit includes an integrator / adder group 12 and a quantizer 13.

  The difference unit 11 inputs an input signal (for example, an audio signal) from a signal source and a feedback signal that is negatively fed back from the constant voltage switch 14 through a feedback loop that passes through the attenuator 15 and the computing unit 16. The signal difference value is obtained. The input signal may be either an analog signal or a digital signal. The input signal may be a 1-bit digital signal.

  The integrator / adder group 12 is a high-order integrator, and generates a difference integration addition signal by integrating and adding the difference signals from the difference unit 11. The quantizer 13 determines the polarity of the differential integral addition signal from the integrator / adder group 12 and converts it to binary (1 bit) to generate a two-phase quantized output signal (digital signal). Here, the quantization threshold of the quantizer 13 is optimally set with respect to the assumed sampling frequency. The quantizer 13 operates in response to the clock signal.

  As shown in FIG. 12, the constant voltage switch 14 includes a first constant voltage switch 14 a and a second constant voltage switch 14 b corresponding to each of the two-phase quantized output signals from the quantizer 13. Each of the first constant voltage switch 14a and the second constant voltage switch 14b is configured by a switching device (for example, FET) connected in a totem pole, and by switching the quantized output signal as a switching control signal, a constant (not shown) is illustrated. A switching signal having a power supply voltage supplied from a voltage source is generated, and power amplification is performed.

  A two-phase pulse amplification signal (switching signal) obtained by power amplification by the constant voltage switch 14 is output to the LPF 17 and the LPF 18 as an output signal and also to the attenuator 15.

  As shown in FIG. 12, the attenuator 15 includes a first attenuator 15a and a second attenuator 15b. The first attenuator 15a includes a resistor R1a and a resistor R2a connected in series between the output terminal of the first constant voltage switch 14a and GND, and a connection point between the resistor R1a and the resistor R2a is a feedback loop. It is connected to a computing unit 16 that forms a part. The signal attenuated by the first attenuator 15 a is output to the calculator 16. In addition, each resistance value of resistance R1a and resistance R2a is set so that it may become the decompression ratio according to the amount of amplification in the 1st constant voltage switch 14a, ie, a power supply voltage.

  The second attenuator 15b is composed of resistors R1b and R2b connected in series between the output terminal of the second constant voltage switch 14b and GND, and the connection point between the resistor R1b and the resistor R2b is one of the feedback loops. It is connected to the arithmetic unit 16 which forms a part. The signal attenuated by the second attenuator 15b is output to the arithmetic unit 16. The resistance values of the resistor R1b and the resistor R2b are set so as to have a reduction ratio corresponding to the amount of amplification in the second constant voltage switch 14b, that is, the power supply voltage.

  The computing unit 16 performs predetermined processing on the two signals from the attenuator 15 and outputs the two signals to the difference unit 11 as feedback signals. Thereby, the attenuator 15 is provided on the feedback loop, attenuates the pulse amplification signal output from the constant voltage switch 14, and negatively feeds back to the difference unit 11 as a feedback signal.

  Next, the operation of the conventional digital switching amplifier configured as described above will be described. First, the difference unit 11 receives an input signal such as an audio signal input from a signal source and a feedback signal negatively fed back through an attenuator 15 by a feedback loop, and obtains a difference signal between these two signals. . The integrator / adder group 12 integrates the difference signals and adds them to form noise, and outputs the resultant signals to the quantizer 13 as difference integration addition signals.

  The quantizer 13 determines the polarity of the differential integral addition signal from the integrator / adder group 12 and converts it to a binary value of “1” or “0” to generate a two-layer quantized output signal. The constant voltage switch 14 generates a two-phase switching signal having a power supply voltage by switching each of the delta-sigma modulated two-phase quantized output signals from the quantizer 13 as a switching control signal.

The attenuator 15 attenuates each of the two-phase output signals from the constant voltage switch 14, and the arithmetic unit 16 performs a predetermined process on the two signals from the attenuator 15 and outputs the differencer 11 as a feedback signal. To output. As a result, the pulse amplification signal output from the constant voltage switch 14 is attenuated to form a feedback loop that is negatively fed back to the differentiator 11 as a feedback signal.
JP 2000-295049 A

  In the conventional digital switching amplifier, as a pressure reducing method in the attenuator 15, voltage division by resistance division is used as shown in FIG. Therefore, since the current flows through the dividing resistor every time the constant voltage switch 14 is switched, the use efficiency of the output signal from the constant voltage switch 14 is lowered. In addition, since a current flows through the dividing resistor, it is necessary to take measures against heat generation. Furthermore, depending on the value of the power supply voltage, the attenuation time in the attenuator 15 may change.

  In addition, the conventional digital switching amplifier employs a form in which the two-phase switching signal output from the constant voltage switch 14 is fed back to the delta-sigma calculator. In the feedback circuit to the delta-sigma arithmetic unit, when the control unit and the output unit are configured by a monolithic IC of one chip, the number of feedback lines is not a problem.

  However, for example, as shown in FIG. 13, when the control unit (including the delta sigma modulator) and the output unit (including the attenuator) have a two-chip configuration or a two-element configuration, feedback is provided from the viewpoint of cost and signal processing. The number of is preferably smaller.

  In the digital switching amplifier having the H-bridge configuration described above, two output signals of A phase and B phase are generated for each channel, but distortion in the time axis direction is generated by the L component of the LPF in each phase. For this reason, it is necessary to feed back the distortion information in the time axis direction of the two output signals. In the case of a 2-channel digital switching amplifier, four wires are required for a feedback signal to the delta-sigma modulation unit, which is not preferable from the viewpoint of cost and assembly.

  The subject of this invention is providing the digital amplifier which can suppress the fall of the use efficiency of an output signal. Another object of the present invention is to provide a digital amplifier capable of reducing the number of wirings.

  In order to solve the above problems, the invention of claim 1 is directed to a delta-sigma modulation unit that generates a quantized output signal by delta-sigma modulation and quantization of an input signal, and a quantum generated by the delta-sigma modulation unit. A power amplifying unit that generates a pulse-amplified output signal by switching a constant voltage according to the output signal, and a feedback loop that feeds back the output signal generated by the power amplifying unit to the delta-sigma modulation unit And an attenuator for generating a feedback signal obtained by attenuating the output signal through the capacitor.

According to a second aspect of the present invention, in the first aspect of the present invention, the attenuator includes a capacitor having one end connected to the output end of the power amplifier and a logic circuit element having an input terminal connected to the other end of the capacitor. It is characterized by
According to a third aspect of the present invention, in the first aspect of the invention, the attenuator includes a capacitor having one end connected to the output end of the power amplifying unit and a window comparator having the input terminal connected to the other end of the capacitor. It is characterized by.

  According to a fourth aspect of the present invention, in the second or third aspect of the present invention, the attenuator includes a protective diode having a cathode electrode connected to the other end of the capacitor and an anode electrode grounded.

  According to a fifth aspect of the present invention, in the second or third aspect of the present invention, the attenuator includes a protection diode in which the cathode electrode is connected to the other end of the capacitor and the anode electrode is grounded, and the output terminal of the power amplifier. An anode electrode is connected to the other end of the capacitor having one end connected to the capacitor, and another protective diode having a cathode electrode connected to a logic power supply.

  According to a sixth aspect of the present invention, in the third aspect of the present invention, the attenuator includes a Zener diode that generates a reference voltage of the window comparator by connecting a cathode electrode to a division point obtained by resistance division of the logic power source and grounding the anode electrode. It is characterized by providing.

  According to the seventh aspect of the present invention, a delta-sigma modulation unit that generates a quantized output signal by performing delta-sigma modulation and quantization of an input signal, and a quantized output signal generated by the delta-sigma modulation unit are defined. A power amplification unit that generates a two-phase output signal that is pulse-amplified by switching the voltage, and a feedback loop that feeds back the two-phase output signal generated by the power amplification unit to the delta-sigma modulation unit; An attenuator for generating a signal obtained by attenuating each of the two-phase output signals, and an exclusive OR circuit for generating a feedback signal obtained by taking an exclusive OR of the two-phase output signals attenuated by the attenuator. It is characterized by providing.

  The invention of claim 8 comprises the waveform shaping circuit for shaping the signal output from the exclusive OR circuit when the power amplifying unit generates a one-phase output signal in the invention of claim 7. Features.

  According to the first to sixth aspects of the invention, since the feedback signal obtained by attenuating the output signal through the capacitor is generated, it is possible to suppress a decrease in the use efficiency of the output signal.

  According to the seventh and eighth aspects of the invention, the number of feedback lines can be reduced, which is more advantageous than the conventional digital switching amplifier in terms of cost and signal processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals as those used in the background art section are used for the portions corresponding to the constituent parts described in the background art section.

  The configuration of the digital amplifier according to the first embodiment of the present invention is the same as the configuration of the conventional digital switching amplifier shown in FIG. 11 except for the internal configuration of the attenuator.

  Note that the delta-sigma modulation unit of the present invention includes an integrator / adder group 12 and a quantizer 13. The power amplification unit of the present invention is configured by a constant voltage switch 14.

  FIG. 1 is a circuit diagram showing a configuration of an attenuator 15c used in the digital amplifier according to Embodiment 1 of the present invention. In the attenuator 15c, the attenuation mechanism is realized as an insulating pressure reducer using a capacitor, and two attenuators 15c are provided as in the conventional attenuators 15a and 15b shown in FIG.

  In the attenuator 15c shown in FIG. 1, a capacitor C1 and a Zener diode ZD1 connected in series are provided between the output terminal of the constant voltage switch 14 and GND. A resistor R1 and a resistor R2 connected in series are provided between the logic voltage and GND. An input terminal of the Schmitt inverter 1 is connected to a connection point P between the capacitor C1 and the Zener diode ZD1 and a connection point between the resistor R1 and the resistor R2. An inverter 2 is connected to the output terminal of the Schmitt inverter 1, and the inverter 2 outputs an output signal Q to the calculator 16.

  The cathode electrode of the Zener diode ZD1 is connected to the other end of the capacitor C1, and the anode electrode of the Zener diode ZD1 is grounded (GND). The Zener diode ZD1 functions as a protective diode that protects the gate oxide film of the Schmitt inverter 1 by suppressing undershoot to the GND side.

  Next, the operation of the attenuator 15c configured as described above and shown in FIG. 1 will be described. The output signal from the constant voltage switch 14 is supplied to the input terminal of the Schmitt inverter 1 via the capacitor C1. A voltage (1.65 V) that is a half of a logic voltage (for example, 3.3 V) is biased at the input terminal of the Schmitt inverter 1 due to resistance division between the resistors R1 and R2, and the output signal changes. When this occurs, a change occurs at the input terminal of the Schmitt inverter 1.

  Since the resistors R1 and R2 only apply a bias voltage to the input terminal of the Schmitt inverter 1, the resistance values can be increased. Therefore, the power consumed by the resistor R1 and the resistor R2 can be reduced.

  FIG. 2 is a waveform diagram showing the operation of the attenuator 15c. FIG. 2A shows a waveform of an output signal from the constant voltage switch 14, which is a pulse amplification signal (switching signal) that is turned on / off at a high voltage such as 18V.

  When this output signal is input to a differentiation circuit composed of a capacitor C1 and a resistor R1, at the point P, as shown in FIG. A signal having a waveform that rises steeply at the rising edge of the output signal and falls sharply at the falling edge of the output signal is obtained.

  This signal is input to the input terminal of the Schmitt inverter 1 and inverted, and further inverted by the inverter 2 and output as a signal Q. As a result, as shown in FIG. 2C, the signal Q decompressed to the logic voltage is output to the arithmetic unit 16.

  As described above, according to the digital amplifier according to the first embodiment, the attenuator 15c generates a feedback signal obtained by attenuating the output signal through the capacitor C1, and thus it is possible to suppress a decrease in use efficiency of the output signal.

  The attenuator 15c of the digital amplifier according to the first embodiment described above may be modified as follows.

(First modification)
FIG. 3 is a circuit diagram illustrating a configuration of a first modification of the attenuator 15d of the digital amplifier according to the first embodiment. The attenuator 15d is configured by adding a Zener diode ZD2 to the attenuator 15c shown in FIG.

  The cathode electrode of the Zener diode ZD2 is connected to one end of the logic voltage and the resistor R2, and the anode electrode of the Zener diode ZD2 is connected to the input terminal of the Schmitt inverter 1. The Zener diode ZD2 functions as a protective diode that protects the gate oxide film of the Schmitt inverter 1 by suppressing overshoot to the logic voltage side.

(Second modification)
FIG. 4 is a circuit diagram showing a configuration of a second modified example using a window comparator instead of the Schmitt inverter 1 of the attenuator 15d shown in FIG. The window comparator has two comparators, a comparator CMP1 that catches the rising edge of the output signal and a comparator CMP2 that catches the falling edge, and an AND circuit AND that takes the logical product of the outputs of the comparators CMP1 and CMP2.

  Further, a resistor R3, a resistor R4, and a resistor R5 connected in series are provided between the logic voltage and GND. The voltage at the connection point between the resistors R4 and R5 is applied as a reference voltage to the non-inverting input terminal of the comparator CMP1. The voltage at the connection point between the resistor R4 and the resistor R3 is applied as a reference voltage to the inverting input terminal of the comparator CMP2.

  The connection point between the capacitor C1 and the Zener diode ZD1, the anode electrode of the Zener diode ZD2, and the connection point between the resistor R1 and the resistor R2 are connected to the inverting input terminal of the comparator CMP1 and the non-inverting input terminal of the comparator CMP2. ing.

  The reference voltage of the comparator CMP1 is taken from the connection point between the resistor R4 and the resistor R5 so that the reference voltage is larger than half of the logic voltage and smaller than the logic voltage. Further, the reference voltage of the comparator CMP2 is taken from the connection point between the resistor R3 and the resistor R4 so as to be a value larger than the GND voltage and smaller than a half of the logic voltage.

  According to this configuration, when the voltage at the connection point between the capacitor C1 and the Zener diode ZD1 is equal to or higher than the voltage at the connection point between the resistors R3 and R4 and equal to or lower than the voltage at the connection point between the resistors R4 and R5. In addition, an H level output signal Q is output from the AND circuit AND to the arithmetic unit 16.

  With this window comparator, a waveform obtained by reducing the output signal can be acquired. The Zener diodes ZD1 and ZD2 have the same functions as the Zener diodes shown in FIGS.

(Third Modification)
FIG. 5 is a circuit diagram illustrating a configuration of a third modification of the attenuator 15f of the digital amplifier according to the first embodiment. An attenuator 15f shown in FIG. 5 is obtained by adding the following configuration to the attenuator 15e shown in FIG.

  The resistor R4 is divided into a resistor R4a and a resistor R4b, the cathode electrode of the Zener diode ZD3 is connected to the connection point between the resistor R4a and the resistor R4b, and the anode electrode of the Zener diode ZD3 is grounded. With this configuration, the accuracy of the reference voltage applied to the comparators CMP1 and CMP2 can be improved.

  FIG. 6 is a circuit diagram showing a configuration of a digital amplifier according to Embodiment 2 of the present invention. The digital amplifier is configured by adding an exclusive OR (XOR) circuit 20 to the digital amplifier according to the first embodiment described above. The exclusive OR circuit 20 takes the exclusive OR of two attenuated signals output from the attenuator 15c (or any one of 15d, 15e, and 15f) and outputs one signal to the arithmetic unit 16.

  FIG. 7 is a timing chart showing the operation of the exclusive OR circuit 20. When a two-phase attenuated signal is input from the attenuator 15c, the exclusive OR circuit 20 specifically receives an attenuated signal from one attenuator 15c1 as shown in FIG. And an attenuated signal as shown in FIG. 7B is input from the other attenuator 15c2. In this case, an exclusive OR of these attenuated signals is taken, an exclusive OR signal as shown in FIG. 7C is generated and output to the arithmetic unit 16.

  With this configuration, as shown in FIG. 8, even if the digital amplifier has a two-chip configuration or a two-element configuration, only one feedback line is required. For this reason, it is more advantageous than the conventional configuration shown in FIG. 13 in terms of cost and signal processing.

  FIG. 7 shows an example in which exclusive OR is performed when the digital amplifier performs two-phase modulation in which two output signals having different pulse widths are generated, but the pulse width is the same and the phase is 180 degrees. The present invention can be modified so as to be applied to the case of one-phase modulation that generates two different output signals. In this case, a waveform shaping circuit 21 as shown in FIG. 9 is used. The waveform shaping circuit 21 can be composed of a D-type flip-flop circuit connected so as to be inverted every time a thin pulse output from the exclusive OR circuit 20 is received.

  FIG. 10 is a timing chart showing operations of the exclusive OR circuit 20 and the waveform shaping circuit 21 in the case of one-phase modulation.

  When a two-phase attenuated signal is input from the attenuator 15c, the exclusive OR circuit 20 specifically receives an attenuated signal from one attenuator 15c1 as shown in FIG. Is input, and the other attenuator 15c2 receives a signal that is 180 degrees out of phase with respect to the attenuated signal from one attenuator 15c1 as shown in FIG. In this case, an exclusive OR of these attenuated signals is taken to generate a thin pulse exclusive OR signal as shown in FIG. To 21.

  As shown in FIG. 10D, the waveform shaping circuit 21 outputs a signal that is inverted every time a thin pulse output from the exclusive OR circuit 20 is received. As a result, a signal obtained by restoring the output signal is generated and output to the arithmetic unit 16.

It is a circuit diagram which shows the structure of the attenuator used with the digital amplifier which concerns on Example 1 of this invention. It is a wave form diagram which shows operation | movement of the attenuator used with the digital amplifier which concerns on Example 1 of this invention. It is a circuit diagram which shows the structure of the 1st modification of the attenuator of the digital amplifier which concerns on Example 1 of this invention. It is a circuit diagram which shows the structure of the 2nd modification of the attenuator of the digital amplifier which concerns on Example 1 of this invention. It is a circuit diagram which shows the structure of the 3rd modification of the attenuator of the digital amplifier which concerns on Example 1 of this invention. It is a circuit diagram which shows the structure of the attenuator used with the digital amplifier which concerns on Example 2 of this invention. It is a timing chart which shows operation | movement of the exclusive OR circuit used with the digital amplifier which concerns on Example 2 of this invention. It is a figure for demonstrating the effect of the digital amplifier which concerns on Example 2 of this invention. It is a figure for demonstrating the waveform shaping circuit used with the modification of the digital amplifier which concerns on Example 2 of this invention. It is a timing chart which shows operation | movement of the modification of the digital amplifier which concerns on Example 2 of this invention. It is a block diagram which shows the electric constitution of the conventional typical digital switching amplifier. It is a circuit diagram which shows the detailed structure of the output part of the conventional digital switching amplifier. It is a figure for demonstrating the problem of the conventional digital switching amplifier.

Explanation of symbols

1 Schmitt Inverter 2 Inverter 11 Differencer 12 Integrator / Adder Group 13 Quantizer 14 Constant Voltage Switch 15, 15 a to 15 f Attenuator 16 Calculator 17, 18 LPF
19 Speaker 20 Exclusive OR circuit 21 Waveform shaping circuit 22 Logic circuit (D flip-flop)
C1 capacitors R1-R5, R1a, R1b, R2a, R2b, R4a, R4b resistors ZD1-ZD3 Zener diodes CMP1, CMP2 comparator AND logic circuit

Claims (8)

A delta-sigma modulation unit that generates a quantized output signal by delta-sigma modulating and quantizing the input signal;
A power amplifying unit that generates a pulse-amplified output signal by switching a constant voltage according to the quantized output signal generated by the delta-sigma modulation unit;
An attenuator that is provided on a feedback loop that feeds back the output signal generated by the power amplification unit to the delta-sigma modulation unit, and that generates a feedback signal obtained by attenuating the output signal through a capacitor;
A digital amplifier comprising: The attenuator is
A capacitor having one end connected to the output end of the power amplifier;
A logic circuit element having an input terminal connected to the other end of the capacitor;
The digital amplifier according to claim 1, further comprising: The attenuator is
A capacitor having one end connected to the output end of the power amplifier;
A window comparator having an input terminal connected to the other end of the capacitor;
The digital amplifier according to claim 1, further comprising: The attenuator is
4. The digital amplifier according to claim 2, further comprising a protective diode having a cathode electrode connected to the other end of the capacitor and an anode electrode grounded. The attenuator is
A protective diode in which a cathode electrode is connected to the other end of the capacitor and an anode electrode is grounded;
3. The power amplifier according to claim 2, further comprising: another protective diode in which an anode electrode is connected to the other end of the capacitor, one end of which is connected to an output end of the power amplifier, and a cathode electrode is connected to a logic power source. The digital amplifier according to claim 3. The attenuator is
4. The digital amplifier according to claim 3, further comprising: a Zener diode that generates a reference voltage of the window comparator by connecting a cathode electrode to a division point obtained by dividing the logic power supply by resistance and grounding an anode electrode. A delta-sigma modulation unit for generating a quantized output signal by delta-sigma modulating and quantizing the input signal;
A power amplifying unit for generating a pulse-amplified two-phase output signal by switching a constant voltage according to the quantized output signal generated by the delta-sigma modulation unit;
An attenuator that is provided on a feedback loop that feeds back the two-phase output signal generated by the power amplification unit to the delta-sigma modulation unit, and that generates a signal obtained by attenuating each of the two-phase output signals;
An exclusive OR circuit for generating a feedback signal obtained by taking an exclusive OR of the two-phase output signals attenuated by the attenuator;
A digital amplifier comprising:   8. The digital amplifier according to claim 7, further comprising a waveform shaping circuit that shapes a signal output from the exclusive OR circuit when the power amplification unit generates a one-phase output signal.

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