JP6399994B2 - High frequency package - Google Patents

High frequency package Download PDF

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JP6399994B2
JP6399994B2 JP2015239242A JP2015239242A JP6399994B2 JP 6399994 B2 JP6399994 B2 JP 6399994B2 JP 2015239242 A JP2015239242 A JP 2015239242A JP 2015239242 A JP2015239242 A JP 2015239242A JP 6399994 B2 JP6399994 B2 JP 6399994B2
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stub
integrated circuit
microwave integrated
monolithic microwave
frequency package
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JP2017107931A (en
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友幸 海野
友幸 海野
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Mitsubishi Electric Corp
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本発明は、モノリシックマイクロ波集積回路を備えた高周波パッケージに関する。   The present invention relates to a high-frequency package including a monolithic microwave integrated circuit.

従来、特許文献１に開示されるように、高周波パッケージは、セラミック又は樹脂を原料とする積層基板に実装されたモノリシックマイクロ波集積回路を動作させるために設けられたバイアス線路に、電磁妨害特性確保の為に使用周波数での４分の１波長のスタブを設けている。   Conventionally, as disclosed in Patent Document 1, a high-frequency package has an electromagnetic interference characteristic secured on a bias line provided to operate a monolithic microwave integrated circuit mounted on a multilayer substrate made of ceramic or resin. For this purpose, a quarter-wave stub at the operating frequency is provided.

特開２００８−４８４４５号公報JP 2008-48445 A

しかしながら、上記従来の技術によれば現状の構成では、４分の１波長スタブは信号用パターンにより平面上に形成され、かつバイアス信号数分の４分の１波長スタブが必要となるため、積層基板面積が大きくなってしまう問題があった。   However, according to the above-described conventional technology, in the current configuration, the quarter-wave stub is formed on the plane by the signal pattern, and a quarter-wave stub corresponding to the number of bias signals is required. There has been a problem that the substrate area becomes large.

本発明は、上記に鑑みてなされたものであって、電磁妨害特性を確保しつつ積層基板の面積の増大を抑制した高周波パッケージを得ることを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to obtain a high-frequency package that suppresses an increase in the area of a multilayer substrate while ensuring electromagnetic interference characteristics.

上述した課題を解決し、目的を達成するために、本発明は、積層基板に実装されたモノリシックマイクロ波集積回路を有する高周波パッケージであって、モノリシックマイクロ波集積回路を動作させるバイアス信号を伝える信号用パターンから分岐するスタブビアを有する。スタブビアの長さは、モノリシックマイクロ波集積回路の使用周波数の波長の４分の１である。   In order to solve the above-described problems and achieve the object, the present invention is a high-frequency package having a monolithic microwave integrated circuit mounted on a multilayer substrate, and a signal for transmitting a bias signal for operating the monolithic microwave integrated circuit A stub via branched from the pattern for use. The length of the stub via is a quarter of the wavelength of the operating frequency of the monolithic microwave integrated circuit.

本発明によれば、電磁妨害特性を確保しつつ積層基板の面積の増大を抑制できるという効果を奏する。   According to the present invention, there is an effect that an increase in the area of the multilayer substrate can be suppressed while ensuring electromagnetic interference characteristics.

本発明の実施の形態１に係る高周波パッケージの構成を示す図The figure which shows the structure of the high frequency package which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る高周波パッケージの構成を示す図The figure which shows the structure of the high frequency package which concerns on Embodiment 2 of this invention.

以下に、本発明の実施の形態に係る高周波パッケージを図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。   Hereinafter, a high-frequency package according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

実施の形態１．
図１は、本発明の実施の形態１に係る高周波パッケージの構成を示す図である。実施の形態１に係る高周波パッケージ２０では、モノリシックマイクロ波集積回路３が実装される積層基板は、第１の積層基板１である。高周波パッケージ２０は、第１の積層基板１にモノリシックマイクロ波集積回路３が搭載されており、第１の積層基板１と第２の積層基板２とは、はんだバンプ１０を介して重ねられている。モノリシックマイクロ波集積回路３を動作させるバイアス信号は、第２の積層基板２から信号用パターン１３、信号用ビア１１、はんだバンプ１０、信号用ビア６、信号用パターン８及びワイヤ５を介してモノリシックマイクロ波集積回路３に供給される。すなわち、モノリシックマイクロ波集積回路３を動作させるバイアス信号は、第１の積層基板１及びリッド４で構成されたパッケージの外から供給される。なお、バイアス信号を供給する上記の経路は、シールド用ビア７、シールド用パターン９、シールド用ビア１２及びシールド用パターン１４によりシールドされている。 Embodiment 1 FIG.
1 is a diagram showing a configuration of a high-frequency package according to Embodiment 1 of the present invention. In the high frequency package 20 according to the first embodiment, the multilayer substrate on which the monolithic microwave integrated circuit 3 is mounted is the first multilayer substrate 1. In the high frequency package 20, the monolithic microwave integrated circuit 3 is mounted on the first multilayer substrate 1, and the first multilayer substrate 1 and the second multilayer substrate 2 are stacked via the solder bumps 10. . The bias signal for operating the monolithic microwave integrated circuit 3 is monolithic from the second laminated substrate 2 through the signal pattern 13, the signal via 11, the solder bump 10, the signal via 6, the signal pattern 8 and the wire 5. It is supplied to the microwave integrated circuit 3. That is, a bias signal for operating the monolithic microwave integrated circuit 3 is supplied from outside the package formed of the first laminated substrate 1 and the lid 4. The path for supplying the bias signal is shielded by the shield via 7, the shield pattern 9, the shield via 12, and the shield pattern 14.

モノリシックマイクロ波集積回路３を動作させるバイアス信号を伝える信号用パターン８からは、スタブビア１５が分岐している。スタブビア１５の長さは、モノリシックマイクロ波集積回路３の使用周波数での波長の４分の１となっている。すなわち、スタブビア１５は、４分の１波長スタブを構成している。なお、スタブビア１５の下端に配線パターンを接続し、配線パターンを含めた導体長さがモノリシックマイクロ波集積回路３の使用周波数での波長の４分の１となるようにしてもよい。また、スタブビア１５は、第１の積層基板１の複数の層に跨がって形成されていてもよい。   A stub via 15 branches off from a signal pattern 8 for transmitting a bias signal for operating the monolithic microwave integrated circuit 3. The length of the stub via 15 is a quarter of the wavelength at the operating frequency of the monolithic microwave integrated circuit 3. That is, the stub via 15 constitutes a quarter wavelength stub. Note that a wiring pattern may be connected to the lower end of the stub via 15 so that the conductor length including the wiring pattern is a quarter of the wavelength at the use frequency of the monolithic microwave integrated circuit 3. Further, the stub via 15 may be formed across a plurality of layers of the first laminated substrate 1.

実施の形態１では、４分の１波長スタブを構成するスタブビア１５は、第１の積層基板１の積層方向に形成されている。したがって、積層基板１の面内で４分の１波長スタブが占有する面積は、４分の１波長スタブを信号用パターン８のみで形成する場合よりも小さくなる。したがって、電磁妨害特性を確保しつつ第１の積層基板１の面積を縮小し、高周波パッケージを小型化することが可能となる。   In the first embodiment, the stub via 15 constituting the quarter wavelength stub is formed in the stacking direction of the first stacked substrate 1. Therefore, the area occupied by the quarter-wave stub in the plane of the multilayer substrate 1 is smaller than when the quarter-wave stub is formed only by the signal pattern 8. Therefore, the area of the first laminated substrate 1 can be reduced while ensuring the electromagnetic interference characteristics, and the high-frequency package can be downsized.

実施の形態２．
図２は、本発明の実施の形態２に係る高周波パッケージの構成を示す図である。実施の形態２に係る高周波パッケージ３０は、第１の積層基板１にモノリシックマイクロ波集積回路３が搭載されており、第１の積層基板１と第２の積層基板２とは、はんだバンプ１０を介して重ねられている。モノリシックマイクロ波集積回路３を動作させるバイアス信号が、第２の積層基板２から信号用パターン１３、信号用ビア１１、はんだバンプ１０、信号用ビア６、信号用パターン８及びワイヤ５を介してモノリシックマイクロ波集積回路３に供給される構造は、実施の形態１と同様である。しかし、実施の形態２では、第１のスタブビア１６は、第１の積層基板１の複数の層に跨がって形成されており、第１の積層基板１の裏面１Ｒに達し、裏面パターン１９を介してはんだバンプ１０に接続されている。第１のスタブビア１６に接続されたはんだバンプ１０は、第２の積層基板２側では、表面パターン２１を介して第２のスタブビア１７に接続されている。 Embodiment 2. FIG.
FIG. 2 is a diagram showing the configuration of the high-frequency package according to Embodiment 2 of the present invention. In the high frequency package 30 according to the second embodiment, the monolithic microwave integrated circuit 3 is mounted on the first multilayer substrate 1, and the first multilayer substrate 1 and the second multilayer substrate 2 have solder bumps 10. Are overlaid. The bias signal for operating the monolithic microwave integrated circuit 3 is monolithic from the second laminated substrate 2 through the signal pattern 13, the signal via 11, the solder bump 10, the signal via 6, the signal pattern 8 and the wire 5. The structure supplied to the microwave integrated circuit 3 is the same as that of the first embodiment. However, in the second embodiment, the first stub via 16 is formed across a plurality of layers of the first multilayer substrate 1, reaches the rear surface 1 </ b> R of the first multilayer substrate 1, and has a rear surface pattern 19. It is connected to the solder bump 10 via The solder bump 10 connected to the first stub via 16 is connected to the second stub via 17 via the surface pattern 21 on the second laminated substrate 2 side.

実施の形態２では、第１のスタブビア１６、はんだバンプ１０、第２のスタブビア１７によって４分の１波長スタブが形成されている。なお、第２のスタブビア１７の下端に接続した配線パターン１８を含めた導体長さがモノリシックマイクロ波集積回路３の使用周波数での波長の４分の１となるようにしてもよい。   In the second embodiment, a quarter-wave stub is formed by the first stub via 16, the solder bump 10, and the second stub via 17. Note that the conductor length including the wiring pattern 18 connected to the lower end of the second stub via 17 may be a quarter of the wavelength at the use frequency of the monolithic microwave integrated circuit 3.

第１のスタブビア１６、はんだバンプ１０及び第２のスタブビア１７で４分の１波長スタブを形成することにより、実施の形態１と比較して、第１の積層基板１を更に小型化することが可能となる。実施の形態２に係る高周波パッケージ３０は、モノリシックマイクロ波集積回路３の使用周波数が低く４分の１波長の寸法が長くなる場合に有効である。   By forming a quarter-wave stub with the first stub via 16, the solder bump 10, and the second stub via 17, the first multilayer substrate 1 can be further downsized as compared with the first embodiment. It becomes possible. The high frequency package 30 according to the second embodiment is effective when the use frequency of the monolithic microwave integrated circuit 3 is low and the size of the quarter wavelength is long.

以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。   The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

１ 第１の積層基板、１Ｒ 裏面、２ 第２の積層基板、３ モノリシックマイクロ波集積回路、４ リッド、５ ワイヤ、６，１１ 信号用ビア、７，１２ シールド用ビア、８，１３ 信号用パターン、９，１４ シールド用パターン、１０ はんだバンプ、１５ スタブビア、１６ 第１のスタブビア、１７ 第２のスタブビア、１８ 配線パターン、１９ 裏面パターン、２０，３０ 高周波パッケージ、２１ 表面パターン。   DESCRIPTION OF SYMBOLS 1 1st laminated substrate, 1R back surface, 2nd laminated substrate, 3 monolithic microwave integrated circuit, 4 lid, 5 wires, 6,11 Signal via, 7,12 Shield via, 8,13 Signal pattern 9, 14 Shield pattern, 10 Solder bump, 15 Stub via, 16 First stub via, 17 Second stub via, 18 Wiring pattern, 19 Back pattern, 20, 30 High frequency package, 21 Surface pattern.

Claims (4)

積層基板に実装されたモノリシックマイクロ波集積回路を有する高周波パッケージであって、
前記モノリシックマイクロ波集積回路を動作させるバイアス信号を伝える信号用パターンから分岐するスタブビアを有し、
前記スタブビアの長さは、前記モノリシックマイクロ波集積回路の使用周波数の波長の４分の１であることを特徴とする高周波パッケージ。 A high frequency package having a monolithic microwave integrated circuit mounted on a multilayer substrate,
A stub via branched from a signal pattern for transmitting a bias signal for operating the monolithic microwave integrated circuit;
The high-frequency package according to claim 1, wherein a length of the stub via is a quarter of a wavelength of a use frequency of the monolithic microwave integrated circuit. 前記スタブビアが前記積層基板の複数の層に跨がって設けられていることを特徴とする請求項１に記載の高周波パッケージ。   The high-frequency package according to claim 1, wherein the stub via is provided across a plurality of layers of the multilayer substrate. モノリシックマイクロ波集積回路が実装された第１の積層基板と、
はんだバンプを介して前記第１の積層基板が重ねられた第２の積層基板とを有し、
前記第１の積層基板は、前記モノリシックマイクロ波集積回路に信号を伝える信号用パターンから分岐する第１のスタブビアを備え、
前記第２の積層基板は、前記はんだバンプを介して前記第１のスタブビアと導通した第２のスタブビアを備え、
前記第１のスタブビア及び前記第２のスタブビアの長さの合計は、前記モノリシックマイクロ波集積回路の使用周波数の波長の４分の１であることを特徴とする高周波パッケージ。 A first laminated substrate on which a monolithic microwave integrated circuit is mounted;
A second laminated substrate on which the first laminated substrate is stacked via solder bumps;
The first laminated substrate includes a first stub via that branches from a signal pattern for transmitting a signal to the monolithic microwave integrated circuit,
The second multilayer substrate includes a second stub via that is electrically connected to the first stub via via the solder bump,
The total length of the first stub via and the second stub via is a quarter of the wavelength of the operating frequency of the monolithic microwave integrated circuit. 前記第１のスタブビアは、前記第１の積層基板の複数の層に跨がって設けられていることを特徴とする請求項３に記載の高周波パッケージ。   The high-frequency package according to claim 3, wherein the first stub via is provided across a plurality of layers of the first laminated substrate.
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JP5407389B2 (en) * 2009-02-09 2014-02-05 富士通株式会社 Printed wiring board
JP2010199109A (en) * 2009-02-23 2010-09-09 Nec Corp Module substrate
JP5334686B2 (en) * 2009-05-27 2013-11-06 三菱電機株式会社 Multi-layer high frequency package substrate
JP2011009505A (en) * 2009-06-26 2011-01-13 Sony Corp Three-dimensional mounting board, and method of manufacturing the same
JP5444915B2 (en) * 2009-07-27 2014-03-19 日本電気株式会社 High frequency module and method for manufacturing high frequency module
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