JP6390369B2 - Semiconductor mounting equipment - Google Patents

Semiconductor mounting equipment Download PDF

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JP6390369B2
JP6390369B2 JP2014231289A JP2014231289A JP6390369B2 JP 6390369 B2 JP6390369 B2 JP 6390369B2 JP 2014231289 A JP2014231289 A JP 2014231289A JP 2014231289 A JP2014231289 A JP 2014231289A JP 6390369 B2 JP6390369 B2 JP 6390369B2
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substrate
wiring board
power supply
wiring
semiconductor
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JP2016096236A (en
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秀明 長岡
秀明 長岡
赤星 知幸
知幸 赤星
水谷 大輔
大輔 水谷
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Fujitsu Ltd
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本発明は、半導体実装装置に関し、例えば、半導体パッケージ基板を実装基板上に実装した半導体実装装置に関する。   The present invention relates to a semiconductor mounting apparatus, for example, a semiconductor mounting apparatus in which a semiconductor package substrate is mounted on a mounting substrate.

近年、半導体パッケージの小型化、大電流化、低抵抗化に対する要請が高まっている。この要請に応えるため、半導体パッケージ基板の周囲から電源供給を行うため配線に対して太線化や複数本化が検討されている。   In recent years, there is an increasing demand for miniaturization, large current, and low resistance of semiconductor packages. In order to meet this demand, a thicker wiring or a plurality of wirings are being studied in order to supply power from the periphery of the semiconductor package substrate.

図6は、従来の半導体装置の実装構造の説明図である。電源供給配線72を設けた配線基板71に電源供給する貫通電源線73を複数本設け、この配線基板71上に半導体ベアチップ62を搭載したパッケージ基板61をBGA(Ball Grid Array)バンプ63を介して接続している。なお、半導体ベアチップ62は、実際にはパッケージ基板61との間にはアンダーフィル樹脂が充填され、また、表面側はモールド樹脂でモールドされている。   FIG. 6 is an explanatory diagram of a conventional semiconductor device mounting structure. A plurality of through power supply lines 73 for supplying power to the wiring substrate 71 provided with the power supply wiring 72 are provided, and the package substrate 61 on which the semiconductor bare chip 62 is mounted on the wiring substrate 71 via BGA (Ball Grid Array) bumps 63. Connected. The semiconductor bare chip 62 is actually filled with an underfill resin between the package substrate 61 and the surface side is molded with a mold resin.

ところが、一般にこのような貫通電源線73は、パッケージ基板のサイズによって許容されるスペースに限界があるため、太線化や複数本化によって大電流化や低抵抗化を実現しようとした場合、半導体パッケージの小型化との両立が困難となる。   However, in general, such a through power supply line 73 has a limited space that is allowed depending on the size of the package substrate. Therefore, when an attempt is made to realize a large current or a low resistance by increasing the number of wires or increasing the number of wires, the semiconductor package It becomes difficult to achieve a balance with downsizing.

そこでこの問題に対処するため、半導体ベアチップの直下の領域にCu電極を形成し、半導体ベアチップの直下から直接電源供給を行う構造とすることが提案されている。図7は従来の半導体装置の改良型実装構造の説明図である。図に示すように、配線基板71の中央部に太いCu電源供給電極74を設け、半導体ベアチップ62の直下においてBGAバンプ63とこのCu電源供給電極74とを接続する。また、このCu電源供給電極74は実装基板81上に直流電源変圧器83を搭載した電源供給ユニット80に設けたBGAバンプ82と接続される。   In order to deal with this problem, it has been proposed to form a Cu electrode in a region directly under the semiconductor bare chip and to supply power directly from directly under the semiconductor bare chip. FIG. 7 is an explanatory view of an improved mounting structure of a conventional semiconductor device. As shown in the figure, a thick Cu power supply electrode 74 is provided at the center of the wiring board 71, and the BGA bump 63 and this Cu power supply electrode 74 are connected directly below the semiconductor bare chip 62. The Cu power supply electrode 74 is connected to a BGA bump 82 provided on a power supply unit 80 in which a DC power transformer 83 is mounted on a mounting substrate 81.

電流は、外部電源配線84及び直流電源変圧器83を介してCu電源供給電極74によって、半導体ベアチップ62の直下から直接電源供給を行う。したがって、電源供給電極の太線化および最短距離化による大電流化・低抵抗化と、半導体パッケージの小型化の両立を図ることができる。   The current is directly supplied from directly below the semiconductor bare chip 62 by the Cu power supply electrode 74 through the external power supply wiring 84 and the DC power supply transformer 83. Therefore, it is possible to achieve both a large current and low resistance by making the power supply electrode thicker and the shortest distance, and a reduction in the size of the semiconductor package.

特開2005−045013号公報JP 2005-045013 A 特開2009−170493号公報JP 2009-170493 A

しかし、図7の構造では、半導体パッケージの温度が変動すること半導体パッケージ基板に反りが発生した場合、半導体ベアチップ直下でCu電源供給電極と接続するBGAバンプに引っ張り応力が発生し、接触不良を引き起こすという問題がある。   However, in the structure of FIG. 7, when the temperature of the semiconductor package fluctuates and the warpage of the semiconductor package substrate occurs, a tensile stress is generated in the BGA bump connected to the Cu power supply electrode directly under the semiconductor bare chip, causing a contact failure. There is a problem.

図8は、従来の半導体装置の改良型実装構造の問題点の説明図である。温度が変動すると、パッケージ基板61に用いられる各材料における熱膨張係数の差異や、パッケージ基板61と配線基板71との間の熱膨張係数の差異等に起因して、パッケージ基板61に反りが発生する。反りが発生すると、図において破線の楕円で示すように、半導体ベアチップ62の直下でCu電源供給電極74と接続するBGAバンプ63に引っ張り応力が発生し、パッケージ基板61−Cu電源供給電極74間で接触不良が発生する。   FIG. 8 is an explanatory view of the problem of the improved mounting structure of the conventional semiconductor device. When the temperature fluctuates, the package substrate 61 warps due to a difference in thermal expansion coefficient between materials used for the package substrate 61, a difference in thermal expansion coefficient between the package substrate 61 and the wiring substrate 71, or the like. To do. When warping occurs, tensile stress is generated in the BGA bump 63 connected to the Cu power supply electrode 74 directly below the semiconductor bare chip 62 as shown by a dashed ellipse in the figure, and between the package substrate 61 and the Cu power supply electrode 74. Contact failure occurs.

また、図7の構造の場合には、Cu電源供給電極74は配線基板71の厚さと同程度の長さを有するため、このCu電源供給電極74の長さに相当する電源供給経路距離が依然として存在している。流れる電流量によっては、この長さのCu電源供給電極74の抵抗でさえも、電源供給を妨げる要因となり得る。   In the case of the structure of FIG. 7, since the Cu power supply electrode 74 has a length approximately the same as the thickness of the wiring board 71, the power supply path distance corresponding to the length of the Cu power supply electrode 74 is still present. Existing. Depending on the amount of current flowing, even this length of resistance of the Cu power supply electrode 74 can be a factor that hinders power supply.

したがって、半導体実装装置において、パッケージに反りが発生した場合にも電源供給電極との接続を良好に保つことを目的とする。   Therefore, an object of the semiconductor mounting apparatus is to maintain a good connection with the power supply electrode even when the package is warped.

開示する一観点からは、半導体チップを搭載したパッケージ基板と、前記パッケージ基板の外形よりも大きな貫通穴を有する第1の配線基板と、前記第1の配線基板より可撓性の高い第2の配線基板とを有し、前記第1の配線基板と前記第2の配線基板は接続電極により結合されるとともに、前記パッケージ基板は、前記第1の配線基板に設けた貫通穴に挿入して前記第2の配線基板上に実装されるとともに、前記第2の配線基板の前記第1の配線基板との結合面と反対側の面に前記パッケージ基板に電源を供給する電源供給ユニットが配置され、前記電源供給ユニットは、実装基板と前記実装基板に設けられた柱状電源電極とを有し、前記柱状電源電極は、前記第2の配線基板に設けられた貫通穴に挿入して前記パッケージ基板の中央部に設けられた接続導体と直接電気的に接続されていることを特徴とする半導体実装装置が提供される。 From one aspect to be disclosed, a package substrate on which a semiconductor chip is mounted, a first wiring substrate having a through hole larger than the outer shape of the package substrate, and a second that is more flexible than the first wiring substrate. A wiring board, wherein the first wiring board and the second wiring board are coupled by a connection electrode, and the package board is inserted into a through-hole provided in the first wiring board. Rutotomoni mounted on the second wiring board, the second power supply unit for supplying power to the package substrate on the surface opposite to the bonding surface of the first wiring substrate of the wiring substrate is disposed, The power supply unit includes a mounting substrate and a columnar power supply electrode provided on the mounting substrate, and the columnar power supply electrode is inserted into a through hole provided in the second wiring substrate and is mounted on the package substrate. In the center It has been kicked connection conductor and electrically connected directly semiconductor mounting device according to claim is provided.

開示の半導体実装装置によれば、パッケージに反りが発生した場合にも電源供給電極との接続を良好に保つことが可能になる。また、それとともに、大電流に耐え得る電源供給構造を実現することができる。   According to the disclosed semiconductor mounting apparatus, it is possible to maintain good connection with the power supply electrode even when the package is warped. In addition, a power supply structure that can withstand a large current can be realized.

本発明の実施の形態の半導体実装装置の概略的断面図である。It is a schematic sectional drawing of the semiconductor mounting apparatus of embodiment of this invention. 本発明の実施の形態の半導体実装装置の作用効果の説明図である。It is explanatory drawing of the effect of the semiconductor mounting apparatus of embodiment of this invention. 本発明の実施例1の半導体実装装置の概略的断面図である。It is a schematic sectional drawing of the semiconductor mounting apparatus of Example 1 of this invention. 本発明の実施例1の半導体実装装置の製造工程の途中までの説明図である。It is explanatory drawing to the middle of the manufacturing process of the semiconductor mounting apparatus of Example 1 of this invention. 本発明の実施例1の半導体実装装置の製造工程の図4以降の説明図である。It is explanatory drawing after FIG. 4 of the manufacturing process of the semiconductor mounting apparatus of Example 1 of this invention. 従来の半導体装置の実装構造の説明図である。It is explanatory drawing of the mounting structure of the conventional semiconductor device. 従来の半導体装置の改良型実装構造の説明図である。It is explanatory drawing of the improved mounting structure of the conventional semiconductor device. 従来の半導体装置の改良型実装構造の問題点の説明図である。It is explanatory drawing of the problem of the improved mounting structure of the conventional semiconductor device.

ここで、図1及び図2を参照して、本発明の実施の形態の半導体実装装置を説明する。図1は本発明の実施の形態の半導体実装装置の概略的断面図であり、半導体チップ7を搭載したパッケージ基板6と、パッケージ基板6の外形よりも大きな貫通穴2を有する第1の配線基板1と、第1の配線基板1より可撓性の高い第2の配線基板3とを備えている。第1の配線基板1は接続導体5により第2の配線基板3と結合している。また、パッケージ基板6は、第1の配線基板1に設けた貫通穴2を貫通して第2の配線基板3に実装されている。なお、第1の配線基板は、典型的にはFR−4を用いた多層プリント配線基板である。   Here, with reference to FIG.1 and FIG.2, the semiconductor mounting apparatus of embodiment of this invention is demonstrated. FIG. 1 is a schematic cross-sectional view of a semiconductor mounting apparatus according to an embodiment of the present invention, in which a package substrate 6 on which a semiconductor chip 7 is mounted and a first wiring substrate having a through hole 2 larger than the outer shape of the package substrate 6. 1 and a second wiring board 3 that is more flexible than the first wiring board 1. The first wiring board 1 is coupled to the second wiring board 3 by connection conductors 5. The package substrate 6 is mounted on the second wiring substrate 3 through the through hole 2 provided in the first wiring substrate 1. Note that the first wiring board is typically a multilayer printed wiring board using FR-4.

第2の配線基板3は、第1の配線基板1の厚さより薄い薄膜状基板、典型的には、フレキシブル基板であることが望ましい。この可撓性によりパッケージ基板6が温度変化により反った場合に、フレキシブル基板も変形して、接続導体8、典型的にはBGAバンプに加わる応力を大幅に低減することができる。   The second wiring substrate 3 is desirably a thin film substrate thinner than the thickness of the first wiring substrate 1, typically a flexible substrate. When the package substrate 6 is warped due to temperature changes due to this flexibility, the flexible substrate is also deformed, and the stress applied to the connection conductor 8, typically BGA bumps, can be greatly reduced.

このような第2の配線基板3に用いられる絶縁層としては、FR−4のような内部にガラスクロスを含んだ不均質構造ではなく、面方向で均一な誘電特性を有している絶縁層、例えば、ポリイミド樹脂或いは液晶ポリマー等が望ましい。このように、面方向で均一な誘電特性を有している絶縁層を用いることにより、第2の配線基板3上の配線パターンを伝送路とすることで、高速信号の品質を劣化させることなく、伝送することができる。   The insulating layer used for the second wiring board 3 is not an inhomogeneous structure including glass cloth inside such as FR-4, but an insulating layer having uniform dielectric characteristics in the plane direction. For example, polyimide resin or liquid crystal polymer is desirable. In this way, by using an insulating layer having a uniform dielectric property in the plane direction, the wiring pattern on the second wiring board 3 is used as a transmission line without deteriorating the quality of the high-speed signal. Can be transmitted.

また、大電流化・低抵抗化のためには、第2の配線基板3の第1の配線基板1との結合面と反対側の面にパッケージ基板6に電源を供給する電源供給ユニット10を配置することが望ましい。この電源供給ユニット10は、柱状電源電極13を設けた実装基板11を有し、第2の配線基板3に設けられた貫通穴4を貫通して柱状電源電極13とパッケージ基板6の中央部に設けられた接続導体8とを直接電気的に接合する。   Further, in order to increase the current and reduce the resistance, a power supply unit 10 that supplies power to the package substrate 6 is provided on the surface of the second wiring substrate 3 opposite to the coupling surface with the first wiring substrate 1. It is desirable to arrange. This power supply unit 10 has a mounting substrate 11 provided with columnar power supply electrodes 13, penetrates through holes 4 provided in the second wiring substrate 3, and is provided at the center of the columnar power supply electrodes 13 and the package substrate 6. The provided connection conductor 8 is directly electrically joined.

なお、柱状電源電極13は、実装基板11に設けられた貫通孔に嵌め込まれており、典型的には、Cu柱状電極或いはCuを主成分とするCu系柱状電極である。特に、柱状電源電極13の高さは、第1の配線基板1の厚さより小さくすることが望ましく、それにより、電源供給経路距離を従来に比べてより短縮することができる。また、実装基板11には、通常は直流電源変圧器12を搭載しておくことが望ましい。   The columnar power supply electrode 13 is fitted into a through-hole provided in the mounting substrate 11 and is typically a Cu columnar electrode or a Cu-based columnar electrode containing Cu as a main component. In particular, it is desirable that the height of the columnar power supply electrode 13 be smaller than the thickness of the first wiring board 1, and thereby the power supply path distance can be further shortened as compared with the conventional case. In addition, it is generally desirable to mount a DC power transformer 12 on the mounting substrate 11.

図2は本発明の実施の形態の半導体実装装置の作用効果の説明図である。本発明の実施の形態においては、パッケージ基板6をフレキシブルな第2の配線基板3に実装しているので、パッケージ基板6に反りが生じても、図において破線の楕円で囲って示したように第2の配線基板3がパッケージ3の反りに追随して変形する。したがって、パッケージ基板6と柱状電源電極13を接続する接続導体8(BGAバンプ)に掛かる応力を緩和することができる。   FIG. 2 is an explanatory diagram of the operational effects of the semiconductor mounting apparatus according to the embodiment of the present invention. In the embodiment of the present invention, since the package substrate 6 is mounted on the flexible second wiring substrate 3, even if the package substrate 6 is warped, as shown by being surrounded by a broken-line ellipse in the drawing. The second wiring board 3 is deformed following the warping of the package 3. Therefore, the stress applied to the connection conductor 8 (BGA bump) connecting the package substrate 6 and the columnar power supply electrode 13 can be relaxed.

また、第2の配線基板3の厚さを第1の配線基板1の厚さより薄くしているので、柱状電源電極13の高さを低くすることができ、パッケージ基板6と電源供給源との間の距離を短縮することができる。   Further, since the thickness of the second wiring board 3 is made thinner than the thickness of the first wiring board 1, the height of the columnar power supply electrode 13 can be reduced, and the package substrate 6 and the power supply source can be reduced. The distance between them can be shortened.

その結果、半導体チップ7を搭載したパッケージ基板6に反りが発生しても第2の配線基板3と接続導体6との接続を良好に保ち、かつ、大電流に耐え得る電源供給構造を実現することができる。   As a result, a power supply structure that can maintain a good connection between the second wiring substrate 3 and the connection conductor 6 and can withstand a large current even when the package substrate 6 on which the semiconductor chip 7 is mounted is warped is realized. be able to.

次に、図3乃至図5を参照して、本発明の実施例1の半導体実装装置を説明する。図3は、本発明の実施例1の半導体実装装置の概略的断面図である。半導体ベアチップ42を搭載したパッケージ基板41の外形よりも大きな貫通穴22を有する配線基板21と、配線基板21より可撓性が高く貫通穴32を設けたフレキシブル基板31をBGAバンプ33で接合する。なお、配線基板21は、FR−4を用いた多層プリント配線基板とする。   Next, with reference to FIGS. 3 to 5, a semiconductor mounting apparatus according to the first embodiment of the present invention will be described. FIG. 3 is a schematic cross-sectional view of the semiconductor mounting apparatus according to the first embodiment of the present invention. A wiring substrate 21 having a through hole 22 larger than the outer shape of the package substrate 41 on which the semiconductor bare chip 42 is mounted and a flexible substrate 31 having a higher flexibility than the wiring substrate 21 and provided with the through hole 32 are joined by a BGA bump 33. The wiring board 21 is a multilayer printed wiring board using FR-4.

半導体ベアチップ42を搭載したパッケージ基板41は貫通穴22内に挿入されて、BGAバンプ43を用いてフレキシブル基板31に接続されている。パッケージ基板41を実装したフレキシブル基板31は電源供給ユニット50に接続される。   The package substrate 41 on which the semiconductor bare chip 42 is mounted is inserted into the through hole 22 and connected to the flexible substrate 31 using BGA bumps 43. The flexible substrate 31 on which the package substrate 41 is mounted is connected to the power supply unit 50.

電源供給ユニット50は、太いCu柱状電極52を設けた実装基板51を有し、フレキシブル基板31に設けられた貫通穴32を貫通してCu柱状電極52とパッケージ基板41の中央部に設けられたBGAバンプ44とが直接電気的に接合されている。   The power supply unit 50 includes a mounting substrate 51 provided with a thick Cu columnar electrode 52, and is provided in the central portion of the Cu columnar electrode 52 and the package substrate 41 through a through hole 32 provided in the flexible substrate 31. The BGA bump 44 is directly electrically joined.

なお、Cu柱状電極52は、実装基板51に設けられ側壁にCuメッキ層が設けられた貫通孔に打ち込みにより嵌め込まれている。このCu柱状電極52の高さは、フレキシブル基板31の厚さを薄くすることにより、配線基板21の厚さより小さくしている。また、実装基板51の裏面には、直流電源変圧器54を搭載しておく。   The Cu columnar electrode 52 is fitted into a through hole provided on the mounting substrate 51 and provided with a Cu plating layer on the side wall. The height of the Cu columnar electrode 52 is made smaller than the thickness of the wiring substrate 21 by reducing the thickness of the flexible substrate 31. Further, a DC power transformer 54 is mounted on the back surface of the mounting substrate 51.

次に、図4及び図5を参照して、本発明の実施例1の半導体実装装置の製造工程を説明する。まず、図4(a)に示すように、厚さhが3mmのFR−4を絶縁材料とした配線基板21にドリル加工によって径wが60mm程度の貫通穴22を形成する。一方、図4(b)に示すように、厚さhが0.5mmのポリイミドを絶縁材料としたフレキシブル基板31にもドリル加工によって径wが30mmの貫通穴32を形成するとともに、基板の周辺部にBGAバンプ33を設ける。なお、ポリイミドを絶縁材料としたフレキシブル基板31は、FR−4のような内部にガラスクロスを含んだ不均質構造ではなく、面方向で均一な誘電特性を有している。また、BGAバンプ33の直径は0.6mmとする。 Next, with reference to FIG.4 and FIG.5, the manufacturing process of the semiconductor mounting apparatus of Example 1 of this invention is demonstrated. First, as shown in FIG. 4 (a), the thickness h 1 is the diameter w 1 by drilling the FR-4 of 3mm on the wiring board 21 in which the insulating material forms a through hole 22 of about 60 mm. On the other hand, as shown in FIG. 4 (b), with diameter w 2 by drilling in the flexible substrate 31 with a thickness h 2 is the 0.5mm of polyimide and the insulating material forms a through hole 32 of 30 mm, the substrate BGA bumps 33 are provided on the periphery of the substrate. The flexible substrate 31 made of polyimide as an insulating material does not have a heterogeneous structure including glass cloth inside like FR-4, but has a uniform dielectric property in the plane direction. The diameter of the BGA bump 33 is 0.6 mm.

次いで、図4(c)に示すように、BGAバンプ33によって、配線基板21とフレキシブル基板31とを、貫通穴22の中心と貫通穴32の中心が一致するように位置合わせして接続する。なお、配線基板21及びフレキシブル基板31には所定の配線パターンが形成されておりフレキシブル基板31は配線基板21の下面に設けた配線パターンの所定の領域でBGAバンプ33により接続される。   Next, as shown in FIG. 4C, the wiring board 21 and the flexible board 31 are aligned and connected by the BGA bump 33 so that the center of the through hole 22 and the center of the through hole 32 coincide. A predetermined wiring pattern is formed on the wiring substrate 21 and the flexible substrate 31, and the flexible substrate 31 is connected by a BGA bump 33 in a predetermined region of the wiring pattern provided on the lower surface of the wiring substrate 21.

次いで、図5(d)に示すように、半導体ベアチップ42を搭載したパッケージ基板41を貫通穴22に挿入して、パッケージ基板41に設けたBGAバンプ43を利用してフレキシブル基板31の上面に設けた配線パターンの所定の領域で接続される。なお、図示は省略しているが、半導体ベアチップ42とパッケージ基板41との間にはアンダーフィル樹脂が充填されており、また、半導体ベアチップ42はモールド樹脂でモールドされている。   Next, as shown in FIG. 5D, the package substrate 41 on which the semiconductor bare chip 42 is mounted is inserted into the through hole 22 and provided on the upper surface of the flexible substrate 31 using the BGA bumps 43 provided on the package substrate 41. Are connected in a predetermined region of the wiring pattern. Although not shown, an underfill resin is filled between the semiconductor bare chip 42 and the package substrate 41, and the semiconductor bare chip 42 is molded with a mold resin.

次いで、図5(e)に示すように、パッケージ基板41を実装したフレキシブル基板31を直径が5mmのCu柱状電極52を設けた電源供給ユニット50に接続する。この電源供給ユニット50は、Cu柱状電極52を設けた厚さが2.5mmの実装基板51を有し、実装基板51は周辺部にBGAバンプ53を有するとともに、裏面に直流電源変圧器54を搭載している。この直流電源電圧54は外部電源配線55を介して外部電源に接続される。   Next, as shown in FIG. 5E, the flexible substrate 31 on which the package substrate 41 is mounted is connected to a power supply unit 50 provided with a Cu columnar electrode 52 having a diameter of 5 mm. This power supply unit 50 has a mounting board 51 with a thickness of 2.5 mm provided with Cu columnar electrodes 52. The mounting board 51 has BGA bumps 53 in the periphery and a DC power transformer 54 on the back surface. It is installed. This DC power supply voltage 54 is connected to an external power supply via an external power supply wiring 55.

パッケージ基板41は半導体ベアチップ42が搭載されている中央部の直下においてパッケージ基板41に設けたBGAバンプ44によりCu柱状電極52と接続される。また、フレキシブル基板31とは、実装基板51の周辺部においてBGAバンプ53によりフレキシブル基板31の下面に設けた配線パターンの所定領域と接続される。外部電源からの電流は、直流電源変圧器54を通してCu柱状電極52に至り、このCu柱状電極52からパッケージ基板41へと送られる。   The package substrate 41 is connected to the Cu columnar electrode 52 by BGA bumps 44 provided on the package substrate 41 immediately below the central portion where the semiconductor bare chip 42 is mounted. Further, the flexible substrate 31 is connected to a predetermined region of the wiring pattern provided on the lower surface of the flexible substrate 31 by a BGA bump 53 in the peripheral portion of the mounting substrate 51. The current from the external power source reaches the Cu columnar electrode 52 through the DC power source transformer 54 and is sent from the Cu columnar electrode 52 to the package substrate 41.

本発明の実施例1に記載された発明においては、パッケージ基板41と接続しているフレキシブル基板31が十分な可撓性を有している。したがって、温度が変動してパッケージ基板41に反りが発生した場合でも、図2に示したように、フレキシブル基板31が中央部が固定された状態のパッケージ基板41の反りに追随して変形するため、BGAバンプ43に掛かる応力を緩和することができる。   In the invention described in the first embodiment of the present invention, the flexible substrate 31 connected to the package substrate 41 has sufficient flexibility. Therefore, even when the temperature fluctuates and the package substrate 41 is warped, as shown in FIG. 2, the flexible substrate 31 is deformed following the warp of the package substrate 41 with the central portion fixed. The stress applied to the BGA bump 43 can be relaxed.

また、フレキシブル基板31の絶縁材料として面方向で均一な誘電特性を有しているポリイミドを用いているので、パッケージ基板41からの高速信号の伝送路をフレキシブル基板31に設けることで、高品質に保ったまま信号を伝送することが可能になる。なお、従来のように、FR−4を絶縁材料として用いた配線基板21は、内部にガラスクロスを含んだ不均質構造を有していることで、基板内部の誘電率分布が不均一となり、伝送信号の品質劣化の原因となる。   In addition, since polyimide having a uniform dielectric property in the plane direction is used as the insulating material of the flexible substrate 31, a high-speed signal transmission path from the package substrate 41 is provided in the flexible substrate 31, so that high quality is achieved. It becomes possible to transmit a signal while keeping it. In addition, the wiring board 21 using FR-4 as an insulating material as in the past has a heterogeneous structure including a glass cloth inside, so that the dielectric constant distribution inside the board becomes non-uniform, It causes the quality deterioration of the transmission signal.

また、電源を直接供給するCu柱状電極52の実装基板51の表面からの高さ(0.6mm+0.5mm)を配線基板21の厚さ(3mm)より小さくしているので、図7に示したように配線基板にCu電源供給電極を設けた場合に比べて、電流供給経路を短くすることができる。   Further, since the height (0.6 mm + 0.5 mm) from the surface of the mounting substrate 51 of the Cu columnar electrode 52 that directly supplies power is made smaller than the thickness (3 mm) of the wiring substrate 21, it is shown in FIG. Thus, the current supply path can be shortened as compared with the case where the Cu power supply electrode is provided on the wiring board.

ここで、実施例1を含む本発明の実施の形態に関して、以下の付記を付す。
(付記1)半導体チップを搭載したパッケージ基板と、前記パッケージ基板の外形よりも大きな貫通穴を有する第1の配線基板と、前記第1の配線基板より可撓性の高い第2の配線基板とを有し、前記第1の配線基板と前記第2の配線基板は接続導体により結合されるとともに、前記パッケージ基板は、前記第1の配線基板に設けた貫通穴に挿入して前記第2の配線基板上に実装されるとともに、前記第2の配線基板の前記第1の配線基板との結合面と反対側の面に前記パッケージ基板に電源を供給する電源供給ユニットが配置され、前記電源供給ユニットは、実装基板と前記実装基板に設けられた柱状電源電極とを有し、前記柱状電源電極は、前記第2の配線基板に設けられた貫通穴に挿入して前記パッケージ基板の中央部に設けられた接続導体と直接電気的に接続されていることを特徴とする半導体実装装置。
(付記2)前記第2の配線基板が、前記第1の配線基板の厚さより薄い薄膜状基板であることを特徴とする付記1に記載の半導体実装装置。
(付記3)前記第2の配線基板の絶縁層が、面方向で均一な誘電特性を有していることを特徴とする付記1または付記2に記載の半導体実装装置。
(付記4)前記絶縁層がポリイミド樹脂或いは液晶ポリマーのいずれかであることを特徴とする付記3に記載の半導体実装装置。
(付記)前記柱状電源電極の高さが、前記第1の配線基板の厚さより小さいことを特徴とする付記1乃至付記4のいずれか1に記載の半導体実装装置。
(付記)前記柱状電源電極は、前記実装基板に設けられた貫通孔に嵌め込まれていることを特徴とする付記に記載の半導体実装装置。
(付記)前記柱状電源電極がCu柱状電極或いはCuを主成分とするCu系柱状電極であることを特徴とする付記または付記に記載の半導体実装装置。
(付記)前記実装基板に、直流電源変圧器が搭載されていることを特徴とする付記乃至付記のいずれか1に記載の半導体実装装置。
Here, the following supplementary notes are attached to the embodiment of the present invention including the first embodiment.
(Appendix 1) A package substrate on which a semiconductor chip is mounted, a first wiring substrate having a through hole larger than the outer shape of the package substrate, and a second wiring substrate having higher flexibility than the first wiring substrate, The first wiring board and the second wiring board are coupled by a connection conductor, and the package board is inserted into a through hole provided in the first wiring board, and the second wiring board is inserted into the second wiring board. Rutotomoni mounted on the wiring board, the second power supply unit for supplying power to the package substrate on the surface opposite to the bonding surface of the first wiring substrate of the wiring substrate is disposed, the power supply The unit has a mounting substrate and a columnar power supply electrode provided on the mounting substrate, and the columnar power supply electrode is inserted into a through hole provided in the second wiring substrate and is provided at a central portion of the package substrate. Established contact Semiconductor mounting apparatus characterized by being directly electrically connected to the conductor.
(Additional remark 2) The said 2nd wiring board is a thin film-like board | substrate thinner than the thickness of the said 1st wiring board, The semiconductor mounting apparatus of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The semiconductor mounting apparatus of Additional remark 1 or Additional remark 2 characterized by the insulating layer of a said 2nd wiring board having a uniform dielectric characteristic in a surface direction.
(Additional remark 4) The said mounting layer is either a polyimide resin or a liquid crystal polymer, The semiconductor mounting apparatus of Additional remark 3 characterized by the above-mentioned.
(Supplementary note 5 ) The semiconductor mounting device according to any one of supplementary notes 1 to 4 , wherein a height of the columnar power supply electrode is smaller than a thickness of the first wiring board.
(Supplementary note 6 ) The semiconductor mounting device according to supplementary note 5 , wherein the columnar power supply electrode is fitted in a through hole provided in the mounting substrate.
(Supplementary note 7 ) The semiconductor mounting device according to Supplementary note 5 or 6 , wherein the columnar power supply electrode is a Cu columnar electrode or a Cu-based columnar electrode containing Cu as a main component.
(Supplementary note 8 ) The semiconductor mounting device according to any one of supplementary notes 1 to 7 , wherein a DC power transformer is mounted on the mounting substrate.

1 第1の配線基板
2 貫通穴
3 第2の配線基板
4 貫通穴
5 接続導体
6 パッケージ基板
7 半導体チップ
8 接続導体
10 電源供給ユニット
11 実装基板
12 直流電源変圧器
13 柱状電源電極
14 接続導体
15 外部電源配線
21 配線基板
22 貫通穴
31 フレキシブル基板
32 貫通穴
33 BGAバンプ
41,61 パッケージ基板
42,62 半導体ベアチップ
43,44,63 BGAバンプ
50 電源供給ユニット
51,81 実装基板
52 Cu柱状電極
53,82 BGAバンプ
54,83 直流電源変圧器
55,84 外部電源線
71 配線基板
72 電源供給配線
73 貫通電源線
74 Cu電源供給電極
DESCRIPTION OF SYMBOLS 1 1st wiring board 2 Through-hole 3 2nd wiring board 4 Through-hole 5 Connection conductor 6 Package board 7 Semiconductor chip 8 Connection conductor 10 Power supply unit 11 Mounting board 12 DC power transformer 13 Column-shaped power electrode 14 Connection conductor 15 External power supply wiring 21 Wiring substrate 22 Through hole 31 Flexible substrate 32 Through hole 33 BGA bump 41, 61 Package substrate 42, 62 Semiconductor bare chip 43, 44, 63 BGA bump 50 Power supply unit 51, 81 Mounting substrate 52 Cu columnar electrode 53, 82 BGA bumps 54 and 83 DC power transformers 55 and 84 External power supply line 71 Wiring board 72 Power supply wiring 73 Through power supply line 74 Cu power supply electrode

Claims (3)

半導体チップを搭載したパッケージ基板と、
前記パッケージ基板の外形よりも大きな貫通穴を有する第1の配線基板と、
前記第1の配線基板より可撓性の高い第2の配線基板と
を有し、
前記第1の配線基板と前記第2の配線基板は接続導体により結合されるとともに、
前記パッケージ基板は、前記第1の配線基板に設けた貫通穴に挿入して前記第2の配線基板上に実装されるとともに、前記第2の配線基板の前記第1の配線基板との結合面と反対側の面に前記パッケージ基板に電源を供給する電源供給ユニットが配置され、
前記電源供給ユニットは、
実装基板と
前記実装基板に設けられた柱状電源電極とを有し、
前記柱状電源電極は、前記第2の配線基板に設けられた貫通穴に挿入して前記パッケージ基板の中央部に設けられた接続導体と直接電気的に接続されていることを特徴とする半導体実装装置。
A package substrate having a semiconductor chip mounted thereon;
A first wiring board having a through hole larger than the outer shape of the package board;
A second wiring board having higher flexibility than the first wiring board;
The first wiring board and the second wiring board are coupled by a connection conductor,
The package substrate, the binding surface between the first inserted and then mounted on the second wiring board in a through hole provided in the wiring board Rutotomoni, the first wiring board of the second wiring board A power supply unit for supplying power to the package substrate is disposed on the opposite side of the surface,
The power supply unit is
Mounting board and
A columnar power supply electrode provided on the mounting substrate;
The columnar power supply electrode is inserted into a through hole provided in the second wiring substrate and is directly electrically connected to a connection conductor provided in a central portion of the package substrate. apparatus.
前記第2の配線基板の絶縁層が、面方向で均一な誘電特性を有していることを特徴とする請求項1に記載の半導体実装装置。   The semiconductor mounting apparatus according to claim 1, wherein the insulating layer of the second wiring board has a uniform dielectric characteristic in a surface direction. 前記柱状電源電極の高さが、前記第1の配線基板の厚さより小さいことを特徴とする請求項1または請求項2に記載の半導体実装装置。 The height of the columnar power electrode, a semiconductor mounting device according to claim 1 or claim 2, wherein the smaller than the thickness of the first wiring board.
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