JP6385817B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a through electrode formed by stacking a plurality of semiconductor chips and capable of relieving when a poor contact occurs in the stacked through electrode.

  FIG. 1 shows a semiconductor device having a configuration in which a plurality (three in this case) of semiconductor chips 101 to 103 are stacked. The semiconductor chips 101 to 103 are provided with circuit blocks 111 to 113. Wirings 121 to 123 and wirings 131 to 133 are connected to the circuit blocks 111 to 113.

  Reference numerals 141 to 143 denote through electrodes connected to the wirings 121 to 123. In the drawing, the semiconductor chips 101 to 103 are drawn apart from each other, and thus separated from the semiconductor chips 101 to 103. It is joined to the book. Such a drawing method is similarly used in all the drawings attached to this specification. The through electrode 141 is a through electrode connected to the wirings 121 to 123, and the through electrode 142 is a through electrode connected to the wirings 131 to 133.

  Further, the through electrode 143 is a redundant through electrode that is not connected anywhere at first. A wiring layer such as a lead frame or a base substrate can be provided on one end side (the lower side in the figure) of the through electrodes 141 to 143. In addition, a wiring layer such as an interface chip with wiring can be provided on the other end side (upper side in the drawing) of the through electrodes 141 to 143.

  In the semiconductor device configured as described above, it is assumed that, for example, as illustrated in FIG. 2, a bonding failure occurs in the through electrode 142 between the semiconductor chip 102 and the semiconductor chip 103. In this case, signals cannot be obtained from the circuit blocks 111 and 112 of the semiconductor chips 101 and 102 above the bonding failure portion D1, resulting in a product failure. On the other hand, the penetration electrode 143 which is a redundant penetration electrode can be used as follows.

  In the semiconductor device as described above, in order to remedy when a poor bonding occurs in the stacked through electrodes, the through electrodes are doubled and used by taking advantage of both, and when one is defective, the other is replaced with the other. Things are known. In addition, a semiconductor device is known in which a through-electrode is doubled and a switch for switching to which of the doubled through-electrodes is provided to switch from a poorly bonded through-electrode to the other through-electrode ( Patent Document 1).

  In addition, in a semiconductor device in which n driver circuits and n receiver circuits are connected by a through electrode, n + 1 through electrodes are provided, and the first driver circuit and the first receiver circuit are the first and first receiver circuits, respectively. The first switch is provided so that the two through electrodes can be selectively connected, and the second driver circuit and the second receiver circuit are configured so that the second and third through electrodes can be selectively connected, respectively. A first switch is provided so that the third driver circuit and the third receiver circuit can selectively connect the third and fourth through electrodes, respectively, and the nth driver circuit. And the nth receiver circuit are provided with an nth switch so that the nth and n + 1th through electrodes can be selectively connected, respectively, and if any one of the through electrodes has a junction failure, Switching A semiconductor device is known in which n driver electrodes and n receiver circuits are communicated with each other by n through electrodes excluding the poorly bonded through electrode (Patent Document 2). reference).

JP 2007-158237 A JP 2011-81887 A

  However, according to the semiconductor device described in Patent Document 1, a double through electrode is required to double the through electrode, which may increase the complexity and size of the configuration and increase the cost. is there.

  In addition, according to the semiconductor device described in Patent Document 2, one through-hole electrode for recovery is provided, and there is a problem that it cannot be dealt with when bonding failure occurs in two or more through-hole electrodes.

  The present invention has been made in view of the current state of such a semiconductor device. When a poor contact occurs in the through electrode, there is no need to double the through electrode, the configuration becomes complicated, the size is increased, and the cost is increased. Therefore, it is an object of the present invention to provide a semiconductor device that can cope with a bonding failure. It is another object of the present invention to provide a semiconductor device that can cope with bonding failure even when bonding failure occurs in two or more through electrodes.

A semiconductor device according to the present invention includes a semiconductor device including a plurality of semiconductor chips each having a circuit block, connected to the circuit block of each semiconductor chip, and provided with a through electrode provided between the semiconductor chips. In the apparatus, a redundant through electrode provided in reserve through each of the semiconductor chips and a spare wiring layer that is stacked separately from the semiconductor chip and does not include a circuit block, wherein the through electrode has poor bonding. And a spare wiring layer having a spare wiring connecting the through electrode and the redundant through electrode in the spare wiring layer when generated, and the semiconductor chip includes the through electrode and the redundant penetration It is characterized in that no spare wiring for connecting between the electrodes is provided .

  The semiconductor device according to the present invention is characterized in that spare wiring layers are provided in the uppermost layer and the lowermost layer of the stack.

  The semiconductor device according to the present invention is characterized in that at least one spare wiring layer is provided in addition to the uppermost layer and the lowermost layer of the stack.

  In the semiconductor device according to the present invention, a spare wiring is provided in a wiring layer for wiring of the semiconductor device provided in the uppermost layer and the lowermost layer of the stack in the semiconductor device, and is used as a spare wiring layer. It is characterized by that.

  In the semiconductor device according to the present invention, the preliminary wiring is performed in a programmable manner by a programmable logic device technique or FPDA (Field Programmable Gate Array).

In the semiconductor device according to the present invention, the spare wiring layer is a semiconductor chip having a spare wiring in which predetermined wiring is made in advance, and is provided in the stack after circuit inspection.

  According to the semiconductor device of the present invention, when a poorly bonded through electrode is generated, the poorly bonded portion is stacked on the stack using the spare wiring that connects between the poorly bonded through electrode and the redundant through electrode. By forming a path toward the direction and a path toward the bottom of the stack, it is possible to relieve the occurrence of defective bonding. For this reason, it is not necessary to provide double penetration electrodes, and it can be avoided that the configuration becomes complicated, large and expensive. Further, since it is only necessary to form a path from the poorly bonded portion toward the upper side of the stack and a path toward the lower side of the stack, it is only necessary to provide a spare wiring layer above and below the poorly bonded portion. It is also possible to cope with a case where bonding failure occurs in the above through electrode.

FIG. 3 is an example of a semiconductor device according to an embodiment of the present invention, and is an assembly perspective view when no poor bonding occurs in the through electrode. FIG. 3 is an example of a semiconductor device according to an embodiment of the present invention, and is an assembly perspective view when a poor bonding occurs in a through electrode. FIG. 4 is an example of a semiconductor device according to the first embodiment of the present invention, and is an assembly perspective view when a bonding failure occurs in a through electrode. FIG. 2 is an assembly perspective view showing an example of the semiconductor device according to the first embodiment of the present invention, and showing a state in which a connection failure is dealt with by a spare wiring in a spare wiring layer after a bonding failure occurs in the through electrode . FIG. 10 is an example of a semiconductor device according to a second embodiment of the present invention, and is an assembly perspective view when a bonding failure occurs in a through electrode. FIG. 10 is a diagram illustrating an example of a semiconductor device according to a second embodiment of the present invention, and is an assembly perspective view showing a state in which a defective bonding is dealt with by a spare wiring in a spare wiring layer after a bonding failure occurs in a through electrode Figure.

  Embodiments of a semiconductor device of the present invention will be described below with reference to the accompanying drawings. In each figure, the same components are denoted by the same reference numerals, and redundant description is omitted. As shown in FIG. 3, the semiconductor device has a configuration in which a plurality of (here, three) semiconductor chips 11 to 13 are stacked. Circuit blocks 21 to 23 are provided on the semiconductor chips 11 to 13. Wires 41 to 43 and wires 51 to 53 are connected to the circuit blocks 21 to 23.

  A spare wiring layer 60 is stacked on top of the stacked semiconductor chips 11 to 13. A spare wiring layer 70 is stacked below the stacked semiconductor chips 11 to 13. The spare wiring layers 60 and 70 can be constituted by a semiconductor chip. Reference numerals 81 to 83 denote through electrodes. Wirings 41 to 43 are connected to the through electrode 81, and wirings 51 to 53 are connected to the through electrode 82. The through electrode 83 is a redundant through electrode.

  A wiring layer such as a lead frame or a base substrate can be provided on one end side (the lower side in the figure) of the through electrodes 81 to 83. In addition, a wiring layer such as an interface chip with wiring can be provided on the other end side (upper side in the drawing) of the through electrodes 81 to 83.

  The spare wiring layers 60 and 70 are provided with a spare wiring (not shown) for connecting between the poorly bonded through electrode and the redundant through electrode 83 when a poorly bonded through electrode is generated. . The spare wiring can adopt a configuration in which programmable wiring is performed by programmable logic device technology or FPDA (Field Programmable Gate Array). The spare wiring is not connected between the redundant through electrode 83 and another through electrode before the relief wiring is repaired in the event of a bonding failure.

  In the semiconductor device according to the first embodiment configured as described above, it is assumed that, for example, as shown in FIGS. 3 and 4, a bonding defect D1 occurs in the through electrode 82 between the semiconductor chip 12 and the semiconductor chip 13. . At this time, the spare wiring 91 for connecting the poorly bonded through electrode 82 and the redundant through electrode 83 is formed in the spare wiring layer 60 and the spare wiring 92 is used as a spare by the configuration in which the programmable wiring described above is performed. The wiring layer 70 is formed (FIG. 4).

  The preliminary wiring 91 connects the through electrode 82 and the redundant through electrode 83, and signals of the wiring 51 and 52 of the circuit blocks 21 and 22 are transmitted by the line L 1 through the through electrode 82, the preliminary wiring 91 and the redundant through electrode 83. It can flow. Further, the through electrode 82 and the redundant through electrode 83 are connected by the spare wiring 92, and the signal of the wiring 43 of the circuit block 23 is caused to flow through the line L2 through the through electrode 82, the spare wiring 92 and the redundant through electrode 83. Can do.

  As described above, according to the semiconductor device according to the first embodiment, when a bonding failure occurs in the through electrodes 81 and 82 between the circuit blocks 21 to 23, the occurrence of the bonding failure can be remedied. Can do.

  In the above description, the spare wiring is formed by a configuration in which programmable wiring is performed, but the invention is not limited to this. The spare wiring layer may be configured as a semiconductor chip having a spare wiring in which predetermined wiring is made in advance, and a semiconductor chip at a poorly bonded portion may be sandwiched from above and below after the circuit inspection. In this case, the spare wiring is provided with a grid-like wiring so as to connect all through electrodes including the redundant through electrode, and the through electrode in which the bonding failure has occurred is connected to the through electrode in which the bonding failure has occurred. It is possible to adopt a configuration in which wiring other than connecting the redundant through electrode is cut by a laser or by an overcurrent.

  In addition, although the spare wiring layer is provided in the semiconductor chip, the spare wiring is provided in the wiring layer for wiring of the semiconductor device provided in the uppermost layer and the lowermost layer of the stack in the semiconductor device as a spare wiring layer. It may be used. That is, in the uppermost layer and the lowermost layer of the stack, a chip or board having wiring for wiring such as lead frame connection is usually arranged. Therefore, spare wiring may be provided in an empty area of the chip or board. By adopting such a configuration, it is not necessary to separately provide a spare wiring layer for the spare wiring, and the thickness of the stack does not increase. Further, since the wiring other than the spare wiring is the wiring of the conventional circuit and has been verified, there is an advantage that it is not necessary to perform new verification.

  Next, a semiconductor device according to a second embodiment will be described. FIG. 5 shows a semiconductor device according to the second embodiment. This semiconductor device has a configuration in which a plurality of (here, six) semiconductor chips 1-1 to 1-6 are stacked. The semiconductor chips 1-1 to 1-6 are provided with circuit blocks and wirings, but are omitted.

  The spare wiring layer 2-1 is laminated on the upper part of the laminated semiconductor chips 1-1 to 1-6, and the spare wiring layer 2-3 is placed on the lower part of the laminated semiconductor chips 1-1 to 1-6. Are stacked. Further, a spare wiring layer 2-2 is inserted between the semiconductor chip 1-3 and the semiconductor chip 1-4.

  The spare wiring layers 2-1 to 2-3 can be constituted by semiconductor chips. Reference numerals 3-1 and 3-2 denote through electrodes. A wiring extending to a circuit block (not shown) is connected to the through electrode 3-1, and the through electrode 3-2 is a redundant through electrode.

  A wiring layer such as a lead frame or a base substrate can be provided on the end side (the lower side in the figure) of the through electrodes 3-1 and 3-12. Further, a wiring layer such as an interface chip with wiring can be provided on the other end side (upper side in the drawing) of the through electrodes 3-1 and 3-2.

  In the spare wiring layers 2-1 to 2-3, when a poorly bonded through electrode is generated, a spare wire that connects the poorly bonded through electrode 3-1 and the redundant through electrode 3-2 ( (Not shown). The spare wiring can adopt a configuration in which programmable wiring is performed by programmable logic device technology or FPDA (Field Programmable Gate Array). The spare wiring is not connected between the redundant through-electrode 3-2 and the other through-electrode before it is remedied when a bonding failure occurs.

  In the semiconductor device according to the second embodiment configured as described above, for example, as illustrated in FIGS. 5 and 6, between the semiconductor chip 1-1 and the semiconductor chip 1-2 and between the semiconductor chip 1-4 and the semiconductor. It is assumed that bonding defects D2 and D3 occur in the through electrode 3-1 between the chips 1-4. That is, there are two joint failure locations.

  At this time, spare wirings 4-1, 4-2, and 4-3 for connecting the poorly bonded through electrodes 3-1 and the redundant through electrodes 3-2 with the above-described programmable wiring are configured as spare wirings. It forms in layer 2-1, 2-2, 2-3 (FIG. 6).

  The through electrode 82 and the redundant through electrode 83 are connected by the spare wiring 4-1, and the signal of the wiring of the semiconductor chip 1-1 is transmitted to the through electrode 3-1, the spare wiring 4-1, and the redundant through electrode 3-2. Via the line L11. Further, the through-electrode 3-1 and the redundant through-electrode 3-2 are connected by the spare wiring 4-2, and signals of the wirings of the semiconductor chips 1-2, 1-3, and 1-4 are transmitted to the through-electrode 3-1. It can be made to flow by the line L12 via the spare wiring 4-2 and the redundant through electrode 3-2. Furthermore, the through electrode 3-1 and the redundant through electrode 3-2 are connected by the spare wiring 4-3, and signals of the wirings of the semiconductor chips 1-5 and 1-6 are transmitted to the through electrode 3-1 and the spare wiring 4-. 3 and the redundant penetrating electrode 3-2.

  As described above, according to the semiconductor device according to the second embodiment, at two locations between the semiconductor chip 1-1 and the semiconductor chip 1-2 and between the semiconductor chip 1-4 and the semiconductor chip 1-4. When a bonding failure occurs in the through electrode 3-1, the occurrence of the bonding failure can be remedied.

  Also in the second embodiment, the spare wiring layer is configured by a semiconductor chip having a spare wiring in which predetermined wiring is made in advance, and the semiconductor chip at a poorly bonded portion is sandwiched from above and below after the circuit inspection. May be provided. In this case, the spare wiring is provided with a grid-like wiring so as to connect all through electrodes including the redundant through electrode, and the through electrode in which the bonding failure has occurred is connected to the through electrode in which the bonding failure has occurred. It is possible to adopt a configuration in which wiring other than connecting the redundant through electrode is cut by a laser or by an overcurrent.

  Further, a spare wiring may be provided in a wiring layer for wiring of the semiconductor device provided in the uppermost layer and the lowermost layer of the stack in the semiconductor device, and used as a spare wiring layer. That is, in the uppermost layer and the lowermost layer of the stack, a chip or board having wiring for wiring such as lead frame connection is usually arranged. Therefore, spare wiring may be provided in an empty area of the chip or board.

  In the second embodiment, three spare wiring layers are provided, but four or more spare wiring layers may be provided. In this way, by increasing the number of spare wiring layers, it is possible to cope with the occurrence of bonding failures at three or more locations in the same through electrode.

11-13, 1-1-1-6 Semiconductor chips 21-23 Circuit blocks 41-43, 51-53 Wiring 81-83, 3-1, 3-2 Penetration electrodes 60, 70 Spare wiring layers 83, 3- 2 Redundant penetration electrodes 91, 92, 4-1, 4-2 Reserve wiring

Claims (6)

In a semiconductor device comprising a plurality of semiconductor chips each having a circuit block, connected to the circuit block of each semiconductor chip and provided with a through electrode provided so as to penetrate between the semiconductor chips .
A redundant through electrode provided in reserve through each of the semiconductor chips ;
A spare wiring layer that is stacked separately from the semiconductor chip and does not include a circuit block, and when a poor connection occurs in the through electrode, a gap between the through electrode and the redundant through electrode is provided in the spare wiring layer. A spare wiring layer having a spare wiring to be connected, and
The semiconductor device, wherein the semiconductor chip is not provided with a spare wiring for connecting the through electrode and the redundant through electrode .   2. The semiconductor device according to claim 1, wherein spare wiring layers are provided in the uppermost layer and the lowermost layer of the stack.   3. The semiconductor device according to claim 2, wherein at least one spare wiring layer is provided in addition to the uppermost layer and the lowermost layer of the stack.   The spare wiring is provided in the wiring layer for wiring of the semiconductor device provided in the uppermost layer and the lowermost layer of the stack in the semiconductor device, and used as the spare wiring layer. 2. A semiconductor device according to item 1.   5. The semiconductor device according to claim 1, wherein the preliminary wiring is performed in a programmable manner by programmable logic device technology or FPDA (Field Programmable Gate Array). 4. The semiconductor according to claim 1, wherein the spare wiring layer is a semiconductor chip having a spare wiring in which predetermined wiring is made in advance, and is provided in the stack after circuit inspection. 5. apparatus.

Images