JP6378857B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to an oscillation circuit, and is particularly useful when applied to a case where an oscillator is driven by stepping down a voltage applied from an external power supply.

  FIG. 10 is a block diagram showing an oscillation circuit using a general crystal oscillator IC according to the prior art. As shown in the figure, the oscillation circuit 100 includes a regulator 2, an oscillator 3, a frequency divider 4, a level shifter 5, and an output circuit 6 integrated in an IC chip 1 (dotted line portion in the figure). The regulator 2 steps down the power supply voltage VDD of the power supply 7 to a predetermined internal constant voltage VREG. The oscillator 3 is driven by the internal constant voltage VREG, and sends an output signal having a predetermined frequency to the frequency divider circuit 4 by vibrating the external crystal resonator 8. The frequency divider 4 is driven by the internal constant voltage VREG, and appropriately divides the frequency of the output signal of the oscillator 3 and sends it to the level shifter 5. The level shifter 5 appropriately amplifies the voltage of the output signal of the oscillator 3 and outputs it. The output circuit 6 functions as a buffer circuit when the output signal of the level shifter 5 is sent to the output terminal 9. Here, the power supply voltage VDD is applied to the level shifter 5 and the output circuit 6.

  In such an IC chip 1, in order to stabilize the oscillation frequency and reduce the power consumption of the entire oscillation circuit 100, the IC chip 1 has a built-in regulator 2 and an internal constant voltage lower than the power supply voltage VDD supplied from the outside. VREG is generated, and this internal constant voltage VREG is used as a driving voltage for the oscillator 3 and the frequency dividing circuit 4.

  Conventionally, a linear regulator has been widely used as the regulator 2 built in the IC chip 1. FIG. 11 is a block diagram showing a configuration of a general linear regulator. As shown in the figure, the regulator 2 uses the operational amplifier 02 so that the internal constant voltage VREG, which is the output voltage, matches the reference voltage VREF, which is the output voltage of the reference voltage source 01, and the on-resistance of the MOS transistor TR is reduced. I have control. The reference voltage source 01 can be preferably configured using a bandgap reference in a CMOS circuit.

  The MOS transistor TR in the regulator 2 shown in FIG. 11 is equivalent to a variable resistance element, and power loss due to resistance always occurs. For example, if the current consumed by the oscillator 3 and the frequency divider 4 driven by the internal constant voltage VREG is I_op, the power loss consumed by the MOS transistor TR in FIG. 11 is P_loss = I_op × (VDD−VREG) I can express.

  A specific numerical value is applied to this and the power loss in the regulator 2 is considered. Here, if [I_op = 20 μA, VDD = 1.8 V, VREG = 0.8 V], P_loss = 20 μA × (1.8 V−0.8 V) = 20 μW. On the other hand, the original power consumption of the oscillator 3 and the frequency dividing circuit 4 is P_op = I_op × VREG = 20 μA × 0.8 V = 16 μW.

  In the low current consumption type oscillation circuit 100 as in this numerical example, in the region where the power supply voltage VDD is relatively higher than the internal constant voltage VREG, the power consumed by the regulator 2 is higher than the power P_op necessary for the original operation. P_loss is bigger.

  Patent Document 1 is known as a prior art that discloses an oscillation circuit (clock signal generation circuit) for the purpose of suppressing current consumption.

Japanese Patent Laying-Open No. 2015-104035

  An object of the present invention is to provide an oscillation circuit capable of reducing power consumption when a power supply voltage is stepped down to an internal constant voltage that is a driving voltage of an oscillator.

The first aspect of the present invention for achieving the above object is as follows:
An oscillation circuit for driving an oscillator by stepping down a power supply voltage applied from a power supply,
Switching type step-down means for stepping down the power supply voltage to a predetermined internal constant voltage by ON / OFF control of the switching element;
And having an oscillator driven by application of the internal constant voltage,
The switching type step-down means is configured to control on / off of the switching element with a clock signal of a predetermined frequency using the output signal of the oscillator,
The switching type step-down means includes a charge mode in which the capacitors are connected in series by a combination of a plurality of capacitors and a plurality of switch means on and off, and a discharge mode in which the capacitors are connected in parallel. In the charging mode, the power supply voltage is applied to both ends of the capacitors connected in series to charge the capacitor, and in the discharging mode, the capacitors are charged with the power supply disconnected. Charging voltage is output,
A capacitive voltage dividing step-down circuit configured to perform on / off control of the switch means by the clock signal;
Further, the switching type voltage step-down means has a first regulator that adjusts the output voltage of the capacity voltage division type step-down circuit together with the capacity voltage division type step-down circuit,
The first regulator includes a first transistor connected between an output side of the capacitive voltage dividing step-down circuit and an output terminal of the switching step-down means;
Based on the first reference voltage representing the predetermined internal constant voltage set to the first reference voltage source and the voltage of the output terminal, the voltage of the output terminal is set to the predetermined internal constant voltage. The oscillation circuit is configured to control one transistor .

The second aspect of the present invention is:
In the oscillation circuit described in the first aspect,
Having a frequency divider for dividing the output signal of the oscillator;
The switching type step-down means is an oscillation circuit configured to control on / off of the switching element by a clock signal of a predetermined frequency output from the frequency dividing circuit.

The third aspect of the present invention is:
In the oscillation circuit described in the first or second aspect,
The first regulator includes a second transistor connected in parallel to the first transistor and having a higher on-resistance than the first transistor between the power source and the output terminal. The second transistor is controlled together with the first transistor so that the voltage at the output terminal becomes the predetermined internal constant voltage based on the first reference voltage and the voltage at the output terminal. It is in the oscillation circuit.

The fourth aspect of the present invention is:
In the oscillation circuit described in the third aspect,
The switching step-down means has a second regulator for stepping down the power supply voltage to a predetermined set voltage and applying it to the capacitive voltage dividing step-down circuit,
The second regulator includes a third transistor connected between the power source and the input side of the capacitive voltage dividing step-down circuit,
Based on the predetermined set voltage set as the second reference voltage source and the input voltage to the capacitive voltage dividing step-down circuit, the third voltage is set so that the input voltage of the capacitive voltage dividing step-down circuit becomes the set voltage. The oscillation circuit is characterized in that the transistor is controlled.

According to a fifth aspect of the present invention,
In the oscillation circuit according to any one of the first to fourth aspects,
Having a duty modulator for controlling the output voltage of the switching step-down means by controlling the duty ratio of the switching element of the switching type step-down means in the on / off state;
The third reference voltage representing the predetermined internal constant voltage is compared with the voltage at the output terminal of the switching step-down means, and the duty ratio is set via the duty modulator so that the deviation between them is zero. The oscillation circuit is characterized by being controlled.

  According to the present invention, since the power source voltage is stepped down to the internal constant voltage that is the driving voltage of the oscillator by the switching step-down means, the power consumption in the oscillation circuit can be reduced as much as possible. At the same time, since the switching clock signal of the switching step-down means is generated based on the output signal of the built-in oscillator, it is not necessary to separately generate a clock signal necessary for switching of the switching type step-down means. Since the oscillation output of itself is used, generation of noise due to interference between different frequencies can be prevented in advance.

It is a block diagram which shows the oscillation circuit which concerns on embodiment of this invention. FIG. 2 is a circuit diagram showing a capacitive voltage dividing step-down circuit as a specific example of the switching step-down means in FIG. FIG. 2 is a circuit diagram showing a capacitive voltage dividing step-down circuit as a specific example of the switching step-down means in FIG. FIG. 2 is a circuit diagram illustrating a specific configuration of a frequency divider circuit in FIG. 1. It is a circuit diagram which shows the switching type pressure | voltage fall means which is the principal part of the 2nd Embodiment of this invention. It is a circuit diagram which shows the switching type pressure | voltage fall means which is the principal part of the 3rd Embodiment of this invention. It is a circuit diagram which shows the switching type pressure | voltage fall means which is the principal part of the 4th Embodiment of this invention. 11 is a graph showing the characteristics of total current consumption with respect to the power supply voltage of the oscillation circuit according to the first embodiment shown in FIG. 1 and the oscillation circuit according to the prior art shown in FIG. It is a circuit diagram which shows the switching type pressure | voltage fall means which is the principal part of the 5th Embodiment of this invention. It is a block diagram which shows the oscillation circuit which concerns on a prior art. It is a circuit diagram which shows the specific structure of the regulator shown in FIG.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing an oscillation circuit according to an embodiment of the present invention. As shown in the figure, an oscillator 200 according to this embodiment includes a switching step-down voltage unit 12, an oscillator 3, a frequency divider circuit 4, a level shifter 5, and an output circuit 6 integrated in an IC chip 11 (dotted line portion in the figure). have. The switching type step-down means 12 steps down the power supply voltage VDD of the power supply 7 to a predetermined internal constant voltage VREG. The specific configuration of the switching type step-down unit 12 will be described in detail later.

  The oscillator 3 is driven by the internal constant voltage VREG, and sends an output signal having a predetermined frequency to the frequency divider circuit 4 by vibrating the external crystal resonator 8. The frequency divider 4 is driven by the internal constant voltage VREG, and appropriately divides the frequency of the output signal of the oscillator 3 and sends it to the level shifter 5. The level shifter 5 appropriately amplifies the voltage of the output signal of the oscillator 3 and outputs it. The output circuit 6 functions as a buffer circuit when the output signal of the level shifter 5 is sent to the output terminal 9. Here, the power supply voltage VDD is applied to the level shifter 5 and the output circuit 6.

  In such an IC chip 11, in order to stabilize the oscillation frequency and reduce the power consumption of the entire oscillation circuit 200, the switching type voltage step-down means 12 is built in the IC chip 11 and is lower than the power supply voltage VDD supplied from the outside. An internal constant voltage VREG is generated. Specifically, the switching step-down means 12 steps down the power supply voltage VDD to the internal constant voltage VREG by on / off control of a switching element (not shown in FIG. 1). Here, the switching element of the switching step-down means 12 is controlled to be turned on / off by a clock signal having a predetermined frequency which is an output signal of the frequency dividing circuit 4. In this case, the external supply voltage VDD is usually in the range of 1.8V ± 10% to 5.0V ± 10%. On the other hand, the internal constant voltage VREG is often set to a very low voltage of 1 V or less recently for low power consumption.

  Thus, in this embodiment, the switching step-down unit 12 is used instead of the regulator 2 in the oscillator 100 shown in FIG. 10, and the on / off state of the switching element of the switching type step-down unit 12 is controlled by the frequency divider 4. Since the output signal is used by using a clock signal having a predetermined frequency, power consumption in the oscillation circuit can be reduced as much as possible (this will be described in detail later). Further, it is not necessary to separately generate a clock signal necessary for switching of the switching type step-down means 12, and the generation of noise due to interference between different frequencies can be prevented by using the oscillation output of the oscillator 3 itself. .

  2 and 3 are circuit diagrams showing a capacity voltage-dividing step-down circuit, which is a specific example of the switching-type step-down means in FIG. 1, in a mode during charging (FIG. 2) and a mode during discharging (FIG. 3), respectively. .

  As shown in FIGS. 2 and 3, the capacitive voltage dividing step-down circuit 13 is composed of two capacitors C1, C2 and five switch means SW1, SW2, SW3, SW4, SW5, and the switch means SW1 to SW5 are turned on. The charging mode shown in FIG. 2 and the discharging mode shown in FIG. 3 are alternately repeated by the off control. That is, in the charging mode, as shown in FIG. 2A, the switch means SW1 and SW2 are turned on and the switch means SW3 to SW5 are turned off, so that the capacitors C1 and C2 are connected between the power source 7 and the ground terminal 14. Connect in series. An equivalent circuit in this case is shown in FIG. On the other hand, in the discharge mode, as shown in FIG. 3A, the switch means SW1 and SW2 are turned off and the switch means SW3 to SW5 are turned on so that the capacitors C1 and C2 are connected between the VREG terminal 15 and the ground terminal 14. Connect in parallel. An equivalent circuit in this case is shown in FIG. Thus, when the capacitors C1 and C2 have the same capacity, the voltage between the capacitors C1 and C2, which is the power supply voltage VDD in the charge mode, is ½ (VDD ) And is generated at the VREG terminal 15 as the internal constant voltage VREG.

  More specifically, in the charging mode, the capacitors C1 and C2 are connected in series, and the Hi-side terminal of the capacitor C1 is connected to the power source 7. On the other hand, in the discharge mode, the capacitors C1 and C2 are connected in parallel, and both the capacitors C1 and C2 have the Hi-side terminal connected to the VREG terminal 15. Here, assuming that the capacitance values of the capacitors C1 and C2 are equal, in the charging mode, the power supply voltage VDD is divided in half by the capacitors C1 and C2, so that the capacitors C1 and C2 correspond to the voltage of VDD / 2. Charge is charged. On the other hand, in the discharge mode, the capacitors C1 and C2 are connected in parallel on the basis of the installation potential GND which is the potential of the ground terminal 14, so that the potential of the VREG terminal 15 is VDD / 2. As described above, by periodically repeating the charging mode and the discharging mode, it is possible to obtain a voltage that is ideally less than half of the power supply voltage VDDV without loss. Here, the internal constant voltage VREG can be smoothed by separately disposing a relatively large capacitor at the VREG terminal 15.

The switch means SW1 to SW5 of the capacitive voltage dividing step-down circuit 13 can be suitably formed by MOS transistors, but their on / off states are controlled by a clock signal CL having a predetermined frequency which is an output signal of the frequency divider circuit 4. FIG. 4 is a circuit diagram showing a detailed configuration of the frequency dividing circuit according to this embodiment. As shown in the figure, the frequency dividing circuit 4 includes n (n = natural number) stage frequency dividers 41, 42,..., 4n connected in series, and any one of the frequency dividers 41 to 4n. A clock selection circuit 45 for selecting an output signal is provided. Then, the output signal of the oscillator 3 supplied via the input terminal 40 is divided by 1/2 ⁿ by n-stage frequency dividers 41 to 4n, and a rectangular pulse signal having a predetermined frequency is obtained via the output terminal 46. And output. At the same time, the clock selection circuit 45 selects a clock signal CL having a predetermined frequency and supplies it to the capacitive voltage dividing step-down circuit 13. Here, by controlling the duty ratio, which is the ratio of each period of the charging mode and discharging mode, T1 (period of charging mode), T2 (period of discharging mode 2), 0 to (VDD / 2) 2 In this range, the internal constant voltage VREG output to the VREG terminal 15 can be controlled.

  Thus, in this embodiment, the output signal of the predetermined frequency generated by the oscillator 3 is appropriately divided to form the switching signals of the switch means SW1 to SW5 of the capacitive voltage dividing step-down circuit 13. Here, in the case of the frequency of the output signal of the oscillator 3, particularly in the case of a low frequency, the output signal of the oscillator 3 can be directly supplied to the capacitive voltage dividing step-down circuit 13 as a switching signal without frequency division. In this case, the frequency dividing circuit 4 can of course be omitted.

<Second Embodiment>
FIG. 5 is a circuit diagram showing another example of the switching type step-down means which is the main part of the second embodiment of the present invention. In the oscillation circuit 200 according to the first embodiment shown in FIG. 1, the switching step-down unit 12 is formed by only the capacitive voltage dividing step-down circuit 13. However, as shown in FIG. 13 and the first regulator 60 can be combined to constitute the switching step-down means 12A. Here, the regulator 60 adjusts the output voltage of the capacitive voltage dividing step-down circuit 13, and has a MOS transistor TR 1 connected between the output side of the capacitive voltage dividing step-down circuit 13 and the VREG terminal 15. . The MOS transistor TR1 is connected via the operational amplifier 64 so that the voltage at the VREG terminal 15 becomes the internal constant voltage VREG based on the reference voltage VREF1 representing the internal constant voltage VREG set in the reference voltage source 63 and the voltage at the VREG terminal 15. To control.

  According to this embodiment, even if a deviation occurs between the output voltage of the capacitive voltage dividing step-down circuit 13 and the internal constant voltage VREG, the internal constant voltage VREG is finally adjusted with high accuracy by the regulator 60. Therefore, the internal constant voltage VREG serving as the drive voltage for the oscillator 3 and the frequency dividing circuit 4 can be held at a predetermined value with high accuracy. Incidentally, in the capacitive voltage dividing step-down circuit 13, the output voltage, that is, the internal constant voltage VREG can be adjusted by controlling the duty ratio. However, the duty ratio control tends to be complicated in the capacitive voltage dividing step-down circuit 13. . On the other hand, in the present embodiment, without using the duty variable circuit, the capacitive voltage dividing step-down circuit 13 with a fixed duty ratio can be simply configured to output, for example, a power supply voltage VDD ÷ 2.

<Third Embodiment>
FIG. 6 is a circuit diagram showing the switching step-down means which is the main part of the third embodiment of the present invention. As shown in the figure, the switching step-down voltage unit 12B in the present embodiment is a capacitive voltage division type by combining the capacitive voltage division type step-down circuit 13 and the first regulator 61, similarly to the switching type voltage step-down unit 12B shown in FIG. Although the output voltage of the step-down circuit 13 is adjusted, the first regulator 61 in this embodiment has a MOS transistor TR2 in addition to the MOS transistor TR1 in the first regulator 60 shown in FIG. That is, the MOS transistor TR2 is selected between the power supply 7 and the VREG terminal 15 in parallel with the MOS transistor TR1 and having a higher on-resistance than the MOS transistor TR1. Then, similarly to the MOS transistor TR1, it is controlled via the operational amplifier 64 so that the voltage of the VREG terminal 15 becomes a predetermined internal constant voltage VREG based on the reference voltage VREF1 and the voltage of the VREG terminal 15. In FIG. 6, the same parts as those in FIG.

According to this embodiment, a smooth start-up of the switching step-down means 12B is ensured when the oscillation circuit 200 is started. In other words, in this embodiment, the capacity voltage-dividing step-down circuit 13 uses the clock signal CL that is the output of the frequency dividing circuit 4, so that the clock signal CL can be obtained at the time of starting when the internal constant voltage VREG cannot be obtained. It becomes difficult, and it is necessary to start the capacitive voltage dividing step-down circuit 13 by some means. In this embodiment, since the power supply voltage VDD is directly applied to the frequency divider circuit 4 via the VREG terminal 15 via the MOS transistor TR2, the drive current of the frequency divider circuit 4 at the start can be supplied satisfactorily. On the other hand, after the capacitive voltage dividing step-down circuit 13 generates the internal constant voltage VREG,
Almost no current flows through the MOS transistor TR2. This is because (ON resistance of MOS transistor TR1) << (ON resistance of MOS transistor TR2). Further, when the power supply voltage VDD decreases, the output of the switching type step-down means 12C begins to decrease, and the overall power consumption reduction effect rapidly deteriorates. However, in this case as well, current can flow through the MOS transistor TR2. It can be operated as a linear regulator similar to the technology. As described above, when the linear regulator is used in combination, the maximum efficiency cannot be obtained, but it is possible to prevent the efficiency from being extremely deteriorated when the power supply voltage VDD is low.

<Fourth embodiment>
FIG. 7 is a circuit diagram showing the switching step-down means which is the main part of the fourth embodiment of the present invention. As shown in the figure, the switching step-down voltage means 12C in the present embodiment has a second regulator 62 in addition to the first regulator 61 shown in FIG. The second regulator 62 steps down the power supply voltage VDD to a predetermined set voltage and applies it to the capacitive voltage dividing step-down circuit 13. The MOS transistor TR3 connected between the power supply 7 and the capacitive voltage dividing step-down circuit 13 is used. have. The MOS transistor TR3 is configured so that the input voltage of the capacitive voltage dividing step-down circuit 13 becomes a predetermined reference voltage VREF2 based on the reference voltage VREF2 set in the reference voltage source 65 and the voltage on the input side of the capacitive voltage dividing step-down circuit 13. It is controlled via the operational amplifier 66. Here, the reference voltage VREF2 can be set to about the power supply voltage VDD / 2. In FIG. 7, the same parts as those in FIG. 6 are denoted by the same reference numerals, and redundant description is omitted.

  According to this embodiment, the high power supply voltage VDD can be greatly stepped down by the regulator 62 and supplied to the capacitive voltage dividing step-down circuit 13. Therefore, it is particularly useful when the power supply voltage VDD is high and the difference from the internal constant voltage VREG is large. More specifically, the oscillator 3 and the like operate at the reference voltage VREF1 (= internal constant voltage VREG) set to the reference voltage VREF1. The voltage of the internal constant voltage VREG itself is accurately controlled by the operational amplifier 64 and the MOS transistors TR1 and TR2. Although the MOS transistor TR2 is directly connected to the power supply 7, the MOS transistor TR2 is connected to the output side of the capacitive voltage dividing step-down circuit 13. Here, as described above, the MOS transistor TR1 is made larger than the MOS transistor TR2, that is, has a low resistance. For example, if the channel lengths of the MOS transistors TR1 and TR2 are the same, the channel width of the MOS transistor TR1 is set to 5 times or more that of the MOS transistor TR2.

  Further, the capacitive voltage dividing step-down circuit 13 in this embodiment is driven by the reference voltage VREF2 controlled by the operational amplifier 66 and the MOS transistor TR3. Therefore, the maximum power reduction effect is exhibited when the power supply voltage VDD is substantially equal to the reference voltage VREF2. This is because the voltage-dividing from the reference voltage VREF2 to the reference voltage -VREF1 is ideally performed without loss by the capacitive voltage dividing step-down circuit 13. Here, if both reference voltages VREF1, VREF2 are set so that the potential difference between the source and drain of the MOS transistor TR1 is small, the power consumption by the MOS transistor TR1 is small.

  The above operation will be described using specific numerical values. The reference voltage VREF1 is a voltage for operating the oscillator 3 with low power consumption, and is set to about 0.8 V here. On the other hand, the reference voltage VREF2, which is a voltage supplied to the capacitive voltage dividing step-down circuit 13, is set to about 1.8V. The MOS transistors TR1 and TR2 are both NMOS transistors with a low threshold (assumed to be approximately 0V here), and the impedance of the MOS transistor TR2 is set to 1/5 of the MOS transistor TR1 by setting the channel width.

  It is assumed that the current I_OP = 20 μA of the operational amplifier current 64 consumed under the internal constant voltage VREG, and a current of about 16 μA flows through the MOS transistor TR1 and about 4 μA flows through the MOS transistor TR2. When the power supply voltage VDD = 1.8V, when the capacitive voltage dividing step-down circuit 13 is (VDD / 2), the output is 0.9V. Therefore, the potential difference between both ends of the MOS transistor TR1 is 0.1V. The loss power at TR1 is 16 μA × 0.1 V = 1.6 μW. The loss power in the MOS transistor TR2 is 4 μA × (1,8−0.8) V = 4 μW. Since the potential difference across the MOS transistor TR3 is zero, the loss power can be ignored. Therefore, the total loss power is 5.6 W. In the case of the regulator 2 shown in FIG. 10, since the loss power under the same power supply condition is 20 μW, the reduction amount of the loss power in this embodiment can be reduced by 14.4 μW, that is, 70% or more. In terms of current consumption, this corresponds to a reduction of about 8 μA.

  Note that, when the power supply voltage VDD becomes higher than 1.8 V, loss power in the MOS transistor TR3 starts to be generated, and the overall power consumption gradually increases. However, the amount of reduction when converted to current consumption is approximately 8 μA and is almost constant. Conversely, when the power supply voltage VDD is lower than 1.8 V, the output of the switching step-down means 12C starts to decrease, and the overall power consumption reduction effect deteriorates rapidly. However, even in such a case, a current can flow through the MOS transistor TR2, so that the conventional linear regulator can be operated. As described above, when the linear regulator is used in combination, the maximum efficiency cannot be obtained, but it is possible to prevent the efficiency from being extremely deteriorated when the power supply voltage VDD is low.

  FIG. 8 is a graph showing a SPICE simulation result of the oscillation circuit having the switching type step-down means 12C shown in FIG. This figure shows current consumption in comparison with the oscillation circuit according to the prior art shown in FIG. The oscillation circuit used for the simulation divides a crystal oscillation of about 16 MHz by 9 stages (1/512) and outputs a clock for clocking of 32 kHz. The clock signal CL of the switching step-down means 12C is taken from the second stage of frequency division (about 4 MHz). The horizontal axis is the power supply voltage VDD applied from the outside, the vertical axis is the entire current consumption including the bias circuit and the output circuit 6 including the operational amplifier 64 and the reference voltage source 63, and the one-dotted line indicates the regulator 2 according to the prior art. When used (see FIG. 10), the solid line represents the current consumption in the case of the fourth embodiment of the present invention (see FIG. 7).

  Referring to FIG. 8, in a region where the power supply voltage VDD is relatively high, a constant current consumption reduction effect is obtained at about 8 μA. In the region where the power supply voltage VDD is extremely low, there is no effect of reducing the current consumption in the case of the fourth embodiment, and only the regulator directly connected to the power supply 7 is effective. I understand that. Thereby, in the present invention, a remarkable reduction effect of current consumption (power consumption) is obtained in a region where the power supply voltage VDD is 1.4 V or more.

<Fifth embodiment>
FIG. 9 is a circuit diagram showing the switching step-down means which is the main part of the fifth embodiment of the present invention. As shown in the figure, the switching step-down unit 12D according to the present embodiment has a duty modulator 69. The duty modulator 69 receives the clock signal CL from the frequency dividing circuit 4 and is a duty ratio that is a ratio of on / off states of the switching elements SW1 to SW5 (see FIGS. 2 and 3) of the capacitive voltage dividing step-down circuit 13. To control. As a result, the internal constant voltage VREG, which is the output voltage of the switching step-down means 12, is controlled to a predetermined value. Therefore, the switching step-down circuit 12 in this embodiment includes a reference voltage source 67 that generates a reference voltage VREF3 representing a predetermined internal constant voltage VREG, and a comparator that compares the reference voltage VREF3 and the output voltage of the switching step-down unit 12. 68. The comparator 68 controls the duty modulator 69 so that the deviation between the internal constant voltage VREG and the reference voltage VREF3 becomes zero, and performs on / off control of the switching elements SW1 to SW5 of the switching step-down means 12 with an optimum duty ratio. Do.

  According to this embodiment, it is possible to adjust the output voltage of the switching step-down circuit 12 by controlling the duty ratio of the clock signal CL having a constant frequency, and to generate the highly accurate internal constant voltage VREG at the VREG terminal 9.

<Other embodiments>
In the above embodiment, the switching step-down means 12A to 12D include the capacitive voltage dividing step-down circuit 13. However, the present invention is not limited to this. The capacitive voltage dividing step-down circuit 13 can perform a predetermined step-down with a simple circuit, but may have other configurations as long as it is a step-down circuit that steps down the power supply voltage VDD. For example, a DC / DC converter may be used. Even in this case, it is essential to use the switching signal as the switching pulse by using the output signal of the oscillator 3 or the clock signal CL obtained by dividing the output signal by the frequency divider 4.

  Further, although the oscillator 3 is a crystal oscillator in the above-described embodiment, it is not limited to this. For example, all types of oscillators such as an RC oscillator and a MEMS oscillator that do not use the crystal resonator 8 can be applied.

  The present invention can be used in the industrial field of manufacturing and selling an oscillation circuit mounted on a mobile device or the like that has a strong demand for low power consumption.

3 Oscillator 4 Dividing Circuit 7 Power Supply 12, 12A to 12D Switching Type Bucking Unit 13 Capacitance Voltage Dividing Step-Down Circuit 60, 61, 62 Regulator 63, 65 Reference Voltage Source 64, 66 Operational Amplifier 69 Duty Modulator 200 Oscillation Circuit VDD Power Supply Voltage VREG Internal constant voltage CL clock signal SW1 to SW5 switch means

Claims (5)

An oscillation circuit for driving an oscillator by stepping down a power supply voltage applied from a power supply,
Switching type step-down means for stepping down the power supply voltage to a predetermined internal constant voltage by ON / OFF control of the switching element;
And having an oscillator driven by application of the internal constant voltage,
The switching type step-down means is configured to control on / off of the switching element with a clock signal of a predetermined frequency using the output signal of the oscillator,
The switching type step-down means includes a charge mode in which the capacitors are connected in series by a combination of a plurality of capacitors and a plurality of switch means on and off, and a discharge mode in which the capacitors are connected in parallel. In the charging mode, the power supply voltage is applied to both ends of the capacitors connected in series to charge the capacitor, and in the discharging mode, the capacitors are charged with the power supply disconnected. Charging voltage is output,
A capacitive voltage dividing step-down circuit configured to perform on / off control of the switch means by the clock signal;
Further, the switching type voltage step-down means has a first regulator that adjusts the output voltage of the capacity voltage division type step-down circuit together with the capacity voltage division type step-down circuit,
The first regulator includes a first transistor connected between an output side of the capacitive voltage dividing step-down circuit and an output terminal of the switching step-down means;
Based on the first reference voltage representing the predetermined internal constant voltage set to the first reference voltage source and the voltage of the output terminal, the voltage of the output terminal is set to the predetermined internal constant voltage. An oscillation circuit characterized by being configured to control one transistor . The oscillation circuit according to claim 1,
Having a frequency divider for dividing the output signal of the oscillator;
The oscillation type circuit is characterized in that the switching type step-down means is configured to control on / off of the switching element by a clock signal of a predetermined frequency output from the frequency dividing circuit. In the oscillation circuit according to claim 1 or 2 ,
The first regulator includes a second transistor connected in parallel to the first transistor and having a higher on-resistance than the first transistor between the power source and the output terminal. The second transistor is controlled together with the first transistor so that the voltage at the output terminal becomes the predetermined internal constant voltage based on the first reference voltage and the voltage at the output terminal. An oscillation circuit. In the oscillation circuit according to claim 3 ,
The switching step-down means has a second regulator for stepping down the power supply voltage to a predetermined set voltage and applying it to the capacitive voltage dividing step-down circuit,
The second regulator includes a third transistor connected between the power source and the input side of the capacitive voltage dividing step-down circuit,
Based on the predetermined set voltage set as the second reference voltage source and the input voltage to the capacitive voltage dividing step-down circuit, the third voltage is set so that the input voltage of the capacitive voltage dividing step-down circuit becomes the set voltage. An oscillation circuit characterized by controlling the transistor. In the oscillation circuit according to any one of claims 1 to 4 ,
Having a duty modulator for controlling the output voltage of the switching step-down means by controlling the duty ratio of the switching element of the switching type step-down means in the on / off state;
The third reference voltage representing the predetermined internal constant voltage is compared with the voltage at the output terminal of the switching step-down means, and the duty ratio is set via the duty modulator so that the deviation between them is zero. An oscillation circuit characterized by controlling.