JP6363266B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more preferably to a method for forming a line pattern having a high aspect ratio indispensable for manufacturing a NAND-flash memory having a three-dimensional structure.

  With the demand for higher speed and higher density of semiconductor devices, development of semiconductor devices having a three-dimensional structure has been actively carried out in recent years. For example, Non-Patent Document 1 discloses a three-dimensional NAND-flash memory (hereinafter abbreviated as 3D-NAND) as an example. FIG. 1 shows a schematic view of a 3D-NAND memory cell in three views. 1A is a top view of a 3D-NAND memory cell viewed from the top, and FIG. 1B is a side view of the top view of FIG. 1A viewed from the right side of the paper (viewed in the y direction). FIG. 1C is a front view of the top view of FIG. 1A viewed from the lower side of the drawing (a structure viewed in the x direction). The memory cell actually extends long in the horizontal direction (y direction) of the drawing, and FIGS. 1A and 1C show only the end portions on both sides of the memory cell. In FIG. 1A, the bit line 33 and the word line 34 shown in FIG. 1C are not shown.

As shown in FIG. 1C, the 3D-NAND memory cell includes a laminated film of a tungsten film 5 (conductive film) and a SiO ₂ film 3 (insulating film) on a semiconductor substrate (Si substrate) 1. The control gate layer 30 is further laminated in a stepped shape, and has a structure in which a cylindrical channel hole 4 filled with polysilicon is formed. In the first stage of the manufacturing process, the control gate layer 30 is formed as a laminated film of the Si ₃ N ₄ film and the SiO ₂ film 3, and the Si ₃ N ₄ film is replaced with the tungsten film 5 during the manufacturing process. . Since the tungsten film 5 included in the control gate layer 30 is operated as a gate electrode, the control gate layer 30 has a terrace structure in which the control gate layers 30 are stacked stepwise, and each is connected to the word line 34 via the contact hole 35. ing. (Hereinafter, the laminated film of the control gate layer 30 is referred to as a control gate group 31 for convenience.) The control gate group 31 is divided in the x direction by grooves (spaces) 32 as shown in FIG. When viewed from above, it has a line-and-space structure as shown in FIG.

  A contact hole 6 is formed on the channel hole 4 and is further connected to a bit line 33 formed thereon. Although not shown, an ONO film is formed as a charge trap material on the inner wall surface of the channel hole 4 (the interface between the wall surface of the hole formed inside the control gate group 30 and the buried polysilicon pillar). Operating as a memory cell capacitor.

A feature of the 3D-NAND memory cell disclosed in Non-Patent Document 1 is that the control gate group 31 is divided in the x direction by a groove 32 as shown in FIG. This groove 32 is formed by etching. 2A and 2B, patterns before and after the formation process of the groove 32 are shown in side views similar to FIG. 2A shows a pattern before etching, and FIG. 2B shows a pattern after etching. In the state before etching shown in FIG. 2 (A), the control gate layer 30 composed of the laminated film of the Si ₃ N ₄ film 2 and the SiO ₂ film 3 is laminated on the Si substrate 1, and polysilicon is formed inside. A channel hole 4 filled with is formed. A line and space resist pattern is formed on the upper surface by lithography, and a groove 32 shown in FIG. 2B is formed by dry etching using the resist pattern as a mask.

  In the memory cell shown in FIG. 1, eight control gate layers 30 are stacked in the control gate group. However, in order to increase the density, the number of stacked layers is increased or the diameter of the channel hole 4 is decreased. Therefore, it is necessary to narrow the gap between the channel holes in the X direction and the Y direction. For example, in Non-Patent Document 1, as the future development, the number of stacked control gate layers 30 will be 128, or the diameter of the channel hole 4 will be reduced to 45 nm to reduce the cost per bit (bit cost). It has been proposed to do.

Proceeding of 2009 symposium on VLSI Technology, P192-193

In the 3D-NAND disclosed in Non-Patent Document 1, when the number of stacked control gate layers 30 is increased in order to increase the density of memory cells, the height of the control gate group 31 increases. If the thickness of the control gate layer 30 is reduced, an increase in the height of the control gate group can be suppressed, but it is difficult in practice. If the tungsten film 5 is thinned, the amount of charge trapped in the charge trapping ONO film becomes too small, and the data retention performance of the NAND-flash memory is degraded. Further, when the SiO ₂ film 3 is thinned, a phenomenon called crosstalk in which erroneous data is written by a signal of an adjacent control gate occurs. For this reason, the film thickness of the tungsten film 5 or the SiO ₂ film 3 cannot actually be made extremely thin.

    Further, when the diameter of the channel hole 4 is reduced to narrow the interval between the channel holes, the width of the control gate group 31 (the length in the x direction in FIG. 1A) is inevitably reduced. Therefore, when the number of stacked layers is increased and the channel hole diameter is reduced, the ratio of the height to the pattern width, that is, the aspect ratio (here, the value obtained by dividing the height by the width) increases.

  As a result of analysis by the present inventor, it has become clear that when the aspect ratio is increased, a pattern deformation called Wiggling occurs in the process of dividing the control gate group 31 into line and space. Wiggling occurs especially when the aspect ratio is 10 or more. Wiggling is a phenomenon in which a pattern with a high aspect ratio undulates from side to side, and FIGS. 3A and 3B respectively show a top view and a side view of a memory cell in which Wiggling has occurred. FIG. 3B shows a cross-sectional view of FIG. 3A taken along the line 1-m, but the adjacent pattern comes into contact with each other, and the etching of the laminated film for forming the grooves 32 stops halfway. Furthermore, since etching does not reach the lower layer, there is a problem that the lower gate electrode is electrically shorted or the channel portion is destroyed by deformation. Further, even if the control gate group 31 is not deformed so as to be in contact with each other, the line and space undulates and the channel position deviates from the design value, so that the channel hole 4 and the contact hole shown in FIG. The problem that 6 cannot connect well also occurs.

  Therefore, an object of the present invention is to provide a semiconductor element block in which a laminated film for forming an active element is formed above a semiconductor substrate, and the laminated film is separated by an interlayer insulating material as in the 3D-NAND. In a semiconductor device provided with this, or a manufacturing method of the said semiconductor device, it is providing the method for suppressing the short circuit of the said semiconductor element blocks resulting from Wiggling, and the semiconductor device which these problems do not generate | occur | produce.

  Another object of the present invention is to provide a semiconductor including a semiconductor element block in which a laminated film for forming a film-like active element is formed above the semiconductor substrate, and the laminated film is separated from each other by an interlayer insulating material. An object of the present invention is to provide a method for manufacturing a semiconductor device or a semiconductor device in which the occurrence of poor connection between the semiconductor element block and a distribution electrode or wiring is suppressed.

  The present invention relates to a method of manufacturing a semiconductor device comprising a three-dimensional memory cell forming step, wherein the three-dimensional memory cell forming step comprises a laminated film of an insulating layer and a conductor layer, and a plurality of stacked control gate layers. Forming a plurality of control gate groups by forming a groove in the plurality of stacked control gate layers by plasma etching and separating the plurality of stacked control gate layers by plasma etching. The length in the longitudinal direction of the control gate group and the height of the control gate group are values obtained by dividing the buckling period, which is a value obtained by dividing the length by two times by a natural number, by the height. It is specified to be smaller than 3.3.

  Furthermore, the present invention provides a method for manufacturing a semiconductor device comprising a three-dimensional memory cell forming step, wherein the three-dimensional memory cell forming step comprises a laminated film comprising an insulating layer and a conductor layer, and a plurality of stacked control gates. Forming a channel hole in a layer, and forming a plurality of control gate groups by forming a groove in the plurality of stacked control gate layers by plasma etching to separate the plurality of stacked control gate layers. The length of the control gate group in the longitudinal direction and the height of the control gate group are defined such that a value obtained by dividing the length by the height is less than 1.65. To do.

  In addition, the present invention provides a plurality of control gate groups in which a plurality of control gate layers are stacked and separated from each other by a groove, channel holes formed in the control gate group, and electrodes in the control gate group via electrodes. In a semiconductor device comprising a connected bit line and a word line connected to the control gate layer via a contact plug, the longitudinal length of the control gate group is divided by the height of the control gate group The length and the height are defined so that the value is less than 1.65.

  Wiggling can be reduced. Or even if Wiggling occurs, the degradation of device characteristics can be kept to a minimum.

(A) Top view showing 3D-NAND memory cell structure, (B) Side view, (C) Front view (A) Side view of memory cell before 3D-NAND etching process, (B) Side view (A) Top view of memory cell in which Wiggling occurs, (B) Side view (A) Top view showing line pattern before buckling occurs, (B) Side view (A) Top view showing line pattern after occurrence of buckling, (B) Same side view Simulation results showing the relationship between the buckling period-pattern height ratio λ / h and the buckling coefficient k 3D-NAND flash memory die in which the memory cell of Example 2 is formed (A) Top view explaining the process which processes the laminated film in the memory cell of Example 1 into a line and space, (B) The side view, (C) The front view The front view explaining the process which processes the laminated film in the memory cell of Example 2 into a line and space Front view Front view (A) Top view explaining the process which processes the laminated film in the memory cell of Example 2 into a line and space, (B) The side view, (C) The front view A) Top view for explaining a process of processing a laminated film in the memory cell of Example 2 into a line and space, (B) a side view, (C) a front view The figure which shows the relationship between the etching depth of aC in the memory cell of Example 2, a buckling coefficient, and a buckling factor. The figure which shows the relationship between the etching depth of a laminated film, the buckling coefficient, and a buckling factor in the memory cell of Example 2. The perspective view which shows the structure of the control gate group of the memory cell of Example 2. Example of laminated film division etching of Example 2 Example of line pattern with initial waviness Line pattern after swell amplification Relationship between initial swell period and swell gain Schematic diagram showing a proposed measure for swell amplification in Example 3 The schematic diagram which shows the deformation | transformation of the line pattern which gave the swell amplification countermeasure of Example 3 Diagram showing the relationship between the etching depth of the mask material (a-C) and the amplitude of the waviness when the mask material is etched with waviness (A) Schematic diagram showing a control gate group of 3D-NAND in which processing defects have occurred due to Wiggling, (B) AA ′ sectional view FIG. 24 shows the relationship between the etching depth of the laminated film and the amplitude of waviness in the control gate group of 3D-NAND in which the processing failure occurs. (A) Top view showing an outline of a 3D-NAND memory cell in which a wiring connection failure occurs, (B) AA ′ sectional view (A) Top view showing a resist mask layout of Example 4, (B) Side view Relationship between etching depth of a-C and waviness amplitude of Example 4 Processed shape after etching the laminated film of Example 4 Relationship between etching depth of a-C and waviness amplitude of Example 4 Example of exposure reticle layout of embodiment 4 Example of resist mask layout of the present invention in Example 4

Example 1
First, a mechanism in which Wiggling occurs in a semiconductor device including a line-and-space semiconductor element block will be described by taking a line pattern formed of a single layer film as an example.

As described above, the control gate layer of 3D-NAND is formed by laminating a SiO ₂ film on a Si ₃ N ₄ film by CVD in the initial stage of the manufacturing process. It is known that not only 3D-NAND manufacturing processes but materials formed by CVD have a minute residual stress during film formation. Further, it was also found that when the laminated film of the control gate layer is processed into a line and space by etching, stress is generated in the laminated film when the laminated film is altered by the etching process, and the laminated film is deformed by this stress. Therefore, it is considered that Wiggling occurs due to the two factors of the residual stress and the deterioration of the laminated film caused by etching, and the laminated film is more likely to generate Wiggling than the single-layered film. .

  In terms of phenomena, Wiggling has two modes, buckling and swell amplification. 4 and 5 show examples of patterns in which buckling occurs before and after buckling. Buckling is a phenomenon in which a straight line pattern 7 as shown in FIGS. 4A and 4B is deformed by a stress and falls down. FIG. 4A shows a top view of the line pattern 7. The height h, the length L in the longitudinal direction (y direction), and the width w (the length in the x direction, the thickness in the short side direction). It is possible to define that the pattern is formed. FIG. 4B is a side view showing an A-A ′ cross section of the line pattern shown in FIG. FIG. 5A shows a top view of a pattern collapsed due to buckling, and the line pattern 7 before the occurrence of buckling is also indicated by a dotted line for reference. FIG. 5B is a side view showing the A-A ′ cross section of the line pattern shown in FIG. 5A, as in FIG. 4B. As shown in FIG. 5A, it is known that when buckling occurs, the pattern undulates with a certain period. This period is called a buckling period λ, and is indicated by λ in FIG.

  As a result of the numerical calculation, it was found that the occurrence condition of buckling is expressed by the following formula 1.

  The left side of Equation 1 is a dimensionless value obtained by multiplying the ratio of the residual stress σ and the Young's modulus E by the square of the aspect ratio h / w. We defined this value as the buckling factor γ. On the other hand, the right side k of Equation 1 is a dimensionless value called a buckling coefficient, and buckling occurs when the buckling factor γ exceeds the buckling coefficient k. As a result of the numerical calculation, it has been found that the pattern height h (see, for example, FIG. 4B) is closely related to the buckling period λ and the pattern height h shown in FIG. In FIG. 6, the numerical calculation result which shows the relationship between buckling coefficient k and value (lambda) / h (dimensionless) is shown. From the results of the numerical calculation, it was found that the buckling coefficient k is a function of the value λ / h and takes the minimum value 1.1 when λ / h is 3.3 regardless of the material and film thickness.

It is known that materials usually used in semiconductor devices, such as SiO ₂ and Si ₃ N ₄ , have a residual stress σ corresponding to several percent of Young's modulus E, and therefore the left side of Equation 1 is always finite. Have a value. For this reason, when the aspect ratio h / w increases, the value on the left side of the above equation 1 increases, and buckling occurs when the aspect ratio h / w exceeds the buckling coefficient k. If σ / E is 1%, buckling may occur when the aspect ratio h / w is around 11 and the buckling factor γ exceeds the minimum value 1.1 of the buckling coefficient k.

  Next, restrictions on the values that the buckling period λ can take will be described. When the length of the line pattern is a finite value L (the length is defined as shown in FIG. 4A), the buckling period λ must satisfy the following condition.

  As described above, buckling is most likely to occur (that is, the buckling coefficient k takes the minimum value 1.1) when λ / h is 3.3, that is, when the value of λ is 3.3h. Considering this and the relationship of Equation 2, 3.3 can be taken as the value of λ / h when L is a multiple of 1.65h. That is, when the relationship between L and h satisfies the relationship of L = 1.65h, k always takes the minimum value 1.1, and buckling occurs with a smaller stress and a smaller aspect ratio.

On the other hand, when L is smaller than 1.65h, the value of λ can only take a value smaller than 3.3h. Therefore, λ / h is always smaller than 3.3, and k is necessarily larger than the minimum value 1.1. Therefore, the stress required for buckling is increased, and the allowable aspect ratio is also increased.

For example, when L = 1.65h, possible values of λ are 3.3h, 3.3h / 2, 3.3h / 3,. Therefore, possible values of λ / h are 3.3, 3.3 / 2, 3.3 / 3. From the relationship shown in FIG. 6, k takes the minimum value 1.1 when the period is λ = 3.3h. For this reason, Wiggling with a period λ = 3.3 h is likely to occur.

  When L = 0.5h, possible values of λ are h, h / 2, h / 3... And possible values of λ / h are 1, 1/2, 1/3 ·・ ・. According to the relationship in FIG. 6, the range that k can take is that it is on the left side of λ / h = 1, and k is the smallest in the period of λ / h = 1, that is, λ = h. Is the case. From the relationship shown in FIG. 6, k at this time is 4.0. The value of k is as large as about 3.6 times that of L = 1.65h. In consideration of the buckling occurrence condition of Equation 1, when the pattern length value is shortened from 1.65h to 0.5h, the stress necessary for buckling occurrence increases 3.6 times. That is, buckling is less likely to occur.

  Therefore, it has been found that Wiggling due to buckling can be suppressed by making the pattern length L smaller than 1.65 times the pattern height h.

  In the present embodiment, a single line pattern has been described as an example. However, if the microfabrication process has a form in which a planar laminated film is separated by etching to form a line and space pattern, buckling is performed. The mechanism of generation is common. Therefore, it goes without saying that the knowledge of this embodiment can be applied to the above-described microfabrication processes in general.

(Example 2)
In the present embodiment, an example in which the technique described in the first embodiment is applied to a 3D-NAND manufacturing process to suppress buckling-induced Wiggling will be described.

  In FIG. 7, the external view of the die | dye which comprises 3D-NAND of a present Example is shown. The die shown in FIG. 7 has a structure in which four 3D-NAND memory cells 70 and peripheral circuits 71 are integrated. The structure of each memory cell is almost the same as that of the memory cell shown in FIG. 1, but the aspect ratio of the control gate group 31 is set to a value that hardly causes buckling.

Next, a 3D-NAND structure in which buckling has occurred and a 3D-NAND structure in which buckling does not occur will be described while comparing them. As described above, buckling occurs at the time of etching in which the groove 32 is formed and the laminated film of the Si ₃ N ₄ film 2 and the SiO ₂ film 3 is separated into a line and space pattern. The space pattern formation process will be described in detail.

8 to 13 are diagrams for explaining the process of forming the line and space pattern. 8A to 8C are diagrams showing the memory cell in the state shown in FIG. 2A in a three-sided view, and FIG. 13 shows the memory cell in the state shown in FIG. That is, FIG. 3 is a three-side view showing the memory cell after etching. In order to avoid the complexity of the drawings, FIGS. 9 to 11 show only the front view of the laminated film of the Si ₃ N ₄ film and the SiO ₂ film in the x direction, and FIG. 12 shows the state immediately before the etching. Displayed in three views.

FIG. 8C shows a laminated film in which a control gate layer 30 composed of a Si ₃ N ₄ film 2 and a SiO ₂ film 3 is further laminated on a Si substrate 1 (that is, a Si ₃ N ₄ film 2 and a SiO ₂ film). 3 is a front view of a laminated film of 34 layers, a total of 68 layers. Since the film thicknesses of the Si ₃ N ₄ film 2 and the SiO ₂ film 3 are each 30 nm, the total film thickness is approximately 2 μm. For convenience of drawing, the drawing shows a cross-sectional view with 8 layers, but in actuality, a sample with a total number of layers of 68 layers was prepared for experiments. A channel hole 4 is formed inside the structure, and the inside is filled with polysilicon. The length of the lowermost Si ₃ N ₄ film 2 in the word line direction (y direction in this embodiment) is L, and the height of the control gate group 31 is h. For convenience of illustration, only a part of the Si substrate 1 is shown, but the Si substrate actually spreads in the horizontal direction and the front-rear direction on the paper surface.

First, an empty portion of the upper portion of the stepped structure of this structure is filled with an SiO ₂ film 8 that is an interlayer insulating material as shown in FIG. 8 (A) or (C). Next, an amorphous carbon (aC) film 9 having a thickness of 1 μm and a SiON film 10 having a thickness of 100 nm are sequentially stacked on the sample by CVD (FIG. 9). Further, a line-and-space resist mask 11 having a line width of 50 nm and a space width of 50 nm as shown in FIG. 10 is formed thereon by a technique called nanoimprint with less LER. In the subsequent etching process, it is necessary to divide the line up to the lowermost Si ₃ N ₄ film 2, so the length of the line pattern is the same as the length L in the y direction of the lowermost Si ₃ N ₄ film 2. It must be more than that. In this example, a resist pattern having a length L was formed. The SiON film 10 is etched along the formed resist mask 11 to form a SiON mask (FIG. 11). Similarly, the aC film 9 is etched along the formed SiON mask to form an aC mask. 12A to 12C show a top view, a side view, and a front view of a memory cell in a state where an aC mask is formed. As can be seen from comparison with FIGS. 12A and 12B, an aC mask is formed on the channel hole 4, and a line-and-space pattern extending in the y direction is formed. The thickness of the finally formed aC mask is 1 μm, and the line width and space width are 50 nm each.

Finally, the laminated film of the Si ₃ N ₄ film 2 and the SiO ₂ film 3 is consistently plasma etched along the aC mask. As a result, a groove 32 is formed in the laminated film, and a control gate group 31 having a line and space pattern is formed separately (FIG. 13). The maximum length in the longitudinal direction of the control gate group 31, that is, the length in the longitudinal direction of the lowermost control gate layer 30 of the step-like structure is L, and the width of the control gate group 31, that is, the direction separated by the grooves. The length is w. As can be seen from FIG. 1C, the word line 34 is formed parallel to the longitudinal direction, and the bit line 33 is formed parallel to the width direction. As can be seen by comparing FIGS. 13A to 13C, in the state immediately after etching, nothing is filled in the groove 32 between the control gate groups 31, and it is independent only by the rigidity of the laminated film. It is in a state (the upper portion of the step-like structure is filled with an SiO ₂ film 8 which is an interlayer insulating material).

  Using the above process, a sample having a length L of the control gate group 31 of 6.6 μm and two samples of 440 nm were prepared, and a test was performed to determine whether buckling occurs.

  6.6 μm is 1.65 times the final pattern height of 2 μm, that is, a multiple of 3.3 μm. From the consideration of Example 1, it is estimated that buckling is very likely to occur, whereas 440 nm is 3.3%. It is estimated that it is smaller than μm and buckling is unlikely to occur.

  For the sample with a length L of 6.6 μm, Wiggling occurred when the a-C film 9 was etched to a depth of 500 nm in the process of FIG. In this case, the relationship between the buckling coefficient k calculated for several possible buckling periods λ = 2L / n and the etching depth h, the minimum value of these buckling coefficients k, the value of the buckling factor γ, and the etching The result of calculating the relationship of the depth h is shown in FIG. Since the length L is as long as 6.6 μm, the buckling period λ can take various values of 13.2 μm or less. For this reason, the minimum value of the buckling coefficient k is almost unchanged at 1.1. On the other hand, the buckling factor γ increases in proportion to the square of the etching depth h. When the etching depth reaches 500 nm, the buckling factor γ becomes larger than the minimum value of the buckling coefficient k. At this time, the aC film 9 has a pattern with an aspect ratio of 10 having a height h of 500 nm and a width w of 50 nm. Moreover, since aC used in this study has a residual stress σ corresponding to 1.2% of Young's modulus E, the buckling factor γ is 1.2. At this point in time, the buckling factor γ becomes larger than the buckling coefficient k, so it is considered that Wiggling occurred due to buckling.

  Next, test results of a sample having a length L of 440 nm will be described. The result was good, and wiggling due to buckling did not occur even when the bottom of the a-C film 9 was etched. In this case, the relationship between the buckling coefficient k calculated for several possible buckling periods λ = 2L / n and the etching depth h, the minimum value of these buckling coefficients k, the value of the buckling factor γ, and the etching The result of calculating the relationship of the depth h is shown in FIG. The length L set in this experiment is as short as 440 nm. Therefore, the buckling period λ can only be 2L, that is, a value of 0.88 μm or less. Therefore, the minimum value of the buckling coefficient k increases at an etch depth h = 266 nm or more where 2L / h = 3.3. For this reason, even at an etch depth of 500 nm where the buckling factor γ exceeds 1.1, that is, an aspect ratio of 10, the buckling factor γ is less than the buckling coefficient k, so that Wiggling due to buckling does not occur.

That is, considering the process in the middle of etching, in order to suppress buckling, the etching depth h ₁ corresponding to an aspect ratio of 10 where the buckling factor γ is around 1.1 and h ₀ satisfying 2L / h ₀ = 3.3 are satisfied. , H ₁ > h ₀ = must hold. In other words, the pattern length L must be less than 16.5 times the width w.

Subsequently, the laminated film of the Si ₃ N ₄ film and the SiO ₂ film under the aC mask prepared by the above test was etched. FIG. 15B shows the relationship between the etching depth of the laminated film and the minimum values of the buckling factor γ and the buckling coefficient k. The residual stresses of the Si ₃ N ₄ film and the SiO ₂ film are both 1.0% of Young's modulus. The range of the horizontal axis of the graph was set from 0 to 2 μm which is the thickness of the laminated film. The value of the buckling factor γ increases in proportion to the square of the height. On the other hand, the minimum value of the buckling coefficient k increases at an etch depth h = 266 nm or more as in the case of FIG. For this reason, in the range of 0 to 2 μm, the value of the buckling factor γ is always smaller than the minimum value of the buckling coefficient k, so it is considered that wiggling due to buckling does not occur, and etching of the laminated film is also performed in actual tests. There was no buckling.

  Next, instead of a-C, the same evaluation was performed using a coating film (SOC) of an organic material with a small residual stress. In the prepared samples, the length L of the control gate group 31 is two, 6.6 μm and 440 nm, as in the case where the mask is aC. The thickness of the SOC mask was 1 μm, and the line width and space width were 50 nm each. In the SOC, the residual stress σ is only 0.16% of the Young's modulus E. Therefore, even when the SOC mask is etched to 1 μm and the aspect ratio reaches 20, the buckling factor γ is 0.64, which is smaller than the minimum value 1.1 of the buckling coefficient k. For this reason, Wiggling due to buckling did not occur in any sample having a length L of 6.6 μm or 440 nm.

Next, using this SOC mask, the laminated film of the Si ₃ N ₄ film and the SiO ₂ film was etched in the manner shown in FIG. For the sample having a length L of 6.6 μm, Wiggling occurred when the laminated film was etched to a depth of 550 nm. In this case, the relationship between the buckling coefficient k calculated for several possible buckling periods λ = 2L / n and the etching depth h, the minimum value of these buckling coefficients k, the value of the buckling factor γ, and the etching The result of calculating the relationship of the depth h is shown in FIG. The length L set in this experiment is as short as 6.6 μm. For this reason, the above-mentioned etch depth of 2L / h = 3.3 is also as large as h = 4.0 μm. Therefore, between 0 and 2 μm, the minimum value of the buckling coefficient k is 1.1 and is almost constant. On the other hand, the buckling factor γ increases in proportion to the square of the etching depth h. When the etching depth reaches 550 nm, the buckling factor γ becomes larger than the minimum value of the buckling coefficient k. The aspect ratio at this time is 11. Considering that the residual stress σ of the laminated film is about 1.0% of the Young's modulus E of the Si ₃ N ₄ film and the SiO ₂ film, the buckling factor γ at this time is 1.21. Therefore, at this point, the buckling factor exceeds the buckling coefficient, and it is considered that Wiggling occurred due to buckling.

  On the other hand, no Wiggling due to buckling occurred in the sample having a length L of 440 nm. Since the pattern length is 440 nm, the dependency of the minimum value of the buckling coefficient k and the buckling factor γ on the etching depth h in this case is the same as in FIG. Therefore, no buckling occurs because the value of the buckling factor γ is always smaller than the minimum value of the buckling coefficient k in the etching depth range of 0 to 2 μm.

  As described above, for a laminated film having a residual stress of about several percent of the Young's modulus E, Wiggling due to buckling may occur when the aspect ratio is large (for example, 10 or more). As a countermeasure for this, it is effective to shorten the length L of the line pattern of the mask, and the value needs to be at least 1.65 times the thickness h of the material to be etched. That is, by forming a mask pattern having a length of 1.65 times or less of the length of the bottom surface of the multilayer film on the top of the multilayer film and performing etching using this as a mask, Wiggling generated in the multilayer film can be suppressed. . FIG. 16 is a perspective view showing the control gate group of this embodiment in which the aspect ratio is defined as described above. The 3D-NAND described in this embodiment has a structure in which a plurality of control gate groups shown in FIG. 16 are formed in a memory cell and the occurrence of Wiggling is suppressed.

  Further, in this embodiment, a comparative experiment is performed under the condition that the thickness and the number of stacked layers of the control gate layers 30 constituting the control gate group 31 are made constant and the length of the lowermost layer (ie, L) is adjusted. However, it goes without saying that the same result can be obtained even if a comparative experiment is performed with L being constant and the height of the control gate group 31 (that is, changing the film thickness or the number of layers of the control gate layer 30).

  Further, in consideration of the middle of etching, it is desirable that the length L of the line pattern is 1.65 times or less of the etching depth at which the aspect ratio (h / w) is 10. In this case, h / w = 10, and L <16.5w, that is, less than 16.5 times the pattern width w is desirable from the relationship of L <1.65h.

  Further, when the length L of the line pattern is 16.5 times or less of the pattern width w, the number of channel holes 4 connected to one gate electrode 5 may be smaller than a desired number. For example, as shown in FIG. 17, the number of channel holes 4 connected to one gate electrode 5 can be increased by increasing the pattern width w of the laminated film and arranging a plurality of channel holes.

  As described above, in this embodiment, the method of suppressing the occurrence of Wiggling by setting the etching depth or the length of the bottom surface of the laminated film within a predetermined range and setting the aspect ratio to a value that hardly causes buckling has been described. Since the residual stress of the laminated film is particularly large in a film formed by CVD, the method of this embodiment is particularly effective for a laminated film formed by CVD, but a single-layer film or other film forming method (for example, It is also effective for a film formed by a sputtering method or the like. In addition, a laminated film that operates as an active element such as a control gate group is often formed by laminating a conductive film and an insulating film, and such a laminated film is often formed by CVD. Therefore, it can be said that the Wiggling suppression method of this embodiment is particularly effective for etching a laminated film for constituting a plurality of active elements.

(Example 3)
In this embodiment, another wiggling mechanism, ie, a swell amplification phenomenon and a principle of suppressing swell amplification will be described. A mask formed by lithography has a defect called line-edge-roughness (LER), and the mask of a line pattern has a feature of waviness about several nm. A phenomenon in which large Wiggling occurs due to this swell is a swell amplification phenomenon. For example, it is assumed that there is a line pattern 7 that swells to the left and right in a sinusoidal shape with a period λ as shown in FIG. FIG. 18B shows a cross-sectional view along AA ′ of FIG.
In this state, it is independent without falling down. Now, assuming that the amplitude of a sine wave representing undulation is virtually a ₀ , the position coordinates of this pattern are expressed by the following equations.

  When the material constituting this pattern has a residual stress σ, a force F that deforms the pattern in the x direction is generated. The value of this force F is expressed by the following equation.

That is, a force F is generated to deform the pattern in the direction of amplifying the swell. Therefore, when there is a residual stress σ in the pattern of FIG. 18, the pattern is deformed in the direction of amplifying the undulation as shown in FIG. 19A and falls down as shown in FIG. When the amplitude of waviness after deformation to a _1, the relationship of the amplitude a ₀ and a ₁ in front of the swell deformation is expressed by the following equation.

  The amplification factor A is greater than 1 even if the buckling factor γ and the buckling coefficient k satisfy the condition that buckling does not occur. That is, the waviness amplification phenomenon can occur under weak stress and low aspect ratio conditions where buckling does not occur.

  As shown in FIG. 20, the gain A increases when the aspect ratio and residual stress are high and the value of γ increases or when the initial waviness period is close to λ / h and the value of k decreases.

In order to suppress this swell amplification phenomenon, there is no choice but to reduce the initial swell amplitude a ₀ by reducing the LER or by reducing the aspect ratio and residual stress to reduce λ. However, both are practically difficult.

  Therefore, we examined a structure that does not affect device characteristics even if swell amplification occurs. When the swell amplification phenomenon occurs, the force F is applied to the portion where the second derivative of the swell is large as described above, resulting in a large deformation. On the contrary, almost no force F is generated in the portion where the second derivative of the undulation is zero, and no deformation occurs.

  Therefore, as a countermeasure, for example, as shown in FIG. 21A, adjacent patterns [7] are waved in a sinusoidal shape with the same period and phase, and the position where the second derivative of the wave is 0, A method of forming a channel hole 4 that affects the device performance at the position of the inflection point of the swell can be considered. In this case, even if swell amplification occurs, the formation location of the channel hole 4 is hardly deformed as shown in FIG. 22A. Therefore, the characteristics are deteriorated by stress, or the position of the channel hole 4 is changed. However, there is no problem that the contact hole cannot be connected with the design value. FIG. 22B shows a cross-sectional view taken along the line AA ′ of FIG. 22A, and it can be seen that the inside of the channel hole 4 is not particularly deformed. In addition, although the amount of deformation is large in the portion where the second order differential is large, the adjacent patterns 7 are deformed in the same direction, so that they do not come into contact and are electrically short-circuited.

Example 4
In this embodiment, the method described in the third embodiment is applied to a 3D-NAND manufacturing process, and a 3D-NAND having a structure that does not affect device characteristics even when swell amplification occurs is described. To do.

In this example, a 3D-NAND memory cell having the structure for suppressing swell amplification described in Example 3 and a 3D-NAND memory cell not provided were prepared for comparison. A 3D-NAND memory cell that does not have a swell amplification suppression structure was produced by the same process as in Example 2, and the pattern length L was 440 nm in order to suppress buckling. As a difference in manufacturing process from Example 2, in the memory cell of this example, the resist mask 11 was formed not by the nanoimprint of Example 2 (see the description of FIG. 10) but by a normal lithography technique. It is known that the resist mask 11 formed by ordinary lithography has irregular undulations with a period of 880 nm and an amplitude of about 1 nm due to LER. Similar to the second embodiment, SiON and aC are sequentially etched along the resist mask 11, and finally, the laminated film of the Si ₃ N ₄ film 2 and the SiO ₂ film 3 is etched consistently.

  As a result, in the aC etching process (see the description of FIG. 13), irregular wiggling occurred due to waviness amplification.

  FIG. 23 shows the relationship between the amplitude of waviness and the etching depth of aC. The amplitude of the undulation gradually increases with the progress of etching (etching depth), and when the 1.0 μm etching is completed, the undulation with an amplitude of 4.7 nm occurs. That is, LER having an amplitude of 4.7 nm is generated in the a-C mask. Furthermore, as a result of performing the etching of the laminated film described with reference to FIG. 13 using this aC mask, Wiggling further increases, and adjacent patterns are partially joined as shown in FIG. Oops. Further, at the junction, as shown in FIG. 24B, the etching of the laminated film stopped halfway.

  FIG. 25 shows the relationship between the amplitude of waviness during etching of the laminated film and the etching depth. The amplitude of the undulation gradually increases as the etching progresses (depth), and when the etching is performed to 2.0 μm, which is equal to the film thickness of the laminated film, there is a undulation having an amplitude of 27 nm and an amplitude of 5.7 times the undulation generated in the aC mask It has occurred. For this reason, it is considered that the adjacent patterns are partially joined.

  Further, it was found that a connection failure occurred in the process of connecting the contact hole 6 serving as a wiring on the channel hole 4. FIG. 26 shows an outline of a poor connection portion. FIG. 26 (A) is a top view of a control gate group in which a connection failure has occurred, and it can be seen that the contact hole 6 is partially off the center of the channel hole 4 where it is originally formed. FIG. 26B is a cross-sectional view taken along the line A-A ′ of FIG. 26A, and it can be seen that a connection failure between the contact hole 6 and the channel hole 4 occurs at the defective portion 61. This is because the channel hole 4 is formed so as to be significantly deviated from the original design position due to an increase in Wiggling.

  Next, a manufacturing process and a device structure of a 3D-NAND memory cell having a swell amplification suppression structure will be described.

First, a control gate layer composed of a laminated film of the Si ₃ N ₄ film 2 and the SiO ₂ film 3 is formed and etched on the Si substrate in order to form the structure shown in FIG. The length L of the laminated film bottom surface and the height h of the laminated film are set to values that do not cause buckling. Next, a resist mask pattern 11 is formed on the aC film. At this time, a sine wave pattern is formed instead of the line and space pattern described in the second embodiment. In this embodiment, the period of the sine wave is set to 200 nm, which is twice the pitch of the channel hole 4, and the amplitude is set to 50 nm. The position of the channel hole 4 is a position corresponding to the second derivative of the sine wave. The phase was adjusted so that the position of the music point). FIG. 27A shows a top view of the sinusoidal resist pattern formed in this embodiment, and FIG. 27B shows a cross-sectional view along AA ′ of FIG.

  When the aC film was etched using the formed resist mask 11, the amplitude slightly increased, but almost no mask displacement occurred at the position where the second derivative of undulation was 0, that is, the position of the channel hole 4. I did not.

  FIG. 28 shows the relationship between the amplitude and the a-C etching depth in the waviness with a period of 200 nm.

  The amplitude of the undulation increases from the initial value of 50 nm given as the amplitude of the sine wave to the value of 53 nm at the etching depth of 100 nm as the etching progresses, but hardly increases thereafter. Moreover, the swell of the 880 nm period resulting from LER was hardly amplified. This is presumably because the long period waviness due to LER was not amplified because the stress was relaxed by increasing the amplitude of the short period (200 nm in this embodiment) waviness at the beginning of etching.

  Using the a-C mask formed in the above manner, the terrace-shaped laminated film shown in FIG. 12 was etched. As a result, the swell increased slightly, but the adjacent patterns were deformed in the same direction as shown in FIG. 29, so that the joining of the patterns was suppressed. Further, as in the case of the a-C etching, almost no deformation of the pattern was observed at the position where the second derivative of the undulation was 0, that is, the position of the channel hole.

  FIG. 30 shows the relationship between the amplitude of waviness and the etching depth when the terrace-shaped laminated film is etched. For waviness with a period of 200 nm, the amplitude of waviness increased from the initial value of 53 nm (aC mask waviness amplitude) to 56 nm (value at an etching depth of 100 nm) with the progress of etching, but has hardly changed since then. . Also, the swell of 880 nm period due to LER was hardly amplified. Further, since there is no position shift of the channel hole 4, no connection failure of the contact hole 6 to the channel hole 4 was observed at all.

  As mentioned above, if the pattern is sine waved from the beginning and the channel hole is formed at a position where the second derivative of the undulation becomes zero, the channel hole part will not be deformed, so the problem caused by Wiggling is avoided. can do. Also, if the adjacent patterns are in the same phase, the adjacent patterns will not come into contact with each other even if the fall of Wiggling increases.

  Further, the shape of the resist mask is not necessarily limited to a sine wave shape, and any shape may be adopted as long as the waveform is such that the second derivative is zero. For example, as shown in FIG. 31, the same effect can be obtained by wobbling the resist mask 11 in a zigzag manner and adjusting the phase so that the formation position of the channel hole 4 coincides with the position where the second derivative of the waviness becomes zero.

  FIG. 32 shows an example of a reticle for forming the zigzag pattern shown in FIG. 31 by lithography. FIG. 32 shows an exposure reticle in which a zigzag Ti mask 13 is formed on the reticle substrate 12. Even with such a zigzag pattern, fluctuations in the channel hole position due to Wiggling can be suppressed. If the amplitude of the undulation is close to the minimum exposure dimension, a resist mask having a sine wave shape can be naturally formed by exposing the zigzag pattern.

(Example 5)
The present embodiment is a semiconductor device having the following configuration.
1) In a semiconductor device including semiconductor elements that operate as active elements and have semiconductor element blocks separated from each other by grooves, the ratio of the maximum length in the longitudinal direction of the semiconductor element blocks divided by the height is A semiconductor device characterized in that it is defined within a range where it does not occur.
2) A plurality of control gate groups in which a plurality of contact gate layers are stacked and separated from each other by a groove, channel holes formed in the control gate groups, and bits connected to the control gate groups via electrodes In a semiconductor device comprising a line and a word line connected to the contact gate layer via a contact plug, the plurality of control gate groups have a shape wavy in the same phase, and the channel hole has a shape of the waviness A semiconductor device characterized in that the semiconductor device is formed at an inflection point position.

  1 ... Si substrate, 2 ... Si3N4, 3 ... SiO2, 4 ... channel hole, 5 ... tungsten gate electrode, 6 ... contact hole, 7 ... pattern, 8 ... SiO2, 9 ... amorphous carbon, 10 ... SiON, 11 ... resist mask , 12 ... reticle substrate, 13 ... TiN mask

Claims (11)

In a method for manufacturing a semiconductor device including a process of forming a three-dimensional memory cell,
The step of forming the three-dimensional memory cell includes a step of forming a channel hole in a plurality of stacked control gate layers constituted by a stacked film of an insulating layer and a conductor layer, and a plurality of stacked control gate layers by plasma etching. Forming a plurality of control gate layers by forming grooves in the plurality of stacked control gate layers,
The length in the longitudinal direction of the control gate group and the height of the control gate group are values obtained by dividing a buckling period, which is a value obtained by dividing a value that doubles the length by a natural number, by the height. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is defined to be smaller than 3. In a method for manufacturing a semiconductor device including a process of forming a three-dimensional memory cell,
The step of forming the three-dimensional memory cell includes a step of forming a channel hole in a plurality of stacked control gate layers constituted by a stacked film of an insulating layer and a conductor layer, and a plurality of stacked control gate layers by plasma etching. Forming a plurality of control gate layers by forming grooves in the plurality of stacked control gate layers,
The length in the longitudinal direction of the control gate group and the height of the control gate group are defined such that a value obtained by dividing the length by the height is less than 1.65. Manufacturing method. In the manufacturing method of the semiconductor device according to claim 2 ,
The method of manufacturing a semiconductor device the ratio of the length to the separated width is the length of said control gate group is characterized der Rukoto less than 16.5. In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device which is characterized that you said the channel hole plurality of rows formed inside the control gate group. In the manufacturing method of the semiconductor device according to any one of claims 1 to 4 ,
Forming the control gate group in a stepped shape such that the length of the upper control gate layer is shorter than the length of the lower control gate layer;
The length of the control gate group in the longitudinal direction is the length of the lowermost control gate layer of the stepped shape,
A method of manufacturing a semiconductor device, wherein the height is the height of the entire stepped shape . In the manufacturing method of the semiconductor device according to claim 1 ,
The method of manufacturing a semiconductor device obtained by dividing the length in the height, characterized in der Rukoto less than 1.65. In the manufacturing method of the semiconductor device according to claim 2 ,
The step of forming a plurality of control gate groups includes a step of forming a line and space pattern on the plurality of stacked control gate layers and the plurality of stacked control gate layers as a mask using the line and space pattern as a mask. Etching step,
The method of manufacturing a semiconductor device, wherein the line and space pattern has a shape in which individual patterns are wavy in the same phase, and the channel hole is located at an inflection point position of the waviness . A plurality of control gate groups in which a plurality of control gate layers are stacked and separated from each other by a groove; a channel hole formed in the control gate group; and a bit line connected to the control gate group via an electrode; In a semiconductor device comprising a word line connected to the control gate layer via a contact plug ,
The semiconductor device in the longitudinal direction of the value obtained by dividing the height of the length said control gate group is characterized that you have defined the said length and said height to be less than 1.65 of said control gate group. The semiconductor device according to claim 8 ,
The semiconductor device the ratio of the length to the separated width is the length of said control gate group is characterized der Rukoto less than 16.5. The semiconductor device according to claim 9.
The semiconductor device the channel hole is characterized that you have a plurality of rows formed inside the control gate group. The semiconductor device according to any one of claims 8 to 10 ,
Forming the control gate group in a stepped shape such that the length of the upper control gate layer is shorter than the length of the lower control gate layer;
The length of the control gate group in the longitudinal direction is the length of the lowermost control gate layer of the stepped shape,
Wherein a height and be Rukoto of the entire stepped shape the height.

Images