JP6321215B2 - 三次元集積回路の製造方法、および方法 - Google Patents
三次元集積回路の製造方法、および方法 Download PDFInfo
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- JP6321215B2 JP6321215B2 JP2016567258A JP2016567258A JP6321215B2 JP 6321215 B2 JP6321215 B2 JP 6321215B2 JP 2016567258 A JP2016567258 A JP 2016567258A JP 2016567258 A JP2016567258 A JP 2016567258A JP 6321215 B2 JP6321215 B2 JP 6321215B2
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Description
[実施例]
本実施形態の例を下記の各項目として示す。
[項目1]
複数の第1の相互接続と複数の第2の相互接続との間に配置される集積回路デバイスレイヤを含む第1の基板を形成する段階と、
メモリデバイスレイヤが前記複数の第1の相互接続および前記複数の第2の相互接続のうちの一方に並置されるように、前記メモリデバイスレイヤを含む第2の基板を前記第1の基板に連結する段階と、
前記第1の基板の一部を除去する段階と、を備える方法。
[項目2]
複数の第1の相互接続と複数の第2の相互接続との間に配置される集積回路デバイスレイヤを含む第1の基板を形成する前記段階は、
前記第1の基板に第1のデバイスレイヤを形成する段階と、
前記第1の基板に複数の第1の相互接続を形成する段階であって、前記複数の第1の相互接続の各々は複数の第1のデバイスの各々に連結される、形成する段階と、
複数の第2のデバイスを含まないデバイスレイヤおよび複数の第2のデバイスを含むデバイスレイヤのうちの一方を前記複数の第1の相互接続の各々に連結する段階であって、前記複数の第2のデバイスを含まないデバイスレイヤが連結される場合、前記方法は複数の第2のデバイスを形成する段階を備える、連結する段階と、
第2のデバイスレイヤに複数の第2の相互接続を形成する段階であって、前記複数の第2の相互接続の各々は前記複数の第2のデバイスの各々に連結される、形成する段階と、を含む、項目1に記載の方法。
[項目3]
前記方法は、前記第1の基板の一部を除去する前記段階の後に、
前記複数の第1の相互接続の各々への複数のコンタクトポイントを形成する段階を備え、前記複数のコンタクトポイントは外部電源への接続のために使用可能である、項目2に記載の方法。
[項目4]
前記複数の第1の相互接続の各々の寸法は、前記複数の第2の相互接続の各々の寸法より大きい、項目2に記載の方法。
[項目5]
前記複数の第1のデバイスは、前記複数の第2のデバイスより高い電圧範囲を有する複数のデバイスを含む、項目2に記載の方法。
[項目6]
前記複数の第2のデバイスは、前記複数の第1のデバイスのピッチより細かいピッチで配置される複数のデバイスを含む、項目2に記載の方法。
[項目7]
複数の第2の相互接続を形成する前記段階は、前記複数の第2の相互接続および前記複数の第2の相互接続に埋め込まれた複数のメモリデバイスを含む相互接続スタックを形成する段階を含む、項目1または2に記載の方法。
[項目8]
前記メモリデバイスレイヤは複数のDRAMデバイスを含む、項目1または2に記載の方法。
[項目9]
項目1から8のいずれか一項に記載の前記方法により形成される三次元集積回路デバイス。
[項目10]
基板上の複数の第1の相互接続と複数の第2の相互接続との間に配置される複数の第1の回路デバイスを含むデバイスレイヤであって、前記複数の第1の相互接続の各々および前記複数の第2の相互接続の各々が前記複数の第1の回路デバイスの各々に連結される、デバイスレイヤと、
前記複数の第1の相互接続および前記複数の第2の相互接続のうちの一方に並置され、および連結される複数のメモリデバイスを含むメモリデバイスレイヤと、
前記複数の第1の相互接続の各々および前記複数の第2の相互接続の各々のうちの一方に連結される複数のコンタクトポイントであって、前記複数のコンタクトポイントは外部電源への接続のために使用可能である、複数のコンタクトポイントと、を備える、装置。
[項目11]
前記デバイスレイヤは第1のデバイスレイヤを含み、前記メモリデバイスは前記複数の第1の相互接続および前記複数の第2の相互接続の一方に並置され、および連結され、前記装置は、
前記複数の第1の相互接続および前記複数の第2の相互接続の他方に並置され、および連結される複数の第2の回路デバイスを含む第2のデバイスレイヤをさらに備える、項目10に記載の装置。
[項目12]
複数の第1のデバイスおよび複数の第2のデバイスのうちの一方は、前記複数の第1のデバイスおよび前記複数の第2のデバイスのうちの他方より高い電圧範囲を有する複数のデバイスを含む、項目10または11に記載の装置。
[項目13]
前記第1のデバイスレイヤの前記複数の第1の回路デバイスは、前記複数の第2の回路デバイスのピッチより細かいピッチで配置される複数のデバイスを含み、前記複数の第1の相互接続はキャリア基板と前記第1のデバイスレイヤとの間に配置される、項目11に記載の装置。
[項目14]
前記複数のコンタクトポイントは、前記複数の第2の相互接続に各々に連結される、項目12に記載の装置。
[項目15]
複数のメモリデバイスは、前記複数の第1の相互接続および前記複数の第2の相互接続のうちの一方の中に配置される、項目10または11に記載の装置。
[項目16]
前記複数のコンタクトポイントは複数の回路コンタクトポイントを含み、前記装置は前記複数の回路コンタクトポイントに連結される複数のパッケージコンタクトポイントを含むパッケージをさらに備える、項目12に記載の装置。
[項目17]
第1の基板に複数の第1のデバイスを含む第1のデバイスレイヤを形成する段階と、
複数の第1の相互接続を形成する段階であって、前記複数の第1の相互接続の各々は前記複数の第1のデバイスの各々に連結される、形成する段階と、
前記複数の第1の相互接続に並置される、複数の第2のデバイスを含む第2のデバイスレイヤを形成する段階と、
前記第2のデバイスレイヤに並置される複数の第2の相互接続を形成する段階と、
メモリデバイスレイヤが前記複数の第2の相互接続に並置されるように、前記メモリデバイスレイヤを含む第2の基板を前記第1の基板に連結する段階と、
前記第1のデバイスレイヤを保持しつつ、前記第1の基板の一部を除去する段階と、を備える、方法。
[項目18]
前記複数の第1の相互接続への複数のコンタクトポイントを形成する段階をさらに備え、前記複数のコンタクトポイントは外部電源への接続のために使用可能である、項目17に記載の方法。
[項目19]
前記複数の第1のデバイスは、前記複数の第2のデバイスより高い電圧範囲を有する複数のデバイスを含む、項目17または18に記載の方法。
[項目20]
前記複数の第2のデバイスは、前記複数の第1のデバイスのピッチより細かいピッチで配置される複数のデバイスを含む、項目17から19のいずれか一項に記載の方法。
[項目21]
複数の第2の相互接続を形成する前記段階は、前記複数の第2の相互接続および前記複数の第2の相互接続に埋め込まれた複数のメモリデバイスを含む相互接続スタックを形成する段階を含む、項目17から19のいずれか一項に記載の方法。
[項目22]
項目17から21のいずれか一項に記載の前記方法により作成される、三次元集積回路。
Claims (22)
- 複数の第1の相互接続と複数の第2の相互接続との間に配置される集積回路デバイスレイヤを含む第1の基板を形成する段階と、
メモリデバイスレイヤが前記複数の第1の相互接続および前記複数の第2の相互接続のうちの一方に並置されるように、前記メモリデバイスレイヤを含む第2の基板を前記第1の基板に連結する段階と、
前記第1の基板の一部を除去する段階と、を備える方法。 - 複数の第1の相互接続と複数の第2の相互接続との間に配置される集積回路デバイスレイヤを含む第1の基板を形成する前記段階は、
前記第1の基板に、第1のデバイスを含む第1のデバイスレイヤを形成する段階と、
前記第1の基板に複数の第1の相互接続を形成する段階であって、前記複数の第1の相互接続の各々は複数の前記第1のデバイスの各々に連結される、形成する段階と、
前記集積回路デバイスレイヤを前記複数の第1の相互接続の各々に連結する段階と、
前記集積回路デバイスレイヤに複数の第2の相互接続を形成する段階であって、前記複数の第2の相互接続の各々は前記集積回路デバイスレイヤの複数の第2のデバイスの各々に連結される、形成する段階と、を含む、請求項1に記載の方法。 - 前記方法は、前記第1の基板の一部を除去する前記段階の後に、
前記複数の第1の相互接続の各々への複数のコンタクトポイントを形成する段階を備え、前記複数のコンタクトポイントは外部電源への接続のために使用可能である、請求項2に記載の方法。 - 前記複数の第1の相互接続の各々の寸法は、前記複数の第2の相互接続の各々の寸法より大きい、請求項2に記載の方法。
- 前記複数の第1のデバイスは、前記複数の第2のデバイスより高い電圧範囲を有する複数のデバイスを含む、請求項2に記載の方法。
- 前記複数の第2のデバイスは、前記複数の第1のデバイスのピッチより細かいピッチで配置される複数のデバイスを含む、請求項2に記載の方法。
- 複数の第2の相互接続を形成する前記段階は、前記複数の第2の相互接続および前記複数の第2の相互接続に埋め込まれた複数のメモリデバイスを含む相互接続スタックを形成する段階を含む、請求項1または2に記載の方法。
- 前記メモリデバイスレイヤは複数のDRAMデバイスを含む、請求項1または2に記載の方法。
- 請求項1から8のいずれか一項に記載の前記方法により三次元集積回路デバイスを製造する方法。
- 基板上の複数の第1の相互接続と複数の第2の相互接続との間に配置される複数の第1の回路デバイスを含むデバイスレイヤであって、前記複数の第1の相互接続の各々および前記複数の第2の相互接続の各々が前記複数の第1の回路デバイスの各々に連結される、デバイスレイヤと、
前記複数の第1の相互接続および前記複数の第2の相互接続のうちの一方に並置され、および連結される複数のメモリデバイスを含むメモリデバイスレイヤと、
前記複数の第1の相互接続および前記複数の第2の相互接続のうちの他方に連結される複数のコンタクトポイントであって、前記複数のコンタクトポイントは外部電源への接続のために使用可能である、複数のコンタクトポイントと、を備える、装置。 - 前記デバイスレイヤは第1のデバイスレイヤを含み、前記メモリデバイスは前記複数の第1の相互接続および前記複数の第2の相互接続の一方に並置され、および連結され、前記装置は、
前記複数の第1の相互接続および前記複数の第2の相互接続の他方に並置され、および連結される複数の第2の回路デバイスを含む第2のデバイスレイヤをさらに備える、請求項10に記載の装置。 - 複数の第1のデバイスおよび複数の第2のデバイスのうちの一方は、前記複数の第1のデバイスおよび前記複数の第2のデバイスのうちの他方より高い電圧範囲を有する複数のデバイスを含む、請求項10または11に記載の装置。
- 前記第1のデバイスレイヤの前記複数の第1の回路デバイスは、前記複数の第2の回路デバイスのピッチより細かいピッチで配置される複数のデバイスを含み、前記複数の第1の相互接続はキャリア基板と前記第1のデバイスレイヤとの間に配置される、請求項11に記載の装置。
- 前記複数のコンタクトポイントは、前記複数の第2の相互接続に各々に連結される、請求項12に記載の装置。
- 複数のメモリデバイスは、前記複数の第1の相互接続および前記複数の第2の相互接続のうちの一方の中に配置される、請求項10または11に記載の装置。
- 前記複数のコンタクトポイントは複数の回路コンタクトポイントを含み、前記装置は前記複数の回路コンタクトポイントに連結される複数のパッケージコンタクトポイントを含むパッケージをさらに備える、請求項12に記載の装置。
- 第1の基板に複数の第1のデバイスを含む第1のデバイスレイヤを形成する段階と、
複数の第1の相互接続を形成する段階であって、前記複数の第1の相互接続の各々は前記複数の第1のデバイスの各々に連結される、形成する段階と、
前記複数の第1の相互接続に並置される、複数の第2のデバイスを含む第2のデバイスレイヤを形成する段階と、
前記第2のデバイスレイヤに並置される複数の第2の相互接続を形成する段階と、
メモリデバイスレイヤが前記複数の第2の相互接続に並置されるように、前記メモリデバイスレイヤを含む第2の基板を前記第1の基板に連結する段階と、
前記第1のデバイスレイヤを保持しつつ、前記第1の基板の一部を除去する段階と、を備える、方法。 - 前記複数の第1の相互接続への複数のコンタクトポイントを形成する段階をさらに備え、前記複数のコンタクトポイントは外部電源への接続のために使用可能である、請求項17に記載の方法。
- 前記複数の第1のデバイスは、前記複数の第2のデバイスより高い電圧範囲を有する複数のデバイスを含む、請求項17または18に記載の方法。
- 前記複数の第2のデバイスは、前記複数の第1のデバイスのピッチより細かいピッチで配置される複数のデバイスを含む、請求項17から19のいずれか一項に記載の方法。
- 複数の第2の相互接続を形成する前記段階は、前記複数の第2の相互接続および前記複数の第2の相互接続に埋め込まれた複数のメモリデバイスを含む相互接続スタックを形成する段階を含む、請求項17から19のいずれか一項に記載の方法。
- 請求項17から21のいずれか一項に記載の前記方法により、三次元集積回路を製造する方法。
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