JP6312195B2 - Integrated circuit device, integrated circuit, display device, and driver IC - Google Patents

Description

  The present invention relates to an integrated circuit device, an integrated circuit, a display device, and a driver IC, and more particularly to an integrated circuit device including a plurality of integrated circuits each including a power supply circuit.

  In an integrated circuit device having a plurality of integrated circuits, when a difference in power supply voltage level between the plurality of integrated circuits becomes a problem, the outputs of the power supply circuits mounted on the plurality of integrated circuits are connected to a common power supply line. Sometimes. A power supply voltage generated on the common power supply line is used in the plurality of integrated circuits. For example, when a display panel (for example, a liquid crystal display panel) is driven by a plurality of driver ICs (integrated circuits), if the voltage level of the boosted power supply voltage generated by the boosted power supply of the driver IC is different, different drivers of the display panel There may be a phenomenon that a difference occurs in an image displayed in a portion driven by an IC. For this reason, the output of the booster power supply of the driver IC is connected to a common power supply line, and a boosted power supply voltage is generated on the common power supply line. The boosted power supply voltage is supplied to a plurality of driver ICs and used for driving the display panel.

  One problem is that when the outputs of power supply circuits integrated in a plurality of integrated circuits are electrically connected to each other, the power supply voltage generated on a common power supply line depends on the configuration and operation of the power supply circuit. It is a point that the abnormality of the power supply circuit of each integrated circuit may not be detected only by monitoring. In the case where the power supply circuits of a plurality of integrated circuits have high capabilities, even if the power supply circuit of one integrated circuit is stopped, there is a case where the power supply voltage of the common power supply line is small. In such a case, considering the influence of noise, it is difficult to detect an abnormality even if a common power line is monitored. On the other hand, in order to ensure the reliability and safety of operation, if an abnormality occurs in the operation of at least one power supply circuit among a plurality of integrated circuits, the abnormality can be appropriately dealt with. desired.

  Accordingly, an object of the present invention is when an abnormality occurs in the operation of at least one power supply circuit in an integrated circuit device configured such that outputs of power supply circuits integrated in a plurality of integrated circuits are electrically connected to each other. Another object is to provide a technique for appropriately dealing with the abnormality.

  In one aspect of the present invention, an integrated circuit device includes a plurality of integrated circuits and a power supply line. The plurality of integrated circuits include a first integrated circuit including a first power supply circuit and a second integrated circuit including a second power supply circuit. The power supply line electrically connects the output of the first power supply circuit and the output of the second power supply circuit. The first power supply circuit includes a first abnormality detection circuit that detects occurrence of abnormality in the first power supply circuit, and the second power supply circuit includes a second abnormality detection circuit that detects occurrence of abnormality in the second power supply circuit. I have. When the first abnormality detection circuit detects the occurrence of an abnormality in the first power supply circuit, the first integrated circuit starts an abnormality stop sequence for stopping the operation of the first integrated circuit and detects the occurrence of an abnormality in the first power supply circuit. A first notification to be notified is sent to the second integrated circuit, and the second integrated circuit starts an abnormal stop sequence for stopping the operation of the second integrated circuit in response to the first notification from the first integrated circuit. On the other hand, when the second abnormality detection circuit detects the occurrence of the abnormality of the second power supply circuit, the second integrated circuit starts an abnormality stop sequence for stopping the operation of the second integrated circuit and detects the abnormality of the second power supply circuit. In response to the second notification from the second integrated circuit, the first integrated circuit starts an abnormal stop sequence for stopping the operation of the first integrated circuit. .

  In another aspect of the present invention, an integrated circuit includes a power supply circuit connected to a power supply line whose output is connected to an output of another integrated circuit, a control circuit, and an interface. The power supply circuit includes an abnormality detection circuit that detects occurrence of an abnormality in the power supply circuit. When the abnormality detection circuit detects the occurrence of an abnormality in the power supply circuit, the control circuit starts an abnormality stop sequence for stopping the operation of the integrated circuit, and the interface performs a first notification for notifying the occurrence of the abnormality in the power supply circuit. To the integrated circuit. When the second notification for notifying the occurrence of the abnormality of the power supply circuit of the other integrated circuit is received by the interface from the other integrated circuit, the control circuit starts an abnormality stop sequence for stopping the operation of the integrated circuit.

  In still another aspect of the present invention, a display device includes a display panel, a plurality of driver ICs, and a power supply line. The plurality of driver ICs include a first driver IC that drives a data line provided in the first portion of the display panel and a second driver IC that drives a data line provided in the second portion of the display panel. A first driver IC among the plurality of driver ICs drives a first power supply circuit and a data line provided in the first portion of the display panel in response to first image data corresponding to the first portion of the display panel. And a first drive circuit. The second driver IC of the plurality of driver ICs drives the data line provided in the second portion of the display panel in response to the second power supply circuit and the second image data corresponding to the second portion of the display panel. And a second drive circuit. The power supply line electrically connects the output of the first power supply circuit and the output of the second power supply circuit. The first power supply circuit includes a first abnormality detection circuit that detects occurrence of abnormality in the first power supply circuit, and the second power supply circuit includes a second abnormality detection circuit that detects occurrence of abnormality in the second power supply circuit. I have. When the first abnormality detection circuit detects the occurrence of an abnormality in the first power supply circuit, the first driver IC starts an abnormality stop sequence for stopping the operation of the first driver IC and notifies the occurrence of the abnormality in the first power supply circuit. In response to the first notification from the first driver IC, the second driver IC starts an abnormal stop sequence for stopping the operation of the second driver IC. When the second abnormality detection circuit detects the occurrence of an abnormality in the second power supply circuit, the second driver IC starts an abnormality stop sequence for stopping the operation of the second driver IC and detects the occurrence of an abnormality in the second power supply circuit. A second notification to be notified is sent to the first driver IC, and the first driver IC starts an abnormal stop sequence for stopping the operation of the first driver IC in response to the second notification from the second driver IC.

  According to the present invention, in an integrated circuit device having a configuration in which outputs of power supply circuits integrated in a plurality of integrated circuits are electrically connected to each other, when an abnormality occurs in the operation of at least one power supply circuit, A technique for appropriately responding to the abnormality is provided.

1 is a block diagram showing a configuration of a liquid crystal display device in a first embodiment of an integrated circuit device according to the present invention. It is a block diagram which shows the structure of the driver IC in 1st Embodiment. FIG. 2 is a circuit diagram illustrating a configuration of a liquid crystal driving power generation circuit in the first embodiment. 3 is a timing chart illustrating an operation of a driver IC (master driver) in the first embodiment. 3 is a timing chart illustrating an operation of a driver IC (slave driver) in the first embodiment. 3 is a timing chart illustrating an operation of a driver IC (master driver) in the first embodiment. 3 is a timing chart illustrating an operation of a driver IC (slave driver) in the first embodiment. 3 is a timing chart illustrating an operation of a driver IC (master driver) in the first embodiment. 3 is a timing chart illustrating an operation of a driver IC (slave driver) in the first embodiment. It is a block diagram which shows the modification of a structure of the liquid crystal display device in 1st Embodiment. It is a block diagram which shows the structure of the liquid crystal display device in 2nd Embodiment of the integrated circuit device which concerns on this invention. It is a block diagram which shows the structure of the driver IC in 2nd Embodiment. It is a conceptual diagram which shows an example of operation | movement of the liquid crystal display device of 2nd Embodiment. It is a figure explaining the problem of the communication error in communication of the communication data between chips between driver ICs. It is a block diagram which shows the example of a structure of the liquid crystal drive circuit in 2nd Embodiment. Gamma curve specified by the correction point data CP0~CP5 included in the correction point data set CP _{_} sel ^k, and is a graph showing the contents of a correction operation in accordance with the comma curve (gamma correction). It is a block diagram which shows the example of a structure of the approximate calculation correction circuit in 2nd Embodiment. It is a block diagram which shows the example of a structure of the characteristic data calculating circuit in 2nd Embodiment. It is a block diagram which shows the example of a structure of the correction point data calculation circuit in 2nd Embodiment. It is a flowchart which shows operation | movement of driver IC in each frame period. It is a conceptual diagram which shows the comparison of the operation | movement when the communication of the characteristic data between driver ICs is performed normally, and the operation | movement when not performed normally. It is a flowchart which shows an example of operation | movement of the correction point data calculation circuit in 1st Embodiment. It is a flowchart which shows the other example of operation | movement of the correction point data calculation circuit in 1st Embodiment. It is a graph explaining the relationship between APL _AVE , γ, and correction point data set CP_L ^{k in} an embodiment. In another _{embodiment, APL AVE,} gamma, and is a graph illustrating the relationship between the correction point data set CP_L ^k. Correction point data set CP # q, and the shape of the gamma curve corresponding to the respective CP # (q + 1), is a graph conceptually showing a shape of a gamma curve corresponding to the correction point data set CP_L ^k. The correction point data set CP_L ^k, is a conceptual diagram showing a technical significance of modified based on the variance sigma _AVE ^2. 10 is a table conceptually showing the relationship between gradation distribution (histogram) and the content of correction calculation when correction point data CP1 and CP4 are corrected based on variance σ _AVE ² . It is a figure which shows operation | movement of driver IC in the modification of 2nd Embodiment.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the integrated circuit device according to the first embodiment of the present invention. The integrated circuit device according to this embodiment is configured as a liquid crystal display device 10 and includes an application processor 1, an LCD (liquid crystal display) panel 2, and two driver ICs 4-1 and 4-2. In the display area 3 of the LCD panel 2, gate lines (also called scanning lines and digit lines), data lines (also called signal lines and source lines), and pixels are arranged. In the present embodiment, each pixel in the display area 3 of the LCD panel 2 has three subpixels (R subpixel, G subpixel, and B subpixel). In the present embodiment, the driver ICs 4-1 and 4-2 have the same configuration (however, the operations are different as described later), and the driver ICs 4-1 and 4-2 are not distinguished from each other. May be collectively referred to as a driver IC4.

The application processor 1 is an arithmetic device that controls the driver ICs 4-1 and 4-2. In particular, the application processor 1 supplies supplies the image data _{D IN1, D IN2} respectively driver IC4-1,4-2, the control data _{D CTRL1, D CTRL2} driver IC4-1,4-2 . The image data D _IN1 is image data corresponding to a portion displayed in the first portion 5-1 of the image displayed in the display area 3 of the LCD panel 2, that is, provided in the first portion 5-1. This is data indicating the gradation of each sub-pixel of the pixel. Similarly, the image data _DIN2 is image data corresponding to the portion displayed in the second portion 5-2 of the image displayed in the display area 3 of the LCD panel 2, that is, in the second portion 5-2. This is data indicating the gradation of each sub-pixel of the provided pixel. The control data D _CTRL1 and D _CTRL2 include commands for controlling the driver ICs 4-1 and _4-2 , respectively.

The driver ICs _4-1 and _4-2 respond to the image data D _IN1 and D _IN2 and the control data D _CTRL1 and D _CTRL2 received from the application processor 1 and the gate lines arranged in the display area 3 of the LCD panel 2 and Drive the data line. Here, the driver IC 4-1 drives a data line provided in the first part 5-1 of the display area 3, and the driver IC 4-2 provides data provided in the second part 5-2 of the display area 3. Drive the line. In FIG. 1, gate line drive signals supplied from the driver ICs 4 to the gate lines are shown as reference signs GOUT1 to GOUTn, and data line drive signals supplied from the driver ICs 4 to the data lines are shown as reference signs S1 to Sm. As shown.

  In addition, the application processor 1 supplies a reset signal RESET to the driver ICs 4-1 and 4-2. The reset signal RESET is a signal that instructs the driver ICs 4-1 and 4-2 to reset.

  FIG. 2 is a block diagram showing the configuration of the driver IC 4. The driver ICs 4-1 and 4-2 have the same configuration. However, one of the driver ICs 4-1 and 4-2 operates as a master driver, and the other operates as a slave driver. Here, the master driver is a driver IC 4 that generates a common reference clock signal RCLK, a common vertical synchronization signal VSYNC, and a common horizontal synchronization signal HSYNC that are commonly used by the driver ICs 4-1 and 4-2. On the other hand, the slave driver is a driver IC 4 that operates in synchronization with the common reference clock signal RCLK, the common vertical synchronization signal VSYNC, and the common horizontal synchronization signal HSYNC generated by the master driver. In normal operation, both the master driver and the slave driver operate in synchronization with the common reference clock signal RCLK, common vertical synchronization signal VSYNC, and common horizontal synchronization signal HSYNC generated by the master driver. In the following description, it is assumed that the driver IC 4-1 is a master driver and the driver IC 4-2 is a slave driver.

  The driver IC 4 includes an interface circuit 11, a register circuit 12, a timing generation circuit 13, a power activation sequencer 14, selectors 15a to 15c, a liquid crystal drive power generation circuit 16, a liquid crystal drive circuit 17, and a power supply abnormality / reset. A detection circuit 18, an abnormality flag flip-flop 19, and an interface 20 are provided.

The interface circuit 11 receives the image data D _IN1 or D _IN2 and transfers it to the liquid crystal drive circuit 17. In addition, the interface circuit 11 interprets the command receives the control data _{D CTRL1} or _{D CTRL2} included in the control data _{D CTRL1} or _{D CTRL2,} the register value of the register circuit 12 is set according to the command.

  The register circuit 12 includes a register group that stores register values used for controlling each circuit of the driver IC 4. The register value stored in the register circuit 12 is used to control the power supply start sequencer 14 and the liquid crystal drive power supply generation circuit 16.

  In the present embodiment, the register circuit 12 includes an abnormality detection register 12a. As will be described later, the abnormality detection register 12a is set when an abnormality of the liquid crystal drive power generation circuit 16 is detected or when an assertion of the reset signal RESET is detected (for example, data “1” as a register value). Is set). When the abnormality detection register 12a is set, under the control of the power activation sequencer 14, the driver IC 4 starts an abnormal stop sequence for stopping its operation. The function of the abnormality detection register 12a will be described in detail later.

  The timing generation circuit 13 generates an internal reference clock signal RCLK_I, an internal vertical synchronization signal VSYNC_I, and an internal horizontal synchronization signal HSYNC_I. Specifically, the timing generation circuit 13 includes an oscillation circuit 13a and a timing counter 13b. The oscillation circuit 13a generates a clock signal that is a source for generating the internal reference clock signal RCLK_I, the internal vertical synchronization signal VSYNC_I, and the internal horizontal synchronization signal HSYNC_I. The timing counter 13b generates the internal reference clock signal RCLK_I, the internal vertical synchronization signal VSYNC_I, and the internal horizontal synchronization signal HSYNC_I by counting the pulses of the clock signal supplied from the oscillation circuit 13a.

  The internal reference clock signal RCLK_I, the internal vertical synchronization signal VSYNC_I, and the internal horizontal synchronization signal HSYNC_I generated by the timing generation circuit 13 of the master driver (driver IC 4-1 in this embodiment) are both the driver ICs 4-1 and 4-2. Are used as a common reference clock signal RCLK, a common horizontal synchronization signal HSYNC, and a common vertical synchronization signal VSYNC for controlling the operation timing of the signal. Specifically, the internal reference clock signal RCLK_I generated by the timing generation circuit 13 of the driver IC 4-1 is supplied to the clock signal line 22 a via the external output terminal 21 a and used as the common reference clock signal RCLK. The clock signal line 22a is connected to the external input terminals 23a of the driver ICs 4-1 and 4-2, and the common reference clock signal RCLK generated on the clock signal line 22a is supplied to the driver IC 4 via the external input terminal 23a. -1, 4-2. Similarly, the internal vertical synchronization signal VSYNC_I and the internal horizontal synchronization signal HSYNC_I generated by the timing generation circuit 13 of the driver IC 4-1 are respectively supplied to the vertical synchronization signal line 22 b and the horizontal synchronization signal line 22 c via the external output terminals 21 b and 21 c. Are used as a common horizontal synchronization signal HSYNC and a common vertical synchronization signal VSYNC common to the driver ICs 4-1 and 4-2. The vertical synchronizing signal line 22b and the horizontal synchronizing signal line 22c are connected to the external input terminals 23b and 23c of the driver ICs 4-1 and 4-2, respectively, and are generated on the vertical synchronizing signal line 22b and the horizontal synchronizing signal line 22c. The common horizontal synchronization signal HSYNC and the common vertical synchronization signal VSYNC thus supplied are supplied to both the driver ICs 4-1 and 4-2 via the external input terminals 23b and 23c.

  Such a configuration is adopted because the skew of the common reference clock signal RCLK, the common horizontal synchronization signal HSYNC and the common vertical synchronization signal VSYNC supplied to the driver ICs 4-1 and 4-2 is reduced, and the operation timing is shifted. This is to reduce the above. For example, if the wiring length from the external output terminal 21a of the driver IC 4-1 (master driver) to the external input terminal 23a of the driver IC 4-1 is the same as the wiring length from the external input terminal 23a of the driver IC 4-2. In principle, the skew of the common reference clock signal RCLK between the driver ICs 4-1 and 4-2 can be eliminated. With respect to the common horizontal synchronization signal HSYNC and the common vertical synchronization signal VSYNC, the skew between the driver ICs 4-1 and 4-2 can be eliminated by the same method.

  The power supply start sequencer 14 is a control circuit that generates a timing control signal for controlling the operation timing of the liquid crystal drive power supply generation circuit 16 in response to the register value stored in the register circuit 42.

  The selectors 15a to 15c include an internal reference clock signal RCLK_I, an internal vertical synchronization signal VSYNC_I, an internal horizontal synchronization signal HSYNC_I, and a common reference clock signal supplied from the external input terminals 23a, 23b, and 23c. RCLK, common horizontal synchronization signal HSYNC, and common vertical synchronization signal VSYNC are selected. The reference clock signal, the vertical synchronization signal, and the horizontal synchronization signal selected by the selectors 15a to 15c are supplied to the power activation sequencer 14 and used for controlling the operation timing of the liquid crystal drive power generation circuit 16.

  The liquid crystal drive power generation circuit 16 is a circuit that generates various power supply voltages used in the driver ICs 4-1 and 4-2. The power supply voltage generated in the liquid crystal drive power generation circuit 16 includes power supply voltages GVDD and GVSS used in the liquid crystal drive circuit 47. Here, the power supply voltages GVDD and GVSS are voltages used as “High level” and “Low level”, respectively, when driving the gate lines of the LCD panel 2. The power supply voltage GVSS is a negative voltage.

  The liquid crystal drive power generation circuit 16 includes an abnormality detection circuit 16a. The abnormality detection circuit 16a monitors various voltages generated in the liquid crystal drive power generation circuit 16 and detects an abnormality in the liquid crystal drive power generation circuit 16 based on the voltages. When an abnormality is detected, the abnormality detection circuit 16a asserts an abnormality detection signal ALM.

  The liquid crystal driving circuit 17 drives data lines and gate lines arranged in the display area 3 of the LCD panel 2. Here, in the present embodiment, the liquid crystal driving circuit 17 uses the power supply voltages GVDD and GVSS for driving the gate lines. When a certain gate line is selected (that is, when a pixel connected to the gate line is driven), the gate line is pulled up to the power supply voltage GVDD. On the other hand, when a certain gate line is not selected, the gate line is pulled down to the power supply voltage GVSS.

  The abnormality flag flip-flop 19 is a flip-flop that holds an abnormality flag. The abnormality flag held by the abnormality flag flip-flop 19 is set when an abnormality of the liquid crystal drive power generation circuit 16 is detected or when an assertion of the reset signal RESET is detected. When the abnormality flag held in the abnormality flag flip-flop 19 is set, the abnormality detection register 12a is also set, and the driver IC 4 starts an operation stop sequence for stopping the operation.

  The selectors 15a to 15c respond to the abnormality flag held by the abnormality flag flip-flop 19 in response to the internal reference clock signal RCLK_I, the internal vertical synchronization signal VSYNC_I, the internal horizontal synchronization signal HSYNC_I, the external input terminal 23a, The common reference clock signal RCLK, the common horizontal synchronizing signal HSYNC and the common vertical synchronizing signal VSYNC supplied from 23b and 23c are selected. When the abnormality flag is not set, the selectors 15a to 15c select the common reference clock signal RCLK, the common horizontal synchronization signal HSYNC, and the common vertical synchronization signal VSYNC supplied from the external input terminals 23a, 23b, and 23c. On the other hand, when the abnormality flag is set, the selectors 15a to 15c select the internal reference clock signal RCLK_I, the internal vertical synchronization signal VSYNC_I, and the internal horizontal synchronization signal HSYNC_I.

  The power supply abnormality / reset detection circuit 18 monitors the abnormality detection signal ALM generated by the abnormality detection circuit 16a of the liquid crystal drive power supply generation circuit 16 and the reset signal RESET supplied from the application processor 1, and detects the abnormality detection signal ALM and the reset. When at least one of the signals RESET is asserted, the abnormality flag held in the abnormality flag flip-flop 19 is set (for example, data “1”).

  The interface 20 performs communication between the driver ICs 4-1 and 4-2. In the present embodiment, the interface 20 exchanges the information of the abnormality flag held in the abnormality flag flip-flop 19 between the driver ICs 4-1 and 4-2, in other words, the driver ICs 4-1 and 4-2. This is used to notify other driver ICs of the occurrence of an abnormality in each liquid crystal drive power supply generation circuit 16.

  The interface 20 of the driver IC 4-1 sends abnormality occurrence notification data ERR1 indicating whether or not the abnormality flag held in the abnormality flag flip-flop 19 of the driver IC 4-1 is set to the interface 20 of the driver IC 4-2. . The abnormality occurrence notification data ERR1 is used as a notification for the driver IC 4-1 to notify the driver IC 4-2 of the occurrence of an abnormality in the liquid crystal drive power generation circuit 16. When the interface 20 of the driver IC 4-2 recognizes that the abnormality flag held in the abnormality flag flip-flop 19 of the driver IC 4-1 is set from the abnormality occurrence notification data ERR1, the abnormality flag flip-flop of the driver IC 4-2. The abnormality flag held in the group 19 is set.

  Similarly, when the interface 20 of the driver IC 4-1 recognizes that the abnormality flag held in the abnormality flag flip-flop 19 of the driver IC 4-2 is set from the abnormality occurrence notification data ERR2, the driver IC 4-1 The abnormality flag held in the abnormality flag flip-flop 19 is set. The abnormality occurrence notification data ERR2 is used as a notification for the driver IC 4-2 to notify the driver IC 4-1 of the occurrence of an abnormality in the liquid crystal drive power generation circuit 16.

  With the function of the interface 20 described above, the driver ICs 4-1 and 4-2 can check the abnormality flag held in the abnormality flag flip-flop 19 of each other. As a result, the value of the abnormality flag held in the abnormality flag flip-flop 19 is matched between the driver ICs 4-1 and 4-2. As will be described later, the operation of matching the value of the abnormality flag held in the abnormality flag flip-flop 19 between the driver ICs 4-1 and 4-2 is the liquid crystal driving power supply in one of the driver ICs 4-1 and 4-2. This is for stopping the operations of both the driver ICs 4-1 and 4-2 when an abnormality of the generation circuit 16 is detected.

  Here, the driver ICs 4-1 and 4-2 may check the abnormality flag held in each abnormality flag flip-flop 19 once in each frame period. In this case, in each frame period, the abnormality occurrence notification data ERR1 is transmitted from the driver IC 4-1 to the driver IC 4-2, and the abnormality occurrence notification data ERR2 is transmitted from the driver IC 4-2 to the driver IC 4-1.

  Further, the driver ICs 4-1 and 4-2 may check the abnormality flag held in the abnormality flag flip-flops 19 once every n horizontal synchronization periods (n is a natural number) or every n lines. . In this case, once in the n horizontal synchronization period, the abnormality occurrence notification data ERR1 is transmitted from the driver IC 4-1 to the driver IC 4-2, and the abnormality occurrence notification data ERR2 is transmitted from the driver IC 4-2 to the driver IC 4-1.

  FIG. 3 is a circuit diagram showing an example of the configuration of the liquid crystal driving power generation circuit 16 integrated in each of the driver ICs 4-1 and 4-2. The liquid crystal drive power generation circuit 16 includes a booster circuit 16b, a GVDD generation circuit 16c, and a GVSS generation circuit 16d in addition to the above-described abnormality detection circuit 16a. The booster circuit 16b boosts the internal power supply voltage using the external connection capacitors 41 to 44 to generate power supply voltages VGH and VGL. Here, the power supply voltage VGL is a negative voltage.

The GVDD generation circuit 16 c includes an amplifier 31, a variable resistance element 32, a resistance element 33, and an output switch 34. The power supply terminal of the amplifier 31 is supplied with the power supply voltage VGH generated by the booster circuit 16b, and the amplifier 31 operates with the power supply voltage VGH. A reference voltage _VREF1 is supplied to one input of the amplifier 31, and a connection node between the variable resistance element 32 and the resistance element 33 is connected to the other input. Amplifier 31, a voltage of a connection node of the variable resistor element 32 and the resistance element 33 with the reference voltage _{V REF1,} outputs the power supply voltage GVDD from its output. The output switch 34 is connected between the output of the amplifier 31 and the ground terminal. The output switch 34 is set to an off state when the liquid crystal driving power generation circuit 46 is operating, and is set to an on state when the liquid crystal driving power generation circuit 46 is stopped.

  The outputs of the GVDD generation circuit 16 c of the driver ICs 4-1 and 4-2, that is, the output of the amplifier 31 are electrically connected via the GVDD line 24. A power supply capacitor 45 is connected to the GVDD line 24.

Similarly, the GVSS generation circuit 16 d includes an amplifier 35, a variable resistance element 36, a resistance element 37, and an output switch 38. The power supply voltage VGL generated by the booster circuit 16b is supplied to the power supply terminal of the amplifier 35, and the amplifier 35 operates with the power supply voltage VGL. A reference voltage _VREF2 is supplied to one input of the amplifier 35, and a connection node between the variable resistance element 36 and the resistance element 37 is connected to the other input. Amplifier 35, a voltage of a connection node of the variable resistor element 36 and the resistance element 37 with the reference voltage _{V REF2,} and outputs a power supply voltage GVSS from its output. The output switch 38 is connected between the output of the amplifier 35 and the ground terminal. The output switch 38 is set to an off state when the liquid crystal driving power generation circuit 16 is operating, and is set to an on state when the liquid crystal driving power generation circuit 16 is stopped.

  The outputs of the GVSS generation circuit 16 d of the driver ICs 4-1 and 4-2, that is, the output of the amplifier 35 are electrically connected via the GVSS line 25. A power supply capacitor 48 is connected to the GVSS line 25.

  Here, since the output of the GVDD generation circuit 16c of the driver ICs 4-1 and 4-2 (that is, the output of the amplifier 31) is electrically connected via the GVDD line 24, the voltage of the GVDD line 24 is monitored. It should be noted that it may not be possible to detect an abnormality in the liquid crystal drive power supply generation circuit 16 by itself. For example, even if an abnormality occurs in the liquid crystal drive power supply generation circuit 16 of the driver IC 4-1, if the drive capability of the amplifier 31 of the driver IC 4-2 is high, the fluctuation of the voltage on the GVDD line 24 is small. This means that no abnormality can be detected even if the GVDD line 24 is monitored. When an abnormality occurs in the liquid crystal drive power generation circuit 16 of the driver IC 4-1, it is desirable to stop both the operations of the driver ICs 4-1 and 4-2 in order to ensure operation reliability. The driver IC 4-2 that has not occurred cannot stop operating even if the GVDD line 24 is monitored.

  Similarly, since the output of the GVSS generation circuit 16d of the driver ICs 4-1 and 4-2 (that is, the output of the amplifier 35) is electrically connected via the GVSS line 25, the voltage of the GVSS line 25 is monitored. It may not be possible to detect an abnormality in the liquid crystal drive power supply generation circuit 16 simply by doing so.

  In the operation of the liquid crystal display device 10 of the present embodiment described below, a technique for dealing with such a problem is adopted. Hereinafter, an operation of the liquid crystal display device 10 according to the present embodiment, particularly, an operation when an abnormality occurs in one of the liquid crystal driving power generation circuits 16 of the driver ICs 4-1 and 4-2 will be described.

  The outline of the operation of the liquid crystal display device 10 of the present embodiment is as follows. In the liquid crystal display device 10 of this embodiment, when an abnormality occurs in the liquid crystal drive power generation circuit 16 of one of the driver ICs 4-1 and 4-2, the other driver is detected by the abnormality occurrence notification data ERR1 or ERR2. The occurrence of an abnormality is notified to the IC, and both the driver ICs 4-1 and 4-2 execute an abnormal operation sequence for stopping the operation.

  In addition, in the abnormal operation sequence, the slave driver (driver IC 4-2 in the present embodiment) uses the common reference clock signal RCLK supplied to the external input terminal 23a as a reference clock signal used for controlling the operation timing. Switching to the internal reference clock signal RCLK_I generated inside. This is to prevent the slave driver from freezing. When the abnormal stop sequence is started, the master driver stops the generation of the internal reference clock signal RCLK_I, that is, the common reference clock signal RCLK at a predetermined timing. If the abnormal operation sequence of the slave driver is not completed by the predetermined timing, the common reference clock signal RCLK is not supplied to the slave driver, so that the operation of the slave driver may be frozen. In order to avoid the freeze of the slave driver, in the liquid crystal display device 10 of this embodiment, the slave driver switches the reference clock signal used for controlling the operation timing to the internal reference clock signal RCLK_I in the abnormal operation sequence.

  Furthermore, the abnormal stop sequence is also started when the reset signal RESET is asserted during the normal display operation. Even in this abnormal operation sequence, the slave driver (driver IC 4-2 in the present embodiment) uses the common reference clock signal RCLK supplied to the external input terminal 23a as the reference clock signal used for controlling the operation timing. Is switched to the internal reference clock signal RCLK_I generated in step S2. Such an operation prevents the slave driver from freezing in the same manner as the abnormal stop sequence performed when an abnormality occurs in the liquid crystal drive power generation circuit 16 of one of the driver ICs 4-1 and 4-2. Is to do.

  Hereinafter, the operation of the liquid crystal display device 10 of the present embodiment will be described in detail with reference to FIGS. 4A, 4B, 5A, 5B, 6A, and 6B.

  FIGS. 4A and 4B show the startup procedure of the driver ICs 4-1 and 4-2 of the liquid crystal display device 10 and the master IC when the driver ICs 4-1 and 4-2 are performing the normal display operation, respectively. The operation when an abnormality occurs in the liquid crystal driving power generation circuit 16 of the driver (that is, the driver IC 4-1) is shown. Here, FIG. 4A shows the operation of the master driver (ie, driver IC 4-1), and FIG. 4B shows the operation of the slave driver (ie, driver IC 4-2).

  In one embodiment, activation of the driver ICs 4-1 and 4-2 of the liquid crystal display device 10 is performed according to the following procedure. First, the reset signal RESET is asserted (see reference numeral 51 in FIGS. 4A and 4B), and the driver ICs 4-1 and 4-2 are set to the sleep mode. Note that in FIGS. 4A and 4B, the reset signal RESET is illustrated as a low-active signal. As a result, the driver ICs 4-1 and 4-2 are in a state where only the minimum necessary circuits are operated. Specifically, the driver ICs 4-1 and 4-2 are logic circuits (specifically, the interface circuit 11, the register circuit 12, the power supply start sequencer 14, the selectors 15a to 15c, the power supply abnormality / reset detection circuit 18, and the abnormality flag. The flip-flop 19, the interface 20), and a circuit (not shown) for generating power supply voltages (power supply voltages IOVCC, VSN, and VDD in FIGS. 4A and 4B) for operating these logic circuits are in a state of operating. In addition, only the internal reference clock signal RCLK_I is generated in the timing generation circuit 13 of the master driver (that is, the driver IC 4-1). The internal reference clock signal RCLK_I generated by the timing generation circuit 13 of the master driver is supplied to both the driver ICs 4-1 and 4-2 as the common reference clock signal RCLK. The selectors 15 a of the driver ICs 4-1 and 4-2 select the common reference clock signal RCLK and supply it to the power activation sequencer 14. At this stage, the liquid crystal drive power generation circuit 16 and the liquid crystal drive circuit 17 do not operate.

  When a certain time has elapsed, the generation of the internal reference clock signal RCLK_I is stopped in the master driver, and the supply of the common reference clock signal RCLK is also stopped.

After that, when the driver ICs 4-1 and 4-2 are set in the sleep mode, when a sleep end command is supplied as control data D _CTRL1 and D _CTRL2 to the driver ICs 4-1 and 4-2, the driver IC 4- 1 and 4-2 perform an operation of leaving the sleep mode. In FIG. 4A and FIG. 4B, the sleep end command is indicated by reference numeral 52.

  More specifically, when the sleep end command 52 is supplied to the driver ICs 4-1 and 4-2, the timing generation circuit 13 of the driver IC 4-1 that is the master driver outputs the common reference clock signal RCLK and the common horizontal synchronization signal HSYNC. Start supplying. That is, the internal reference clock signal RCLK_I and the internal horizontal synchronization signal HSYNC_I generated by the timing generation circuit 13 of the driver IC 4-1 are both used as the common reference clock signal RCLK and the common horizontal synchronization signal HSYNC by both the driver ICs 4-1 and 4-2. To be supplied. At this time, the selectors 15 a and 15 c select the common reference clock signal RCLK and the common horizontal synchronization signal HSYNC and supply them to the power activation sequencer 14.

  After a sufficiently long standby time has elapsed from the supply of the sleep end command 52, the timing generation circuit 13 of the driver IC 4-1 as the master driver starts supplying the common vertical synchronization signal VSYNC. That is, the internal vertical synchronization signal VSYNC_I generated by the timing generation circuit 13 of the driver IC 4-1 is supplied as a common vertical synchronization signal VSYNC to both the driver ICs 4-1 and 4-2. At this time, the selector 15 b selects the common vertical synchronization signal VSYNC and supplies it to the power activation sequencer 14.

  Further, the power activation sequencers 14 of both the driver ICs 4-1 and 4-2 are synchronized with the first pulse appearing in the common vertical synchronization signal VSYNC after the sleep end command 52 is supplied. Start booting. When the activation of the liquid crystal driving power generation circuit 16 is started, the output switches 34 and 38 are switched from the on state to the off state. Further, the boosting operation of the booster circuit 16b is started, and the power supply voltages VGH and VGL are started to be supplied to the amplifiers 31 and 35, respectively. The amplifiers 31 and 35 are supplied with the power supply voltages VGH and VGL, and start outputting the power supply voltages GVDD and VGSS, respectively.

  Thereafter, the liquid crystal drive circuit 17 of the driver ICs 4-1 and 4-2 starts displaying a specific pattern image on the display area 3 of the LCD panel 2. Specifically, the liquid crystal drive circuit 17 supplies the gate line drive signals GOUT1 to GOUTn to the gate lines, sequentially drives the gate lines to the high level (in this embodiment, the power supply voltage VGDD), Voltage level data line drive signals S1 to Sm are supplied to the data lines. As a result, a specific pattern image is displayed in the display area 3 of the LCD panel 2.

Thereafter, when the display on command 53 is supplied to the driver ICs 4-1 and 4-2, the normal display operation is started. In particular, liquid crystal drive circuit 17 supplies the data line driving signals S1~Sm corresponding to the image data _{D IN1, D IN2} to the data lines, thereby displaying a desired image in the display area 3 of the LCD panel 2 Is done.

  Thereafter, it is assumed that an abnormality has occurred in the liquid crystal driving power generation circuit 16 of the master driver (ie, driver IC 4-1) while the driver ICs 4-1 and 4-2 are performing a normal display operation. In this case, in the driver IC 4-1, the occurrence of abnormality is detected in the liquid crystal drive power generation circuit 16, and an abnormal stop sequence for stopping the operation of the driver IC 4-1 is started.

  Specifically, the abnormality detection circuit 16a of the liquid crystal drive power generation circuit 16 asserts the abnormality detection signal ALM when detecting the occurrence of an abnormality in the liquid crystal drive power generation circuit 16. Further, the power supply abnormality / reset detection circuit 18 of the driver IC 4-1 sets the abnormality flag stored in the abnormality flag flip-flop 19 in response to the assertion of the abnormality detection signal ALM. Further, when the abnormality flag is set, the abnormality detection register 12a of the register circuit 12 is set, and the power activation sequencer 14 starts an abnormal stop sequence in response to the setting of the abnormality detection register 12a.

  Further, the fact that the abnormality flag of the abnormality flag flip-flop 19 of the master driver (ie, driver IC4-1) is set is notified to the sleeve driver (ie, driver IC4-2) by the abnormality occurrence notification data ERR1, and the driver IC4- 2 also starts the abnormal stop sequence.

  Specifically, in the driver IC 4-2, the abnormality flag stored in the abnormality flag flip-flop 19 is set in response to the abnormality occurrence notification data ERR 1. Further, when the abnormality flag is set, the abnormality detection register 12a of the register circuit 12 is set, and the power activation sequencer 14 starts an abnormal stop sequence in response to the setting of the abnormality detection register 12a.

When the abnormal stop sequence is started, the following operation is performed.
In the sleeve driver (that is, the driver IC 4-2), the reference clock signal used for controlling the operation timing by the power activation sequencer 14 is generated inside the sleep driver from the common reference clock signal RCLK generated by the master driver. Switched to the internal reference clock signal RCLK_I. As described above, the switching of the reference clock signal used to control the operation timing to the internal reference clock signal RCLK_I is for preventing the sleeve driver from freezing.

  More specifically, the selector 15a of the sleeve driver selects the internal reference clock signal RCLK_I in response to the set of the abnormality flag stored in the abnormality flag flip-flop 19. As a result, the internal reference clock signal RCLK_I is supplied to the power activation sequencer 14.

  In parallel, a vertical synchronizing signal and a horizontal synchronizing signal used for controlling the operation timing are internally generated in the sleep driver from the common vertical synchronizing signal VSYNC and the common horizontal synchronizing signal HSYNC generated by the master driver. It is switched to the synchronization signal VSYNC_I and the internal horizontal synchronization signal HSYNC_I. Specifically, the selectors 15b and 15c of the sleeve driver select the internal vertical synchronization signal VSYNC_I and the internal horizontal synchronization signal HSYNC_I, respectively, in response to the abnormality flag set, and supply them to the power activation sequencer 14.

  Further, in both the driver ICs 4-1 and 4-2, under the control of the power activation sequencer 14, the liquid crystal driving circuit 17 sets the data line driving signals S1 to Sm to the ground potential GND and the gate line driving signals GOUT1 to GOUT1. All gate lines are set to a high level (that is, power supply voltage GVDD) by GOUTn. As a result, the data lines and pixels in the display area 3 are discharged. Thereafter, the operation of the liquid crystal drive power generation circuit 16 is stopped, and generation of the power supply voltages VGH, VGL, GVDD, and GVSS is stopped. As a result, the potentials of the GVDD line 24 and the GVSS line 25 return to the ground potential. Further, generation of the power supply voltages IOVCC, VSN, and VDD is also stopped. Thus, the abnormal stop sequence of the driver ICs 4-1 and 4-2 is completed.

  As described above, in the liquid crystal display device 10 according to the present embodiment, when an abnormality occurs in the liquid crystal driving power generation circuit 16 of the master driver (ie, the driver IC 4-1), the occurrence of abnormality occurs. The slave driver (that is, the driver IC 4-2) is notified by the notification data ERR1, and the abnormal stop sequence is executed in both the master driver and the slave driver. This means that when an abnormality occurs in the liquid crystal drive power supply generation circuit 16 of the master driver (that is, the driver IC 4-1), appropriate measures are taken in both the master driver and the slave driver.

  On the other hand, FIGS. 5A and 5B show that an abnormality has occurred in the liquid crystal drive power generation circuit 16 of the slave driver (that is, the driver IC 4-2) when the driver ICs 4-1 and 4-2 are performing a normal display operation. Shows the operation of the hour. Here, FIG. 5A shows the operation of the master driver (ie, driver IC 4-1), and FIG. 5B shows the operation of the slave driver (ie, driver IC 4-2).

  If an abnormality occurs in the liquid crystal drive power generation circuit 16 of the slave driver (ie, driver IC 4-2) while the driver ICs 4-1 and 4-2 are performing normal display operation, an abnormal stop sequence starts in the slave driver. Is done. Specifically, the abnormality detection circuit 16a of the liquid crystal drive power generation circuit 16 of the slave driver detects the occurrence of abnormality and asserts the abnormality detection signal ALM. Further, the power supply abnormality / reset detection circuit 18 of the driver IC 4-2 sets the abnormality flag stored in the abnormality flag flip-flop 19 in response to the assertion of the abnormality detection signal ALM. Further, when the abnormality flag is set, the abnormality detection register 12a of the register circuit 12 is set, and the power activation sequencer 14 starts an abnormal stop sequence in response to the setting of the abnormality detection register 12a.

  Further, the master driver (ie, driver IC4-1) is notified by the abnormality occurrence notification data ERR2 that the abnormality flag of the abnormality flag flip-flop 19 of the slave driver (ie, driver IC4-2) is set, and the driver IC4- 1 also starts the abnormal stop sequence.

  Specifically, in the driver IC 4-1, the abnormality flag stored in the abnormality flag flip-flop 19 is set in response to the abnormality occurrence notification data ERR 2. Further, when the abnormality flag is set, the abnormality detection register 12a of the register circuit 12 is set, and the power activation sequencer 14 starts an abnormal stop sequence in response to the setting of the abnormality detection register 12a.

When the abnormal stop sequence is started, the following operation is performed.
In the sleeve driver (that is, the driver IC 4-2), the reference clock signal, the vertical synchronization signal, and the horizontal synchronization signal used for controlling the operation timing are the common reference clock signal RCLK and the common vertical synchronization signal generated by the master driver. The VSYNC and the common horizontal synchronization signal HSYNC are switched to the internal vertical synchronization signal VSYNC_I and the internal horizontal synchronization signal HSYNC_I generated inside the sleep driver. Specifically, the selectors 15a, 15b, and 15c of the sleeve driver select the internal vertical synchronization signal VSYNC_I and the internal horizontal synchronization signal HSYNC_I, respectively, and supply them to the power activation sequencer 14 in response to the abnormality flag set. As described above, the reference clock signal used for operation timing control is switched to the internal reference clock signal RCLK_I in order to prevent the sleeve driver from freezing.

  Further, in both the driver ICs 4-1 and 4-2, under the control of the power activation sequencer 14, the liquid crystal driving circuit 17 sets the data line driving signals S1 to Sm to the ground potential GND and the gate line driving signals GOUT1 to GOUT1. All gate lines are set to a high level (that is, power supply voltage GVDD) by GOUTn. As a result, the data lines and pixels in the display area 3 are discharged. Thereafter, the operation of the liquid crystal drive power generation circuit 16 is stopped, and generation of the power supply voltages VGH, VGL, GVDD, and GVSS is stopped. As a result, the potentials of the GVDD line 24 and the GVSS line 25 return to the ground potential. Further, generation of the power supply voltages IOVCC, VSN, and VDD is also stopped. Thus, the abnormal stop sequence of the driver ICs 4-1 and 4-2 is completed.

  As described above, in the liquid crystal display device 10 of the present embodiment, when an abnormality occurs in the liquid crystal drive power generation circuit 16 of one of the driver ICs 4-1 and 4-2, an abnormality occurs. The occurrence of an abnormality is notified to the other driver IC by the notification data ERR1 or ERR2, and both of the driver ICs 4-1 and 4-2 execute an abnormal operation sequence for stopping the operation. As a result, even when an abnormality occurs in the liquid crystal drive power generation circuit 16 of one of the driver ICs 4-1 and 4-2, both the driver ICs 4-1 and 4-2 are shifted to a safe state. be able to.

  6A and 6B are timing charts showing the operation of the liquid crystal display device 10 when the reset signal RESET is asserted while the driver ICs 4-1 and 4-2 are performing the normal display operation. Here, FIG. 6A shows the operation of the master driver (ie, driver IC 4-1), and FIG. 6B shows the operation of the slave driver (ie, driver IC 4-2). Note that in FIGS. 6A and 6B, the reset signal RESET is illustrated as a low-active signal.

  Even when the reset signal RESET is asserted while the driver ICs 4-1 and 4-2 are performing the normal display operation, the abnormal stop sequence is started in both the driver ICs 4-1 and 4-2. Specifically, in each of the driver ICs 4-1 and 4-2, the power supply abnormality / reset detection circuit 18 sets the abnormality flag stored in the abnormality flag flip-flop 19 in response to the assertion of the reset signal RESET. . When the abnormality flag is set, the abnormality detection register 12a of the register circuit 12 is set, and the power activation sequencer 14 starts an abnormal stop sequence in response to the setting of the abnormality detection register 12a.

  Also in this case, in the sleeve driver (that is, the driver IC 4-2), the reference clock signal, the vertical synchronization signal, and the horizontal synchronization signal used for controlling the operation timing are the common reference clock signal RCLK, The common vertical synchronizing signal VSYNC and the common horizontal synchronizing signal HSYNC are switched to the internal vertical synchronizing signal VSYNC_I and the internal horizontal synchronizing signal HSYNC_I generated inside the sleep driver. Specifically, the selectors 15a, 15b, and 15c of the sleeve driver select the internal vertical synchronization signal VSYNC_I and the internal horizontal synchronization signal HSYNC_I, respectively, in response to the setting of the abnormality flag, and supply them to the power activation sequencer 14. As described above, the reference clock signal used for operation timing control is switched to the internal reference clock signal RCLK_I in order to prevent the sleeve driver from freezing.

  Further, in both the driver ICs 4-1 and 4-2, under the control of the power activation sequencer 14, the liquid crystal driving circuit 17 sets the data line driving signals S1 to Sm to the ground potential GND and the gate line driving signals GOUT1 to GOUT1. All gate lines are set to a high level (that is, power supply voltage GVDD) by GOUTn. As a result, the data lines and pixels in the display area 3 are discharged. Thereafter, the operation of the liquid crystal drive power generation circuit 16 is stopped, and generation of the power supply voltages VGH, VGL, GVDD, and GVSS is stopped. As a result, the potentials of the GVDD line 24 and the GVSS line 25 return to the ground potential. Further, generation of the power supply voltages IOVCC, VSN, and VDD is also stopped. Thus, the abnormal stop sequence of the driver ICs 4-1 and 4-2 is completed.

  As understood from the above, in the liquid crystal display device 10 of the present embodiment, information that an abnormality has occurred in the liquid crystal drive power supply generation circuit 16 of the driver ICs 4-1 and 4-2 is the abnormality detection register 12a of the register circuit 12. Stored in By utilizing this fact, the application processor 1 monitors the abnormality detection register 12a of the register circuit 12 of the driver ICs 4-1 and 4-2, and thereby the liquid crystal driving power generation circuit 16 of the driver ICs 4-1 and 4-2. An operation for recognizing the occurrence of the abnormality may be performed.

  Specifically, the application processor 1 sets the value of the abnormality detection register 12a of the register circuit 12 of the driver ICs 4-1 and 4-2 at an appropriate time interval (for example, once every predetermined number of frame periods). 1 is requested to the driver ICs 4-1 and 4-2. In response to the request, the driver ICs 4-1 and 4-2 send control data indicating the value of the abnormality detection register 12a of the register circuit 12 of the driver ICs 4-1 and 4-2 to the application processor 1. When the application processor 1 detects from the received control data that the abnormality detection register 12a of at least one of the driver ICs 4-1 and / or 4-2 is set, an abnormal stop sequence is generated in the driver ICs 4-1 and 4-2. A return routine for returning the driver ICs 4-1 and 4-2 to their original states (that is, returning them to the normal display operation state) at an appropriate timing such that a sufficient time elapses. Run.

  In one embodiment, in the return routine, the driver ICs 4-1 and 4-2 are activated by the same procedure as illustrated in FIGS. 4A and 4B, and the driver ICs 4-1 and 4-2 perform the normal display operation. It returns to the state to do. Specifically, the application processor 1 asserts the reset signal RESET (see reference numeral 51 in FIGS. 4A and 4B), and then, after a predetermined time has elapsed, issues a sleep end command 52 to the driver ICs 4-1, 4- 2 is supplied. Thereafter, the application processor 1 supplies a display on command 53 to the driver ICs 4-1 and 4-2. As a result, the driver ICs 4-1 and 4-2 are activated according to the above-described procedure, and the driver ICs 4-1 and 4-2 are returned to the normal display operation state.

  In the above embodiment, the liquid crystal display device 10 including the two driver ICs 4-1 and 4-2 is presented, but the number of driver ICs may be three or more. In this case, one of the plurality of driver ICs operates as the master driver, and the remaining driver ICs operate as slave drivers.

  FIG. 7 is a diagram illustrating an example of the configuration of the liquid crystal display device 10 when three driver ICs 4-1, 4-2, and 4-3 are provided. In the configuration of FIG. 7, a communication bus 6 is formed on the LCD panel 2, and the driver ICs 4-1 to 4-3 exchange abnormality occurrence notification data ERR 1, ERR 2, and ERR 3 through the communication bus 6. Here, the abnormality occurrence notification data ERR1 is data used as a notification that the driver IC 4-1 notifies the other driver ICs 4-2 and 4-3 that an abnormality has occurred in its own liquid crystal drive power supply generation circuit 16. is there. Similarly, the abnormality occurrence notification data ERR2 and ERR3 are data used as notification for the driver ICs 4-2 and 4-3 to notify other driver ICs that an abnormality has occurred in its own liquid crystal drive power supply generation circuit 16. is there.

  When the driver ICs 4-1, 4-2, 4-3 detect that an abnormality has occurred in their own liquid crystal drive power generation circuit 16, the above-described abnormal stop sequence is started. The driver ICs 4-1 4-2, and 4-3 are also notified when abnormality has occurred in the liquid crystal drive power generation circuit 16 by other driver ICs by the abnormality occurrence notification data ERR1, ERR2, and ERR3. The above-described abnormal stop sequence is started. At this time, in the two driver ICs operating as slave drivers, when an abnormal stop sequence is performed, a reference clock signal, a vertical synchronization signal, and a horizontal synchronization signal used for controlling the operation timing are generated internally. The internal reference clock signal RCLK_I, the internal vertical synchronization signal VSYNC_I, and the internal horizontal synchronization signal HSYNC_I are switched.

  Although the liquid crystal display device 10 is presented in the above embodiment, the present invention is equipped with a plurality of integrated circuits in which the outputs of the power supply circuits integrated with each other are electrically connected to each other. Note that it is generally applicable to integrated circuit devices. In this case, one of the plurality of integrated circuits is selected as a master device, and the remaining integrated circuits operate as slave devices.

(Second Embodiment)
FIG. 8 is a diagram showing a configuration of a liquid crystal display device 10A according to the second embodiment of the present invention, and FIG. 9 is a block diagram showing a configuration of driver ICs 4-1 and 4-2 in the second embodiment. is there. In the present embodiment, the interface 20 is used not only for exchanging the abnormality occurrence notification data ERR1 and ERR2 between the driver ICs 4-1 and 4-2, but also for exchanging other data. Hereinafter, data exchanged between the driver ICs 4-1 and 4-2 is referred to as inter-chip communication data D _CHIP .

More specifically, in this embodiment, the interface 20 is used for exchanging feature data between the driver ICs 4-1 and 4-2. The feature data refers to the feature amount of the image of the portion of the display area 3 of the LCD panel 2 (that is, the first portion 5-1 and the second portion 5-2) driven by the driver ICs 4-1 and 4-2. It is the data shown. Driver IC4-1 from the image data D _IN1 supplied thereto, the feature data indicating the calculating the feature amount of an image displayed on the first part 5-1 of the display area 3 of the LCD panel 2, calculated features Is sent to the driver IC 4-2 as inter-chip communication data D _CHIP . Similarly, driver IC4-2 from the image data D _IN2 supplied thereto, calculates the feature amount of the image displayed on the second part 5-2 of the display area 3 of the LCD panel 2, the calculated features The indicated feature data is sent to the driver IC 4-1 as inter-chip communication data D _CHIP .

The exchanged feature data is obtained by correcting image data D _IN1 and D _IN2 for improving the image quality of an image displayed in the display area 3 of the LCD panel 2 (for example, image data D _IN1 and D _IN2 for contrast enhancement). Correction). In the liquid crystal drive circuit 17 of the driver IC 4-1, the correction calculation of the image data D _IN1 is performed, and the corrected image data obtained by the correction calculation is used for driving the data line of the first portion 5-1. Similarly, the liquid crystal driving circuit 17 of the driver IC4-2 is performed the correction calculation of the image data D _IN2, corrected image data obtained by the correction calculation, the driving of the data line of the second part 5-2 Used.

In addition, in the second embodiment, the LCD driver 7 is controlled by one of the driver ICs 4-1 and 4-2 (driver IC 4-2 in FIG. 8). The LCD driver 7 is a circuit that drives an LCD backlight 8 that illuminates the LCD panel 2. As will be described later, the LCD driver 7 generates the LED drive current I _DRV in response to the luminance control signal S _PWM supplied from the driver IC 4-2. The brightness control signal S _PWM is a pulse signal generated by PWM (pulse width modulation), and the LED drive current I _DRV has a waveform corresponding to the waveform of the brightness control signal S _PWM (corresponding waveform). . The LED backlight 8 is driven by the LED driving current I _DRV and illuminates the LCD panel 2. In the configuration of FIG. 8, the driver IC 4-2 supplies the brightness control signal S _PWM to the LCD driver 7, but the driver IC 4-1 may supply the brightness control signal S _PWM to the LCD driver 7.

  Various parameters can be used as the feature amount included in the feature data exchanged between the driver ICs 4-1 and 4-2. In one embodiment, APL (average picture level) calculated for each color (that is, calculated for each of the R subpixel, the G subpixel, and the B subpixel) may be used as the feature amount. In another embodiment, a histogram of sub-pixel gradations calculated for each color may be used as the feature amount. In still another embodiment, a combination of APL calculated for each color and gradation dispersion (or standard deviation) of subpixels may be used as the feature amount.

If the image data _{D IN1, D IN2} supplied to the driver IC4-1,4-2 is RGB data, the feature amount is obtained by performing the RGB-YUV conversion on the image data _{D IN1, D IN2} It may be calculated from the brightness data (or Y data). In this case, in one embodiment, APL calculated from the luminance data may be used as the feature amount. Each driver IC 4-i performs RGB-YUV conversion on the image data D _INi to calculate luminance data indicating the luminance of each pixel, and the luminance of each pixel of the image displayed in the i-th portion 5-i. APL is calculated as the average value of. In another embodiment, a histogram of pixel brightness may be used as the feature quantity. In still another embodiment, a combination of APL calculated as an average value of luminance and luminance variance (or standard deviation) may be used as the feature amount.

One feature of the display device of the present embodiment is that in each of the driver ICs 4-1 and 4-2, the display area 3 of the LCD panel 2 is based on the feature data exchanged between the driver ICs 4-1 and 4-2. That is, the entire feature amount of the image displayed on the screen is calculated, and the correction calculation is performed on the image data D _IN1 and D _IN2 according to the calculated feature amount. According to such an operation, it is possible to perform a correction calculation according to the entire feature amount of the image displayed in the display area 3 of the LCD panel 2 calculated in each of the driver ICs 4-1 and 4-2.

  FIG. 10 is a conceptual diagram showing an example of the operation of the display device of the present embodiment. Although FIG. 10 illustrates an example in which APL calculated from luminance data is used as the feature amount, the present invention is not limited to this.

As shown in Figure 10, the driver IC4-1 (first driver) from the image data _{D IN1} sent to it, it is displayed in the first part 5-1 of the display area 3 of the LCD panel 2 Calculate the APL of the image. Similarly, driver IC4-2 (second driver) from the image data _{D IN2} that has been sent to it, calculates the APL of the image displayed on the second part 5-2 of the display area 3 of the LCD panel 2. In the example of FIG. 10, the driver IC 4-1 calculates the APL of the image displayed on the first part 5-1, as 104, and the driver IC 4-2 calculates the APL of the image displayed on the second part 5-2. Is calculated as 176.

  Further, the driver IC 4-1 transmits feature data indicating the APL (APL of the image displayed on the first part 5-1) calculated by the driver IC 4-1 to the driver IC 4-2, and the driver IC 4-2 calculates it. The characteristic data indicating the APL (APL of the image displayed in the second part 5-2) is transmitted to the driver IC 4-1.

The driver IC 4-1 calculates the APL calculated by itself (that is, the APL of the image displayed in the first portion 5-1) and the APL indicated by the feature data received from the driver IC 4-2 (that is, the second APL). The total APL of the image displayed in the display area 3 of the LCD panel 2 is calculated from the APL of the image displayed in the portion 5-2. Here, the average value APL _AVE of the APL of the image displayed in the first part 5-1 and the APL of the image displayed in the second part 5-2 is the total APL of the image displayed in the display area 3. is there. In the example of FIG. 10, since the APL of the image displayed in the first portion 5-1 is 104 and the APL of the image displayed in the second portion 5-2 is 176, the driver IC 4-1 The value APL _AVE is calculated as 140.

Similarly, the driver IC 4-2 calculates the APL calculated by itself (that is, the APL of the image displayed in the second portion 5-2) and the APL indicated by the feature data received from the driver IC 4-1 (that is, APL of the image displayed on the second portion 5-1, and the APL of the entire image displayed on the display area 3 of the LCD panel 2, that is, the APL of the image displayed on the first portion 5-1. Then, an average value APL _AVE of the APL of the image displayed in the second part 5-2 is calculated. In the example of FIG. 10, the driver IC 4-2 calculates the average value APL _AVE as 140 in the same manner as the driver IC 4-1.

The driver IC 4-1 performs a correction operation on the image data D _IN1 according to the entire APL (that is, the average value APL _AVE ) of the image displayed in the display area 3 calculated by the driver IC 4-1, and obtains it by the correction calculation. The pixels provided in the first portion 5-1 are driven according to the corrected image data. Similarly, driver IC4-2 performs correction operation on the image data D _IN2 according to the average value APL _AVE that it has calculated, the second portion 5 in accordance with the corrected image data obtained by the correction calculation -2 is driven.

Here, since the average value APL _AVE calculated by each of the driver ICs 4-1 and 4-2 is the same value (in principle), as a result, each of the driver ICs 4-1 and 4-2 has the LCD It is possible to perform a correction calculation according to the entire feature amount of the image displayed in the display area 3 of the panel 2. As described above, in this embodiment, the driver ICs 4-1 and 4-2 do not have to send image data corresponding to the entire image of the display area 3 of the LCD panel 2 to each of the driver ICs 4-1 and 4-2. Each can perform a correction operation according to the entire feature amount of the image displayed in the display area 3 of the LCD panel 2.

  In addition to the APL calculated as the average value of the luminance, the pixel luminance histogram and the pixel luminance variance (or standard deviation) can be used as the feature amount included in the feature data as described above. Street.

There are three desirable characteristics as the feature amount indicated in the feature data exchanged as the inter-chip communication data D _CHIP . First, it is desirable to have a large amount of information about the images of the first part 5-1 and the second part 5-2 of the display area 3 of the LCD panel 2. Second, it is desirable that the entire feature amount of the image in the display area 3 of the LCD panel 2 can be reproduced by simple calculation. Third, it is desirable that the amount of feature data is small.

From these viewpoints, a suitable example of the feature amount included in the feature data is a combination of APL (that is, the average of the gradation of the subpixel) and the root mean square of the gradation of the subpixel calculated for each color. . As a feature quantity exchanged between the driver ICs 4-1 and 4-2, a combination of the APL calculated for each color and the root mean square of the gradation of the sub-pixels is adopted, so that the driver ICs 4-1 and 4-2 are used. In each of these, the APL of the entire image displayed on the display area 3 of the LCD panel 2 and the root mean square of the gradation of the sub-pixels are calculated, and further, the entire image displayed on the display area 3 of the LCD panel 2 is calculated. The variance σ ² of subpixel gradation can be calculated. Specifically, for each color, the entire APL of the image displayed in the display area 3 of the LCD panel 2 can be calculated from the APLs of the images displayed in the first part 5-1 and the second part 5-2. is there. Further, for each color, the display is performed in the display area 3 of the LCD panel 2 from the APL calculated for each of the images displayed in the first part 5-1 and the second part 5-2 and the root mean square of the subpixel gradation. The gradation dispersion σ ² of the sub-pixels of the entire image to be calculated can be calculated. APL and subpixel gradation variance σ ² is a combination of parameters suitable for roughly grasping the subpixel gradation distribution, and by performing a correction operation based on such parameters, It is possible to appropriately correct the contrast of the image. Furthermore, the combination of the APL and the root mean square of the sub-pixel gradation calculated for each color is small as a data amount (for example, compared with a histogram). Thus, the combination of the APL calculated for each color and the root mean square of the sub-pixels has characteristics desirable as a feature amount included in the feature data.

From the viewpoint that the data amount is even smaller, it is preferable to use a combination of the APL calculated as the average value of the pixel luminance (that is, the average of the pixel luminance) and the square average of the pixel luminance as the feature amount. is there. By adopting a combination of the APL calculated as the average value of the luminance of the pixel and the root mean square of the luminance as the feature quantity exchanged between the driver ICs 4-1 and 4-2, the driver IC 4-1, In each of 4-2, the APL of the entire image displayed on the display area 3 of the LCD panel 2 and the root mean square of the luminance of the pixels are calculated, and the entire image displayed on the display area 3 of the LCD panel 2 is calculated. A variance σ ² of luminance of pixels can be calculated. Specifically, the APL of the entire image displayed in the display area 3 of the LCD panel 2 can be calculated from the APLs of the images displayed in the first part 5-1 and the second part 5-2. The entire image displayed in the display area 3 of the LCD panel 2 from the APL calculated for each of the images displayed in the first part 5-1 and the second part 5-2 and the root mean square of the luminance of the pixels. The luminance variance σ ² of the pixels can be calculated. The APL and the luminance distribution of the pixel are a combination of parameters suitable for roughly grasping the luminance distribution of the pixel. Furthermore, the combination of APL and the root mean square of pixel luminance is the amount of data (compared to, for example, the combination of APL and the root mean square of subpixel gradation calculated for each color as described above). As small as. As described above, the combination of the APL calculated as the average value of the luminance of the pixel and the square average of the luminance of the pixel has characteristics desirable as a feature amount included in the feature data.

One problem that may occur in the operation shown in FIG. 10 is that a communication error occurs in the communication for exchanging the inter-chip communication data D _CHIP between the driver ICs 4-1 and 4-2 (that is, exchanging feature data). When this occurs, the image displayed in the display area of the LCD panel 2 may be disturbed. In particular, if a signal line used for communication of inter-chip communication data D _CHIP between the driver ICs 4-1 and 4-2 is provided on the glass substrate of the LCD panel 2, a communication error is likely to occur. FIG. 11 is a diagram for explaining a problem of communication error in communication of inter-chip communication data D _CHIP between driver ICs 4-1 and 4-2.

For example, in the operation of FIG. 11, it is assumed that communication from the driver IC 4-2 to the driver IC 4-1 is normally performed, but a communication error has occurred in communication from the driver IC 4-1 to the driver IC 4-2. More specifically, a communication error occurs when the feature data indicating the APL calculated by the driver IC 4-1 (APL of the image displayed on the first portion 5-1) is transmitted to the driver IC 4-2. As a result, it is assumed that the driver IC 4-2 recognizes that the APL of the image displayed in the first portion 5-1 is 12. In this case, the driver IC 4-2 erroneously calculates APL _AVE of the entire image displayed in the display area of the LCD panel 2 as 94. On the other hand, the driver IC 4-1 correctly calculates 140 the total APL _{AVE of the} image displayed in the display area of the LCD panel 2. As a result, the driver ICs 4-1 and 4-2 perform different correction calculations, and the boundary between the first part 5-1 and the second part 5-2 of the display area of the LCD panel 2 can be visually recognized. turn into.

  In the specific configuration and operation of the driver ICs 4-1 and 4-2 described below, the driver ICs 4-1 and 4-2 are identical even if the feature data cannot be normally transmitted in a certain frame period. Thus, a technical technique that enables the correction calculation of the first part 5-1 and the second part 5-2 of the display area of the LCD panel 2 can be visually recognized. The problem of becoming is avoided. Hereinafter, specific configurations and operations of the driver ICs 4-1 and 4-2 will be described in detail.

FIG. 12 is a block diagram showing an example of the configuration of the liquid crystal drive circuit 17 of the driver ICs 4-1 and 4-2 in the second embodiment. Hereinafter, the driver ICs 4-1 and 4-2 may be collectively referred to as a driver IC 4-i. At this time, image data sent to the driver IC 4-i may be described as image data D _INi .

The liquid crystal driving circuit 17 of each of the driver ICs 4-1 and 4-2 uses the interface 20 to exchange the inter-chip communication data D _CHIP with the liquid crystal driving circuit 17 of another driver IC (4-2 or 4-1). . Here, the inter-chip communication data D _CHIP received from the other driver IC by the interface 20 includes feature data and communication state notification data generated by the other driver IC. Here, hereinafter, the feature data transmitted from another driver IC is referred to as input feature data D _{CHR_IN} . Communication state notification data transmitted from another driver IC is referred to as communication state notification data _{DST_IN} .

The input feature data D _{CHR_IN} indicates the feature amount calculated by the other driver IC. For example, the input feature data D _{CHR_IN} received from the driver IC 4-2 by the driver IC _4-1 is the feature amount calculated by the driver IC 4-2 (that is, the feature amount of the image displayed in the second portion 5-2). Show.

Further, the communication status notification data _{DST_IN} indicates whether the other driver IC has received the feature data normally. For example, the communication status notification data DST_IN received from the driver IC _4-2 by the driver IC 4-1 indicates whether the driver IC 4-2 has received the feature data normally (from the driver IC 4-1). Each driver IC 4-i can _know from the communication state notification data _{DST_IN whether} other driver ICs have received the feature data normally. The interface 20 _supplies the input feature data D _{CHR_IN} and the communication state notification data D _{ST_IN} received from another driver IC to the liquid crystal drive circuit 17.

On the other hand, the inter-chip communication data D _CHIP transmitted from the interface 20 to the other driver IC is generated by the driver IC in which the interface 20 is integrated, and the characteristic data and the communication state notification data to be transmitted to the other driver IC. Is included. The feature data to be transmitted to another driver IC generated in the driver IC in which the interface 20 is integrated is hereinafter referred to as output feature data D _{CHR_OUT} . Further, the communication status notification data to be transmitted to other driver ICs is indicated below as communication status notification data _{DST_OUT} .

The output feature data D _{CHR_OUT} indicates a feature amount calculated by a driver IC in which the interface 20 is integrated. For example, the output feature data D _{CHR_OUT} transmitted by the interface 20 of the driver IC 4-1 indicates the feature amount calculated by the driver IC 4-1 and is transmitted to the driver IC 4-2.

Further, the communication status notification data _{DST_OUT} indicates whether the driver IC in which the interface 20 is integrated normally receives the feature data. For example, the communication status notification data D _{ST_OUT} transmitted by the interface 20 of the driver IC 4-1 indicates whether the driver IC 4-1 has normally received the input feature data D _{CHR_IN} . The communication status notification data DST_OUT generated in the driver IC _4-1 is sent to the interface 20 of the driver IC 4-2 and used in processing in the driver IC 4-2.

  The liquid crystal drive circuit 17 of each driver IC 4-i includes a display memory 61, a correction point data set supply circuit 62, an approximate calculation correction circuit 63, a color reduction processing circuit 64, a latch circuit 65, and a data line drive circuit 66. A gradation voltage generation circuit 67, a timing control circuit 68, and a backlight luminance adjustment circuit 69.

The display memory 61 is used to temporarily hold the image data D _INi inside the driver IC 4-i. The display memory 61 has a capacity capable of storing an image of one frame. In the present embodiment in which the gradation of each sub-pixel of the pixel of the LCD panel 2 is represented by 8 bits, the capacity of the display memory 61 is V × 3H × 8 bits. The display memory 61 sequentially outputs the stored image data D _INi .

The correction point data set supply circuit 62 supplies correction point data sets CP_sel ^R , CP_sel ^G , CP_sel ^B (hereinafter, these may be collectively referred to as correction point data set CP_sel ^k ) to the approximate calculation correction circuit 63. To do. Here, the correction point data set CP_sel ^k is data that specifies the input / output relationship of the correction calculation performed in the approximate calculation correction circuit 63. In the present embodiment, the gamma correction is used as a correction calculation is performed in the approximate operation and correction circuit 63, correction point data set CP_selG ^k is a set of data that determines the shape of the gamma curve that is applied to the gamma correction. Each correction point data set _CP _ sel ^k, 6 one correction point data: by being constituted by CP0 to CP5, a set of correction point data CP0 to CP5, the shape of the gamma curve corresponding to a certain gamma value γ It is specified.

Here, in order to enable gamma correction using different gamma values for the image data D _INi of the R subpixel, the G subpixel, and the B subpixel, in the present embodiment, the R subpixel, G A correction point data set is selected for each of the sub-pixel and the B sub-pixel. The correction point data set selected for the R subpixel is described as a correction point data set CP_sel ^R , the correction point data set selected for the G subpixel is described as a correction point data set CP_sel ^G, and for the B subpixel. The selected correction point data set is described as a correction point data set CP_sel ^B.

Figure 13 is a gamma curve specified by the correction point data CP0~CP5 included in the correction point data set _CP _ sel ^k, and shows the contents of the correction calculation (gamma correction) in accordance with the comma curve. The correction point data CP0 to CP5 are respectively defined as points on a coordinate system having the image data D _INi as the horizontal axis (first axis) and the corrected image data D _OUT as the vertical axis (second axis). Here, the correction point data CP0 and CP5 are located at both ends of the comma curve. The correction point data CP2 and CP3 are at positions near the center of the comma curve. The correction point data CP1 is at a position between the correction point data CP0 and CP2, and the correction point data CP4 is at a position between the correction point data CP3 and CP5. The shape of the comma curve is designated by appropriately determining the positions of the correction point data CP1 to CP4.

For example, as shown in FIG. 13, by determining the positions of the correction point data CP1 to CP4 at positions below a straight line connecting the positions of both ends of the comma curve, the gamma curve is determined to have a downwardly convex shape. it can. As described below, the approximate in operation and correction circuit 63, correction point data set CP _{_} sel ^k corrected image data gamma correction is performed by the gamma curve having a shape specified by the correction point data CP0~CP5 contained in D _OUT is generated.

Here, the correction point data set supply circuit 62 of the driver IC 4-i according to the present embodiment has a function of calculating the image feature amount of the i-th portion 5-i of the display area 3 of the LCD panel 2 from the image data _DINi. Have. Further, the correction point data set supply circuit 62 of the driver IC 4-i uses the feature amount calculated by the driver IC 4-i and the feature amount indicated in the input feature data D _{CHR_IN} received from the other driver IC, so that the LCD panel 2 calculating an overall characteristic amount of an image in the display area 3, in response to the overall characteristic amount of the display area 3 of the image of the LCD panel 2, and has a function of determining the correction point data set CP_selG ^k.

In one embodiment, the feature amount exchanged between the driver ICs 4-1 and 4-2 is the average of the sub-pixel gradations for each color (that is, for each of the R sub-pixel, the G sub-pixel, and the B sub-pixel). A combination of the APL calculated as a value and the root mean square of the gradation of the sub-pixel is employed. The correction point data set supply circuit 62 of the driver IC 4-i calculates the APL of the image of the i-th part 5-i of the display area 3 of the LCD panel 2 from the image data D _INi and the root mean square of the gradation of the subpixels. Calculation is performed for each of the R subpixel, the G subpixel, and the B subpixel. The correction point data set supply circuit 62 of the driver IC 4-i further includes the feature amount calculated by the correction point data set supply circuit 62 and other driver ICs for each of the R subpixel, the G subpixel, and the B subpixel. The entire feature amount of the image in the display area 3 of the LCD panel 2 is calculated from the feature amount indicated in the input feature data D _{CHR_IN} received from the above. Specifically, from the APL of the R subpixel calculated by the correction point data set supply circuit 62 and the APL of the R subpixel indicated in the input feature data D _{CHR_IN} received from the other driver IC, the LCD panel The APL of the entire R subpixel of the image in the second display area 3 is calculated. Further, the mean square of the gradation of the R subpixel calculated by the correction point data set supply circuit 62 and the mean square of the gradation of the R subpixel indicated in the input feature data D _{CHR_IN} received from another driver IC. From the above, the mean square of the gradation of the entire R subpixel of the image in the display area 3 of the LCD panel 2 is calculated. Furthermore, the variance σ ² of the R subpixel gradation is calculated from the APL of the entire image in the display area 3 of the LCD panel 2 calculated for the R subpixel and the root mean square of the subpixel gradation. The APL of the R sub-pixel and the gradation variance σ ² are used to determine the correction point data set CP_sel ^R. Similarly, for the G subpixel, the APL of the entire image in the display area 3 of the LCD panel 2 and the root mean square of the gradation of the subpixel are calculated, and further, the variance σ ² of the gradation of the G subpixel is calculated. . The calculated APL of the G sub-pixel and the gradation variance σ ² are used to determine the correction point data set CP_sel ^G. For the B subpixel, the APL of the entire image in the display area 3 of the LCD panel 2 and the root mean square of the gradation of the subpixel are calculated, and further, the variance σ ² of the gradation of the B subpixel is calculated. The calculated APL of the B subpixel and gradation variance σ ² are used to determine the correction point data set CP_sel ^B.

In another embodiment, the APL calculated as the average value of the pixel luminance and the pixel as the feature amount exchanged between 6-1 and 6-2 exchanged between the driver ICs 4-1 and 4-2. A combination of the root mean square is used. Here, the luminance of each pixel is obtained by performing RGB-YUV conversion from the RGB data of the pixel indicated in the image data D _INi . The correction point data set supply circuit 62 of the driver IC 4-i performs RGB-YUV conversion on the image data D _INi (which is RGB data), and the image of the i-th portion 5-i of the display area 3 of the LCD panel 2 The luminance of each pixel is calculated, and the APL and the mean square of the luminance of the pixel are calculated from the calculated luminance of each pixel. The correction point data set supply circuit 62 of the driver IC 4-i further includes the feature amount calculated by the correction point data set supply circuit 62 and the feature amount indicated in the input feature data D _{CHR_IN} received from another driver IC. From the above, the entire feature amount of the image in the display area 3 of the LCD panel 2 is calculated. The APL of the entire image in the display area 3 of the LCD panel 2 and the mean square of the luminance of the pixels are used to calculate the luminance variance σ ² , and further determine correction point data sets CP_sel ^R , CP_sel ^G , CP_sel ^B. Used for. In this case, the correction point data sets CP_sel ^R , CP_sel ^G , CP_sel ^B may be the same. The configuration and operation of the correction point data set supply circuit 62 will be described in detail later.

Approximate operation and correction circuit 63 performs gamma correction by the specified gamma curve by the correction point data set CP_selG ^k sent from the correction point data set supplied circuit 62 to the image data D _INi, corrected image data D _OUT Is generated.

The corrected image data D _OUT is data having a larger number of bits than the image data D _INi . _{Increasing the} number of bits of the post-correction image data D _OUT more than the image data D _INi is effective because the pixel gradation information is not lost by the correction operation. In this embodiment in which the image data D _INi represents the gradation of each subpixel of each pixel by 8 bits, the corrected image data _DOUT is, for example, data representing the gradation of each subpixel of each pixel by 10 bits. Generated.

For the gamma calculation performed by the approximate calculation correction circuit 63, an arithmetic expression is used instead of the LUT. Eliminating the LUT from the approximate calculation correction circuit 63 is effective for reducing the circuit scale of the approximate calculation correction circuit 63 and reducing the power consumption necessary for switching the gamma value. However, for the gamma correction by the approximate calculation correction circuit 63, an approximate expression is used instead of an exact expression. Approximate operation and correction circuit 63 determines coefficients of the approximate expression from the correction point data set CP_selG ^k sent from the correction point data set supplied circuit 62 is used in the gamma correction, thereby, the gamma correction with the desired gamma value I do. In order to perform gamma correction by an exact formula, it is necessary to perform a power operation, which increases the circuit scale. In the present embodiment, the circuit scale is reduced by performing gamma correction using an approximate expression that does not include a power.

FIG. 14 is a block diagram illustrating an example of the configuration of the approximate calculation correction circuit 63. Hereinafter, of the image data D _INi , data indicating the gradation of the R subpixel is referred to as image data D _INi ^R. Similarly, of the image data D _INi , data indicating the gradation of the G subpixel is described as image data D _INi ^G, and data indicating the gradation of the B subpixel is described as image data D _INi ^B. Further, of the corrected image data _{D OUT,} describes data indicating the gradation of the R sub-pixel and the corrected image data _{D OUT} ^R. Similarly, among the corrected image data D _OUT , data indicating the gradation of the G subpixel is described as corrected image data D _OUT ^G, and data indicating the gradation of the B subpixel is corrected image data D _OUT ^B It describes.

The approximate calculation correction circuit 63 includes approximate calculation units 63R, 63G, and 63B prepared for the R subpixel, the G subpixel, and the B subpixel, respectively. The approximate calculation units 63R, 63G, and 63B perform gamma correction by an arithmetic expression on the image data D _INi ^R , D _INi ^G , and D _INi ^B , respectively, and the corrected image data D _OUT ^R , D _OUT ^G , and D _OUT ^B is generated. As described above, the number of bits of the corrected image data D _OUT ^R , D _OUT ^G , and D _OUT ^B is larger than the number of bits of the image data D _INi ^R , D _INi ^G , and D _INi ^B and is 10 bits. is there.

Coefficient arithmetic expression approximate operation units 63R uses in the gamma correction is determined by the correction point data CP0~CP5 the correction point data set CP_selG ^R. Similarly, coefficients of arithmetic expressions used by the approximate arithmetic units 63G and 63B for gamma correction are determined by correction point data CP0 to CP5 of correction point data sets CP_sel ^G and CP_sel ^B , respectively.

  The functions of the approximate calculation units 63R, 63G, and 63B are the same except that the image data input thereto and the correction point data are different. Hereinafter, the approximate calculation units 63R, 63G, and 63B may be referred to as approximate calculation units 63k when they are not distinguished from each other.

Returning to FIG. 12, the color reduction processing circuit 64, the latch circuit 65, and the data line driving circuit 66 correspond to the i-th portion of the display area 3 of the LCD panel 2 in accordance with the corrected image data D _OUT output from the approximate calculation correction circuit 63. It functions as a drive unit for driving the 5-i data line. Specifically, the color reduction processing circuit 64 performs color reduction processing on the corrected image data D _OUT generated by the approximate calculation correction circuit 63 to generate color reduction image data D _{OUT_D} . The latch circuit 65 latches the color-reduced image data D _{OUT_D} from the color-reduction processing circuit 64 in response to the latch signal S _STB supplied from the timing control circuit 68, and transfers the latched color-reduced image data D _{OUT_D} to the data line driving circuit 66. To do. The data line driving circuit 66 drives the data line of the i-th portion 5-i of the display area 3 of the LCD panel 2 in response to the color-reduced image data D _{OUT_D} sent from the latch circuit 65. Specifically, the data line driving circuit 66 selects a corresponding gradation voltage from among a plurality of gradation voltages supplied from the gradation voltage generation circuit 67 in response to the subtractive color image data D _{OUT_D} , and the corresponding LCD. The data line of panel 2 is driven to the selected gradation voltage. In the present embodiment, the number of gradation voltages supplied from the gradation voltage generation circuit 67 is 255.

The timing control circuit 68 controls the timing of the driver IC 4-i in response to the control data D _CTRLi supplied to the driver IC 4-i. Specifically, the timing control circuit 68 generates a frame signal S _FRM and a latch signal S _STB in response to the control data D _CTRLi and supplies them to the correction point data set supply circuit 62 and the latch circuit 65, respectively. The frame signal S _FRM is a signal that notifies the correction point data set supply circuit 62 of the start of each frame period. The frame signal S _FRM is asserted at the beginning of each frame period. The latch signal S _STB is a signal that permits the latch circuit 65 to latch the subtractive color image data _{DOUT_D} . The operation timings of the correction point data set supply circuit 62 and the latch circuit 65 are controlled by the frame signal S _FRM and the latch signal S _STB .

The backlight luminance adjustment circuit 69 generates a luminance control signal S _PWM that controls the LED driver 7. The luminance control signal S _PWM is a pulse signal generated by pulse width modulation (PWM) performed in response to the APL data D _APL supplied from the correction point data set supply circuit 62. Here, APL data _{D APL} is the APL that is used to determine the correction point data set CP_selG ^k in the correction point data set supplied circuit 62. The luminance control signal S _PWM is supplied to the LED driver 7, and the luminance of the LED backlight 8 is controlled by the luminance control signal S _PWM . Note that the luminance control signal S _PWM generated by one backlight luminance adjustment circuit 69 of the driver ICs 4-1 and 4-2 is supplied to the LED driver 7 and generated by the other backlight luminance adjustment circuit 69. The luminance control signal S _PWM is not used.

  Next, the configuration and operation of the correction point data set supply circuit 62 of each driver IC 4-i will be described. As illustrated in FIG. 12, the correction point data set supply circuit 62 includes a feature data calculation circuit 71, a calculation result storage memory 72, and a correction point data calculation circuit 73.

  FIG. 15 is a block diagram showing a configuration of the feature data calculation circuit 71. The feature data calculation circuit 71 includes a feature data calculation circuit 81, an error detection code addition circuit 82, an inter-chip communication detection circuit 83, a full-screen feature data calculation circuit 84, a communication state storage memory 85, and a communication confirmation circuit 86. And.

The feature data calculation circuit 81 of the driver IC 4-i calculates and calculates the feature amount of the image displayed in the i-th portion 5-i of the display area 3 of the LCD panel 2 in the current frame period from the image data D _INi . Feature data D _{CHR_i} indicating the feature _value is output. As described above, in one embodiment, the i-th portion 5 calculated for each of the R subpixel, the G subpixel, and the B subpixel as the feature amount exchanged between the driver ICs 4-1 and 4-2. The APL of the image displayed at -i and the root mean square of the subpixel gradation are used. In this case, the feature data D _{CHR_i} includes the following data:
(A) APL of the R sub-pixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “APL _i ^R ”)
(B) APL of the G sub-pixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “APL _i ^G ”)
(C) APL of the B subpixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “APL _i ^B ”)
(D) The root mean square of the gradation of the R sub-pixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “<g _R ² > _i ”)
(E) Root mean square of the gradation of the G sub-pixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “<g _G ² > _i ”)
(F) Root mean square of gradation of B subpixel of image displayed in i-th portion 5-i (hereinafter, described as “<g _B ² > _i ”)

Here, if the gradation of each R subpixel of the image displayed in the i-th portion 5-i is g _jR , the APL and the square of the gradation of the R subpixel of the image displayed in the i-th portion 5-i. The average is calculated as:
^{_{APL i R = Σg jR / n}} ··· (1a)
<G _R ² > _i = Σ (g _jR ) ² / n (2a)
Here, n is the number of pixels included in the i-th portion 5-i of the display area 3 of the LCD panel 2 (that is, the number of R subpixels), and Σ is the sum for the i-th portion 5-i. Represents.

Similarly, if the gradation of each G subpixel of the image displayed in the i-th portion 5-i is g _jG , the APL and the square of the gradation of the G subpixel of the image displayed in the i-th portion 5-i. The average is calculated as:
APL _i ^G = Σg _jG / n (1b)
< _{G G} ² > _i = Σ (g _jG ) ² / n (2b)

Further, if the gradation of each B subpixel of the image displayed in the i-th portion 5-i is g _jB , the APL and the mean square of the gradation of the B subpixel of the image displayed in the i-th portion 5-i Is calculated by the following formula:
APL _i ^B = Σg _jB / n (1c)
<G _B ² > _i = Σ (g _jB ) ² / n (2c)

On the other hand, when the APL calculated as the average of the luminance of the pixel and the average of the square of the luminance are used as the feature amount exchanged between the driver ICs _{4-1 and 4-2} , the feature data D _{CHR_i} includes the following data: Contains:
(A) APL of each pixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “APL _i ”)
(B) The root mean square of the luminance of each pixel of the image displayed in the i-th portion 5-i (hereinafter referred to as “<Y ² > _i ”)

Here, if the luminance gradation of each pixel of the image displayed in the i-th portion 5-i is Y _j , the APL of the image displayed in the i-th portion 5-i and the root mean square of the luminance of the pixel are Calculated with the formula:
APL _i ^R = ΣY _j / n (1d)
<Y ² > _i = Σ (Y _j ² ) / n (2d)
Here, n is the number of pixels included in the i-th portion 5-i of the display area 3 of the LCD panel 2 (that is, the number of R subpixels), and Σ is the sum for the i-th portion 5-i. Represents.

The feature data D _{CHR_i} calculated in this way is _sent to the error detection code adding circuit 82 and the full-screen feature data calculation circuit 84.

The error detection code addition circuit 82 adds an error detection code to the feature data D _{CHR_i} by the feature data calculation circuit 81 and generates output feature data D _{CHR_OUT} that is feature data to be transmitted to another driver IC. The output feature data D _{CHR_OUT} is transferred to the interface 20 and transmitted to other driver ICs as inter-chip communication data D _CHIP . Since the output feature data D _{CHR_OUT} includes an error detection code, when the other driver IC receives the transmitted output feature data D _{CHR_OUT} as the input feature data D _{CHR_IN} , the input feature data D _{CHR_IN} is normal. It is possible to determine whether it has been received successfully.

The chip-to-chip communication detection circuit 83 receives input feature data D _{CHR_IN} that is feature data transmitted from another driver IC from the interface 20, and further performs error detection on the received input feature data D _{CHR_IN} to input feature data D _It is determined whether or not _{CHR_IN} has been normally received. The inter-chip communication detection circuit 83 further outputs the determination result as communication state notification data _{DST_OUT} . The communication status notification data _{DST_OUT} includes communication ACK (acknowledged) data indicating that communication is normally performed or communication NG (no good) data indicating that communication is not normally performed.

Specifically, the input feature data D _{CHR_IN} received from another driver IC includes the error correction code added by the error detection code addition circuit 82 of the other driver IC. The inter-chip communication detection circuit 83 performs error detection on the input feature data D _{CHR_IN} received from another driver IC using this error correction code. If no data error is detected in the input feature data D _{CHR_IN} , the inter-chip communication detection circuit 83 determines that the input feature data D _{CHR_IN} has been normally received, and transmits communication ACK data as the communication status notification data D _{ST_OUT.} Output. On the other hand, when an error that cannot be corrected is detected, the inter-chip communication detection circuit 83 outputs communication NG data as communication status notification data _{DST_OUT} . The output communication status notification data _{DST_OUT} is sent to the communication confirmation circuit 86. In addition, the inter-chip communication detection circuit 83 _{passes the} communication state notification data _{DST_OUT} to the interface 20. The communication state notification data D _{ST_OUT} delivered to the interface 20 is transmitted to other driver ICs as inter-chip communication data D _CHIP .

An error-correctable code may be used as the error detection code. In such a case, when detecting an error that can be corrected, the inter-chip communication detection circuit 83 performs error correction and outputs the input feature data D _{CHR_IN} in which the error is corrected. In this case, the inter-chip communication detection circuit 83 determines that communication has been normally performed, and outputs communication ACK data as communication state notification data _{DST_OUT} . On the other hand, when an error that cannot be corrected is detected, the inter-chip communication detection circuit 83 outputs communication NG data as communication status notification data _{DST_OUT} .

The full-screen feature data calculation circuit 84 _displays the feature data D _{CHR_i} calculated by the feature data calculation circuit 81 and the input feature data D _{CHR_IN} received from the inter-chip communication detection circuit 83 in the display area 3 of the LCD panel 2. The entire feature amount of the image to be obtained is obtained by calculation, and full-screen feature data D _{CHR_C} indicating the obtained feature amount is calculated. Here, the full screen feature data D _{CHR_C} indicates the overall feature amount of the image displayed in the display area 3 of the LCD panel 2 in the current frame period. In the following, when this is emphasized, it is described as “current frame full-screen feature data D _{CHR_C} ”.

When the root mean square of the APL calculated for each color and the gradation of the sub-pixel is adopted as the feature amount exchanged between the driver ICs 4-1 and 4-2, the full-screen feature data calculation circuit 84 is an LCD panel. The APL of the entire image in the display area 3 of 2 and the root mean square of the gradation of the sub-pixel are calculated for each color. Further, the full-screen feature data calculation circuit 84 further calculates the display area 3 of the LCD panel 2 from the APL of the entire image in the display area 3 of the LCD panel 2 and the root mean square of the gradation of the subpixels calculated for each color. The gradation variance σ ² of the entire sub-pixel of the image is calculated. In this case, the current frame full-screen feature data D _{CHR_C} generated by the full-screen feature data calculation circuit 84 includes the following data:
(A) APL calculated for the entire R subpixel of the display area 3 of the LCD panel 2 (hereinafter referred to as “APL _{AVE_R} ”)
(B) APL calculated for the entire G subpixel of the display area 3 of the LCD panel 2 (hereinafter referred to as “APL _{AVE_G} ”)
(C) APL calculated for the entire B subpixel of the display area 3 of the LCD panel 2 (hereinafter referred to as “APL _{AVE_B} ”)
(D) Dispersion of gradation of the R sub-pixel in the entire display area 3 of the LCD panel 2 (hereinafter referred to as “σ _{AVE_R} ² ”).
(E) Gradation dispersion of the entire G subpixel in the display area 3 of the LCD panel 2 (hereinafter referred to as “σ _{AVE_G} ² ”).
(F) Dispersion of gradation of B subpixels in the entire display area 3 of the LCD panel 2 (hereinafter referred to as “σ _{AVE_B} ² ”).

APL _{AVE_R} , APL _{AVE_G} , APL _{AVE_B} , σ _{AVE_R} ² , σ _{AVE_G} ² , and σ _{AVE_B} ² are calculated as follows. First, consider the full-screen feature data calculation circuit 84 of the driver IC 4-1.

The full-screen feature data calculation circuit 84 of the driver IC 4-1 includes feature data D _{CHR — 1} calculated by the feature data calculation circuit 81 of the driver IC _4-1 and feature data received as input feature data D _{CHR_IN} from the driver IC 4-2. D _{CHR — 2} (which is calculated by the feature data calculation circuit 81 of the driver IC 4-2). The full-screen feature data calculation circuit 84 of the driver IC _4-1 describes the APL (APL ₁ ^R ) of the R subpixel of the image displayed in the first portion 5-1 described in the feature data D _{CHR — 1} and the feature data. APL _{AVE_R} is calculated as an average value of APL (APL ₂ ^R ) of the R sub-pixel of the image displayed in the second portion 5-2 described in D _{CHR_2} (that is, input feature data D _{CHR_IN} ). That is,
APL _{AVE_R} = (APL ₁ ^R + APL ₂ ^R ) / 2 (3a)
Similarly, APL _{AVE_G} and APL _{AVE_B} are calculated by the following equations:
APL _{AVE_G} = (APL ₁ ^G + APL ₂ ^G ) / 2 (3b)
APL _{AVE_B} = (APL ₁ ^B + APL ₂ ^B ) / 2 (3c)

In addition, the full-screen feature data calculation circuit 84 of the driver IC _4-1 describes the root mean square of the gradations of the R subpixels of the image displayed in the first part 5-1 described in the feature data D _{CHR —} 1 <g _R ^2> _1, the characteristic data _{D CHR_2} (i.e., the input feature data _{D CHR_IN)} to be described, the square mean of the gradation of the R sub-pixels of the image displayed on the second part 5-2 ^{_<g R} 2> _As the average value of 2, the square mean <g _R ² > _AVE of the gradation of the R subpixels of the entire image in the display area 3 of the LCD panel 2 is calculated. That is,
<G _R ² > _AVE = (<g _R ² > ₁ + <g _R ² > ₂ ) / 2 (4a)
Similarly, the mean square <g _G ² > _AVE and <g _B ² > _AVE of the gradation of the entire G subpixel and B subpixel of the image in the display area 3 of the LCD panel 2 are obtained by the following equations:
< _{G G} ² > _AVE = (<g _G ² > ₁ + <g _G ² > ₂ ) / 2 (4b)
<G _B ² > _AVE = (<g _B ² > ₁ + <g _B ² > ₂ ) / 2 (4c)

Furthermore, σ _{AVE_R} ² , σ _{AVE_G} ² , and σ _{AVE_B} ² are calculated by the following equations:
σ _{AVE_R} ² = <g _R ² > _AVE − (APL _{AVE_R} ) ² (5a)
^{_{σ AVE_G 2 = <g G 2}} > AVE - (APL AVE_G) 2 ··· (5b)
^{_{σ AVE_B 2 = <g B 2}} > AVE - (APL AVE_B) 2 ··· (5c)

It will be easily understood that APL _{AVE_R} , APL _{AVE_G} , APL _{AVE_B} , σ _{AVE_R} ² , σ _{AVE_G} ² , and σ _{AVE_B} ² can be calculated in the same manner by the full screen feature data calculation circuit 84 of the driver IC 4-2.

On the other hand, when the APL calculated as the average value of the luminance of each pixel and the root mean square of the luminance of the pixel are adopted as the feature amount exchanged between the driver ICs 4-1 and 4-2, the full screen feature data calculation is performed. The circuit 84 calculates the mean square of the APL and the luminance of the pixels for the entire image in the display area 3 of the LCD panel 2. Here, APL is defined as the average value of the luminance of the entire pixels of the image in the display area 3 of the LCD panel 2. The full-screen feature data calculation circuit 84 further calculates the luminance of the entire pixel of the image in the display area 3 of the LCD panel 2 from the APL of the entire image in the display area 3 of the LCD panel 2 and the root mean square of the luminance of the pixel. The variance σ ² is calculated. In this case, the current frame full-screen feature data D _{CHR_C} generated by the full-screen feature data calculation circuit 84 includes the following data:
(A) APL calculated for all pixels in the display area 3 of the LCD panel 2 (hereinafter referred to as “APL _AVE ”)
(B) Dispersion of luminance of all pixels in the display area 3 of the LCD panel 2 (hereinafter referred to as “σ _AVE ² ”).

Calculation of APL _AVE and σ _AVE ² in each of the driver ICs 4-1 and 4-2 is performed as follows. First, the full-screen feature data calculation circuit 84 of the driver IC 4-1 receives the feature data D _{CHR — 1} calculated by the feature data calculation circuit 81 of the driver IC 4-1 and the input feature data D _{CHR_IN} from the driver IC _4-2 . Feature data D _{CHR_2} (which is calculated by the feature data calculation circuit 81 of the driver IC 4-2) is supplied. The full-screen feature data calculation circuit 84 of the driver IC _4-1 describes the APL (APL ₁ ) of each pixel of the image displayed in the first part 5-1 described in the feature data D _{CHR — 1} and the feature data D _{CHR — 2.} APL _AVE is calculated as an average value of APL (APL ₂ ) of each pixel of the image displayed in the second portion 5-2 described in (that is, input feature data D _{CHR_IN} ). That is,
APL _AVE = (APL ₁ + APL ₂ ) / 2 (3d)

Further, the full-screen feature data calculation circuit 84 of the driver IC _4-1 describes the root mean square of the gradations of the R subpixels of the image displayed in the first portion 5-1 described in the feature data D _{CHR —} 1 <Y ^2. ₁ and the mean square of the gradations of the R sub-pixels of the image displayed in the second part 5-2 described in the feature data D _{CHR_2} (that is, the input feature data D _{CHR_IN} ) <Y ² > ₂ . As an average value, the mean square <Y ² > _AVE of the gradations of the R subpixels of the entire image in the display area 3 of the LCD panel 2 is calculated. That is,
<Y ² > _AVE = (<Y ² > ₁ + <Y ² > ₂ ) / 2 (4d)

Furthermore, σ _AVE ² is calculated by the following formula:
σ _AVE ² = <Y ² > _AVE − (APL _AVE ) ² (5d)

It will be easily understood that APL _AVE and σ _AVE ² can be calculated in the same manner by the full-screen feature data calculation circuit 84 of the driver IC 4-2.

Thus the current frame full-screen feature data _{D CHR_C} is calculated in both the driver IC4-1,4-2, the current frame is calculated whole screen feature data _{D CHR_C} is, the correction point data calculation and calculation result storage memory 72 To the circuit 73.

The communication state storage memory 85 receives the communication state notification data _{DST_IN} transmitted from another driver IC from the interface 20 and temporarily stores it. The communication status notification data _{DST_IN} is data indicating whether or not the other driver IC has received the input feature data _{DCHR_IN} normally, and includes communication ACK data or communication NG data. The communication status notification data _{DST_IN} stored in the communication status storage memory 85 is sent to the communication confirmation circuit 86.

Communication confirmation circuit 86, the communication state notification data _{D ST_IN} received from the communication state notification data _{D ST_OUT} the communication state storage memory 85 received from the inter-chip communication detection circuit 83, the communication between the driver IC4-1,4-2 It is determined whether or not the feature data has been exchanged normally. When both the communication status notification data _{DST_OUT} and the communication status notification data _{DST_IN} are communication ACK data in a certain frame period, the communication confirmation circuit 86 performs communication between the driver ICs _4-1 and _{4-2 in} the frame period. It is determined that the feature data has been exchanged normally, and the communication confirmation signal _SCMF is asserted. On the other hand, when at least one of the communication status notification data _{DST_OUT} and the communication status notification data _{DST_IN} is communication NG data in a certain frame period, the communication confirmation circuit 86 determines whether the communication is performed between the driver ICs _4-1 and _{4-2 in} the frame period. It is determined that the feature data has not been exchanged normally in the communication, and the communication confirmation signal _SCMF is negated.

Returning to Figure 12, the operation result storing memory 72 has a function of storing captures whole screen feature data _{D CHR_C} in response to the communication confirmation signal _{S CMF.} In the frame period in which the communication confirmation signal _SCMF is asserted (that is, the frame period in which communication between the driver ICs _{4-1 and 4-2} is normally performed), the full-screen feature data D _{CHR_C} is stored in the calculation result storage memory. 72. On the other hand, in the frame period in which the communication confirmation signal _SCMF is negated, the contents of the calculation result storage memory 72 are not updated. That is, at the start of a certain frame period, the calculation result storage memory 72 is a frame period before the frame period and in the last frame period in which communication between the driver ICs 4-1 and 4-2 is normally performed. The calculated full-screen feature data D _{CHR_C} is stored. Hereinafter, the full screen feature data D _{CHR_C} stored in the calculation result storage memory 72 will be _referred to as previous frame full screen feature data D _{CHR_P} . The previous frame full screen feature data D _{CHR_P} is supplied to the correction point data calculation circuit 73.

_Note that the previous-frame full-screen feature data D _{CHR_P} is not necessarily the full-screen feature data D _{CHR_C} calculated for the frame period immediately before the current frame period. For example, when the communication between the driver ICs _{4-1 and 4-2} is not normally performed over two frame periods including the current frame period, the full-screen feature data D _{CHR_C} calculated for the two frame periods before is _{displayed in the} entire previous frame. It is stored as screen feature data D _{CHR_P} and supplied to the correction point data calculation circuit 73.

Correction point data calculation circuit 73 is schematically operates as follows: the correction point data calculation circuit 73, the total current frame whole screen feature data D _{CHR_C} or previous frame in response to the communication confirmation signal S _CMF select one of the screen feature data _{D CHR_P,} it supplies the correction point data set CP_selG ^k corresponding to full-screen feature data selected in the approximate operation and correction circuit 63. Specifically, the correction point data calculation circuit 73 is in the frame period in which the communication confirmation signal _SCMF is asserted (that is, in the frame period in which the communication between the driver ICs 4-1 and 4-2 is normally performed). The correction point data set CP_sel ^k is determined using the current frame full-screen feature data D _{CHR_C} . On the other hand, in the frame period in which the communication confirmation signal _SCMF is negated (that is, in the frame period in which the communication between the driver ICs 4-1 and 4-2 is not normally performed), the calculation result storage memory 72 stores the communication confirmation signal SCMF. The correction point data set CP_sel ^k is determined using the previous frame full-screen feature data D _{CHR_P} .

Such an operation is performed in the correction point data calculation circuits 73 of the driver ICs 4-1 and 4-2. Thereby, in the frame period in which the communication between the driver ICs 4-1 and 4-2 is not normally performed, the communication between the driver ICs 4-1 and 4-2 is performed in each of the driver ICs 4-1 and 4-2. The full frame feature data D _{CHR_P} of the previous frame of the latest frame period in which the correction is normally performed is used to determine the correction point data set CP_sel ^k . Therefore, the driver ICs 4-1 and 4-2 perform different correction calculations, and the boundary between the first part 5-1 and the second part 5-2 of the display area 3 of the LCD panel 2 can be visually recognized. The problem of becoming can be solved.

  FIG. 16 is a block diagram showing a configuration of the correction point data calculation circuit 73. The correction point data calculation circuit 73 includes a feature data selection circuit 87, a correction point data set storage register 88a, an interpolation calculation / selection circuit 88b, and a correction point data addition / subtraction circuit 89.

Wherein the data selection circuit 87 has a function of selecting one of the communication confirmation signal _{S CMF} current frame full-screen feature data in response to _{D CHR_C} or previous frame whole screen feature data _{D CHR_P.} The feature data selection circuit 87 outputs APL data D _APL indicating APL included in the selected full-screen feature data and distributed data D _σ2 indicating variance σ ² included in the selected full-screen feature data. To do. The APL data D _APL is sent to the interpolation calculation / selection circuit 88b, and the dispersion data _Dσ2 is sent to the correction point data addition / subtraction circuit 89.

Here, when the combination of APL and the mean square of the gradation of the sub-pixel calculated for each color is adopted as the feature amount exchanged between the driver ICs 4-1 and 4-2, the APL data D _APL is It is generated and _{APL ave_R} calculated for the whole of the R sub-pixels in the display area 3 of the LCD panel 2, and _{APL AVE_G} calculated for G sub-pixel, as data describing the calculated _{APL AVE_B} for B subpixels The Here, the APL data D _APL is generated as 3M-bit data representing APL _{AVE_R} , APL _{AVE_G} , and APL _{AVE_B} with M bits. Moreover, distributed data D _{.sigma. @ 2} is a variance sigma _{ave_R} ² gradation calculated for the whole of the R sub-pixels in the display area 3 of the LCD panel 2, and variance sigma _{AVE_G} ² gradation calculated for G sub-pixels, It is generated as data describing the gradation variance σ _{AVE — B} ² calculated for the B subpixel.

On the other hand, when the combination of the APL calculated as the average value of the luminance of each pixel and the root mean square of the luminance of the pixel is adopted as the feature quantity exchanged between the driver ICs 4-1 and 4-2, the APL data D _{The APL} includes APL _AVE calculated as the average value of the luminance of each pixel for the entire display area 3 of the LCD panel 2, and the variance data D _σ2 is calculated for the entire pixels of the display area 3 of the LCD panel 2. Brightness variance σ _AVE ² . Here, the APL data D _APL is generated as data representing APL _AVE with M bits.

Here, the APL data D _APL is also sent to the above-described backlight luminance adjustment circuit 69 and used for generation of the luminance control signal S _PWM . That is, the luminance of the LED backlight 8 is controlled according to the APL data D _APL . When a combination of APL and the mean square of the gradation of the sub-pixel calculated for each color is adopted as a feature amount exchanged between the driver ICs _4-1 and _4-2 , APL _{AVE_R} , APL _{AVE_G} , APL _{AVE_B} Are subjected to RGB-YUV conversion, and a luminance control signal S _PWM is generated in accordance with the luminance data Y _AVE obtained by the RGB-YUV conversion. That is, the luminance of the LED backlight 8 is controlled according to the luminance data _YAVE . On the other hand, when the combination of the APL calculated as the average value of the luminance of each pixel and the root mean square of the luminance of the pixel is adopted as the feature quantity exchanged between the driver ICs 4-1 and 4-2, the APL data D _A luminance control signal S _PWM is generated in accordance with APL _AVE described in APL. That is, the luminance of the LED backlight 8 is controlled according to APL _AVE .

The correction point data set storage register 88a includes a plurality of correction point data sets CP # used as original data for calculating correction point data sets CP_sel ^R , CP_sel ^G , CP_sel ^B that are finally supplied to the approximate calculation correction circuit 63. 1 to CP # m are stored. The correction point data sets CP # 1 to CP # m correspond to different gamma values γ, and each of the correction point data sets CP # 1 to CP # m is composed of correction point data CP0 to CP5.

（２）γ≧１の場合

ここで、Ｄ_ＩＮ ^ＭＡＸは、画像データＤ_ＩＮｉの許容最大値であり、Ｄ_ＯＵＴ ^ＭＡＸは、補正後画像データＤ_ＯＵＴの許容最大値である。Ｋは、下記式：
Ｋ＝（Ｄ_ＩＮ ^ＭＡＸ＋１）／２， ・・・（７）
で与えられる定数である。また、Ｇａｍｍａ［ｘ］は、ガンマ補正の厳密式を表す関数であり、下記式によって定義される：

Correction point data CP0 to CP5 of the correction point data set CP # j corresponding to a certain gamma value γ are calculated as follows.
(1) When γ <1

(2) When γ ≧ 1

Here, D _IN ^MAX is an allowable maximum value of the image data D _INi , and D _OUT ^MAX is an allowable maximum value of the corrected image data D _OUT . K is the following formula:
K = (D _IN ^MAX +1) / 2, (7)
Is a constant given by. Gamma [x] is a function that represents an exact expression for gamma correction, and is defined by the following expression:

In the present embodiment, the correction point data sets CP # 1 to CP # m are expressed as the correction point data set CP # j arbitrarily selected from the correction point data sets CP # 1 to CP # m as the j increases. 8) is determined to be large. That is, if the gamma value determined for the correction point data set CP # j is γ _j ,
γ ₁ <γ ₂ <... <γ _m-1 <γ _m (9)

The number of correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a is 2 ^{M- (N-1)} sets. Here, M is the number of bits used to describe APL _{AVE_R} , APL _{AVE_G} , and APL _{AVE_B} in the APL data D _APL as described above, and N is smaller than M and 2 or more. Is a predetermined integer. That is, m = 2 ^{M− (N−1)} . The correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a may be supplied from the application processor 1 to each driver IC 4-i as an initial setting.

Interpolation calculation / selection circuit 88b has APL data _{D APL} correction point data set CP_L depending on ^R, CP_L ^G, the function of determining the CP_L ^B. Correction point data set CP_L ^R, CP_L ^G, CP_L ^B eventually approximate operation and correction circuit correction point data set supplied to 63 CP_sel ^R, CP_sel ^G, with intermediate data which is used to calculate the CP_selG ^B Each includes correction point data CP0 to CP5. In the following, the correction point data sets CP_L ^R, CP_L ^G, CP_L ^B are collectively, may be described as the correction point data set CP_L ^k.

Specifically, when the APL data D _APL is data describing APL _{AVE_R} , APL _{AVE_G} , and APL _{AVE_B} calculated for each of the R sub-pixel, the G sub-pixel, and the B sub-pixel, in one embodiment, an interpolation operation is performed. / Selection circuit 88b selects any one of the above-described correction point data sets CP # 1 to CP # m according to APL _{AVE_k} (k = “R”, “G” or “B”), and selects the selected correction point The data set may be determined as a correction point data set CP_L ^k (k = “R”, “G” or “B”).

Instead, the interpolation calculation / selection circuit 88b may determine the correction point data set CP_L ^k (k = “R”, “G” or “B”) as follows. The interpolation calculation / selection circuit 88b is configured to select two of the correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a in accordance with APL _{AVE_k} described in the APL data D _APL. Two correction point data sets: correction point data sets CP # q and CP # (q + 1) are selected. q is an integer of 1 or more and m-1. Furthermore interpolation calculation / selection circuit 88b is a correction point data CP0~CP5 the correction point data set CP_L ^k, respectively, the two correction point data set CP # q selected, correction points CP # (q + 1) data CP0~CP5 It is calculated by interpolation calculation. The correction point data CP0~CP5 the correction point data set CP_L ^k, 2 two correction point data set CP # q selected, be calculated by interpolation calculation of the correction point data CP0~CP5 of CP # (q + 1), the correction point This is useful in that the gamma value used for gamma correction can be finely adjusted even if the number of correction point data sets CP # 1 to CP # m stored in the data set storage register 88a is small.

On the other hand, when the APL _AVE calculated as the average value of the luminance of the pixel is described in the APL data D _APL , the interpolation calculation / selection circuit 88b performs the above-described correction point data sets CP # 1 to CP # according to the APL _AVE. select one of #m, the correction point data set selected, the correction point data sets CP_L ^R, CP_L ^G, it may be determined as CP_L ^B. In this case, the correction point data sets CP_L ^R, CP_L ^G, CP_L ^B are both consistent with the correction point data set selected equal to each other.

Alternatively, interpolation calculation / selection circuit 88b is as follows correction point data set CP_L ^R, CP_L ^G, it may be determined CP_L ^B. The interpolation calculation / selection circuit 88b is configured to select two of the correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a in accordance with APL _AVE described in the APL data D _APL. Two correction point data sets: correction point data sets CP # q and CP # (q + 1) are selected. q is an integer of 1 or more and m-1. Furthermore interpolation calculation / selection circuit 88b, the correction point data sets CP_L ^R, CP_L ^G, each correction point data CP0~CP5 of CP_L ^B, respectively, the two correction point data set CP # q selected, CP # (q + 1 ) Of the correction point data CP0 to CP5. Again, the correction point data sets CP_L ^R, CP_L ^G, CP_L ^B are equal to each other. Correction point data set CP_L ^R, CP_L ^G, calculates the correction point data CP0~CP5 of CP_L ^B, 2 two correction point data set CP # q selected by the interpolation calculation of the correction point data CP0~CP5 of CP # (q + 1) This makes it possible to finely adjust the gamma value used for gamma correction even if the number of correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a is small. Useful in terms.

The correction point data set CP_L described ^R, CP_L ^G, the interpolation calculations performed in determining the CP_L ^B will be described in detail later.

The correction point data sets CP_L ^R , CP_L ^G , CP_LB determined by the interpolation calculation / selection circuit 88 ^b are sent to the correction point data addition / subtraction circuit 89.

The correction point data add-subtract circuit 89, the distributed data D _{.sigma. @ 2} Based on the correction point data set CP_L ^R sent from the feature data selection circuit 87, CP_L ^G, modify the CP_L ^B, is supplied to the final approximate operation and correction circuit 63 Correction point data sets CP_sel ^R , CP_sel ^G , CP_sel ^B are calculated.

In particular, distributed data D _{.sigma. @ 2} is a variance sigma _{ave_R} ² gradation calculated for the whole of the R sub-pixels in the display area 3 of the LCD panel 2, G subpixel distribution of gradation sigma calculated for _{AVE_G} ² And the gradation variance σ _{AVE — B} ² calculated for the B subpixel, the correction point data adding / subtracting circuit 89 corrects the correction point data sets CP_sel ^R and CP_sel as follows. ^G and CP_sel ^B are calculated. The correction point data add-subtract circuit 89 on the basis of the variance sigma _{ave_R} ² calculated for R sub-pixels, modifies the correction point data CP1, CP4 of the correction point data set CP_L ^R. Modified correction point data CP1, CP4 is used as the correction point data CP1, CP4 of the correction point data set CP_selG ^R. The correction point data CP0 of correction point data set CP_L ^R, CP2, CP3, CP5 is directly used as the correction point data CP0, CP2, CP3, CP5 of the correction point data set CP_selG ^R.

Similarly, the correction point data add-subtract circuit 89, based on the variance σ _{AVE_G} ² gradation calculated for G sub-pixels, modifies the correction point data CP1, CP4 of the correction point data set CP_L ^G. Modified correction point data CP1, CP4 is used as the correction point data CP1, CP4 of the correction point data set CP_selG ^G. Furthermore, the correction point data add-subtract circuit 89, based on the variance σ _{AVE_B} ² of the calculated tone for B sub-pixels, modifies the correction point data CP1, CP4 of the correction point data set CP_L ^B. The corrected correction point data CP1 and CP4 are used as the correction point data CP1 and CP4 of the correction point data set CP_sel ^B. Correction point data set CP_L ^G, the correction point data CP0 of CP_L ^B, CP2, CP3, CP5 are intact, the correction point data sets CP_selG ^G, it is used as the correction point data CP0, CP2, CP3, CP5 of CP_selG ^B.

On the other hand, the distributed data D _{.sigma. @ 2} is, when produced as data that describes the variance sigma _AVE ² of luminance of the entire pixels in the display area 3 of the LCD panel 2, the correction point data add-subtract circuit 89, variance sigma _AVE ² based on, it modifies the correction point data sets CP_L ^R, CP_L ^G, the correction point data CP1, CP4 of CP_L ^B. The corrected correction point data CP1 and CP4 are used as correction point data CP1 and CP4 of the correction point data sets CP_sel ^R , CP_sel ^G and CP_sel ^B. The correction point data sets CP_L ^R, CP_L ^G, the correction point data CP0, CP2, CP3, CP5 of CP_L ^B is intact, the correction point data sets CP_selG ^R, CP_selG ^G, the correction point data CP0 of CP_selG ^B, CP2, CP3 , CP5. Note that in this case, the correction point data sets CP_L ^R , CP_L ^G , CP_L ^B are equal to each other, and thus the resulting correction point data sets CP_sel ^R , CP_sel ^G , CP_sel ^B are also equal to each other.

Correction point data set CP_L ^R, CP_L ^G, the correction point data set CP_selG ^R by modification of CP_L ^B, CP_sel ^G, the calculation of CP_selG ^B will be described later in detail.

  Next, the operation of the liquid crystal display device of the present embodiment, particularly the operation of the driver ICs 4-1 and 4-2 will be described. FIG. 17 is a flowchart showing the operation of the driver ICs 4-1 and 4-2 in each frame period.

In the feature data calculation circuit 81 of the feature data calculation circuit 71 of the driver ICs _4-1 and _4-2 , the image data D _IN1 and D _IN2 are analyzed, respectively, and the feature data D _{CHR_1} and D _{CHR_2} are calculated (step S01). . As described above, the characteristic data _{D CHR_1} is data indicating the characteristic quantity of image displayed in the first part 5-1 of the LCD panel 2, it is calculated from the image data _{D IN1} supplied to the driver IC4-1 The Similarly, feature data _{D CHR_2} is data indicating the characteristic quantity of image displayed in the first part 5-2 of the LCD panel 2, it is calculated from the image data _{D IN2} supplied to the driver IC4-2.

Subsequently, the feature data D _{CHR_1} calculated in the driver IC _4-1 is sent from the driver IC 4-1 to the driver IC 4-2, and the feature data calculated in the driver IC 4-2 from the driver IC 4-2 to the driver IC 4-1. Data D _{CHR_1} is sent (step S02). Specifically, the driver IC 4-1 transmits output feature data D _{CHR_OUT} obtained by adding an error detection code to the feature data D _{CHR — 1} calculated by the feature data calculation circuit 81 to the driver IC 4-2. The error detection code is added by the error detection code addition circuit 82. The driver IC 4-2 receives the output feature data D _{CHR_OUT} transmitted from the driver IC _4-1 as the input feature data D _{CHR_IN} . Similarly, the driver IC 4-2 transmits output feature data D _{CHR_OUT} obtained by adding an error detection code to the feature data D _{CHR_2} calculated by the feature data calculation circuit 81 to the driver IC 4-1. The driver IC 4-1 receives the output feature data D _{CHR_OUT} transmitted from the driver IC _4-2 as the input feature data D _{CHR_IN} .

Inter-chip communication detection circuit 83 of the driver IC4-1, using the error detecting code added to the input feature data _{D CHR_IN,} determining whether the input feature data _{D CHR_IN} transmitted from the driver IC4-2 has been received normally (Step S03).

Specifically, when the inter-chip communication detection circuit 83 of the driver IC 4-1 does not detect a data error in the input feature data D _{CHR_IN} (or when an error correction code is used, uncorrectable data). If no error is detected), it is determined that the input feature data D _{CHR_IN} has been normally received, and communication ACK data is output as communication state notification data D _{ST_OUT} . Communication state notification data _{DST_OUT} including communication ACK data is sent from driver IC 4-1 to driver IC 4-2. That is, communication ACK data is sent from the driver IC 4-1 to the driver IC 4-2 (step S04). The state where the communication ACK data is sent from the driver IC 4-1 to the driver IC 4-2 will be referred to as “communication state # 1” below.

On the other hand, when a data error is detected (or when an error correction code is used, an error that cannot be corrected) is detected, the inter-chip communication detection circuit 83 of the driver IC 4-1. _Outputs communication NG data as communication status notification data _{DST_OUT} . Communication state notification data _{DST_OUT} including communication NG data is sent from the driver IC 4-1 to the driver IC 4-2. That is, communication NG data is sent from the driver IC 4-1 to the driver IC 4-2 (step S05). Hereinafter, a state in which the communication NG data is sent from the driver IC 4-1 to the driver IC 4-2 will be referred to as “communication state # 2”.

Similarly, inter-chip communication detection circuit 83 of the driver IC4-2, using the error detecting code added to the input feature data _{D CHR_IN,} input feature data _{D CHR_IN} transmitted from the driver IC4-1 is received normally (Step S06).

Specifically, the inter-chip communication detection circuit 83 of the driver IC 4-2 does not detect a data error in the input feature data D _{CHR_IN} (or if an error correction code is used, uncorrectable data). If no error is detected), it is determined that the input feature data D _{CHR_IN} has been normally received, and communication ACK data is output as communication state notification data D _{ST_OUT} . Communication state notification data _{DST_OUT} including communication ACK data is sent from the driver IC 4-2 to the driver IC 4-1. That is, communication ACK data is sent from the driver IC 4-2 to the driver IC 4-1 (step S07). The state in which the communication ACK data is sent from the driver IC 4-2 to the driver IC 4-1 will be referred to as “communication state # 3” below.

On the other hand, when a data error is detected (or when an error correction code is used, an error that cannot be corrected) is detected, the inter-chip communication detection circuit 83 of the driver IC 4-2. _Outputs communication NG data as communication status notification data _{DST_OUT} . Communication state notification data _{DST_OUT} including communication NG data is sent from the driver IC 4-2 to the driver IC 4-1. That is, communication NG data is sent from the driver IC 4-2 to the driver IC 4-1 (step S08). The state in which the communication NG data is sent from the driver IC 4-2 to the driver IC 4-1 will be referred to as “communication state # 4” below.

In each frame period, the following four state combinations can occur:
Combination A: Combination of communication states # 1, # 3 Combination B: Combination of communication states # 1, # 4 Combination C: Combination of communication states # 2, # 3 Combination D: Combination of communication states # 2, # 4

When the state of the combination A occurs (that is, when communication ACK data is sent from the driver IC 4-1 to the driver IC 4-2 and communication ACK data is sent from the driver IC 4-2 to the driver IC 4-1). In both the driver ICs _{4-1 and 4-2,} the current frame full-screen feature data D _{CHR_C} calculated in the current frame period is selected. Further, a correction point data set CP_sel ^k is determined according to the current frame full-screen feature data D _{CHR_C} , and the determined correction point data set CP_sel ^k is sent to the approximate calculation correction circuit 63 and image data D _IN1 , D Used for _IN2 correction calculation. At this time, the current frame full-screen feature data D _{CHR_C} is stored in the calculation result storage memory 72.

Specifically, when the state of the combination A occurs, both the communication status notification data D _{ST_OUT} and D _{ST_IN} supplied to the communication confirmation circuit 86 are communication ACK data in both the driver ICs _4-1 and _4-2. become. Each of the communication confirmation circuits 86 of the driver ICs _4-1 and _4-2 may recognize that the state of the combination A has occurred because both the communication state notification data D _{ST_OUT} and D _{ST_IN} are communication ACK data. it can. In this case, the communication confirmation circuit 86 of the driver ICs 4-1 and 4-2 asserts the communication confirmation signal _SCMF . In response to the communication confirmation signal _{S CMF} is asserted, in both driver IC4-1,4-2, feature data selection circuit 87 of the correction point data calculation circuit 73, a current frame full-screen feature data _{D CHR_C} select. Correction point data calculation circuit 73, in response to the current frame full-screen feature data _{D CHR_C} selected, determines the correction point data set CP_selG ^k. In addition, the operation result storing memory 72, in response to the communication confirmation signal S _CMF is asserted, stores capture the current frame full-screen feature data D _{CHR_C.} As a result, the previous frame full-screen feature data D _{CHR_P} stored in the calculation result storage memory 72 is updated to the current frame full-screen feature data D _{CHR_C} calculated in the current frame period.

On the other hand, when a state other than the combination A occurs (that is, when the state of the combination B, C, or D occurs), the previous frame full-screen feature data D _{CHR_P} is selected in both the driver ICs _{4-1 and 4-2.} Is done. Here, when a state other than the combination A occurs, that is, when the state of the combination B, C, or D occurs, from the driver IC 4-1 to the driver IC 4-2 and / or from the driver IC 4-2. This means that communication NG data has been sent to the driver IC 4-1. Further, the correction point data set CP_sel ^k is determined in accordance with the previous frame full-screen feature data D _{CHR_P} , and the determined correction point data set CP_sel ^k is sent to the approximate calculation correction circuit 63 to receive the image data D _IN1 , D Used for _IN2 correction calculation. At this time, the previous frame full-screen feature data D _{CHR_P} stored in the calculation result storage memory 72 is not updated.

Specifically, when the state of the combination B, C, or D occurs, at least the communication state notification data D _{ST_OUT} and D _{ST_IN} supplied to the communication confirmation circuit 86 in both the driver ICs _4-1 and _4-2 . One becomes communication NG data. Each of the communication confirmation circuits 86 of the driver ICs _4-1 and _4-2 indicates that the state of the combination B, C, or D has occurred because at least one of the communication state notification data D _{ST_OUT} and D _{ST_IN} is communication NG data. Can be recognized. In this case, the communication confirmation circuit 86 of the driver IC4-1,4-2 negates the communication confirmation signal _{S CMF.} In response to the communication confirmation signal S _CMF being negated, the feature data selection circuit 87 of the correction point data calculation circuit 73 _{receives the} previous frame full screen feature data D _{CHR_P} in both the driver ICs _4-1 and _4-2 . select. Correction point data calculation circuit 73, according to the frame full-screen feature data _{D CHR_P} before the selected determines the correction point data set CP_selG ^k. At this time, the operation result storing memory 72, the communication confirmation signal S _CMF is negated, held without updating the previous frame full-screen feature data D _{CHR_P.}

By the process described above, the combination A, B, C, in any case and D, so that the correction point data set CP_selG ^k is determined. The approximate calculation correction circuit 63 of the driver IC 4-1 performs gamma correction corresponding to the gamma curve determined by the correction point data set CP_selk on the image data D _IN <b> ¹ by an arithmetic expression, and outputs corrected image data D _OUT . To do. Similarly, the approximate operation and correction circuit 63 of the driver IC4-2 is the image data _{D IN2,} the correction point data set CP_selG ^k corrected corresponding gamma correction to the gamma curve performed by arithmetic expression image data determined by the D _OUT is output. Each of the data line driving circuits 66 of the driver ICs 4-1 and 4-2 responds to the output corrected image data _DOUT (more precisely, the reduced color image data generated from the corrected image data _DOUT). In response to _{DOUT_D} , the data lines of the first portion 5-1 and the second portion 5-2 of the display area 3 of the LCD panel 2 are driven.

  FIG. 18 shows a comparison between the operation when the feature data communication is normally performed between the driver ICs 4-1 and 4-2 and the operation when the feature data is not normally transmitted. FIG. 18 illustrates only the APL calculated as the average value of the pixel luminances among the feature amounts that can be described in the feature data exchanged between the driver ICs 4-1 and 4-2. The same processing is also performed for these parameters (for example, the APL calculated for each color, the mean square of the gradation of the sub-pixel, and the mean square of the luminance of the pixel).

The operation in the case where the feature data communication is normally performed between the driver ICs 4-1 and 4-2 is illustrated in the left column of FIG. The operation when the feature data is normally communicated between the driver ICs 4-1 and 4-2 is as follows. Driver IC4-1 from the image data _{D IN1} that has been sent to it, calculates the feature amount of the image displayed in the first part 5-1 of the display area 3 of the LCD panel 2. Similarly, driver IC4-2 from the image data _{D IN2} that has been sent to it, calculates the feature amount of the image displayed on the second part 5-2 of the display area 3 of the LCD panel 2. In the example of FIG. 13, the driver IC 4-1 calculates the APL of the image displayed in the first part 5-1, as 104, and the driver IC 4-2 calculates the APL of the image displayed in the second part 5-2. Is calculated as 176.

  Further, the driver IC 4-1 transmits feature data indicating the calculated feature amount (the feature amount of the image displayed in the first portion 5-1) to the driver IC 4-2. Is transmitted to the driver IC 4-1, which indicates the feature amount calculated by (the feature amount of the image displayed in the second portion 5-2).

The driver IC 4-1 calculates the feature amount calculated by itself (that is, the feature amount of the image displayed in the first portion 5-1) and the feature amount indicated in the feature data received from the driver IC 4-2 (that is, The feature amount of the entire image displayed in the display area 3 of the LCD panel 2 is calculated from the feature amount of the image displayed in the second portion 5-2. Here, regarding APL, the average value APL _AVE of the APL of the image displayed in the first portion 5-1 and the APL of the image displayed in the second portion 5-2 is the image of the image displayed in the display area 3. The overall APL. In the example of FIG. 18, since the APL of the image displayed in the first part 5-1 is 104 and the APL of the image displayed in the second part 5-2 is 176, the driver IC 4-1 The value APL _AVE is calculated as 140.

Similarly, the driver IC 4-2 calculates the feature amount calculated by itself (that is, the feature amount of the image displayed in the second portion 5-2) and the feature indicated by the feature data received from the driver IC 4-1. From the amount (that is, the feature amount of the image displayed in the second portion 5-1), the entire feature amount of the image displayed in the display area 3 of the LCD panel 2 is calculated. For APL, an average value APL _AVE of the APL of the image displayed in the first portion 5-1 and the APL of the image displayed in the second portion 5-2 is calculated. In the example of FIG. 13, the driver IC 4-2 calculates the average value APL _AVE as 140 in the same manner as the driver IC 4-1.

The driver IC 4-1 performs a correction operation on the image data D _IN1 according to the overall feature amount (average value APL _{AVE for} APL) of the image displayed on the display area 3 of the LCD panel 2 calculated by the driver IC 4-1. And the pixels provided in the first portion 5-1 are driven in accordance with the corrected image data D _OUT obtained by the correction calculation. Similarly, driver IC4-2 performs correction operation on the image data D _IN2 depending on the overall characteristic amounts of the image displayed on the display area 3 that it has calculated, the corrected obtained by the correction calculation driving a pixel provided in the second portion 5-2 in accordance with the image data _{D OUT.}

The operation when the feature data communication between the driver ICs 4-1 and 4-2 is not normally performed is illustrated in the right column of FIG. The operation when the feature data is not normally communicated between the driver ICs 4-1 and 4-2 is as follows. Calculating driver IC4-1,4-2 is, from the image data _{D IN1, D IN2,} first part 5-1 of the display area 3 of the LCD panel 2, a feature value of the image displayed on the second part 5-2 The operation of transmitting the feature data indicating the calculated feature amount from one to the other is the same as when the feature data is normally communicated.

  Here, it is assumed that the communication of the feature data from the driver IC 4-1 to the driver IC 4-2 is not normally performed. For example, although the APL of the image of the first part 5-1 originally calculated by the driver IC 4-1 is 104, the feature data received by the driver IC 4-2 is the data of the first part 5-1. Assume that the APL of the image indicates 12.

In this case, the driver IC 4-2 does not correctly calculate the entire APL of the image displayed in the display area 3 of the LCD panel 2. However, since the driver IC 4-2 can know by error detection that the feature data has not been normally communicated from the driver IC 4-1 to the driver IC 4-2, the driver IC 4-2 is stored in the calculation result storage memory 72. a correction operation is performed on the image data D _IN2 by using the feature amounts shown in the previous frame whole screen feature data D _{CHR_P} you are.

Further, the driver IC4-1, from the communication state notification data _{D ST_IN} received from the driver IC4-2, communication feature data from the driver IC4-1 to the driver IC4-2 is to know that it was not successful Therefore, the correction calculation is performed on the image data D _IN1 using the feature amount indicated in the previous frame full-screen feature data D _{CHR_P} stored in the calculation result storage memory 72. Driver IC4-1,4-2, according to the corrected image data _{D OUT} obtained by the correction calculation, respectively, the first portion 5-1, and drives the pixels provided in the second part 5-2 .

As described above, in this embodiment, when the feature data communication between the driver ICs 4-1 and 4-2 is not normally performed, the previous frame stored in the calculation result storage memory 72. Since the correction calculation is performed using the feature amount indicated in the full-screen feature data D _{CHR_P} , the first portion 5-1 and the second portion 2 of the display area 3 of the LCD panel 2 can be used even when communication is not normally performed. It can prevent that the boundary of the part 5-2 becomes visually recognizable.

FIG. 19A shows correction point data calculation in the case where a combination of the APL and the mean square of the gradation of the sub-pixel calculated for each color is adopted as the feature amount exchanged between the driver ICs 4-1 and 4-2. 7 is a flowchart showing an operation of a circuit 73. In this case, the current frame full-screen feature data D _{CHR_C} and the previous frame full-screen feature data D _{CHR_P} are all APL data D _APL describing APL _{AVE_R} , APL _{AVE_G} , APL _{AVE_B} , and σ _{AVE_R} ² , σ _{AVE_R} ^2. _Note that the distribution data D _σ ² describing σ _{AVE — R} ² is included. Correction point data calculation circuit 73, from the current frame full-screen feature data _{D CHR_C} or previous frame whole screen feature data _{D CHR_P} with such contents, determines the correction point data set CP_selG ^k supplied to the approximate operation and correction circuit 63 .

First, in response to the communication confirmation signal _{S CMF} transmitted from the communication confirmation circuit 86, one of the current frame full-screen feature data _{D CHR_C} or previous frame whole screen feature data _{D CHR_P} is selected by the feature data selection circuit 87 ( Step S11A). The feature data selected in step S11A is hereinafter referred to as selected feature data. _{Regardless of whether the} selected feature data is the current frame full screen feature data D _{CHR_C} or the previous frame full screen feature data D _{CHR_P} , the selected feature data is APL data D _APL describing APL _{AVE_R} , APL _{AVE_G} , APL _{AVE_B} , and _Note that the distribution data D _σ2 describing σ _{AVE_R} ² , σ _{AVE_R} ² , and σ _{AVE_R} ² are included.

Further, the gamma value is determined by the interpolation calculation / selection circuit 88b according to the APL data D _APL included in the selected feature data (step S12A). The gamma value is determined for each color (that is, for each of the R subpixel, the G subpixel, and the B subpixel). Gamma values for the red or R sub-pixel gamma ^R, the gamma value gamma ^G for green or G subpixels, the gamma value gamma ^B for blue or B subpixels, _{respectively,} APL _{AVE_R,} APL _{AVE_G,} the larger the _{APL AVE_B} It is determined to be larger. The gamma values γ ^R , γ ^G , γ ^G are determined, for example, by the following formula:
γ ^R = γ _STD ^R + APL _{AVE_R} · η ^R (10a)
γ ^G = γ _STD ^G + APL _{AVE_G} · η ^G (10b)
γ ^B = γ _STD ^B + APL _{AVE_B} · η ^B (10c)
Here, γ _STD ^R , γ _STD ^G , and γ _STD ^B are reference gamma values, which are predetermined constants. γ _STD ^R , γ _STD ^G , and γ _STD ^B may be the same or different from each other. Further, η ^R , η ^G , and η ^B are predetermined proportionality constants. η ^R , η ^G , and η ^B may be the same or different from each other.

After the gamma values γ ^R , γ ^G , and γ ^B are determined, correction point data sets CP_L ^R , CP_L ^G , CP_L ^B according to the gamma values γ ^R , γ ^G , γ ^B by the interpolation calculation / selection circuit 88b. Is determined (step S13A).

In one embodiment, one of the correction point data sets CP # 1 to CP # m described above is selected according to APL _{AVE_k} (k = “R”, “G” or “B”), and the selected correction point data is selected. The set may be determined as a correction point data set CP_L ^k (k = “R”, “G” or “B”). FIG. 20 is a graph for explaining the relationship between APL _{AVE_k} and γ ^k and the correction point data set CP_L ^k when the correction point data set CP_L ^k is determined in this way. The larger the APL _{AVE_k} , the larger the gamma value γ ^k is set, and the correction point data set CP # j having a larger j value is selected.

In another embodiment, the correction point data set CP_L ^k (k = “R”, “G” or “B”) may be determined as follows. First, out of the correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a according to the upper (MN) bits of APL _{AVE_k} described in the APL data D _APL. These two correction point data sets: correction point data sets CP # q and CP # (q + 1) are selected. Here, as described above, M is the number of bits of APL _{AVE_k} , and N is a predetermined constant. Q is an integer of 1 to m-1. The larger the APL _{AVE_k} , the larger the gamma value γ ^k is set, and the correction point data sets CP # q and CP # (q + 1) that have a larger q value are selected.

Furthermore, the correction point data set CP_L ^k of the correction point data CP0 to CP5, respectively, are calculated by interpolation calculation of the correction point data CP0 to CP5 of the two correction point data set CP # q selected, CP # (q + 1) . More specifically, the correction point data sets CP0 to CP5 of the correction point data set CP_L ^k (k is any of “R”, “G”, and “B”) are the two selected correction point data sets CP # q. , CP # (q + 1) is calculated from the correction point data CP0 to CP5 by the following equation.
CPα_L ^k = CPα (#q) +
{(CPα (# q + 1) −CPα (#q) / 2 ^N } × APL _{AVE_k} [N−1: 0],
(11)
α: integer from 0 to 5, CPα_L ^k : correction point data CPα of the correction point data set CP_L ^k
CPα (#q): Correction point data CPα of the selected correction point data set CP # q
CPα (# q + 1): Correction point data CPα of the selected correction point data set CP # (q + 1)
APL _{AVE_k} [N-1: 0]: Lower N bits of APL _{AVE_k}

FIG. 21 is a graph for explaining the relationship between APL _{AVE_k} and γ ^k and the correction point data set CP_L ^k when determined in this way. The larger the APL _{AVE_k} , the larger the gamma value γ ^k is set, and the correction point data sets CP # q and CP # (q + 1) that have a larger q value are selected. The correction point data set CP_L ^k is determined so as to correspond to a gamma value that is an intermediate value between the gamma values γ _q and γ _{q + 1} corresponding to the correction point data sets CP # q and CP # (q + 1). Become.

22, the correction point data sets CP # q, and the shape of the gamma curve corresponding to the respective CP # (q + 1), it is a graph conceptually showing a shape of a gamma curve corresponding to the correction point data set CP_L ^k. Results correction point data CParufa the correction point data set CP_L ^k is the correction point data sets CP # q, CP # (q + 1) each of the correction point data CPα (#q), is calculated by interpolation calculation of CPα (# q + 1) (Α is an integer from 0 to 5), and the gamma curve corresponding to the correction point data set CP_L ^k is between the gamma curves corresponding to the correction point data sets CP # q and CP # (q + 1), respectively. Shape.

Returning to Figure 19A, after the correction point data set CP_L ^k is determined, the correction point data set CP_L ^k is modified according to the dispersion σ _{AVE_k} ² described in the distributed data D _{.sigma. @ 2} (step S14). The corrected correction point data set CP_L ^k is finally supplied to the approximate calculation correction circuit 63 as the correction point data set CP_sel ^k (step S14A).

FIG. 23 is a conceptual diagram showing the technical significance of correcting the correction point data set CP_L ^k based on the variance σ _{AVE_k} ² . A large variance σ _{AVE — k} ² means that there are a large number of sub-pixels separated from APL _{AVE — k} , in other words, a large image contrast. When the contrast of the image is large, the approximate calculation correction circuit 63 performs correction calculation so as to enhance the contrast, so that the contrast of the image can be expressed while suppressing the luminance of the LED backlight 8.

The correction point data CP1, CP4 of the correction point data set CP_L ^k has a large influence on the contrast, in the present embodiment, the correction point data CP1, CP4 of the correction point data set CP_L ^k in response to variance σ _{AVE_k} ² Control Is done. Correction of the correction point data set CP_L ^k of the correction point data CP1 is, the larger the variance σ _{AVE_k} ^2, so that the correction point data CP1 of the final approximate correction point data set CP_selG ^k supplied to the arithmetic correction circuit 63 is reduced To be done. Further, the correction of the correction point data set CP_L ^k of the correction point data CP4 is, the larger the variance σ _{AVE_k} ^2, eventually approximate operation and correction circuit correction point data set supplied to 63 CP_selG ^k of the correction point data CP4 is small To be done. By such correction, when the contrast of the image is large, the correction calculation in the approximate calculation correction circuit 63 is performed so as to enhance the contrast. In the present embodiment, is not performed modifications the correction point data set CP_L ^k of the correction point data CP0, CP2, CP3, CP5. That is, the correction point data CP0 of correction point data set CP_selG ^k, CP2, CP3, CP5 is the correction point data CP0, CP2, CP3, the same value as CP5 of the correction point data set CP_L ^k.

In one embodiment, the correction point data CP1, CP4 of the correction point data set CP_selG ^k is calculated by the following equation:
CP1_sel ^R = CP1_L ^R − (D _IN ^MAX _{−σ AVE_R} ² ) · ξ ^R (12a)
_{^{CP1_sel G = CP1_L G - (D}} IN MAX -σ AVE_G 2) · ξ G ··· (12b)
CP1_sel ^B = CP1_L ^B − (D _IN ^MAX− σ _{AVE_B} ² ) · ξ ^B (12c)
CP4_sel ^R = CP4_L ^R + (D _IN ^MAX _{−σ AVE_R} ² ) · ξ ^R (13a)
_{^{CP4_sel G = CP4_L G + (D}} IN MAX -σ AVE_G 2) · ξ G ··· (13b)
_{^{CP4_sel B = CP4_L B + (D}} IN MAX -σ AVE_B 2) · ξ B ··· (13c)
Here, D _IN ^MAX is an allowable maximum value of the image data D _IN1 and D _IN2 . Further, ξ ^R , ξ ^G , and ξ ^B are predetermined proportional constants. ξ ^R , ξ ^G , and ξ ^B may be the same or different from each other. ^Further, CP1_sel ^k, CP4_sel k are each a correction point data CP1, CP4 of the correction point data set CP_sel ^k, CP1_L ^k, CP4_L ^k, respectively, at the correction point data CP1, CP4 of the correction point data set CP_L ^k is there.

FIG. 24 conceptually shows the relationship between the gradation distribution (histogram) and the content of the correction calculation when the correction point data CP1 and CP4 are corrected by the above formula. Even if APL _{AVE_k} is the same, if the contrast is different, the variance σ _{AVE_k} ² is different. In an image having many sub-pixels whose gradation is close to APL _{AVE_k} , the contrast is small, and in this case, the variance σ _{AVE_k} ² is small. In such a case, the correction is performed such that the correction point data CP1 becomes smaller and the correction point data CP4 becomes larger, thereby enhancing the contrast (right column). On the other hand, in an image having many subpixels whose gradation is _far from APL _{AVE_k} , the contrast is large, and in this case, the variance σ _{AVE_k} ² is large. In such a case, only a small correction is made to the correction point data CP1 and CP4, and the contrast is not enhanced (right column). It will be understood that the above equations (12a) to (12c) and (13a) to (13c) satisfy such a condition.

Returning to FIG. 19A, the approximate operation units 63R, 63G, and 63B of the approximate operation correction circuit 63 of the driver ICs 4-1 and 4-2 are respectively corrected point data sets CP_sel ^R , CP_sel ^G , CP_sel calculated in this way. ^The image data D _INi ^R , D _INi ^G , and D _INi ^B are corrected using ^B to generate post-correction image data D _OUT ^R , D _OUT ^G , and D _OUT ^B (step S15A).

補正点データＣＰ１が補正点データＣＰ０よりも大きいということは、ガンマ補正に使用されるガンマ値γが１より小さいことを意味していることに留意されたい。 Each approximate operation units of the driver IC 4-i 63k calculates the corrected image data _{D OUT} ^k from image data _{D INi} ^k by the following equation:
^{_{(1) D INi k <D}} IN Center, and, CP1> For CP0:

It should be noted that the fact that the correction point data CP1 is larger than the correction point data CP0 means that the gamma value γ used for gamma correction is smaller than 1.

補正点データＣＰ１が補正点データＣＰ０以下であるということは、ガンマ補正に使用されるガンマ値γが１以上であることを意味していることに留意されたい。 _{^{(2) D INi k <D}} IN Center, and in the case of CP1 ≦ CP0:

It should be noted that the fact that the correction point data CP1 is not more than the correction point data CP0 means that the gamma value γ used for gamma correction is not less than 1.

^₍₃₎ D _INi ^k> In the case of ^{D IN Center:}

Here, the intermediate data value D _IN ^Center is the following formula using the allowable maximum value D _IN ^MAX of the image data D _INi :
D _IN ^Center = D _IN ^MAX / 2, (15)
It is a value defined by. K is a parameter given by the above equation (7). Furthermore, D _INS , PD _INS , and ND _INS appearing in the equations (14a) to (14c) are values defined as follows:
(A) D _INS
D _INS is a value determined depending on the image data _{D INi} ^k, is given by the following equation:

式（１６ａ）、（１６ｂ）、（１７ｂ）から理解されるように、パラメータＲは、Ｄ_ＩＮｉ ^ｋの１／２乗に比例する値であり、従って、ＰＤ_ＩＮＳは、画像データＤ_ＩＮｉ ^ｋの１／２乗に比例する項、及び１乗に比例する項を含む式で算出される値である。 (B) PD _INS
PD _INS is defined by the following equation (17a) using the parameter R defined by equation (17b):

Equation (16a), (16b), as is understood from (17b), the parameter R _is a value proportional to the square root of _{D INi} ^k, _{therefore, PD INS} is the image data _{D INi} ^k It is a value calculated by an expression including a term proportional to the 1/2 power and a term proportional to the first power.

式（１６ａ）、（１６ｂ）、（１８）から理解されるように、ＮＤ_ＩＮＳは、画像データＤ_ＩＮｉ ^ｋの２乗に比例する項を含む式で算出される値である。 (C) ND _INS
ND _INS is given by:

Equation (16a), (16b), as is understood from _{(18), ND INS} is a value calculated by an equation containing a term proportional to the square of the image data _{D INi} ^k.

The corrected image data D _OUT ^R , D _OUT ^G , and D _OUT ^B calculated by the approximate calculation correction circuit 63 according to the series of equations described above are sent to the color reduction processing circuit 64. The color reduction processing circuit 64 performs color reduction processing on the corrected image data D _OUT ^R , D _OUT ^G , and D _OUT ^B to generate color reduction image data D _{OUT_D} . The reduced color image data D _{OUT_D} is sent to the data line driving circuit 66 through the latch circuit 65, and the data line of the LCD panel 2 is driven in accordance with the reduced color image data D _{OUT_D} .

On the other hand, FIG. 19B shows a case where a combination of APL calculated as an average value of pixel luminance and a mean square of pixel luminance is adopted as a feature amount exchanged between driver ICs 4-1 and 4-2. 7 is a flowchart showing an operation of a correction point data calculation circuit 73. In this case, the current frame full screen feature data D _{CHR_C} and the previous frame full screen feature data D _{CHR_P} are both APL data D _APL that describes the entire APL _{AVE of the} image displayed in the display area 3 of the LCD panel 2, It should be noted that the distribution data D _σ2 describing σ _AVE is included. Correction point data calculation circuit 73, from the current frame full-screen feature data _{D CHR_C} or previous frame whole screen feature data _{D CHR_P} with such contents, determines the correction point data set CP_selG ^k supplied to the approximate operation and correction circuit 63 .

First, in response to the communication confirmation signal _{S CMF} transmitted from the communication confirmation circuit 86, one of the current frame full-screen feature data _{D CHR_C} or previous frame whole screen feature data _{D CHR_P} is selected as the selected characteristic data (step S11B ). Also selected feature data is either of the current frame full-screen feature data _{D CHR_C} or previous frame whole screen feature data _{D CHR_P,} selected feature data _describes the _{APL AVE} APL data _{D APL,} and, describe sigma _AVE ² Note that the distributed data D _σ2 is included.

Further, the gamma value is determined by the interpolation calculation / selection circuit 88b according to the APL data D _APL included in the selected feature data (step S12B). When a combination of the APL calculated as the average value of the pixel luminance and the root mean square of the pixel luminance is adopted as the feature amount exchanged between the driver ICs 4-1 and 4-2, the gamma value γ is all It is determined as a value common to all colors. Here, the gamma value γ is determined so as to increase as the APL _AVE described in the APL data D _APL increases. The gamma value γ is determined, for example, by the following formula:
γ = γ _STD + APL _AVE · η (19)
Here, γ _STD is a reference gamma value, and η is a predetermined proportionality constant.

After gamma value gamma is determined, by interpolation / selection circuit 88b, in accordance with the gamma value gamma, correction point data set CP_L ^R, CP_L ^G, is CP_L ^B is determined (step S13B). When a combination of an APL calculated as an average value of pixel luminance and a mean square of pixel luminance is adopted as a feature amount exchanged between the driver ICs 4-1 and 4-2, a correction point data set is used. CP_L ^R, CP_L ^G, CP_L ^B Note, be determined to be equal to each other.

In one _{embodiment, APL AVE} depending on selected one of the correction point data set CP # 1~CP # m described above, the correction point data sets CP_L ^R correction point data set selected, CP_L ^G, as CP_L ^B You may decide. In this way, the correction point data set CP_L ^R, CP_L ^G, _APL when CP_L ^B is determined _AVE, gamma, and the relationship of the correction point data set CP_L ^k is a as illustrated in FIG. 20 of the above is there.

In other embodiments, as follows correction point data set CP_L ^R, CP_L ^G, it may be determined CP_L ^B. First, among the correction point data sets CP # 1 to CP # m stored in the correction point data set storage register 88a according to the upper (MN) bits of APL _AVE described in the APL data D _APL. These two correction point data sets: correction point data sets CP # q and CP # (q + 1) are selected. Here, as described above, M is the number of bits of APL _AVE , and N is a predetermined constant. Q is an integer of 1 to m-1. The larger the APL _AVE , the larger the gamma value γ ^k is set, and the correction point data sets CP # q and CP # (q + 1) having a larger q value are selected.

Furthermore, the correction point data sets CP_L ^R, CP_L ^G, the correction point data CP0~CP5 of CP_L ^B, respectively, of the two selected correction point data set CP # q, CP # correction point data CP0~CP5 of (q + 1) Calculated by interpolation calculation. More specifically, the correction point data sets CP0 to CP5 of the correction point data set CP_L ^k (k is any of “R”, “G”, and “B”) are the two selected correction point data sets CP # q. , CP # (q + 1) is calculated from the correction point data CP0 to CP5 by the following equation.
CPα_L ^k = CPα (#q) +
{(CPα (# q + 1) −CPα (#q) / 2 ^N } × APL _AVE [N−1: 0],
... (20)
α: integer from 0 to 5, CPα_L ^k : correction point data CPα of the correction point data set CP_L ^k
CPα (#q): Correction point data CPα of the selected correction point data set CP # q
CPα (# q + 1): Correction point data CPα of the selected correction point data set CP # (q + 1)
APL _AVE [N-1: 0]: Lower N bits of APL _AVE

The relationship between APL _AVE and γ and the correction point data set CP_L ^k when the correction point data set CP_L ^k is determined in this way is as shown in FIG. The correction point data sets CP # q, and the shape of the gamma curve corresponding to the respective CP # (q + 1), the shape of the gamma curve corresponding to the correction point data set CP_L ^k is a as illustrated in FIG. 22 is there.

Returning to FIG. 19B, the correction point data sets CP_L ^R, after CP_L ^G, is CP_L ^B are determined, the correction point data sets CP_L ^R, CP_L ^G, CP_L ^B is dispersed is described in distributed data D σ2 σ _{AVE ²} Is corrected according to (step S14B). Modified correction point data set CP_L ^R, CP_L ^G, CP_L ^B is, the correction point data sets CP_selG ^R, CP_selG ^G, as CP_selG ^B, is supplied to the final approximate operation and correction circuit 63 (step S14B). Here, when the combination of the APL calculated as the average value of the pixel luminance and the square average of the pixel luminance is adopted as the feature amount exchanged between the driver ICs 4-1 and 4-2, the correction point data Note that the sets CP_sel ^R , CP_sel ^G , CP_sel ^B are determined to be equal to each other.

In one embodiment, the correction point data CP1, CP4 of the correction point data set CP_selG ^k is calculated by the following equation:
CP1_sel ^k = CP1_L ^k − (D _IN ^MAX −σ _AVE ² ) · ξ (12a)
CP4_sel ^k = CP4_L ^k + (D _IN ^MAX −σ _AVE ² ) · ξ (13a)
Here, D _IN ^MAX is an allowable maximum value of the image data D _IN1 and D _IN2 . Ξ is a predetermined proportionality constant. ^Further, CP1_sel ^k, CP4_sel k are each a correction point data CP1, CP4 of the correction point data set CP_sel ^k, CP1_L ^k, CP4_L ^k, respectively, at the correction point data CP1, CP4 of the correction point data set CP_L ^k is there. The relationship between the gradation distribution (histogram) and the content of the correction calculation when the correction point data CP1 and CP4 are corrected by the above formula is as shown in FIG.

Referring back to FIG. 19B, the approximate operation units 63R, 63G, and 63B of the approximate operation correction circuit 63 of the driver ICs 4-1 and 4-2 are corrected point data sets CP_sel ^R , CP_sel ^G , CP_sel calculated in this way, respectively. image data _D ^INi R using _^B, performs correction operation on the _{D INi} ^G, and _{D INi} ^B, corrected image data _{D ^OUT R, D} ^{OUT _G,} and generates the _{D OUT} ^B (step S15B). Correction point data set CP_sel ^R, CP_sel ^G, the correction operation in accordance with CP_selG ^B, the image data _{D ^INi R, D} ^{INi _G,} and the corrected image data from the _{^{D INi B D OUT R, D}} OUT G, and _{D OUT} ^B Is the same as the case where a combination of APL and the mean square of the gradation of the sub-pixel calculated for each color is adopted as a feature quantity exchanged between the driver ICs 4-1 and 4-2. (See the above formulas (14a) to (14c), (15), (16a), (16b), (17a), (17b), (18)).

  As described above, in the liquid crystal display device 10 of the present embodiment, when an abnormality occurs in the liquid crystal driving power generation circuit 16 of one of the driver ICs 4-1 and 4-2, the driver The interface 20 of the IC transmits the abnormality notification data ERR1 or ERR2 to the interface 20 of the other driver IC. As a result, the occurrence of an abnormality is notified to the other IC driver IC, and both of the driver ICs 4-1 and 4-2 execute an abnormal operation sequence for stopping the operation. As a result, even when an abnormality occurs in the liquid crystal drive power generation circuit 16 of one of the driver ICs 4-1 and 4-2, both the driver ICs 4-1 and 4-2 are shifted to a safe state. be able to.

  In addition, the interface 20 of the driver ICs 4-1 and 4-2 is used for exchanging other data in addition to the abnormality notification data ERR1 and ERR2. More specifically, in this embodiment, the interface 20 is used for exchanging feature data between the driver ICs 4-1 and 4-2. The interface 20 is used both for exchanging the abnormality occurrence notification data ERR1 and ERR2 between the driver ICs 4-1 and 4-2 and for exchanging other data (for example, feature data). Contributes to reduction.

In each of the driver ICs 4-1 and 4-2, the total feature amount of the image displayed on the display area 3 of the LCD panel 2 is based on the feature data exchanged between the driver ICs 4-1 and 4-2. The calculated calculation is performed on the image data D _IN1 and D _IN2 according to the calculated feature amount. According to such an operation, it is possible to perform a correction calculation according to the entire feature amount of the image displayed in the display area 3 of the LCD panel 2 calculated in each of the driver ICs 4-1 and 4-2.

Furthermore, when the feature data communication between the driver ICs _4-1 and _4-2 is not normally performed, the feature indicated in the previous frame full-screen feature data D _{CHR_P} stored in the calculation result storage memory 72 Since the correction calculation is performed using the amount, the boundary between the first portion 5-1 and the second portion 5-2 of the display area 3 of the LCD panel 2 can be visually recognized even when communication is not normally performed. Can be prevented.

  In the above, the configuration in which the pixels of the display area 3 of the LCD panel 2 are driven by the two driver ICs 4-1 and 4-2 is illustrated. However, as illustrated in FIG. The pixels in the display area 3 of the LCD panel 2 may be driven by the driver IC.

In this case, a communication bus 6 is formed in the LCD panel 2, and the driver ICs 4-1 to 4-3 transmit the inter-chip communication data D _CHIP , more specifically, feature data and communication status notification data through the communication bus 6. Exchange. Each of the driver ICs 4-1 to 4-3 calculates the current frame full-screen feature data from the feature data (D _{CHR_i} ) generated by itself and the feature data (D _{CHR_IN} ) received from the outside. As described above, the APL calculated for each of the R sub-pixel, the G sub-pixel, and the B sub-pixel and the root mean square of the gradation are used as the feature amount exchanged between the driver ICs 4-1 to 4-3. In this case, the average value of the APL described in the feature data D _{CHR_1} and D _{CHR_2} is calculated as the APL of the entire image displayed in the display area 3 of the LCD panel 2, and is described in the feature data D _{CHR_1} and D _{CHR_2} . The average value of the mean square of the gradation of the subpixels being calculated is calculated as the mean square of the gradation of the entire subpixel of the image displayed in the display area 3 of the LCD panel 2. Furthermore, the variance of the subpixel gradation is calculated from the APL of the entire image displayed on the display area 3 of the LCD panel 2 and the root mean square of the subpixel gradation, and is displayed on the display area 3 of the LCD panel 2. A correction operation is performed according to the APL of the entire image and the gradation dispersion of the sub-pixels. Further, when the APL calculated as the average value of the pixel luminance and the root mean square of the pixel luminance are used as the feature amount exchanged between the driver ICs 4-1 to 4-3, the feature data D _{CHR_1} , D The average value of the APL described in _{CHR_2} is calculated as the APL of the entire image displayed in the display area 3 of the LCD panel 2, and the square of the gradation of the pixel described in the feature data _{DCHR_1} and _{DCHR_2} The average average value is calculated as the root mean square of the luminance of all the pixels of the image displayed in the display area 3 of the LCD panel 2. Further, the variance of the pixel luminance is calculated from the APL of the entire image displayed on the display area 3 of the LCD panel 2 and the square average of the luminance of the pixel, and the entire image displayed on the display area 3 of the LCD panel 2 is calculated. A correction operation is performed according to the dispersion of the APL and the luminance of the pixels.

Further, each of the driver ICs _4-1 to _4-3 has the current frame full screen feature when all of the communication state notification data _{DST_OUT} generated by itself and the communication state notification data _{DST_IN} received from the outside are communication ACK data. Select data, otherwise select previous frame full screen feature data. According to such an operation, in a display device including three or more driver ICs, even when communication is not normally performed, the same correction calculation can be performed in all the driver ICs.

  FIG. 25 is a flowchart showing a modified example of the operation of the liquid crystal display device according to the second embodiment of the present invention, and shows the operation of the driver ICs 4-1 and 4-2 in each frame period in the modified example. In the modification described below, the operation for unifying the correction calculation in the driver ICs 4-1 and 4-2 (that is, the operation for causing the driver ICs 4-1 and 4-2 to perform the same correction calculation) is changed. Is done.

First, in each of the characteristic data calculating circuit 71 of the driver IC4-1,4-2, respectively, the image data _{D IN1, D IN2} is analyzed, the feature data _{D CHR_1, D CHR_2} is calculated (step S21). As described above, the characteristic data _{D CHR_1} is data indicating the characteristic quantity of image displayed in the first part 5-1 of the LCD panel 2, it is calculated from the image data _{D IN1} supplied to the driver IC4-1 The Similarly, feature data _{D CHR_2} is data indicating the characteristic quantity of image displayed in the first part 5-2 of the LCD panel 2, it is calculated from the image data _{D IN2} supplied to the driver IC4-2. Also in the present modification, as in the second embodiment described above, each of the R subpixel, the G subpixel, and the B subpixel is calculated as the feature amount calculated in each of the driver ICs 4-1 and 4-2. The APL and the root mean square of the subpixel gradation may be used. Further, as the feature amount calculated in each of the driver ICs 4-1 and 4-2, an APL calculated as an average value of pixel luminance and a square average of pixel luminance may be used.

Subsequently, the feature data D _{CHR_1} calculated by the driver IC _4-1 is sent from the driver IC 4-1 to the driver IC 4-2 (step S22). Specifically, the driver IC 4-1 transmits output feature data D _{CHR_OUT} obtained by adding an error detection code to the feature data D _{CHR — 1} calculated by the feature data calculation circuit 81 to the driver IC 4-2. The error detection code is added by the error detection code addition circuit 82. The driver IC 4-2 receives the output feature data D _{CHR_OUT} transmitted by the driver IC _4-1 as the input feature data D _{CHR_IN} .

Inter-chip communication detection circuit 83 of the driver IC4-2, using the error detecting code added to the input feature data _{D CHR_IN,} determining whether the input feature data _{D CHR_IN} transmitted from the driver IC4-1 has been received normally (Step S23). Specifically, the inter-chip communication detection circuit 83 of the driver IC 4-2 does not detect a data error in the input feature data D _{CHR_IN} (or if an error correction code is used, uncorrectable data). If no error is detected), it is determined that the input feature data D _{CHR_IN} has been normally received, and communication ACK data is generated as communication state notification data D _{ST_OUT} . On the other hand, when a data error is detected (or when an error correction code is used, an error that cannot be corrected) is detected, the inter-chip communication detection circuit 83 of the driver IC 4-2. _Outputs communication NG data as communication status notification data _{DST_OUT} .

In step S23, when the driver IC 4-2 determines that the input feature data D _{CHR_IN} transmitted from the driver IC _4-1 has been normally received, the operations of steps S24 to S27 described below are performed.

In step S 24, first, the driver IC 4-2 calculates the input feature data D _{CHR_IN} (that is, the feature data D _{CHR — 1} ) received from the driver IC _4-1 and the driver IC 4-2 by itself in the full-screen feature data calculation circuit 84. The current frame full-screen feature data is calculated from the feature data D _{CHR_2} . The calculation method of the current frame full-screen feature data is the same as in the first embodiment. For example, when the APL calculated for each color and the mean square of the gradation are used as the feature _amount , the average value of the APL described in the feature data D _{CHR_1} and D _{CHR_2} is displayed in the display area 3 of the LCD panel 2. The average value of the root mean square calculated as the APL of the entire displayed image and described in the feature data D _{CHR — 1} and D _{CHR —} 2 is the pixel level for the entire image displayed in the display area 3 of the LCD panel 2. Calculated as the root mean square. Further, the variance of the gradation of the subpixel is calculated from the APL of the entire image displayed in the display area 3 of the LCD panel 2 and the root mean square of the gradation of the subpixel calculated for each color. The correction calculation is performed according to the APL of the entire image displayed in the display area 3 of the LCD panel 2 and the gradation distribution of the subpixels. Further, when the APL calculated as the average value of the pixel luminance and the square average of the pixel luminance are used as the feature amount, the average value of the APL described in the feature data D _{CHR_1} and D _{CHR_2} is the LCD panel. is calculated as the total APL of the image displayed on the second display area 3, characteristic data _{D CHR_1,} the average value of the mean square of the luminance described in the _{D CHR_2} is displayed on the display area 3 of the LCD panel 2 Calculated as the root mean square of the luminance of the pixels for the entire image. Further, the variance of the luminance of the pixel is calculated from the APL calculated for the entire image displayed in the display area 3 of the LCD panel 2 and the root mean square of the luminance of the pixel. The correction calculation is performed in accordance with the APL of the entire image displayed on the display area 3 of the LCD panel 2 and the luminance distribution of the pixels.

In step S24, the driver IC 4-2 further generates data obtained by adding an error correction code to the current frame full-screen feature data as output feature data D _{CHR_OUT} , and generates the generated output feature data D _{CHR_OUT} and communication ACK data. The communication state notification data _{DST_OUT} including the data is transmitted to the driver IC 4-1 that is the slave driver. In this case, the driver IC _4-1 receives the data obtained by adding the error correction code to the current frame full-screen feature data as the input feature data D _{CHR_IN} , and transmits the communication status notification data D _{ST_OUT} including the communication ACK data to the communication status notification data D. It will be received as _{ST_IN} .

Then, inter-chip communication detection circuit 83 of the driver IC4-1, using the error detecting code added to the input feature data _{D CHR_IN,} input feature data _{D CHR_IN} transmitted from the driver IC4-2 (i.e., the current frame It is determined whether the (full-screen feature data) has been received normally (step S25). Specifically, the inter-chip communication detection circuit 83 of the driver IC 4-1 does not detect a data error in the input feature data D _{CHR_IN} (that is, the current frame full-screen feature data to which the error detection code is added) (or When an error correction code is used and no uncorrectable data error is detected), it is determined that the input feature data D _{CHR_IN} has been received normally, and communication ACK data is _transmitted as communication status notification data D _{ST_OUT} Is output. Communication state notification data _{DST_OUT} including communication ACK data is sent from driver IC 4-1 to driver IC 4-2. That is, communication ACK data is sent from the driver IC 4-1 to the driver IC 4-2 (step S26).

On the other hand, if a data error is detected in step S25 (or if an error that cannot be corrected if an error correction code is used), the inter-chip communication of the driver IC 4-1 is performed. The detection circuit 83 outputs communication NG data as communication state notification data _{DST_OUT} . Communication state notification data _{DST_OUT} including communication NG data is sent from the driver IC 4-1 to the driver IC 4-2. That is, communication NG data is sent from the driver IC 4-1 to the driver IC 4-2 (step S27).

Further, when the driver IC 4-2 determines in step S23 that the input feature data D _{CHR_IN} transmitted from the driver IC 4-1 has not been normally received, the operations of steps S28 to S31 described below are performed.

In step S28, the driver IC _4-2 generates, as output feature data D _{CHR_OUT} , data obtained by adding an error correction code to dummy data in the same format as the current frame full-screen feature data, and the generated output feature data D _{CHR_OUT} , Communication state notification data _{DST_OUT} including communication NG data is transmitted to the driver IC 4-1 as a slave driver. In this case, the driver IC4-1 receives the data and add the error correction code to the dummy data as the input feature data _{D CHR_IN,} receives the communication state notification data _{D ST_OUT} including communication NG data as the communication state notification data _{D ST_IN} It will be.

Then, inter-chip communication detection circuit 83 of the driver IC4-1, using the error detecting code added to the input feature data _{D CHR_IN,} input feature data _{D CHR_IN} transmitted from the driver IC4-2 (i.e., dummy data ) Is normally received (step S29). Specifically, the inter-chip communication detection circuit 83 of the driver IC 4-1 does not detect a data error in the input feature data D _{CHR_IN} (that is, dummy data to which an error detection code is added) (or an error correction code). If uncorrectable data error is not detected), it is determined that the input feature data D _{CHR_IN} has been normally received, and communication ACK data is output as communication state notification data D _{ST_OUT} . Communication state notification data _{DST_OUT} including communication ACK data is sent from driver IC 4-1 to driver IC 4-2. That is, communication ACK data is sent from the driver IC 4-1 to the driver IC 4-2 (step S30).

On the other hand, if a data error is detected in step S29 (or if an error that cannot be corrected if an error correction code is used), the inter-chip communication of the driver IC 4-1 is performed. The detection circuit 83 outputs communication NG data as communication state notification data _{DST_OUT} . Communication state notification data _{DST_OUT} including communication NG data is sent from the driver IC 4-1 to the driver IC 4-2. That is, communication NG data is sent from the driver IC 4-1 to the driver IC 4-2 (step S31).

Each of the driver ICs _4-1 and _4-2 has the current frame full-screen characteristics from the communication state notification data D _{ST_OUT} generated by the inter-chip communication detection circuit 83 and the communication state notification data D _{ST_IN} received from the outside. Select whether to perform correction calculation using data or previous frame full screen feature data (that is, whether to generate correction point data set CP_sel ^k from current frame full screen feature data or previous frame full screen feature data) To do. Each of the driver ICs _4-1 and _4-2 includes both communication state notification data D _{ST_OUT} generated by the inter-chip communication detection circuit 83 and communication state notification data D _{ST_IN} received from the outside as communication ACK data. In some cases, the current frame full screen feature data is selected. Here, in the driver IC 4-2, the current frame full-screen feature data calculated by the full-screen feature data calculation circuit 84 included in the driver IC 4-2 is selected. In the driver IC 4-1, from the driver IC 4-2. The transmitted current frame full screen feature data is selected. When the current frame full-screen feature data is selected, the contents of the calculation result storage memory 72 are updated to the current frame full-screen feature data in each of the driver ICs 4-1 and 4-2.

When at least one of the communication status notification data D _{ST_OUT} and D _{ST_IN} is communication NG data, each of the driver ICs _4-1 and _{4-2 selects} the previous frame full-screen feature data stored in the calculation result storage memory 72. To do. Here, when the driver IC 4-1 receives the communication NG data from the driver IC 4-2 (that is, when the feature data D _{CHR_1} is not normally received), the driver IC 4-1 receives dummy data instead of the current frame full-screen feature data. Will receive. However, in this case, since the previous frame full screen feature data is selected, there is no problem in operation.

Also in this modification, in each of the driver ICs 4-1 and 4-2, the image data D _IN1 and D _{IN2 are applied} to the image data D _IN1 and D _IN2 according to the feature amount calculated for the entire image displayed in the display area 3 of the LCD panel 2. The correction calculation is performed. According to such an operation, it is possible to perform a correction calculation according to the entire feature amount of the image displayed in the display area 3 of the LCD panel 2 calculated in each of the driver ICs 4-1 and 4-2.

Further, when the communication of the feature data (or the current frame full screen feature data) between the driver ICs 4-1 and 4-2 is not normally performed, the previous frame full screen feature stored in the calculation result storage memory 72 is displayed. Since the correction calculation is performed using the feature amount indicated in the data D _{CHR_P} , even if the communication is not normally performed, the first portion 5-1 and the second portion 5- It can be prevented that the boundary of 2 becomes visually recognizable.

  In the modification described above, the driver IC 4-2 receives the feature data and the communication state notification data from the driver IC 4-1, and transmits the current frame full-screen feature data and the communication state notification data to the driver IC 4-1. However, the operations of the driver ICs 4-1 and 4-2 may be interchanged. That is, the driver IC 4-1 may receive the feature data and the communication state notification data from the driver IC 4-2, and perform an operation of transmitting the current frame full-screen feature data and the communication state notification data to the driver IC 4-2.

  In the modification described above, the operation of the configuration in which the liquid crystal display device includes two driver ICs is described. However, as illustrated in FIG. A liquid crystal display device including the same can also be realized. In this case, a specific driver IC (for example, driver IC 4-2) receives the feature data and the communication state notification data from all the other driver ICs, and sends the current frame full-screen feature data to all the other driver ICs. And communication status notification data. Each driver IC selects the current frame full screen feature data if all of the communication status notification data generated by itself and the communication status notification data received from the outside are communication ACK data, otherwise, the previous frame full screen Select feature data. According to such an operation, in a display device including three or more driver ICs, even when communication is not normally performed, the same correction calculation can be performed in all the driver ICs.

  Although the embodiments of the present invention are specifically described above, the present invention should not be construed as being limited to the above-described embodiments. It will be apparent to those skilled in the art that the present invention may be practiced with various modifications. In particular, although the embodiment in which the present invention is applied to a liquid crystal display device has been described above, it should be noted that the present invention is applicable to a display device including a display panel driver in general.

1: Application processor 2: LCD panel 3: Display area 4, 4A, 4B: Driver IC
5-1: First part 5-2: Second part 6: Communication bus 7: LED driver 8: LED backlight 10, 10A: Liquid crystal display device 11: Interface circuit 12: Register circuit 12a: Abnormality detection register 13: Timing Generation circuit 13a: Oscillation circuit 13b: Timing counter 14: Power activation sequencers 15a, 15b, 15c: Selector 16: Liquid crystal drive power generation circuit 16a: Abnormality detection circuit 16b: Boost circuit 16c: GVDD generation circuit 16d: GVSS generation circuit 17: Liquid crystal drive circuit 18: Reset detection circuit 19: Abnormal flag flip-flop 20: Interfaces 21a, 21b, 21c: External output terminal 22a: Clock signal line 22b: Vertical synchronization signal line 22c: Horizontal synchronization signal lines 23a, 23b, 23c: External Input terminal 24: GVDD line 25: GVSS line 31: amplifier 32: variable resistance element 33: resistance element 34: output switch 35: amplifier 36: variable resistance element 37: resistance element 38: output switch 41: external connection capacitor 42: register circuit 45: power supply Capacitor 46: Liquid crystal drive power generation circuit 47: Liquid crystal drive circuit 48: Power supply capacitor 52: Sleep end command 53: Display on command 61: Display memory 62: Correction point data set supply circuit 63: Approximate calculation correction circuits 63R, 63G, 63B, 63k: Approximate calculation unit 64: Color reduction processing circuit 65: Latch circuit 66: Data line drive circuit 67: Gradation voltage generation circuit 68: Timing control circuit 69: Backlight brightness adjustment circuit 71: Feature data calculation circuit 72: Calculation Result storage memory 73: correction point data Output circuit 81: Feature data calculation circuit 82: Error detection code addition circuit 83: Inter-chip communication detection circuit 84: Full screen feature data operation circuit 85: Communication state storage memory 86: Communication confirmation circuit 87: Feature data selection circuit 88a: Correction Point data set storage register 88b: interpolation calculation / selection circuit 89: correction point data addition / subtraction circuit

Claims (12)

A plurality of integrated circuits;
A power line,
The plurality of integrated circuits are:
A first integrated circuit comprising a first power supply circuit;
A second integrated circuit comprising a second power supply circuit,
The power supply line electrically connects the output of the first power supply circuit and the output of the second power supply circuit,
The first power supply circuit includes a first abnormality detection circuit that detects occurrence of an abnormality in the first power supply circuit;
The second power supply circuit includes a second abnormality detection circuit that detects occurrence of an abnormality in the second power supply circuit,
When the first abnormality detection circuit detects the occurrence of an abnormality in the first power supply circuit, the first integrated circuit starts an abnormality stop sequence for stopping the operation of the first integrated circuit and the first power supply circuit A first notification is sent to the second integrated circuit to notify the occurrence of the abnormality, and the second integrated circuit performs the operation of the second integrated circuit in response to the first notification from the first integrated circuit. Start the abnormal stop sequence to stop,
When the second abnormality detection circuit detects the occurrence of an abnormality in the second power supply circuit, the second integrated circuit starts an abnormality stop sequence for stopping the operation of the second integrated circuit and the second power supply circuit. A second notification for notifying the occurrence of the abnormality is sent to the first integrated circuit, and the first integrated circuit performs the operation of the first integrated circuit in response to the second notification from the second integrated circuit. An integrated circuit device that starts an abnormal stop sequence to stop. An integrated circuit device according to claim 1,
The first integrated circuit generates a common reference clock signal for controlling operation timing of the first integrated circuit and the second integrated circuit when the integrated circuit device is performing a normal operation.
The second integrated circuit includes a timing generation circuit for generating an internal reference clock signal,
When the integrated circuit device performs the normal operation, the common reference clock signal generated by the first integrated circuit is used to control the operation timing of the second integrated circuit.
When an abnormal stop sequence for stopping the operation of the second integrated circuit is started in response to the first notification, the second integrated circuit controls the internal reference clock signal to control the operation timing of the second integrated circuit. The integrated circuit device that switches to the operation that is used. An integrated circuit device according to claim 2, wherein
And an arithmetic unit for controlling the first integrated circuit and the second integrated circuit,
The arithmetic device supplies a reset signal to the first integrated circuit and the second integrated circuit,
When the reset signal is asserted while the normal operation is performed, the first integrated circuit and the second integrated circuit start an abnormal stop sequence for stopping the respective operations,
When an abnormal stop sequence for stopping the operation of the second integrated circuit is started in response to the reset signal, the second integrated circuit uses the internal reference clock signal to control the operation timing of the second integrated circuit. Integrated circuit device that switches to the operation used. An integrated circuit device according to claim 1,
And an arithmetic unit for controlling the first integrated circuit and the second integrated circuit,
The first integrated circuit includes a first abnormality detection register in which information indicating that the first abnormality detection circuit has detected occurrence of an abnormality in the first power supply circuit is stored.
The second integrated circuit includes a second abnormality detection register in which information indicating that the second abnormality detection circuit has detected occurrence of an abnormality in the second power supply circuit is stored.
When the arithmetic unit monitors the first abnormality detection register and the second abnormality detection register and detects that the abnormality stop sequence is started in the first integrated circuit and the second integrated circuit, the abnormality stop sequence is detected. An integrated circuit device that executes a return routine that activates the first integrated circuit and the second integrated circuit at a timing after completion. A power supply circuit whose output is connected to a power supply line connected to the output of another integrated circuit;
A control circuit;
An integrated circuit comprising an interface,
The power supply circuit includes an abnormality detection circuit that detects occurrence of an abnormality in the power supply circuit,
When the abnormality detection circuit detects the occurrence of an abnormality in the power supply circuit, the control circuit starts an abnormality stop sequence for stopping the operation of the integrated circuit, and the interface notifies the occurrence of an abnormality in the power supply circuit. Send a first notification to another integrated circuit,
When the second notification for notifying the occurrence of the abnormality of the power supply circuit of the other integrated circuit is received by the interface from the other integrated circuit, the control circuit performs an abnormality stop sequence for stopping the operation of the integrated circuit. Integrated circuit to start. A display panel;
A plurality of driver ICs;
A power line,
The plurality of driver ICs are:
A first driver IC for driving a data line provided in a first portion of a display area of the display panel;
Second driver IC for driving data lines provided in the second portion of the display area
Including
The first driver IC of the plurality of driver ICs is
A first power supply circuit;
A first drive circuit for driving data lines provided in the first portion in response to first image data corresponding to the first portion of the display area;
The second driver IC of the plurality of driver ICs is
A second power supply circuit;
A second drive circuit for driving data lines provided in the second portion in response to second image data corresponding to the second portion of the display area;
The power supply line electrically connects the output of the first power supply circuit and the output of the second power supply circuit,
The first power supply circuit includes a first abnormality detection circuit that detects occurrence of an abnormality in the first power supply circuit;
The second power supply circuit includes a second abnormality detection circuit that detects occurrence of an abnormality in the second power supply circuit,
When the first abnormality detection circuit detects the occurrence of an abnormality in the first power supply circuit, the first driver IC starts an abnormality stop sequence for stopping the operation of the first driver IC and the first power supply circuit. In response to the first notification from the first driver IC, the second driver IC performs the operation of the second driver IC. Start the abnormal stop sequence to stop,
When the second abnormality detection circuit detects the occurrence of an abnormality in the second power supply circuit, the second driver IC starts an abnormality stop sequence for stopping the operation of the second driver IC and the second power supply circuit. A second notification for notifying the occurrence of the abnormality is sent to the first driver IC, and the first driver IC performs the operation of the first driver IC in response to the second notification from the second driver IC. Display device that starts an abnormal stop sequence to stop. The display device according to claim 6,
The first driver IC is configured to calculate, from the first image data, first feature data indicating a feature amount of a first image displayed in the first portion of the display area,
The second driver IC is configured to calculate second feature data indicating a feature amount of a second image displayed in the second portion of the display area from the second image data,
The first driver IC is commonly used for transmitting the first notification and the first feature data to the second driver IC, and the second notification and the second notification from the second driver IC. A first interface that is commonly used to receive feature data;
The second driver IC is commonly used for transmission of the second notification and the second feature data to the first driver IC, and the first notification from the first driver IC and the first driver IC. It has a second interface that is commonly used to receive feature data,
The first driver IC uses the first feature data and the second feature data to calculate first full-screen feature data indicating an entire feature amount of an image displayed in the display area of the display panel. Then, a correction calculation based on the first full-screen feature data is performed on the first image data to generate first corrected image data, and the display in response to the first corrected image data Configured to drive the first portion of the region;
The second driver IC generates the second corrected image data by performing the same correction calculation on the second image data as the correction calculation performed by the first driver IC, and generates the second corrected image data. A display device configured to drive the second portion of the display area in response to data. The display device according to claim 7,
The second driver IC uses the first feature data and the second feature data received from the first driver IC to indicate an overall feature amount of an image displayed in the display area of the display panel. Display configured to calculate second full-screen feature data and perform the correction operation on the second image data according to the second full-screen feature data to generate the second corrected image data. apparatus. A display device according to any one of claims 6 to 8,
The first driver IC generates a common reference clock signal that controls the operation timing of the first driver IC and the second driver IC when the display device is performing a normal display operation.
The second driver IC includes a timing generation circuit that generates an internal reference clock signal,
When the display device performs the normal display operation, the operation timing of the second driver IC is controlled by the common reference clock signal generated by the first driver IC ,
When an abnormal stop sequence for stopping the operation of the second driver IC is started in response to the first notification, the second driver IC controls the operation timing of the second driver IC by the internal reference clock signal. The display device that switches to the action to be performed. The display device according to claim 9,
And an arithmetic device for controlling the first driver IC and the second driver IC.
The arithmetic device supplies a reset signal to the first driver IC and the second driver IC,
When the reset signal is asserted when the normal display operation is performed, the first driver IC and the second driver IC start an abnormal stop sequence for stopping the respective operations,
When an abnormal stop sequence for stopping the operation of the second driver IC is started in response to the reset signal, the operation timing of the second driver IC is controlled by the internal reference clock signal. A display device that switches to an operation. A display panel driver for driving a data line provided in a first portion of a display area of a display panel,
A power supply circuit whose output is connected to a power supply line connected to the output of another display panel driver;
A drive unit configured to receive a power supply voltage from the power supply circuit and drive the first portion of the display area;
A control circuit;
A display panel driver comprising an interface,
The power supply circuit includes an abnormality detection circuit that detects occurrence of an abnormality in the power supply circuit,
When the abnormality detection circuit detects the occurrence of an abnormality in the power supply circuit, the control circuit starts an abnormality stop sequence for stopping the operation of the display panel driver, and the interface detects the occurrence of an abnormality in the power supply circuit. Send a first notification to notify the other display panel driver;
When the second notification for notifying the occurrence of an abnormality in the power supply circuit of the other display panel driver is received from the other display panel driver by the interface, the control circuit causes an abnormality to stop the operation of the display panel driver. Display panel driver that starts the stop sequence. The display panel driver according to claim 11,
The drive unit receives input image data corresponding to a first image displayed in the first portion of the display area, and calculates first feature data indicating a feature amount of the first image from the input image data. Configured as
The interface is commonly used to transmit the first feature data and the first notification to the other display panel driver, and the feature amount of the second image displayed in the second portion of the display area. Used in common for receiving the second feature data and the second notification from the other display panel driver,
The drive unit uses the first feature data and the second feature data to calculate full-screen feature data indicating an entire feature amount of an image displayed in the display area of the display panel, and A display panel driver that performs correction calculation based on screen feature data on the input image data to generate corrected image data, and drives the first portion of the display area in response to the corrected image data.

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