KR20190070379A - Display device and method of driving the same - Google Patents

Abstract

A display device comprises: a display panel including pixels; a gate driving unit providing a gate signal to the pixels; a data driving unit generating a first initialization completing signal and providing a data signal to the pixels; and a control unit generating a second initialization completing signal based on the first initialization completing signal and a status signal and controlling the gate driving unit and data driving unit based on the second initialization completing signal. The first initialization completing signal is activated when an initialization operation of the data driving unit is completed. The status signal is activated when an initialization operation of the control unit is completed.

Description

DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME [0002]

The present invention relates to a display device, and more particularly, to a display device that controls a power-on sequence and a method of driving the display device.

Generally, the display apparatus includes a display panel and a panel driver. The display panel includes a plurality of pixels. The panel driver includes a gate driver for supplying a gate signal to the pixels, a data driver for supplying data signals to the pixels, a gate driver, and a timing controller for controlling the data driver.

Generally, the display apparatus has a power-on sequence for each of the elements (e.g., timing controller, power management circuit, gate driver, data driver, etc.) of the panel driver. A delay time for various signals is set using the register value so that the power-on sequence between the components is satisfied. However, if the delay register value is not properly set, the power-on sequence between the components is not satisfied and the abnormal screen can be displayed at the beginning of the driving of the display panel.

It is an object of the present invention to provide a display device which is automatically controlled to satisfy a power-on sequence.

It is another object of the present invention to provide a method of driving a display device.

It should be understood, however, that the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the spirit and scope of the present invention.

In order to accomplish one object of the present invention, a display device according to embodiments of the present invention includes a display panel including pixels, a gate driver for providing a gate signal to the pixel, a first initialization completion signal, And a data driver for generating a second initialization completion signal based on the first initialization completion signal and the state signal and controlling the gate driver and the data driver based on the second initialization completion signal And a control unit. The first initialization completion signal may be activated when the initialization operation of the data driver is completed. The status signal may be activated when the initialization operation of the controller is completed.

According to an embodiment, the data driver may provide the data signal to the pixel based on the second initialization completion signal. The control unit may provide the gate driver with a first control signal based on the second initialization completion signal.

According to one embodiment, the status signal includes a first signal indicating that the value of the setting register has been loaded, a second signal indicating that correction data for correcting the input image data has been loaded, and a second signal indicating that the input voltage has reached the target voltage 3 < / RTI > signal.

According to an embodiment, the control unit may include a first signal generator for outputting a ready signal based on the first signal, the second signal, the third signal, and the first initialization completion signal, And a first signal controller for outputting the first control signal to the gate driver based on the second initialization completion signal.

According to an embodiment, the first signal generator may include a first AND gate for performing a logical product of the first signal and the second signal to generate a first enable signal, and a second AND gate for comparing the input voltage and the target voltage A second comparator for generating the third signal, a second AND gate for ANDing the first enable signal and the third signal to generate a second enable signal, And a third logical product gate for performing the logical product of the first initialization completion signal to generate the ready signal.

According to an embodiment, when the second initialization completion signal is inactivated, the first signal controller may inactivate at least one of the vertical start signal and the gate clock signal as the first control signal.

According to an embodiment, the power supply unit may further include a power supply unit for adjusting the input voltage to reach the target voltage by using a resistance string.

According to an embodiment, the controller may provide a second control signal to the data driver. Wherein the data driver includes a second signal generator for generating the first initialization completion signal based on a start frame control signal for restoring a reference clock signal and an operation flag signal indicating an operation state of the data driver, A second signal control unit for controlling the output of the second control signal based on the signal and at least one data driving circuit for generating the data signal based on the second control signal received from the second signal control unit can do.

According to an embodiment, when the second initialization completion signal is inactivated, the second signal controller may deactivate at least one of a horizontal start signal, a data clock signal, and a load signal as the second control signal.

According to an embodiment, the second signal generator may include a control interface for communicating with the controller, outputting the operation flag signal and the second control signal, a start frame control signal and an operation flag signal, And a flip-flop for generating the activated first initialization complete signal when the third enable signal is activated.

In order to accomplish one object of the present invention, a display device according to embodiments of the present invention includes a display panel including a pixel, a gate driver for providing a gate signal to the pixel, a first initialization completion A data driver for generating a first initialization completion signal and a second initialization completion signal based on the first initialization completion signal and the state signal and for generating a second initialization completion signal based on the first initialization completion signal and the state signal, And a controller for controlling the data driver. The data driver may block the data signal when the second initialization completion signal is inactivated.

According to another aspect of the present invention, there is provided a method of driving a display device, comprising: generating a first initialization completion signal that is activated when a data driver completes an initialization operation of the data driver; Generating a second initialization completion signal based on a first initialization completion signal and a state signal activated when the initialization operation of the controller is completed, and generating a second initialization completion signal based on the second initialization completion signal, To the driving unit.

According to an embodiment, the data driver may further include a step of outputting a data signal based on the second initialization completion signal.

According to an embodiment of the present invention, the step of outputting the data signal may include the steps of: limiting the output of the second control signal when the second initialization completion signal is inactivated; And outputting the data signal based on the second control signal.

According to an embodiment, the second control signal may include at least one of a horizontal start signal, a data clock signal, and a load signal.

According to one embodiment, the status signal includes a first signal indicating that the value of the setting register has been loaded, a second signal indicating that correction data for correcting the input image data has been loaded, and a second signal indicating that the input voltage has reached the target voltage 3 < / RTI > signal.

According to an embodiment, the generating of the second initialization completion signal may include outputting a ready signal based on the first signal, the second signal, the third signal, and the first initialization completion signal And delaying the ready signal to generate the second initialization complete signal.

According to an embodiment, the step of generating the ready signal may include the steps of generating a first enable signal by performing an AND operation between the first signal and the second signal, comparing the input voltage with the target voltage, 3 signal, generating a second enable signal by performing a logical product of the first enable signal and the third signal, and outputting the second enable signal and the first initialization completion signal as a logical product And generating the ready signal.

According to an embodiment, the first initialization completion signal may be generated based on a start frame control signal and an operation flag signal for recovering a reference clock signal.

According to an embodiment, the first control signal may include at least one of a vertical start signal and a gate clock signal.

In the display device according to the embodiments of the present invention, the controller receives a signal indicating the stabilization state (i.e., the first initialization completion signal) from the data driver, and controls the gate driver and the data driver to operate when the data driver is in a stabilized state can do. Further, the data driver may receive a signal indicating the stabilization state (i.e., the second initialization completion signal) from the control unit, and may control whether the data signal is output based on the signal. Therefore, the display device is automatically controlled so that the power-on sequence is automatically satisfied, so there is no need to set a delay register value for the power-on sequence.

The method of driving the display device according to the embodiments of the present invention automatically controls the display device so that the power-on sequence is satisfied, so that the abnormal display phenomenon that is caused as the delay register value is not appropriately set is prevented, It is possible to prevent the possibility of an error due to the error.

However, the effects of the present invention are not limited to the above effects, and may be variously extended without departing from the spirit and scope of the present invention.

1 is a block diagram showing a display device according to embodiments of the present invention.
2 is a diagram showing an example of a first sequence control unit included in the display device of FIG.
3 is a diagram showing an example of a second sequence control unit included in the display device of FIG.
4 is a timing chart showing an example in which the power-on sequence is controlled by the first sequence controller and the second sequence controller included in the display device of FIG.
5 is a block diagram showing an example of a data driver included in the display device of FIG.
6 is a block diagram showing an example of a gate driver included in the display device of FIG.
7 and 8 are views for explaining a communication method between a control unit and a data driver included in the display device of FIG.
FIG. 9 is a diagram for explaining the effect of the display device of FIG. 1;
10 is a diagram showing another example of the first sequence control unit included in the display device of FIG.
11 is a flowchart showing a method of driving a display device according to embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

1 is a block diagram showing a display device according to embodiments of the present invention.

Referring to FIG. 1, a display device 1000 includes a display panel 100, a gate driver 200, a data driver 300, and a timing controller 500.

The display panel 100 may display a video by receiving a data signal DS generated based on the video data DATA provided from the timing controller 500. [ The display panel 100 may include gate lines GL, data lines DL, and a plurality of pixels PX. The gate lines GL may extend in a first direction D1 and may be arranged in a second direction D2 perpendicular to the first direction D1. The data lines DL extend in the second direction D2 and may be arranged in the first direction D1. Each of the pixels PX may include a thin film transistor 110 electrically connected to the gate line GL and the data line DL, a liquid crystal capacitor 130 connected to the thin film transistor 110, and a storage capacitor 150 have.

The gate driver 200, the data driver 300, and the timing controller 500 may be defined as a panel driver for driving the display panel 100.

The gate driver 200 generates the gate signal GS in response to the vertical start signal STV and the gate clock signal CPV provided from the timing controller 500 and supplies the gate signal GS to the gate line GL. As shown in FIG.

The data driver 300 may output the data signal DS to the data line DL in response to the horizontal start signal STH and the data clock signal CLK provided from the timing controller 500. [

The data driver 300 may include a second sequence controller 310 for controlling the power-on sequence in conjunction with the timing controller 500. The second sequence control unit 310 generates the activated first initialization completion signal LK1 when the internal signals of the data driver 300 are stabilized (i.e., when the initialization operation of the data driver is completed) It is possible to provide the signal LK1 to the first sequence control unit 550 of the timing control unit 500. [ In response to the activated second initialization completion signal LK2 received from the first sequence control unit 550, the second sequence control unit 310 outputs the data signal DS to the pixel PX so that the data driver supplies the data signal DS to the pixel PX. (E.g., the second control signal CTL2). On the other hand, when the second initialization completion signal LK2 is inactivated, the second sequence control unit 310 may block the data signal DS from being supplied to the pixel PX.

The timing controller 500 may receive the input video data IDATA and the control signal CON from the outside. The control signal CON may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal CK. The timing controller 500 generates digital image data according to the operation condition of the display panel 100 based on the input image data IDATA and provides the generated image data to the data driver 300 . The timing controller 500 may generate the horizontal start signal STH using the horizontal synchronizing signal Hsync and then output the horizontal start signal STH to the data driver 300. [ The timing controller 500 may generate the vertical start signal STV using the vertical synchronization signal Vsync and then output the vertical start signal STV to the gate driver 200. [ The timing controller 500 generates the gate clock signal CPV and the data clock signal CLK using the clock signal CK and then outputs the gate clock signal CPV to the gate driver 200, And can output the data clock signal CLK to the data driver 300. In one embodiment, the data clock signal CLK may be embedded in the image data (DATA).

The timing controller 500 may include a first sequence controller 550 for controlling the power-on sequence in conjunction with the data driver 300. The first sequence controller 550 may determine whether the components of the display device 1000 are stabilized and generate a second initialization completion signal LK2 when stabilized. In one embodiment, the first sequence controller 550 may determine that the data driver 300 is in a stable state when receiving the activated first initialization completion signal LK1 from the second sequence controller 310 . The first sequence control unit 550 generates a second initialization completion signal (a first initialization completion signal) based on a state signal that is activated when the first initialization completion signal and the internal signals of the timing controller 500 are stabilized (i.e., when the initialization operation of the control unit is completed) LK2).

Also, the timing controller 500 may provide the gate driver 200 with the first control signal CTL1 based on the second initialization completion signal LK2. For example, when the second initialization completion signal LK2 is activated, the timing controller 500 supplies the first control signal CTL1 including the vertical start signal STV and the gate clock signal CPV to the gate driver 200 so that the gate driver 200 can be normally driven. On the other hand, when the second initialization completion signal LK2 is inactivated, the timing controller 500 deactivates at least one of the vertical start signal STV and the gate clock signal CPV, Can not be outputted.

Although the first sequence controller 550 is included in the timing controller 500 in FIG. 1, the present invention is not limited thereto. For example, the first sequence control unit 550 may be implemented as a separate circuit outside the timing control unit 500.

2 is a diagram showing an example of a first sequence control unit included in the display device of FIG.

Referring to FIG. 2, the first sequence controller 550 of the timing controller 500A may control the signals so that the timing controller 500A and the data driver 300 interlock with each other to satisfy the power-on sequence.

The first sequence controller 550 may include a first signal generator 510 and a delay circuit 530.

The first signal generator 510 can output the ready signal ALL_RDY based on the status signal and the first initialization completion signal LK1. Here, the status signal may include at least one of a first signal I2C_DONE, a second signal SPI_DONE, and a third signal VON_FB. Here, the first signal I2C_DONE indicates that the value of the setting register is loaded. For example, the first signal I2C_DONE may indicate whether the settings of the timing controller 500A stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory), the settings of the power supply unit, and the like are loaded. The second signal SPI_DONE indicates whether or not the correction data for correcting the input image data has been loaded. For example, the second signal SPI_DONE may be stored in the flash memory, and may indicate whether or not the compensation data for storing the compensation value according to the pixel and gradation is loaded to compensate for the smear of the display panel. The third signal VON_FB may indicate that the input voltage VON 'supplied to the control unit 500A has reached the target voltage VTG for use in the control unit 500A.

In one embodiment, the first signal generator 510 includes a first AND gate 511, a second AND gate 513, a third AND gate 515, and a first comparator 517 can do. The first AND gate 511 may perform the logical product operation (i.e., AND operation) of the first signal I2C_DONE and the second signal SPI_DONE to generate the first enable signal EN1. The first comparator 517 may generate the third signal VON_FB by comparing the input voltage VON 'and the target voltage VTA. The second AND gate 513 may generate the second enable signal EN2 by performing a logical product of the first enable signal EN1 and the third signal VON_FB. The third AND gate 515 can generate a ready signal ALL_RDY by performing a logical product of the second enable signal EN2 and the first initialization completion signal LK1.

Here, the input voltage VON 'may be a voltage adjusted from an external circuit (for example, the power supply 600). For example, in the DC-DC converter, the first voltage VON is adjusted so as to reach the target voltage VTA used in the timing control section 500A by the resistance column (i.e., the resistors R1 and R2 connected in series) So that the input voltage VON 'can be supplied to the timing control unit 500A.

The delay circuit 530 can ensure stability for the power-on sequence by delaying the signal. The delay circuit 530 can generate the second initialization completion signal LK2 by delaying the ready signal ALL_RDY. For example, the delay circuit 530 may include a capacitor for delaying the signal output.

The timing controller 500A includes a first signal controller 580A that outputs a first control signal (e.g., a vertical start signal STV ') to the gate driver based on the second initialization completion signal LK2 . For example, when the second initialization completion signal LK2 is inactivated, the first signal controller 580A can control the vertical start signal STV to be not outputted as the first control signal by turning off the switch . When the second initialization completion signal LK2 is activated, the first signal controller 580A can control the vertical start signal STV to be outputted as the first control signal by turning on the switch.

2, the first signal generator 510 includes a first AND gate 511, a second AND gate 513, a third AND gate 515, and a first comparator 517. However, the structure of the first signal generator 510 is not limited thereto. The first signal generator 510 may be implemented in various structures capable of outputting the ready signal ALL_RDY based on the first to third signals and the first initialization completion signal LK1.

3 is a diagram showing an example of a second sequence control unit included in the display device of FIG.

Referring to FIG. 3, the second sequence controller 310 of the data driver 300 may control the signals so that the timing controller 500 and the data driver 300 interlock with each other to satisfy the power-on sequence.

The second sequence control unit 310 may include a second signal generation unit 311 and a second signal control unit 316.

The second signal generator 311 generates the first initialization completion signal FK1 based on the start frame control signal SFC for restoring the reference clock signal and the operation flag signal FLOCK indicating the operation state of the data driver can do.

In one embodiment, the second signal generator 311 may include a control interface 312, a NOR gate 313, and a flip flop 314.

The control interface 312 may communicate with the timing controller 500 and output an operation flag signal FLOCK and a second control signal (e.g., a data clock signal CLK). For example, the control interface 312 is an interface between the timing controller 500 and the data driver. The control interface 312 includes pins (USI-1P, USI-1N, USI-2P, USI- 2N, etc.) to the timing controller 500.

The NOR gate 313 can perform the NOR operation on the start frame control signal SFC and the operation flag signal FLOCK to generate the third enable signal LOCK_I. Here, the start frame control signal SFC may be a clock training control signal that determines an interval during which the internal clock signal is trained. For example, the start frame control signal SFC may be received from the timing control section. (I.e., a vertical blank period) of the start frame control signal SFC at the interface between the timing control unit and the data driving unit. For example, the data driver may receive the setting value for restoring the internal reference clock of the driver during the vertical blank period, and the clock data recovery of the data driver may be operated. That is, the start frame control signal SFC can be used as a signal for informing the operation of restoring the reference clock signal of the data driver 300 for each vertical blanking period. The operation flag signal FLOCK indicates a flag indicating a state in which the internal signal of the data driver is stably operated. For example, the operation flag signal FLOCK may be a low level voltage at the time when the reference clock used in the data driver is normally operated (i.e., has a normal waveform).

The flip-flop 314 can generate the activated first initialization completion signal LK1 when the third enable signal LOCK_I is activated.

The second signal controller 316 can control the output of the second control signal (e.g., the data clock signal CLK) based on the second initialization completion signal LK2. In one embodiment, when the second initialization completion signal LK2 is inactivated, the second signal controller 316 outputs the horizontal start signal STH, the data clock signal CLK, and the load signal TP May be inactivated. Accordingly, when the second initialization completion signal LK2 is inactivated, the second signal controller 316 can control the data driving circuit 330 not to output the data signal. On the other hand, when the data driving unit and the timing control unit are stabilized and the second initialization completion signal LK2 is activated, the data driving circuit 330 supplies the second control signal to the data driving circuit 330 ).

4 is a timing chart showing an example in which the power-on sequence is controlled by the first sequence controller and the second sequence controller included in the display device of FIG.

2 to 4, the power-on sequence of the display device can be sequentially performed by the first sequence controller and the second sequence controller.

The start frame control signal SFC and the operation flag signal FLOCK correspond to the low voltage level and the NOR gate 313 receives the start frame control signal SFC and the operation flag signal FLOCK at the first time point TP1, To generate an activated third enable signal LOCK_I. The flip-flop 314 can receive the activated third enable signal LOCK_I and output the activated first initialization completion signal LK1. After the first time point TP1, the first initialization completion signal LK1 can maintain the high voltage level.

Since both the first signal I2C_DONE, the second signal SPI_DONE and the third signal VON_FB as well as the first initialization completion signal LK1 are activated at the second time point TP2, the activated ready signal ALL_RDY Can be output. The ready signal ALL_RDY may be delayed by the delay circuit 530 for the delay time DT.

The vertical start signal STV and the data clock signal CLK are generated in the timing controller before the third time point TP3 but the second initialization completion signal LK2 corresponds to the low voltage level It may not be outputted to the driver and the data driving circuit.

At the third time point TP3, the delay circuit 530 can output the delayed ready signal ALL_RDY, that is, the activated second initialization completion signal LK2. Accordingly, after the third time point TP3, the vertical start signal STV 'and the data clock signal CLK' can be output to the gate driver and the data driver circuit, respectively. After the third time point TP3, the gate driver supplies the gate signal to the pixel, and the data driver supplies the data signal VDATA to the pixel, so that the display panel can be driven.

Therefore, the display apparatus can drive the display panel after confirming whether the timing control section and the data driving section are stabilized, thereby preventing the abnormal display phenomenon.

5 is a block diagram showing an example of a data driver included in the display device of FIG.

Referring to FIG. 5, the data driving circuit 330 may generate an analog data signal based on the video data DATA 'and the second control signals STH', CLK ', and the like. At least one of the video data DATA 'and the second control signals STH', CLK ', etc. is provided to the data driving circuit 330 through the second sequence control unit 310, May provide the data signal to the pixel after the timing control unit and the data driving unit are stabilized. In one embodiment, the data driving circuit 330 may include a shift register 331, a latch 333, a digital-analog converter 335, and an output buffer 337.

The shift register 331 can receive the horizontal start signal STH 'and the data clock signal CLK'. The shift register 342 can generate the sampling signal by shifting the horizontal start signal STH 'in synchronization with the data clock signal CLK'.

The latch 333 can latch the image data (DATA ') in response to the sampling signal. The latch unit 344 can output the latched image data in response to the load signal TP '.

The digital-analog converter 335 may convert the latched input image data into a data signal based on the gamma reference voltage VGREF.

The output buffer unit 348 may output the data signal to the data lines DL1 to DLm.

5, the data driving circuit 330 includes the shift register 331, the latch 333, the digital-analog converter 335, and the output buffer 337, May have various structures in which the video data (DATA ') is converted into a data signal and the output of the data signal is limited by the second sequence control unit.

6 is a block diagram showing an example of a gate driver included in the display device of FIG.

Referring to FIG. 6, the gate driver 200 may include a plurality of stages STG1 to STGn. Each of the stages STG1 to STGn may include an input terminal IN, a first clock terminal CT1, a second clock terminal CT2, and an output terminal OUT.

The first gate clock signal CPV1 'and the second gate clock signal CPV2' having different timings are applied to the first clock terminal CT1 and the second clock terminal CT2 of the stages STG1 to STGn . For example, the second gate clock signal CPV2 'may be the inverted signal of the first gate clock signal CPV1'. In the neighboring stages, the first gate clock signal CPV1 'and the second gate clock signal CPV2' may be inverted from each other. For example, the first gate clock signal CPV1 'is applied as the first clock signal to the first clock terminal CT1 of the odd-numbered stage (for example, STG1) The second gate clock signal CPV2 'may be applied as the second clock signal. On the contrary, the second gate clock signal CPV2 'is applied as the first clock signal to the first clock terminal CT1 of the even-numbered stage (for example, STG2), and the second clock signal The first gate clock signal CPV1 'may be applied as a signal.

The vertical start signal STV 'or the output signal of the previous stage may be applied to the input terminal IN of the stages STG1 to STGn. That is, the vertical start signal STV 'is applied to the input terminal IN of the first stage STG1 and the output signal of the previous stage is applied to the input terminal IN of the remaining stages STG2 to STGn . The output terminal OUT of the stages STG1 to STGn can output a gate signal to the gate line.

7 and 8 are views for explaining a communication method between a control unit and a data driver included in the display device of FIG.

7 and 8, in the protocol between the timing controller and the data driver, the first initialization completion signal LK1 and the second initialization completion signal LK2 are allocated to a part of the configuration packet, The initialization completion signals can be transmitted without any initialization.

As shown in FIG. 7, setting data such as the temperature of the driving chip as well as the video data and the control signal may be transmitted between the timing controller and the data driver. For example, by assigning a first initialization completion signal (LK1) and a second initialization completion signal (LK2) to a part of the set packet in the protocol between the timing controller and the data driver, initialization completion signals are transmitted between the timing controller and the data driver .

8, when the data driver includes a plurality of data driving circuits (i.e., a plurality of data driving chips), only one of the plurality of data driving chips sets the LOCK flag to the high level . The information of the data driving circuit in which the LOCK flag is set can be accessed and the first initialization completion signal of the data driving circuit can be provided to the timing control section. Therefore, the first initialization completion signal of the data driving circuits is time-divided and provided to the timing controller, so that the initialization completion signals can be transmitted without additional wiring.

FIG. 9 is a diagram for explaining the effect of the display device of FIG. 1;

9, the display device according to the exemplary embodiment of the present invention loads setting register values I2C such as a timing controller setting, a DC-DC converter setting, a gamma setting, a power level setting, and the like, And a control signal (e.g., a vertical start signal STV) for driving the driver after the delay time DLY has elapsed may be provided. If control signals are output before the setting register values I2C are loaded or before the input voltage VON is stably supplied, an abnormal image may be displayed on the display panel. On the other hand, in the case of the display device according to the embodiments of the present invention, since the setting register values I2C are loaded and the control signals are provided to the driver after the voltage VON is stably supplied, the power-on sequence is satisfied And the reliability can be improved.

10 is a diagram showing another example of the first sequence control unit included in the display device of FIG.

Referring to FIG. 10, the first sequence controller 550 of the timing controller 500B may control the signals so that the timing controller 500B and the data driver 300 interlock with each other to satisfy the power-on sequence. The timing control unit 500B according to the present embodiment is different from the timing control unit 500A of FIG. 2 except that the vertical start signal STV 'and the gate output signal CPVx' The same reference numerals are used for the same or similar components, and redundant description will be omitted.

The first sequence controller 550 may include a first signal generator 510 and a delay circuit 530.

The first signal generator 510 can output the ready signal ALL_RDY based on the status signal and the first initialization completion signal LK1. In one embodiment, the first signal generator 510 includes a first AND gate 511, a second AND gate 513, a third AND gate 515, and a first comparator 517 can do.

The delay circuit 530 can ensure stability for the power-on sequence by delaying the signal.

The timing controller 500B includes a first signal controller 580B that outputs a vertical start signal STV 'and a gate output signal CPVx' as a first control signal to the gate driver based on the second initialization completion signal LK2, . ≪ / RTI > For example, when the second initialization completion signal LK2 is inactivated using the switch, the first signal controller 580B outputs the vertical start signal STV and the gate output signal CPVx as the first control signal .

11 is a flowchart showing a method of driving a display device according to embodiments of the present invention.

11, after the initializing operation of the data driver and the initializing operation of the controller are completed, a method of driving the display device provides control signals for driving the display device to the gate driver and the data driving circuit, thereby assuring a power-on sequence .

The data driver may generate a first initialization completion signal LK1 that is activated when the initialization operation of the data driver is completed. Specifically, power is supplied to the display device (S10), and the data driver determines whether the start frame control signal (SFC) received from the control unit and the operation flag signal (FLOCK) indicating the operation state of the data driver correspond to the low voltage level (S20). The data driver may confirm that the data driver is stabilized when the start frame control signal SFC and the operation flag signal FLOCK correspond to the low voltage level and may set the third enable signal LOCK_I to the high voltage level. For example, the third enable signal LOCK_I may be generated by performing a NOR operation on the start frame control signal SFC and the operation flag signal FLOCK. When the third enable signal LOCK_I is set to the high voltage level (S30), the data driver may output the activated first initialization completion signal LK1 to the control unit (S40).

The control unit may generate the second initialization completion signal LK2 based on the first initialization completion signal LK1 and the state signals I2C_DONE, SPI_DONE, and VON_FB that are activated when the initialization operation of the control unit is completed. In one embodiment, the status signal includes a first signal (I2C_DONE) indicating that the value of the setting register has been loaded, a second signal (SPI_DONE) indicating that correction data for correcting the input image data has been loaded, And a third signal (VON_FB) indicating that it has been reached. For example, when all of the first initialization completion signal LK1, the first signal I2C_DONE, the second signal SPI_DONE, and the third signal VON_FB are activated (S50), the control unit outputs the activated ready signal ALL_RDY) is output, and the ready signal ALL_RDY may be delayed (S60) for a delay time by the delay circuit.

Whether or not the delayed ready signal ALL_RDY, that is, the activated second initialization completion signal LK2, is output (S70).

The timing controller before the activation of the second initialization completion signal LK2 limits the output of the first control signals (e.g., STV ', CPVx') and the data driver outputs the second control signal (e.g., CLK ' (S80).

When the second initialization completion signal LK2 is activated, the control unit provides a first control signal (e.g., STV ', CPVx') to the gate driver and a data driver supplies a second control signal (e.g., CLK 'To the data driving circuit (S90). In one embodiment, the first control signal may include at least one of a vertical start signal STV 'and a gate clock signal CPVx'.

That is, the timing controller can control whether or not the gate driver is operated based on the second initialization completion signal LK2. For example, the timing controller may limit the output of the first control signal when the second initialization completion signal LK2 is inactivated. On the other hand, the timing controller may provide the gate driver with the first control signal so that the gate driver normally generates the gate signal when the second initialization completion signal LK2 is activated. In one embodiment, the first control signal may comprise at least one of a vertical start signal and a gate clock signal.

And the data driver can output the data signal based on the second initialization completion signal LK2. For example, the data driver may limit the output of the second control signal when the second initialization completion signal LK2 is inactivated. On the other hand, the data driver may output the second control signal when the second initialization completion signal LK2 is activated, and may provide the data signal to the display panel. In one embodiment, the second control signal may include at least one of a horizontal start signal, a data clock signal, and a load signal.

The display panel may be driven (S100) by providing the display signal with the gate signal and the data signal.

Therefore, the driving method of the display device automatically controls the display device so that the power-on sequence is satisfied, so that the risk of human error can be prevented.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, The present invention may be modified and changed by those skilled in the art. For example, in the above description, the display device is a liquid crystal display device, but the type of display device is not limited thereto.

The present invention can be variously applied to an electronic apparatus having a display device. For example, the present invention can be applied to a computer, a notebook, a mobile phone, a smart phone, a smart pad, a PMP, a PDA, an MP3 player, a digital camera, a video camcorder,

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. You will understand.

100: display panel 200: gate driver
300: Data driver 310: Second sequence controller
330: Data driving circuit 500: Timing control part
510: first signal generator 530: delay circuit
550: first sequence control unit 600: power supply unit
1000: display device

Claims (20)

A display panel including pixels;
A gate driver for providing a gate signal to the pixel;
A data driver for generating a first initialization completion signal and providing a data signal to the pixel; And
And a control unit for generating a second initialization completion signal based on the first initialization completion signal and the state signal and controlling the gate driver and the data driver based on the second initialization completion signal,
Wherein the first initialization completion signal is activated when the initialization operation of the data driver is completed,
Wherein the status signal is activated when the initialization operation of the controller is completed. The data driver according to claim 1, wherein the data driver supplies the data signal to the pixel based on the second initialization completion signal,
Wherein the control unit provides a first control signal to the gate driver based on the second initialization completion signal. 3. The apparatus of claim 2, wherein the status signal comprises a first signal indicating that the value of the setting register has been loaded, a second signal indicating that correction data for correcting input image data has been loaded, and a second signal indicating that the input voltage has reached the target voltage 3 < / RTI > signal. 4. The apparatus of claim 3, wherein the control unit
A first signal generator for outputting a ready signal based on the first signal, the second signal, the third signal, and the first initialization completion signal;
A delay circuit for generating the second initialization completion signal by delaying the ready signal; And
And a first signal controller for outputting the first control signal to the gate driver based on the second initialization completion signal. 5. The apparatus of claim 4, wherein the first signal generator
A first AND gate for ANDing the first signal and the second signal to generate a first enable signal;
A first comparator for comparing the input voltage and the target voltage to generate the third signal;
A second AND gate for ANDing the first enable signal and the third signal to generate a second enable signal; And
And a third AND gate for performing an AND operation on the second enable signal and the first initialization completion signal to generate the ready signal. The display device according to claim 4, wherein, when the second initialization completion signal is inactivated, the first signal controller deactivates at least one of a vertical start signal and a gate clock signal as the first control signal. The method of claim 3,
Further comprising a power supply for adjusting the input voltage to reach the target voltage by using a resistance string. 3. The apparatus of claim 2, wherein the control unit provides a second control signal to the data driver,
The data driver
A second signal generator for generating the first initialization completion signal based on a start frame control signal for restoring a reference clock signal and an operation flag signal indicating an operation state of the data driver;
A second signal controller for controlling the output of the second control signal based on the second initialization completion signal; And
And at least one data driving circuit for generating the data signal based on the second control signal received from the second signal control unit. The apparatus of claim 8, wherein the second signal controller deactivates at least one of a horizontal start signal, a data clock signal, and a load signal as the second control signal when the second initialization completion signal is inactivated Display device. 9. The apparatus of claim 8, wherein the second signal generator
A control interface that communicates with the control unit, and outputs the operation flag signal and the second control signal;
A NOR gate for performing a NOR operation on the start frame control signal and the operation flag signal to generate a third enable signal; And
And a flip-flop for generating the activated first initialization completion signal when the third enable signal is activated. A display panel including pixels;
A gate driver for providing a gate signal to the pixel;
A data driver for generating a first initialization completion signal to be activated when the initialization operation is completed and providing a data signal to the pixel; And
And a control unit for generating a second initialization completion signal based on the first initialization completion signal and the state signal and controlling the gate driver and the data driver based on the second initialization completion signal,
Wherein the data driver blocks the data signal when the second initialization completion signal is inactivated. Generating a first initialization completion signal that is activated when the initialization operation of the data driver is completed;
Generating a second initialization completion signal based on the first initialization completion signal and a state signal activated when the initialization operation of the controller is completed; And
And the control unit provides the first control signal to the gate driver based on the second initialization completion signal. 13. The method of claim 12,
And the data driver outputs a data signal based on the second initialization completion signal. 14. The method of claim 13, wherein outputting the data signal comprises:
Limiting the output of the second control signal when the second initialization completion signal is inactivated; And
And outputting the second control signal when the second initialization completion signal is activated, and outputting the data signal based on the second control signal. 15. The method of claim 14, wherein the second control signal includes at least one of a horizontal start signal, a data clock signal, and a load signal. 13. The apparatus of claim 12, wherein the status signal comprises a first signal indicating that the value of the setting register has been loaded, a second signal indicating that correction data for correcting input image data has been loaded, and a second signal indicating that the input voltage has reached the target voltage 3 < / RTI > signal. 17. The method of claim 16, wherein generating the second initialization complete signal comprises:
Outputting a ready signal based on the first signal, the second signal, the third signal, and the first initialization completion signal; And
And delaying the ready signal to generate the second initialization completion signal. 18. The method of claim 17, wherein generating the ready signal comprises:
Performing a logical product of the first signal and the second signal to generate a first enable signal;
Comparing the input voltage and the target voltage to generate the third signal;
Generating a second enable signal by ANDing the first enable signal and the third signal; And
And generating the ready signal by performing an AND operation between the second enable signal and the first initialization completion signal. 18. The method according to claim 17, wherein the first initialization completion signal is generated based on a start frame control signal and an operation flag signal for restoring a reference clock signal. 13. The method of claim 12, wherein the first control signal includes at least one of a vertical start signal and a gate clock signal.

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