JP6307844B2 - Printed wiring board - Google Patents

Description

The present invention relates to a printed wiring board.

Patent Document 1 discloses a wiring board. The wiring board shown in FIG. 1 of Patent Document 1 has a cylindrical through-hole conductor, a plug material filled in the through-hole conductor, a cover conductor layer covering the through-hole conductor, the plug material, and a cover conductor layer. It has a plurality of via conductors formed. In FIG. 1 of Patent Document 1, the cover conductor layer is denoted by reference numeral 12.

Japanese Patent Laid-Open No. 2002-076636

As the density of printed wiring boards is increasing, the diameter of via conductors is decreasing. Therefore, in the printed wiring board having the filling resin in the through-hole conductor as shown in FIG. 1 of Patent Document 1, the difference between the physical properties of the filling resin in the through-hole conductor and the physical properties of the insulating substrate forming the core substrate. Therefore, it is expected that the connection reliability between the cover conductor layer and the via conductor on the cover conductor layer is lowered. It is considered that such a problem becomes particularly remarkable when the bottom diameter of the via conductor is 55 μm or less. In addition, the functionality of electronic components mounted on printed wiring boards is increasing. Therefore, the heat generation is large. Due to heat generation, the stress acting between the cover conductor layer and the via conductor on the cover conductor layer is expected to increase. It is considered that the connection reliability between the cover conductor layer and the via conductor on the cover conductor layer decreases due to the thermal stress. When the printed wiring board of patent document 1 is used for a vehicle-mounted board | substrate, it is guessed that connection reliability becomes low under the influence of a thermal stress.

An object of the present invention is to provide a printed wiring board having high connection reliability.

A printed wiring board according to a first aspect of the present invention includes an insulating substrate having a first surface and a second surface opposite to the first surface, a through hole penetrating the insulating substrate, and a wall of the through hole. A cylindrical through-hole conductor formed on the first substrate, a filling resin filling the through-hole conductor, and a first surface formed on the first surface of the insulating substrate and covering the through-hole conductor and the filling resin. A core substrate formed by a through hole land and a second through hole land formed on the second surface of the insulating substrate and covering the through hole conductor and the filling resin; and a first surface of the insulating substrate; An upper interlayer resin insulation layer formed on the first through-hole land, an upper conductor layer formed on the upper interlayer resin insulation layer and including an upper via land, and the upper interlayer resin Penetrate the insulation layer, Having a plurality of upper via conductor connecting serial upper via land and the first through hole land. The plurality of upper via conductors are formed immediately above the first through-hole land, and the plurality of upper via conductors surround a central via conductor located on the filling resin and the central via conductor. look-containing ambient via conductor includes a uppermost interlayer resin insulation layer formed on the conductor layer of the upper and the upper interlayer resin insulating layers, the uppermost via land formed on the uppermost interlayer resin insulation layer An uppermost conductor layer; and a plurality of uppermost via conductors that pass through the uppermost interlayer resin insulation layer and connect the upper via land and the uppermost via land, and the plurality of uppermost via conductors are formed as central via conductors. A peripheral via conductor surrounding the central via conductor, the central via conductor of the uppermost via conductor being located on the central via conductor of the upper via conductor and the peripheral via conductor of the uppermost via conductor; Not located on the periphery via conductor of said upper via conductor.

A printed wiring board according to another aspect of the present invention includes an insulating substrate having a first surface and a second surface opposite to the first surface, a through hole penetrating the insulating substrate, and a wall of the through hole. A cylindrical through-hole conductor formed, a filling resin filling the through-hole conductor, and a first through formed on the first surface of the insulating substrate and covering the through-hole conductor and the filling resin A core substrate formed by a hole land and a second through-hole land formed on the second surface of the insulating substrate and covering the through-hole conductor and the filling resin; a first surface of the insulating substrate; An upper interlayer resin insulation layer formed on the first through-hole land, an upper conductor layer formed on the upper interlayer resin insulation layer and including the upper via land, and the upper interlayer resin insulation Penetrates the layer and before Having a ring-shaped via conductors connected to the upper side of the via land of the first through hole land. The ring-shaped via conductor is formed immediately above the first through-hole land, and further, the upper interlayer resin insulation layer and the uppermost interlayer resin insulation layer formed on the upper conductor layer, An uppermost conductor layer including the uppermost via land formed on the uppermost interlayer resin insulating layer; and a ring-shaped via conductor that penetrates the uppermost interlayer resin insulating layer and connects the upper via land and the uppermost via land. And the diameter of the ring-shaped via conductor that penetrates the upper interlayer resin insulation layer is different from the diameter of the ring-shaped via conductor that penetrates the uppermost interlayer resin insulation layer.

1A and 1C are schematic views showing the first through-hole land and the upper via conductor on the first through-hole land, and FIG. 1B is a printed wiring according to the first embodiment. It is sectional drawing of a board. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 1st Embodiment. FIG. 9A is a schematic diagram showing the arrangement of the upper via conductor and the uppermost via conductor according to the first embodiment, and FIG. 9B shows the lower via conductor according to the first embodiment. FIG. 9C is a schematic diagram showing the arrangement of the lowermost via conductor, and FIG. 9C is a schematic diagram showing the arrangement of the upper via conductor and the uppermost via conductor according to a modified example of the first embodiment. FIG. 10A is a view showing the first through-hole land and the upper via conductor on the first through-hole land according to the second embodiment, and FIG. 10B is a printed wiring board according to the second embodiment. FIG. FIG. 10C is a schematic diagram showing the first through-hole land, the first opening, and the ring-shaped via conductor. Process drawing which shows the manufacturing method of the printed wiring board which concerns on 2nd Embodiment. The schematic diagram which shows arrangement | positioning of the ring-shaped via conductor on the through-hole land which concerns on 2nd Embodiment, and the ring-shaped via conductor on a land. The schematic diagram which shows arrangement | positioning of the upper ring-shaped via conductor and uppermost ring-shaped via conductor which concern on the modification of 2nd Embodiment. The schematic diagram which shows arrangement | positioning of the 1st land and 1st through-hole land which concern on 1st Embodiment.

[First embodiment]
A cross section of the printed wiring board 10 of the first embodiment is shown in FIG. The printed wiring board 10 has a core substrate 30. The core substrate 30 has a first surface F, a second surface S opposite to the first surface F, and an insulating substrate 20 having a through hole 33 for a through hole conductor, and an inner wall of the through hole 33. A cylindrical through-hole conductor 36, a filling resin (resin filler) 37 filled in the through-hole conductor, and a first through-hole formed on the first surface F so as to cover the resin filler 37 A land 36FR and a second through-hole land 36SR that covers the resin filler 37 and is formed on the second surface S are provided. The first through hole land 36FR is included in the first conductor layer 34F formed on the first surface F of the insulating substrate, and the second through hole land 36SR is formed on the second surface S of the insulating substrate. It is included in the second conductor layer 34S. The first through hole land 36FR and the second through hole land 36SR cover the through hole 33, the through hole conductor 36, and the resin filler 37. The size of the first and second through hole lands 36FR and 36SR is larger than the size of the through hole. The first through-hole land 36FR and the second through-hole land 36SR are connected by a through-hole conductor 36. The first conductor layer 34F has a first through-hole land 36FR, and the second conductor layer 34S has a second through-hole land 36SR. The shapes of the first through-hole land 36FR and the second through-hole land 36SR are preferably circles.
The core substrate has a first surface F and a second surface opposite to the first surface F. The first surface of the core substrate and the first surface of the insulating substrate are the same surface, and the second surface of the core substrate and the second surface of the insulating substrate are the same surface.
The through hole 33 has a first opening 333 on the first surface. A straight line passing through the center of gravity of the first opening 333 and perpendicular to the first surface F is the center of gravity axis X1 of the through hole 33.

The shape of the through-hole lands 36FR and 36SR is a circle or a polygon. In the first embodiment, the shape of the through-hole land (cover conductor layer) is a hexagon. FIG. 1A shows a plan view of the through-hole land 36FR of the first embodiment.

The printed wiring board 10 further includes an upper buildup layer 55 </ b> F on the first surface F of the core substrate 30. The upper buildup layer 55F includes an insulating layer (upper interlayer resin insulating layer) 50F formed on the first surface F of the core substrate 30, a conductive layer (upper conductive layer) 58F on the insulating layer 50F, and an insulating layer. An upper via conductor 60F that penetrates 50F and connects the conductor layer 58F and the first conductor layer 34F is provided. The via conductor 60F has a plurality of via conductors 60FP formed immediately above the first through-hole land 36FR. The physical properties differ between the through-hole conductor, the resin filler, and the insulating substrate. Therefore, a large stress is applied between the through hole land and the via conductor on the through hole land. Physical properties are a thermal expansion coefficient and a Young's modulus. However, the via conductor 60FP includes a central via conductor (first central via conductor) 60FPC and a peripheral via conductor (first peripheral via conductor) 60FPO surrounding the central via conductor 60FPC. Therefore, the stress acting on the interface between the cover conductor layer (through hole land) and the via conductor on the cover conductor layer is dispersed in the center and the periphery. Therefore, the connection reliability between the cover conductor layer and the via conductor on the cover conductor layer is improved. Moreover, since the heat transfer path is formed at the center and the periphery, heat dissipation is improved. Thermal stress is reduced. Connection reliability increases. There are a plurality of surrounding via conductors at positions close to the through-hole conductor. Therefore, heat is transmitted through the surrounding via conductor and the through-hole conductor. Thermal stress is reduced.

The central via conductor 60FPC and the surrounding via conductor 60FPO are formed in the opening 51F formed in the insulating layer 50F. The opening for the central via conductor is indicated by the symbol 51FPC, and the opening for the surrounding via conductor is indicated by the symbol 51FPO. The opening 51F has a bottom opening 515 on the first through-hole land. A straight line passing through the center of gravity of the bottom opening 515 and perpendicular to the first surface F is the center of gravity axis X2 of the opening 51F.
The central via conductor 60FPC is formed on the resin filler 37. The center-of-gravity axis X1 of the through hole preferably passes through the bottom opening 515C of the opening 51FPC for the central via conductor. In this case, the central via conductor is formed on the center of gravity axis of the through hole. The central via conductor is formed on the center of gravity of the first opening. However, it is preferable that the centroid axis X2C of the opening for the first central via conductor and the centroid axis X1 of the through hole do not overlap. Stress is distributed.

A surrounding via conductor surrounds the central via conductor. The number of surrounding via conductors is preferably three or more.
Preferably, a central via conductor is formed at the center of the circle, and a surrounding via conductor is formed on the circumference of the circle. The bottom opening 515C of the opening for the central via conductor is formed on the center of the circle. The center of the circle may not coincide with the center of gravity of the bottom opening 515C. The center of the circle is located in the bottom opening 515C. The bottom opening 515O of the opening for the surrounding via conductor is located on the circumference. The center of gravity and the circumference of the bottom opening 515O may not overlap. The circumference passes through the bottom opening 515O. The center of gravity of the bottom opening 515C of the opening for the central via conductor is preferably positioned on the center of the circle, and the center of gravity of the bottom opening 515O of the opening for the surrounding via conductor is preferably positioned on the circumference. When the bottom opening is a circle, the center of the bottom opening 515C and the center of the circle do not have to coincide with each other. The center of the bottom opening 515O may not be located on the circumference.

The surrounding via conductor is preferably formed in a portion (through hole land on the insulating substrate) formed on the insulating substrate in the through hole land. In this case, the center of gravity axis of the opening for the surrounding via conductor does not pass through the through hole. Furthermore, it is preferable that the entire bottom opening 515O of the opening for the surrounding via conductor is formed on the through-hole land on the insulating substrate. When the through hole land on the resin filler and the through hole land on the insulating substrate are compared, the through hole land on the resin filler is likely to be deformed by a heat cycle. Therefore, the peripheral via conductor is formed on the through hole land on the insulating substrate.

The surrounding via conductor is preferably located at the apex of the through-hole land or the polygon of the land. Stress is evenly distributed to each surrounding via conductor. The polygon is preferably a regular polygon. An example of the arrangement of the via conductor 60FP is shown in FIG. FIG. 1A shows a plan view of the through-hole land. In FIG. 1A, the through-hole land is formed in a hexagonal shape. The bottoms of the central via conductor and the surrounding via conductors are indicated by circles on the through-hole lands. The peripheral via conductor is located at the apex of the hexagon and corresponds to the apex of the through-hole land. The surrounding via conductors are formed at equal intervals.

In FIG. 1A, a surrounding via conductor is formed corresponding to the apex of the through-hole land. Since stress tends to concentrate on the apex, if a peripheral via conductor exists on the line connecting the center of gravity of the through-hole land and the apex of the through-hole land, the stress acting between the peripheral via conductor and the through-hole land tends to increase. Further, cracks are likely to occur in the interlayer resin insulation layer starting from the apex of the land. Therefore, it is preferable that the surrounding via conductors are formed at equal intervals and located between the vertices of the through-hole lands. In this case, the bottom of the surrounding via conductor is not formed on the line connecting the center of gravity of the through-hole land and the vertex of the through-hole land (FIG. 1C). The bottom of the via conductor is in contact with the through-hole land.

The upper conductor layer 58F includes lands of a central via conductor and a surrounding via conductor. The land of the via conductor is formed of a conductor on the via conductor protruding from the via conductor opening and a conductor formed around the via conductor and formed on the upper interlayer resin insulating layer. The via conductor and the land of the via conductor are directly connected. As shown in FIG. 1B, the lands of the surrounding via conductors and the lands of the central via conductor are connected. Each peripheral via conductor and the central via conductor are connected to one land (first land) 58FP. The first land is an upper via land. The shape of the upper via land 58FP may be the same as or different from the shape of the first through-hole land. If the shapes are the same, a circle is preferred. When the shape of the via conductor land (upper via land) 58FP on the first through hole land and the shape of the first through hole land are polygons, it is preferable that the vertex of the first land and the vertex of the through hole land do not overlap. . If they overlap, the distance between the top of the first land and the top of the through-hole land becomes short, so that the upper interlayer resin insulation layer is likely to crack. With the light perpendicular to the first surface of the core substrate, the first land 58FP is projected onto the through-hole land at an equal magnification. When the vertex of the first land is located on the line connecting the center of gravity of the through-hole land and the vertex of the through-hole land, the vertex of the first land and the vertex of the first through-hole land overlap. When the vertex of the first land overlaps the vertex of the first through-hole land, both vertices completely overlap.

Preferably, the size of the first through hole land is the same as the size of the first land, or the size of the first land is larger than the size of the first through hole land. When the first land is large, the first land preferably covers the first through-hole land. An example is shown in FIG. A solid line indicates the outer periphery of the first land, and a dotted line indicates the outer periphery of the first through-hole land. Cracks starting from the outer periphery of the first through-hole land are prevented.

Upper buildup layer 55F is further insulated from insulating layer 50F and insulating layer (outermost interlayer resin insulating layer) 150F formed on conductive layer 58F and conductive layer (uppermost conductive layer) 158F formed on insulating layer 150F. There is a via conductor (upper via conductor) 160F that penetrates the layer 150F and connects the conductor layer 58F and the conductor layer 158F. The via conductor 160F is formed in an opening for the via conductor 160F that penetrates the insulating layer 150F. The via conductor 160F includes a central via conductor (second central via conductor) 160FPC formed on the first land and a peripheral via conductor (second peripheral via conductor) 160FPO surrounding the second central via conductor 160FPC. Therefore, the stress acting on the interface between the first land and the via conductor on the first land is dispersed in the center and the periphery. Therefore, the connection reliability between the first land and the via conductor on the first land is improved. Moreover, since the heat transfer path is formed at the center and the periphery, heat dissipation is improved. Thermal stress is reduced. Connection reliability increases.

The opening for the second central via conductor 160FPC and the opening for the second peripheral via conductor 160FPO have a bottom opening on the first land.
The first central via conductor and the second central via conductor preferably overlap. That is, the center of gravity axis of the opening for the first central via conductor 60FPC passes through the bottom opening of the opening for the second central via conductor 160FPC.
In FIG. 1, the first peripheral via conductor and the second peripheral via conductor overlap. In this example, even if an electronic component having a large calorific value is mounted on the upper buildup layer, heat dissipation is good. As shown in the figure, when the number of surrounding via conductors is five or more, the heat dissipation effect is improved. When the first surrounding via conductor and the second surrounding via conductor overlap, the center of gravity axis of the opening for the first surrounding via conductor 60FPO passes through the bottom opening of the opening for the second surrounding via conductor 160FPO. Since the thermal stress is reduced, connection reliability is improved.

The land of the second central via conductor and the land of the second peripheral via conductor are the same as the first land. The land of the second central via conductor and the land of the second peripheral via conductor are connected to each other to form one second land (upper via land) 158FP. The second land is included in the uppermost conductor layer 158F. In FIG. 1, the shape of the second land, the shape of the first land, and the shape of the first through-hole land are the same. The size of the second land, the size of the first land, and the size of the first through-hole land can be changed. The size of the second land is preferably larger than the size of the first land, and the size of the first land is preferably larger than the size of the first through-hole land. Preferably, the second land covers the first land, and the first land covers the first through-hole land. An example of this is shown in FIG. The circle indicated by the solid line is the outer periphery of the second land 158FP, the circle indicated by the chain line is the first land 58FP, and the circle indicated by the dotted line is the first through-hole land 36FR.

The printed wiring board 10 further includes a lower buildup layer 55S on the second surface S of the core substrate 30. The lower buildup layer 55S includes an insulating layer (lower interlayer resin insulating layer) 50S formed on the second surface S of the core substrate 30, and a conductor layer (lower conductor layer) 58S on the insulating layer 50S. And the lower via conductor 60S connecting the second conductor layer 34S and the lower conductor layer 58S. Similar to the upper via conductor, the lower via conductor has a first central via conductor 60SPC and a first peripheral via conductor 60SPO on the second through-hole land.

The first central via conductor in the upper buildup layer is the upper first central via conductor, and the first central via conductor in the lower buildup layer is the lower first central via conductor. The first peripheral via conductor in the upper buildup layer is the upper first peripheral via conductor, and the first peripheral via conductor in the lower buildup layer is the lower first peripheral via conductor. The upper first central via conductor and the lower first central via conductor are the same. The upper first peripheral via conductor and the lower first peripheral via conductor are the same. The arrangement of the lower first central via conductor and the lower first peripheral via conductor is the same as the arrangement of the upper first central via conductor and the upper first peripheral via conductor.
The lower conductor layer 58S has a first land (lower via land), like the upper conductor layer. The first land included in the upper conductor layer is the upper first land, and the first land included in the lower conductor layer is the lower first land. The size and arrangement of the upper via land and the size and arrangement of the lower via land are the same.

The lower buildup layer 55S further includes an insulating layer 50S, an insulating layer (lowermost interlayer resin insulating layer) 150S on the conductive layer 58S, a conductive layer (lowermost conductive layer) 158S, and an insulating layer 150S on the insulating layer 150S. And a lowermost via conductor (160S) connecting the lower conductor layer and the lowermost conductor layer. The lowermost via conductor has a second central via conductor and a second peripheral via conductor on the lower first land, like the uppermost via conductor. The second central via conductor in the upper buildup layer is the uppermost second central via conductor, and the second central via conductor in the lower buildup layer is the lowermost second central via conductor. The second peripheral via conductor in the upper buildup layer is the uppermost second peripheral via conductor, and the second peripheral via conductor in the lower buildup layer is the lowermost second peripheral via conductor. The uppermost second central via conductor and the lowermost second central via conductor are the same. The uppermost second peripheral via conductor is the same as the lowermost second peripheral via conductor.
The lowermost conductor layer (158S) has a second land (lowermost via land) in the same manner as the uppermost conductor layer. The second land included in the uppermost conductor layer is the uppermost second land, and the second land included in the lowermost conductor layer is the lowermost second land. The arrangement of the lowermost second central via conductor and the lowermost second peripheral via conductor and the arrangement of the uppermost second central via conductor and the uppermost second peripheral via conductor are the same. The size and arrangement of the uppermost via land and the size and arrangement of the lowermost via land are the same.

The printed wiring board of the first embodiment further includes an upper solder resist layer 70F having an opening 71F that exposes the conductor layer 158F on the upper buildup layer 55F. The printed wiring board has a solder resist layer 70S having an opening 71S exposing the conductor layer 158S on the lower buildup layer 55S. The conductor layer exposed from the opening of the solder resist layer functions as a pad. A protective film (not shown) such as Ni / Au, Ni / Pd / Au, Sn, OSP is formed on the pad.

9A shows the first through-hole land 36FR, the upper first land 58FR, the upper first central via conductor 60FPC, the uppermost second central via conductor 160FPC, the upper first peripheral via conductor 60FPO and the uppermost first land via conductor 60FPO. The arrangement of the second peripheral via conductor 160FPO is shown.
FIG. 9A shows an upper first through-hole land, an upper first land, an upper first central via conductor, an uppermost second central via conductor, an upper first peripheral via conductor and an uppermost second periphery. A via conductor is shown. In FIG. 9A, they are projected at the same magnification on a plane parallel to the first surface of the core substrate with light perpendicular to the first surface.
In this example, the first center via conductor and the second center via conductor overlap. On the other hand, the first peripheral via conductor and the second peripheral via conductor do not overlap. The second peripheral via conductor is not formed on the first peripheral via conductor. The center of gravity axis of the opening for the first surrounding via conductor 60FPO does not pass through the bottom opening of the opening for the second surrounding via conductor 160FPO. In FIG. 9A, the shape of the first through-hole land and the shape of the first land are hexagons. And the vertex of the 1st land and the vertex of the 1st through hole land have shifted. The position of the surrounding via conductor corresponds to the vertex of the land. The first peripheral via conductors and the second peripheral via conductors are alternately arranged at equal intervals. Stress is evenly distributed. Heat is transferred evenly. Connection reliability is improved. In FIG. 9A, the angle between the straight line connecting the center of gravity of the land and the center of gravity of the first surrounding via conductor and the straight line connecting the center of gravity of the land and the center of gravity of the second surrounding via conductor is 30 degrees. According to this example, stress is relieved at the land between the first peripheral via conductor 60FPO and the second peripheral via conductor 160FPO. Further, no stress is concentrated between the through-hole land and the surrounding via conductor on the through-hole land. When the uppermost second land is similarly projected onto the same surface, the vertex of the second land may overlap the vertex of the first land or the first through-hole land. However, stress does not concentrate unless the vertices overlap. Insulating layer is hard to crack.

FIG. 9B shows the second through-hole land 36SR, the lower first land 58SP, the lower first central via conductor 60SPC, the lowermost second central via conductor 160SPC, and the lower first peripheral via conductor. The arrangement of 60 SPO and the lowermost second peripheral via conductor 160 SPO is shown. These arrangements are the same as the arrangement described in FIG. Similarly to the uppermost second land, the apex of the lowermost second land may overlap the apex of the lower first land or the second through-hole land. However, stress does not concentrate unless the vertices overlap. Each insulating layer is difficult to crack.

In a printed wiring board (existing in-vehicle printed wiring board) widely used for in-vehicle use, the uppermost conductor layer and the lowermost conductor layer are connected by a through-hole conductor that penetrates the printed wiring board.
On the other hand, in the printed wiring board according to the first embodiment, the uppermost conductor layer and the lowermost conductor layer have a through-hole conductor, a through-hole land sandwiching the through-hole conductor, and a central via conductor formed immediately above the through-hole land. And the peripheral via conductor, the first land, and the central via conductor formed immediately above the first land and the peripheral via conductor. The via conductor of the first embodiment is a filled via. In addition, a plurality of filled vias are formed on the through-hole land or the first land. Therefore, according to the first embodiment, the amount of the conductor connecting the uppermost conductor layer and the lowermost conductor layer is increased. Heat dissipation is improved. Further, since stress is distributed to the plurality of via conductors, connection reliability through the via conductors is increased. If the peripheral via conductor does not have a stacked via structure, the connection reliability between the peripheral via conductor and the land connected to the bottom of the peripheral via conductor is increased. Since the number of surrounding via conductors is larger than the number of central via conductors, connection reliability and heat dissipation are improved if the surrounding via conductors are not of a stacked via structure. In the stacked via structure, the bottom of the upper via conductor is positioned on the upper surface of the lower via conductor. The central via conductor preferably has a stacked via structure.

The example of the dimension of the printed wiring board of 1st Embodiment is shown below.
The thickness of the insulating substrate 20 is 700 μm. The thickness of the interlayer resin insulation layers 50F, 50S, 150F, and 150S is 60 μm. The thickness of the interlayer resin insulation layer is the distance between adjacent conductor layers. The thickness of the conductor layers 58F, 58S, 158F, 158S is 35 μm. The solder resist layers 70F and 70S have a thickness of 30 μm. The thickness of the printed wiring board is 1.21 mm. The diameter D1 of the through hole 33 for the through hole conductor is 400 μm. In the first embodiment, since the via conductor is formed on the land of the through-hole conductor, the land diameter W1 (see FIG. 1A) of the through-hole conductor is 520 μm.
Existing in-vehicle printed wiring boards do not have through-hole lands that cover through-holes for through-hole conductors. Therefore, if an existing in-vehicle printed wiring board has through holes for through-hole conductors of the same size, the diameter of the land of the through-hole conductors becomes 650 μm. According to the printed wiring board of 1st Embodiment, size reduction is achieved.
The diameter (bottom diameter) d2 of the bottom opening of the opening for the via conductor on the conductor layer is 90 μm, and the diameter (top diameter) d1 of the opening for the via conductor at the interface between the via conductor and the land of the via conductor. Is 100 μm. d1 and d2 are shown in FIG. 6 (B).

The manufacturing method of the printed wiring board 10 of 1st Embodiment is shown by FIGS.
(1) A double-sided copper-clad laminate 20A in which a copper foil 32 is laminated on both sides of the insulating substrate 20 is a starting material. The thickness of the insulating substrate is 700 μm. The insulating substrate has a first surface F and a second surface S opposite to the first surface. A blackening process (not shown) is performed on the surface of the copper foil 32 (FIG. 2A). Through holes 33 for through-hole conductors are formed in the insulating substrate with a drill (FIG. 2B). The diameter D1 of the through hole 33 is 400 μm.

(2) The plated film 26 is formed by the electroless plating process and the electrolytic plating process, and the through-hole conductor 36 made of the plated film 26 is formed on the inner wall of the through hole 33 (FIG. 3A). A resin filler 37 is filled in the through-hole conductor (FIG. 3B).

(3) Electroless plating film 23 is formed on resin filler 37 and plating film 26 (FIG. 4A). Further, an electrolytic plating film 24 is formed on the electroless plating film 23 (FIG. 4B).

(4) An etching resist 25 is formed on the electrolytic plating film 24 (FIG. 5A). The electrolytic plating film 24, the electroless plating film 23, the plating film 26, and the copper foil 32 exposed from the etching resist 25 are removed. Thereafter, the etching resist is removed, and conductor layers 34F and 34S and through-hole lands 36FR and 36SR are formed. The core substrate 30 is completed (FIG. 5B).

(5) A B-stage prepreg and a copper foil 49 are sequentially laminated on the core substrate 30. A resin film for an interlayer resin insulation layer may be laminated instead of the prepreg. The prepreg has a reinforcing material such as a glass cloth, but the resin film for an interlayer resin insulation layer does not have a reinforcing material. Both preferably contain inorganic particles such as glass particles. The prepreg on the first surface and the second surface of the core substrate is cured. Insulating layers (interlayer resin insulating layers) 50F and 50S are formed on the first surface and the second surface of the core substrate (FIG. 6A).

(6) Via conductor openings 51F and 51S reaching the conductor layers 34F and 34S and the through-hole lands 36FR and 36SR are formed in the copper foils 49 and 49 and the insulating layers 50F and 50S (FIG. 6B). The openings 51F and 51S have a top surface and a bottom surface opposite to the top surface. The top surface diameter d1 is 100 μm, and the bottom surface diameter d2 is 90 μm. The opening 51F includes an opening 51FPC for the central via conductor reaching the through-hole land 36FR and an opening 51FPO for the surrounding via conductor. The opening 51S includes an opening 51SPC for the central via conductor reaching the through-hole land 36SR and an opening 51SPO for the surrounding via conductor.

(7) An electroless plating film 52 is formed on the inner wall of the via conductor opening and the copper foil 49 by the electroless plating process (FIG. 7A).

(8) A plating resist 54 is formed on the electroless plating film 52, and an electrolytic plating film 56 is formed on the electroless plating film 52 exposed from the plating resist by electrolytic plating. Via conductors 60F and 60S are formed in the via conductor openings 51F and 51S (FIG. 7B). The via conductors 60F and 60S include a central via conductor and a surrounding via conductor formed on the through-hole land.

(9) Subsequently, the plating resist 54 is removed with 5% NaOH. Thereafter, the copper foil 49 and the electroless plating film 52 exposed from the electrolytic copper plating film are removed by etching. Conductive layers 58F and 58S made of metal foil 49, electroless plated film 52, and electrolytic plated film 56 are formed (FIG. 8A). The conductor layers 58F and 58S include upper and lower first lands. The thickness of the conductor layers 58F and 58S is 35 μm.

(10) Thereafter, the steps shown in FIGS. 6A to 8A are performed. Uppermost and lowermost interlayer resin insulation layers (150F, 150S), uppermost and lowermost conductor layers (158F, 158S) and uppermost and lowermost via conductors (160F, 160S) are formed (FIG. 8B). The uppermost and lowermost via conductors 160F and 160S include a central via conductor and a surrounding via conductor. The top and bottom conductor layers 158F, 158S include the top and bottom second lands. The upper and lower buildup layers are completed.

(11) An upper solder resist layer 70F having an opening 71F for exposing the uppermost conductor layer is formed on the upper buildup layer 55F. A lower solder resist layer (70S) having an opening (71S) for exposing the lowermost conductor layer is formed on the lower buildup layer (55S) (FIG. 1 (B)). The opening 71F has an opening 71FP for exposing the uppermost second land. The opening 71S has an opening 71SP for exposing the lowermost second land. The conductor layer exposed from the opening of the solder resist layer functions as a pad. There are a plurality of openings 71FP and 71SP exposing the second lands. A plurality of pads are formed on the second land. The second land includes a plurality of pads.

(12) A protective film (not shown) formed of a nickel layer and a gold layer on the nickel layer is formed on the pad. In addition to the nickel-gold layer, a protective film made of a nickel-palladium-gold layer can be used.

[Modification of the first embodiment]
FIG. 9C shows a projected view of the central via conductor, the surrounding via conductor, and the land of the printed wiring board according to the modified example of the first embodiment. In FIG. 9C, the uppermost second central via conductor and the upper first central via conductor, the uppermost second peripheral via conductor, the upper first peripheral via conductor, and the upper first peripheral via conductor on the first through-hole land. The land and the uppermost second land are projected at the same magnification with light perpendicular to the first surface of the core substrate.
In FIG. 9C, the sizes of the first through-hole land, the first land, and the second land are the same. The shape of the through-hole land, the shape of the first land, and the shape of the second land are circles.
Similarly to FIG. 9A, the center of gravity axis of the first central via conductor passes through the bottom surface of the second central via conductor. The first central via conductor and the second central via conductor overlap.
Similarly to FIG. 9A, the center of gravity axis of the first peripheral via conductor does not pass through the bottom surface of the second peripheral via conductor. The first peripheral via conductor and the second peripheral via conductor do not overlap.
The centroid axis of the via conductor is a straight line that passes through the centroid of the bottom opening of the via conductor opening and is perpendicular to the first surface of the core substrate. The bottom surface of the via conductor is a via conductor formed in the bottom opening of the via conductor opening.
Since the shape of each land is a circle, stress is not concentrated at a specific location on the outer periphery of the land. No cracks starting from the land. When the first peripheral via conductor and the second peripheral via conductor are overlapped, heat is directly transmitted, so that the thermal stress is reduced. Connection reliability increases. When the upper and lower via conductors overlap, a stack structure is formed by the upper and lower via conductors. If the first peripheral via conductor and the second peripheral via conductor do not overlap, stress is not concentrated between the first peripheral via conductor and the through-hole land. Connection reliability is improved. The first peripheral via conductor and the second peripheral via conductor are preferably formed on a through-hole land located on the insulating substrate. The effect of the resin filler is reduced. Connection reliability is improved.

[Second Embodiment]
A cross section of the printed wiring board 10 of the second embodiment is shown in FIG. The printed wiring board 10 has the same core substrate 30 as in the first embodiment.

The printed wiring board 10 of the second embodiment has a first conductor layer and a second conductor layer similar to those of the first embodiment.
FIG. 10A shows a plan view of the first through-hole land 36FR. The first and second through-hole lands are formed in a circular shape.

The printed wiring board 10 further includes an upper buildup layer 55 </ b> F on the first surface F of the core substrate 30. Similar to the first embodiment, the upper build-up layer 55F includes an upper interlayer resin insulation layer, an upper conductor layer, an upper via conductor, an uppermost interlayer resin insulation layer, an uppermost conductor layer, and an uppermost via conductor. Have.
In the first embodiment, the upper via conductor has a central via conductor and a peripheral via conductor, but the printed wiring board 10 of the second embodiment does not have a central via conductor and a peripheral via conductor. Instead, the upper via conductor has a first ring-shaped via conductor 60FR immediately above the first through-hole land. The bottom of the ring-shaped via conductor is drawn with a dotted line in FIG. The bottom of the ring-shaped via conductor is formed in the inner dotted line and the outer dotted line. The distance from the center of the ring-shaped via conductor to the inner dotted line is the inner diameter WI, and the distance from the center of the ring-shaped via conductor to the outer dotted line is the outer diameter WO.

The bottom of the first ring-shaped via conductor is located on the filling resin. Alternatively, the bottom of the first ring-shaped via conductor (the upper first ring-shaped via conductor) is located on the through-hole land on the insulating substrate. The bottom of the ring-shaped via conductor is preferably located on the through-hole land on the insulating substrate (FIG. 10C). The connection area between the via conductor and the through hole land is increased. The stress is reduced by forming the via conductor on the insulating substrate. In FIG. 10C, the first opening 333 of the through hole 33 is indicated by a chain line, the first through-hole land 36FR is indicated by a solid line, and the bottom of the ring-shaped via conductor is formed within a dotted line.

The upper conductor layer has an upper first land as in the first embodiment. Similar to the first embodiment, the size of the upper first land in the second embodiment is larger than the size of the through hole for the through-hole conductor. As shown in FIG. 10B, the size of the first through-hole land and the size of the first land are the same.

In the first embodiment, the uppermost via conductor has a central via conductor and a peripheral via conductor, but the printed wiring board 10 of the second embodiment does not have a central via conductor and a peripheral via conductor. Instead, the uppermost via conductor has a second ring-shaped via conductor (uppermost second ring-shaped via conductor) 160FR immediately above the first land. The bottom of the ring-shaped via conductor is drawn with a dotted line in FIG. The bottom of the ring-shaped via conductor is formed in the inner dotted line and the outer dotted line. In FIG. 10A, the first ring-shaped via conductor and the second ring-shaped via conductor overlap. The inner diameter of the first ring-shaped via conductor and the inner diameter of the second ring-shaped via conductor are the same, and the outer diameter of the first ring-shaped via conductor and the outer diameter of the second ring-shaped via conductor are The same.

The bottom of the second ring-shaped via conductor is located on the filling resin. Alternatively, the bottom of the second ring-shaped via conductor is located on the through-hole land on the insulating substrate. The bottom of the ring-shaped via conductor is preferably located on the through hole land on the insulating substrate. The connection area between the ring-shaped via conductor and the through-hole land is increased. The stress is reduced by forming the via conductor on the insulating substrate.

The uppermost conductor layer has the uppermost second land as in the first embodiment. Similar to the first embodiment, the size of the uppermost second land in the second embodiment is larger than the size of the through hole for the through-hole conductor. As shown in FIG. 10B, the size of the first through-hole land and the size of the second land are the same.
The 1st and 2nd land in connection with 1st Embodiment and 2nd Embodiment may have a part which does not have a conductor in a land.

The printed wiring board 10 further includes a lower buildup layer 55S on the second surface S of the core substrate 30. Similarly to the first embodiment, the lower buildup layer 55S includes the lower interlayer resin insulation layer 50S, the lower conductor layer 58S, the lower via conductor 60S, the lowermost interlayer resin insulation layer 150S, and the uppermost interlayer resin insulation layer 150S. It has a lower conductor layer (158S) and a lowermost via conductor (160S).
The lower via conductor is similar to the upper via conductor. A first ring-shaped via conductor (lower first ring-shaped via conductor) 60SR is provided on the second through-hole land.
The lower conductor layer is the same as the upper conductor layer. The lower conductor layer has a lower first land.
The bottom via conductor is similar to the top via conductor. A second ring-shaped via conductor (bottom second ring-shaped via conductor) 160SR is provided on the first land.
The lowermost conductor layer is the same as the uppermost conductor layer. The lowermost conductor layer has a lowermost second land.
The ring-shaped via conductor is formed by connecting surrounding via conductors. Therefore, the printed wiring board of the first embodiment is manufactured by forming the central via conductor on the printed wiring board of the second embodiment. The surrounding via conductor of the first embodiment may be formed of a ring-shaped via conductor.

The upper surface of the ring-shaped via conductor formed on the through-hole land or the first land is preferably recessed. Stress is distributed. The connection reliability between the first ring-shaped via conductor and the second ring-shaped via conductor is increased.
Since the via conductor is formed in a ring shape, the connection area between the first ring-shaped via conductor and the through-hole land and between the second ring-shaped via conductor and the first land is increased. Connection reliability is improved. Further, heat is transferred from the uppermost conductor layer to the lowermost conductor layer via the ring-shaped via conductor. Since the ring-shaped via conductor has a large conductor volume, heat dissipation is improved. Thermal stress is reduced. In order to reduce thermal stress, the second ring-shaped via conductor is preferably formed on the first ring-shaped via conductor. When the bottom of the second ring-shaped via conductor is projected onto the interface between the upper interlayer resin insulation layer and the first land with light perpendicular to the first surface of the core substrate, the second ring-shaped via All the bottoms of the conductors are located on the top surface of the first ring-shaped via conductor. The bottom and top surface do not have to coincide completely. Examples thereof are shown in FIGS. 12A and 12B. FIG. 12A shows the position of the first ring-shaped via conductor and the position of the second ring-shaped via conductor in the upper buildup layer. FIG. 12B shows the position of the first ring-shaped via conductor and the position of the second ring-shaped via conductor in the lower buildup layer. In FIGS. 12A and 12B, the inner diameter of the first ring-shaped via conductor and the inner diameter of the second ring-shaped via conductor are the same, and the outer diameter of the first ring-shaped via conductor is outside. The diameter and the outer diameter of the second ring-shaped via conductor are the same. The bottom of the second ring-shaped via conductor and the top surface of the first ring-shaped via conductor do not completely coincide. If the bottom and the upper surface do not completely overlap, stress does not concentrate between the through-hole land and the first ring-shaped via conductor. Connection reliability increases. In FIGS. 12A and 12B, the first land and the through-hole land do not overlap. Cracks starting from the side surface of the first land and the side surface of the through-hole land are unlikely to occur. The through hole land and land of the printed wiring board of the first embodiment may not overlap. However, the first land and the through hole land may overlap. Since the printed wiring board is small, the stress caused by the warp of the printed wiring board is small.

The printed wiring board of the second embodiment further has solder resist layers 70F and 70S similar to the printed wiring board of the first embodiment.

A protective film (not shown) similar to the printed wiring board of the first embodiment is formed on the pads exposed through the openings 71F and 71S of the solder resist layers 70F and 70S.

In the printed wiring board of the first and second embodiments, the uppermost conductor layer and the lowermost conductor layer are connected by the via conductor and the through-hole conductor. In an existing on-vehicle printed wiring board, the uppermost conductor layer and the lowermost conductor layer are connected by a through-hole conductor penetrating the printed wiring board. Due to this difference, in the printed wiring board of the embodiment, stress is applied between the via conductor and the land. However, in the printed wiring board of the embodiment, a plurality of via conductors are formed on the land. Alternatively, a ring-shaped via conductor is formed on the land. In the embodiment, since the connection area between the land and the via conductor is large, the stress per unit area applied to the portion is small. A through-hole conductor of an existing in-vehicle printed wiring board penetrates the printed wiring board. Therefore, the length of the through-hole conductor is increased. Accordingly, the stress applied to the connection portion between the through-hole conductor and the land is large. The stress between the via conductor and the land in the embodiment is smaller than the stress between the through-hole conductor and the land of the existing in-vehicle printed wiring board. The connection reliability of the printed wiring board of the embodiment is increased.

Except for the dimension of the ring-shaped via conductor, the dimensions of the elements of the printed wiring board of the second embodiment and the printed wiring board of the first embodiment are the same. The outer diameter WO of the ring-shaped via conductor is, for example, 125 μm, and the inner diameter WI is 75 μm.

A method for manufacturing the printed wiring board 10 of the second embodiment is shown in FIG.
(1) Similar to the first embodiment, the steps shown in FIGS. 2A to 6A are performed. Insulating layers (interlayer resin insulating layers) 50F and 50S are formed on the first surface F and the second surface S of the core substrate 30 (11 (A)).

(2) Via conductor openings 51F reaching the conductor layers 34F and 34S and ring-shaped via conductor openings 51FR and 51SR are formed in the copper foils 49 and 49 and the insulating layers 50F and 50S (FIG. 11). (B)). The ring-shaped openings 51FR and 51SR are formed on the through hole land. The openings 51F and 51S and the ring-shaped openings 51FR and 51SR are tapered toward the conductor layers 34F and 34S.
The ring-shaped openings 51FR and 51SR are formed by skiving processing using a laser. Thereafter, the printed wiring board of the second embodiment is manufactured by a method similar to the method shown in FIGS.

[Modification of Second Embodiment]
FIG. 13 is a projection view of a first ring-shaped via conductor and a second ring-shaped via conductor according to a modification of the second embodiment.
In FIG. 13A, the inner diameter of the first ring-shaped via conductor is larger than the inner diameter of the second ring-shaped via conductor, and the outer diameter of the first ring-shaped via conductor is the second ring-shaped via conductor. It is larger than the outer diameter of the conductor.
In FIG. 13B, the inner diameter of the first ring-shaped via conductor is smaller than the inner diameter of the second ring-shaped via conductor, and the outer diameter of the first ring-shaped via conductor is the second ring-shaped via conductor. It is smaller than the outer diameter of the conductor.
13A and 13B, the outer shape of the small ring-shaped via conductor is smaller than the inner diameter of the large ring-shaped via conductor.
The first ring-shaped via conductor and the second ring-shaped via conductor do not overlap. Since the first ring-shaped via conductor and the second ring-shaped via conductor do not overlap, there is a first land between the first ring-shaped via conductor and the second ring-shaped via conductor. ing. As shown in FIG. 13B, when the size of the first ring-shaped via conductor is smaller than the size of the second ring-shaped via conductor, the first ring-shaped via conductor is formed on the first land. being surrounded. A cross-sectional view of FIG. 13B is shown in FIG. When the size of the second ring-shaped via conductor is smaller than the size of the first ring-shaped via conductor, the second ring-shaped via conductor is surrounded by the first land. As described above, the first land in the horizontal direction exists between the first ring-shaped via conductor and the second ring-shaped via conductor. The stress is relieved by the first land.
In FIG. 13C, the first ring-shaped via conductor and the second ring-shaped via conductor are different in size and partially overlap. A diagonal line is drawn in the overlapping part. The inner periphery and outer periphery of the bottom of the first ring-shaped via conductor are drawn with a chain line, and the inner periphery and outer periphery of the bottom of the second ring-shaped via conductor are drawn with a dotted line. This example is excellent in terms of heat dissipation and stress relaxation. A printed wiring board having high connection reliability can be obtained.

DESCRIPTION OF SYMBOLS 10 Printed wiring board 30 Core board | substrate 36 Through-hole conductor 36FR, 36SR Through-hole land 50F, 50S Insulating layer 58FP, 58SP First land 60F Upper via conductor 60FR Upper first ring-shaped via conductor 150F, 150S Insulating layer 158FP 158SP Second land 160F Top via conductor 160FR Top second ring-shaped via conductor

Claims (4)

An insulating substrate having a first surface and a second surface opposite to the first surface, a through hole penetrating the insulating substrate, a cylindrical through-hole conductor formed on the wall of the through hole, and the through A filling resin filling the inside of the hole conductor, a first through-hole land formed on the first surface of the insulating substrate and covering the through-hole conductor and the filling resin, and formed on the second surface of the insulating substrate A core substrate formed of the through-hole conductor and a second through-hole land covering the filling resin;
An upper interlayer resin insulating layer formed on the first surface of the insulating substrate and the first through-hole land;
An upper conductor layer formed on the upper interlayer resin insulation layer and including an upper via land;
A printed wiring board having a plurality of upper via conductors penetrating the upper interlayer resin insulation layer and connecting the upper via land and the first through-hole land,
The plurality of upper via conductors are formed immediately above the first through-hole land, and the plurality of upper via conductors are a central via conductor located on the filling resin and a peripheral via surrounding the central via conductor. the conductor only including,
An uppermost interlayer resin insulation layer formed on the upper interlayer resin insulation layer and the upper conductor layer; an uppermost conductor layer formed on the uppermost interlayer resin insulation layer and including an uppermost via land; and A plurality of top via conductors that penetrate the top interlayer resin insulation layer and connect the upper via land and the top via land, the plurality of top via conductors surrounding a central via conductor and the central via conductor; Including a via conductor, the central via conductor of the uppermost via conductor being located on the central via conductor of the upper via conductor, and the peripheral via conductor of the uppermost via conductor being the periphery of the upper via conductor Not located on via conductor. An insulating substrate having a first surface and a second surface opposite to the first surface, a through hole penetrating the insulating substrate, a cylindrical through-hole conductor formed on the wall of the through hole, and the through A filling resin filling the inside of the hole conductor, a first through-hole land formed on the first surface of the insulating substrate and covering the through-hole conductor and the filling resin, and formed on the second surface of the insulating substrate A core substrate formed of the through-hole conductor and a second through-hole land covering the filling resin;
An upper interlayer resin insulating layer formed on the first surface of the insulating substrate and the first through-hole land;
An upper conductor layer formed on the upper interlayer resin insulation layer and including an upper via land;
A printed wiring board having a plurality of upper via conductors penetrating the upper interlayer resin insulation layer and connecting the upper via land and the first through-hole land,
The plurality of upper via conductors are formed immediately above the first through-hole land, and the plurality of upper via conductors are a central via conductor located on the filling resin and a peripheral via surrounding the central via conductor. Including conductors,
The through hole has a first opening on the first surface, the central via conductor is located on the center of gravity of the first opening, the central via conductor is formed at the center of a circle, and the peripheral via conductor Is located on the circumference of the circle,
Furthermore, the uppermost interlayer resin insulation layer formed on the upper interlayer resin insulation layer and the upper conductor layer, and the uppermost conductor layer including the uppermost via land formed on the uppermost interlayer resin insulation layer; A plurality of uppermost via conductors that pass through the uppermost interlayer resin insulation layer and connect the upper via land and the uppermost via land, and the plurality of uppermost via conductors include a central via conductor and the central via conductor. Including a surrounding via conductor, wherein the central via conductor of the uppermost via conductor is positioned on the central via conductor of the upper via conductor, and the peripheral via conductor of the uppermost via conductor is positioned on the circumference And
When the peripheral via conductor of the uppermost via conductor is projected onto the first through-hole land with light perpendicular to the first surface of the insulating substrate, the peripheral via conductor and the upper side of the uppermost via conductor are projected. The peripheral via conductors of the via conductors are alternately arranged. An insulating substrate having a first surface and a second surface opposite to the first surface, a through hole penetrating the insulating substrate, a cylindrical through-hole conductor formed on the wall of the through hole, and the through A filling resin filling the inside of the hole conductor, a first through-hole land formed on the first surface of the insulating substrate and covering the through-hole conductor and the filling resin, and formed on the second surface of the insulating substrate A core substrate formed of the through-hole conductor and a second through-hole land covering the filling resin;
An upper interlayer resin insulating layer formed on the first surface of the insulating substrate and the first through-hole land;
An upper conductor layer formed on the upper interlayer resin insulation layer and including an upper via land;
A printed wiring board having a ring-shaped via conductor passing through the upper interlayer resin insulation layer and connecting the upper via land and the first through-hole land,
The ring-shaped via conductor is formed immediately above the first through-hole land ,
Furthermore, the uppermost interlayer resin insulation layer formed on the upper interlayer resin insulation layer and the upper conductor layer, and the uppermost conductor layer including the uppermost via land formed on the uppermost interlayer resin insulation layer; A ring-shaped via conductor that passes through the uppermost interlayer resin insulation layer and connects the upper via land and the uppermost via land;
The diameter of the ring-shaped via conductor that penetrates the upper interlayer resin insulation layer is different from the diameter of the ring-shaped via conductor that penetrates the uppermost interlayer resin insulation layer. 4. The printed wiring board according to claim 3 , wherein the diameter of the ring-shaped via conductor that penetrates the upper interlayer resin insulation layer is larger than the diameter of the ring-shaped via conductor that penetrates the uppermost interlayer resin insulation layer.

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