JP6301501B2 - パイプラインレジスタを中間ストレージとして利用すること - Google Patents

パイプラインレジスタを中間ストレージとして利用すること Download PDF

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Publication number
JP6301501B2
JP6301501B2 JP2016567367A JP2016567367A JP6301501B2 JP 6301501 B2 JP6301501 B2 JP 6301501B2 JP 2016567367 A JP2016567367 A JP 2016567367A JP 2016567367 A JP2016567367 A JP 2016567367A JP 6301501 B2 JP6301501 B2 JP 6301501B2
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Japan
Prior art keywords
gpr
value
instruction
pipeline
gprs
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Expired - Fee Related
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JP2016567367A
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English (en)
Japanese (ja)
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JP2017516226A (ja
JP2017516226A5 (enExample
Inventor
チェン、リン
ドゥ、ユン
ウダヤクマラン、スメシュ
ジャン、チホン
グルバー、アンドリュー・イバン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
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Qualcomm Inc
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Publication date
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Publication of JP2017516226A5 publication Critical patent/JP2017516226A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2016567367A 2014-05-12 2015-04-21 パイプラインレジスタを中間ストレージとして利用すること Expired - Fee Related JP6301501B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/275,047 US9747104B2 (en) 2014-05-12 2014-05-12 Utilizing pipeline registers as intermediate storage
US14/275,047 2014-05-12
PCT/US2015/026850 WO2015175173A1 (en) 2014-05-12 2015-04-21 Utilizing pipeline registers as intermediate storage

Publications (3)

Publication Number Publication Date
JP2017516226A JP2017516226A (ja) 2017-06-15
JP2017516226A5 JP2017516226A5 (enExample) 2017-11-09
JP6301501B2 true JP6301501B2 (ja) 2018-03-28

Family

ID=53267556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016567367A Expired - Fee Related JP6301501B2 (ja) 2014-05-12 2015-04-21 パイプラインレジスタを中間ストレージとして利用すること

Country Status (6)

Country Link
US (1) US9747104B2 (enExample)
EP (1) EP3143495B1 (enExample)
JP (1) JP6301501B2 (enExample)
KR (1) KR101863483B1 (enExample)
CN (1) CN106462391B (enExample)
WO (1) WO2015175173A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102299008B1 (ko) * 2014-10-16 2021-09-06 삼성전자주식회사 어플리케이션 프로세서와 이를 포함하는 반도체 시스템
US11144367B2 (en) 2019-02-08 2021-10-12 International Business Machines Corporation Write power optimization for hardware employing pipe-based duplicate register files

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6145075A (en) 1998-02-06 2000-11-07 Ip-First, L.L.C. Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file
US6052769A (en) 1998-03-31 2000-04-18 Intel Corporation Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction
US6094716A (en) 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
US6745319B1 (en) * 2000-02-18 2004-06-01 Texas Instruments Incorporated Microprocessor with instructions for shuffling and dealing data
JP3719509B2 (ja) 2002-04-01 2005-11-24 株式会社ソニー・コンピュータエンタテインメント シリアル演算パイプライン、演算装置、算術論理演算回路およびシリアル演算パイプラインによる演算方法
US6934831B2 (en) * 2002-05-09 2005-08-23 International Business Machines Corporation Power reduction mechanism for floating point register file reads
EP1606706A2 (en) * 2003-03-19 2005-12-21 Koninklijke Philips Electronics N.V. Use of bypassing in a pipelined instruction processor
US7337305B2 (en) * 2003-11-24 2008-02-26 Sun Microsystems, Inc. Method and pipeline architecture for processing multiple swap requests to reduce latency
GB2409059B (en) 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
US7613905B2 (en) * 2006-04-06 2009-11-03 Texas Instruments Incorporated Partial register forwarding for CPUs with unequal delay functional units
US20120254591A1 (en) * 2011-04-01 2012-10-04 Hughes Christopher J Systems, apparatuses, and methods for stride pattern gathering of data elements and stride pattern scattering of data elements
WO2013101323A1 (en) 2011-12-30 2013-07-04 Intel Corporation Micro-architecture for eliminating mov operations
US9575754B2 (en) 2012-04-16 2017-02-21 Apple Inc. Zero cycle move

Also Published As

Publication number Publication date
JP2017516226A (ja) 2017-06-15
KR20170007742A (ko) 2017-01-20
EP3143495A1 (en) 2017-03-22
EP3143495B1 (en) 2023-08-16
EP3143495C0 (en) 2023-08-16
CN106462391B (zh) 2019-07-05
US20150324196A1 (en) 2015-11-12
KR101863483B1 (ko) 2018-05-31
CN106462391A (zh) 2017-02-22
WO2015175173A1 (en) 2015-11-19
US9747104B2 (en) 2017-08-29

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