CN106462391B - 利用管线寄存器作为中间存储器的方法、处理单元及计算机可读存储媒体 - Google Patents

利用管线寄存器作为中间存储器的方法、处理单元及计算机可读存储媒体 Download PDF

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Publication number
CN106462391B
CN106462391B CN201580024902.1A CN201580024902A CN106462391B CN 106462391 B CN106462391 B CN 106462391B CN 201580024902 A CN201580024902 A CN 201580024902A CN 106462391 B CN106462391 B CN 106462391B
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China
Prior art keywords
gpr
value
gprs
pipeline
instruction
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Expired - Fee Related
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CN201580024902.1A
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English (en)
Chinese (zh)
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CN106462391A (zh
Inventor
陈林
杜云
苏梅西·乌达亚库马兰
张弛红
安德鲁·埃文·格鲁贝尔
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN106462391A publication Critical patent/CN106462391A/zh
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Expired - Fee Related legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
CN201580024902.1A 2014-05-12 2015-04-21 利用管线寄存器作为中间存储器的方法、处理单元及计算机可读存储媒体 Expired - Fee Related CN106462391B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/275,047 US9747104B2 (en) 2014-05-12 2014-05-12 Utilizing pipeline registers as intermediate storage
US14/275,047 2014-05-12
PCT/US2015/026850 WO2015175173A1 (en) 2014-05-12 2015-04-21 Utilizing pipeline registers as intermediate storage

Publications (2)

Publication Number Publication Date
CN106462391A CN106462391A (zh) 2017-02-22
CN106462391B true CN106462391B (zh) 2019-07-05

Family

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CN201580024902.1A Expired - Fee Related CN106462391B (zh) 2014-05-12 2015-04-21 利用管线寄存器作为中间存储器的方法、处理单元及计算机可读存储媒体

Country Status (6)

Country Link
US (1) US9747104B2 (enExample)
EP (1) EP3143495B1 (enExample)
JP (1) JP6301501B2 (enExample)
KR (1) KR101863483B1 (enExample)
CN (1) CN106462391B (enExample)
WO (1) WO2015175173A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102299008B1 (ko) * 2014-10-16 2021-09-06 삼성전자주식회사 어플리케이션 프로세서와 이를 포함하는 반도체 시스템
US11144367B2 (en) 2019-02-08 2021-10-12 International Business Machines Corporation Write power optimization for hardware employing pipe-based duplicate register files

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6145075A (en) * 1998-02-06 2000-11-07 Ip-First, L.L.C. Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file
US20030200237A1 (en) * 2002-04-01 2003-10-23 Sony Computer Entertainment Inc. Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline
US20030212880A1 (en) * 2002-05-09 2003-11-13 International Business Machies Corporation Power reduction mechanism for floating point register file reads
US6745319B1 (en) * 2000-02-18 2004-06-01 Texas Instruments Incorporated Microprocessor with instructions for shuffling and dealing data
US20050114634A1 (en) * 2003-11-24 2005-05-26 Sun Microsystems, Inc. Internal pipeline architecture for save/restore operation to reduce latency
CN1761940A (zh) * 2003-03-19 2006-04-19 皇家飞利浦电子股份有限公司 具有数据旁路的流水线指令处理器
US20070239971A1 (en) * 2006-04-06 2007-10-11 Ajit Deepak Gupte Partial Register Forwarding for CPUs With Unequal Delay Functional Units
CN103562856A (zh) * 2011-04-01 2014-02-05 英特尔公司 用于数据元素的跨步图案聚集及数据元素的跨步图案分散的系统、装置及方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052769A (en) 1998-03-31 2000-04-18 Intel Corporation Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction
US6094716A (en) 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
GB2409059B (en) 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
WO2013101323A1 (en) 2011-12-30 2013-07-04 Intel Corporation Micro-architecture for eliminating mov operations
US9575754B2 (en) 2012-04-16 2017-02-21 Apple Inc. Zero cycle move

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6145075A (en) * 1998-02-06 2000-11-07 Ip-First, L.L.C. Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file
US6745319B1 (en) * 2000-02-18 2004-06-01 Texas Instruments Incorporated Microprocessor with instructions for shuffling and dealing data
US20030200237A1 (en) * 2002-04-01 2003-10-23 Sony Computer Entertainment Inc. Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline
US20030212880A1 (en) * 2002-05-09 2003-11-13 International Business Machies Corporation Power reduction mechanism for floating point register file reads
CN1761940A (zh) * 2003-03-19 2006-04-19 皇家飞利浦电子股份有限公司 具有数据旁路的流水线指令处理器
US20050114634A1 (en) * 2003-11-24 2005-05-26 Sun Microsystems, Inc. Internal pipeline architecture for save/restore operation to reduce latency
US20070239971A1 (en) * 2006-04-06 2007-10-11 Ajit Deepak Gupte Partial Register Forwarding for CPUs With Unequal Delay Functional Units
CN103562856A (zh) * 2011-04-01 2014-02-05 英特尔公司 用于数据元素的跨步图案聚集及数据元素的跨步图案分散的系统、装置及方法

Also Published As

Publication number Publication date
JP2017516226A (ja) 2017-06-15
US20150324196A1 (en) 2015-11-12
EP3143495A1 (en) 2017-03-22
WO2015175173A1 (en) 2015-11-19
CN106462391A (zh) 2017-02-22
JP6301501B2 (ja) 2018-03-28
KR20170007742A (ko) 2017-01-20
KR101863483B1 (ko) 2018-05-31
EP3143495B1 (en) 2023-08-16
EP3143495C0 (en) 2023-08-16
US9747104B2 (en) 2017-08-29

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Granted publication date: 20190705

Termination date: 20200421