JP6299578B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP6299578B2
JP6299578B2 JP2014253272A JP2014253272A JP6299578B2 JP 6299578 B2 JP6299578 B2 JP 6299578B2 JP 2014253272 A JP2014253272 A JP 2014253272A JP 2014253272 A JP2014253272 A JP 2014253272A JP 6299578 B2 JP6299578 B2 JP 6299578B2
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor element
metal
semiconductor device
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014253272A
Other languages
Japanese (ja)
Other versions
JP2016115806A (en
Inventor
卓矢 門口
卓矢 門口
清文 中島
清文 中島
慎介 青木
慎介 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP2014253272A priority Critical patent/JP6299578B2/en
Publication of JP2016115806A publication Critical patent/JP2016115806A/en
Application granted granted Critical
Publication of JP6299578B2 publication Critical patent/JP6299578B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、放熱板を有し樹脂封止された半導体装置に関する。   The present invention relates to a semiconductor device having a heat sink and sealed with resin.

パワー半導体モジュールとして、半導体素子と、当該半導体素子で発生した熱を放熱フィンへと導く放熱板とを含み、全体が樹脂封止された実装構造を有するものがある。当該放熱板は、例えば特許文献１および２に記載されているように、高熱伝導率を有するセラミックス材などからなる絶縁基板の両面に金属層が接合された構成をなす。放熱板の一方の金属層は回路配線をなすとともに、封止樹脂内で例えば半導体素子からの伝熱を行う金属体に接合され、他方の金属層は封止樹脂外に設けられた放熱フィンに接合される。   Some power semiconductor modules have a mounting structure that includes a semiconductor element and a heat radiating plate that guides heat generated in the semiconductor element to heat radiating fins and is entirely resin-sealed. For example, as described in Patent Documents 1 and 2, the heat radiating plate has a configuration in which metal layers are bonded to both surfaces of an insulating substrate made of a ceramic material having high thermal conductivity. One metal layer of the heat sink forms circuit wiring and is joined to a metal body that conducts heat from, for example, a semiconductor element in the sealing resin, and the other metal layer is attached to a heat radiating fin provided outside the sealing resin. Be joined.

特開２００８−０４１７５２号公報JP 2008-04-1752 A 特開２０１４−０６０４１０号公報JP 2014-060410 A

しかしながら、上述の実装構造においては、放熱板に備えられた絶縁基板と封止樹脂との密着性が低い。特に、絶縁基板の側面には、パワー半導体モジュールの冷熱サイクルに伴い大きな応力がかかる。したがって、封止樹脂が絶縁基板から剥がれることを抑制することが望ましい。   However, in the above-described mounting structure, the adhesion between the insulating substrate provided in the heat sink and the sealing resin is low. In particular, a large stress is applied to the side surface of the insulating substrate as the power semiconductor module cools and cools. Therefore, it is desirable to suppress the sealing resin from peeling off from the insulating substrate.

本発明は、上記課題に鑑み、放熱板に備えられた絶縁基板から封止樹脂が剥離することを抑制することのできる半導体装置を提供するものである。   In view of the above problems, the present invention provides a semiconductor device capable of suppressing the sealing resin from being peeled off from an insulating substrate provided in a heat sink.

第１の発明は、半導体装置であって、半導体素子と、前記半導体素子からの熱を放熱する放熱板と、前記半導体素子および前記放熱板の周囲を封止する封止樹脂とを備え、前記放熱板は、セラミックスよりなる絶縁基板と、前記絶縁基板の両面に積層された金属層とを有し、前記絶縁基板の側面に金属被膜が設けられている。   The first invention is a semiconductor device comprising a semiconductor element, a heat radiating plate that radiates heat from the semiconductor element, and a sealing resin that seals the periphery of the semiconductor element and the heat radiating plate, The heat radiating plate has an insulating substrate made of ceramics and a metal layer laminated on both surfaces of the insulating substrate, and a metal film is provided on a side surface of the insulating substrate.

第１の発明によれば、絶縁基板の側面に金属被膜が設けられている。金属被膜と封止樹脂との密着性は良好である。したがって、絶縁基板に対する封止樹脂の密着性は、当該金属被膜が設けられない場合と比較して向上する。これにより、冷熱サイクル時に絶縁基板の側面の周辺に応力が集中することにより封止樹脂が剥離しやすくなるという不具合を回避することができる。   According to the first invention, the metal film is provided on the side surface of the insulating substrate. The adhesion between the metal coating and the sealing resin is good. Therefore, the adhesion of the sealing resin to the insulating substrate is improved as compared with the case where the metal coating is not provided. As a result, it is possible to avoid the problem that the sealing resin is easily peeled off due to stress concentration around the side surface of the insulating substrate during the thermal cycle.

本発明によれば、放熱板に備えられた絶縁基板から封止樹脂が剥離することを抑制することのできる半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can suppress that sealing resin peels from the insulated substrate with which the heat sink was equipped can be provided.

本発明の実施形態に係る半導体装置の構成を示す断面図Sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention 本発明の実施形態に係る半導体装置の製造方法の一部を説明する図であり、（ａ）〜（ｄ）は絶縁基板の側面に金属被膜を形成する工程を説明する図It is a figure explaining a part of manufacturing method of the semiconductor device concerning the embodiment of the present invention, and (a)-(d) is a figure explaining the process of forming a metal coat on the side of an insulating substrate.

以下、図１および図２を参照しながら、実施の形態について詳細に説明する。本実施形態に係る半導体装置は、半導体素子と放熱板と封止樹脂とを備えている。放熱板はセラミックスよりなる絶縁基板と、当該絶縁基板の両面に積層された金属層とを有している。そして、絶縁基板の側面に金属被膜が設けられている。   Hereinafter, embodiments will be described in detail with reference to FIGS. 1 and 2. The semiconductor device according to the present embodiment includes a semiconductor element, a heat sink, and a sealing resin. The heat sink has an insulating substrate made of ceramics and a metal layer laminated on both surfaces of the insulating substrate. A metal film is provided on the side surface of the insulating substrate.

[半導体装置の構成]
図１に、本実施形態に係る半導体装置１の構成を示す。 [Configuration of semiconductor device]
FIG. 1 shows a configuration of a semiconductor device 1 according to the present embodiment.

半導体装置１は、半導体素子Ｄを備えている。半導体素子Ｄは、例えばパワー半導体素子のチップからなり、ここではＩＧＢＴ（Insulated Gate Bipolar Transistor）のチップであるとする。   The semiconductor device 1 includes a semiconductor element D. The semiconductor element D is composed of, for example, a chip of a power semiconductor element, and here, it is assumed that it is an IGBT (Insulated Gate Bipolar Transistor) chip.

半導体素子Ｄから見て上側に、順に、金属ブロック１１、ヒートスプレッダ１２、および、放熱板１３が積層されている。半導体素子Ｄから見て下側に、順に、ヒートスプレッダ２２および放熱板２３が積層されている。   A metal block 11, a heat spreader 12, and a heat radiating plate 13 are sequentially stacked on the upper side when viewed from the semiconductor element D. A heat spreader 22 and a heat radiating plate 23 are sequentially stacked on the lower side as viewed from the semiconductor element D.

半導体素子Ｄと金属ブロック１１とは接合層３１により接合されている。金属ブロック１１とヒートスプレッダ１２とは接合層３２により接合されている。半導体素子Ｄとヒートスプレッダ２２とは接合層３３により接合されている。金属ブロック１１、ヒートスプレッダ１２、および、ヒートスプレッダ２２は例えば銅からなる。接合層３１、接合層３２、および、接合層３３は、例えばはんだからなる。   The semiconductor element D and the metal block 11 are joined by a joining layer 31. The metal block 11 and the heat spreader 12 are joined by a joining layer 32. The semiconductor element D and the heat spreader 22 are bonded by a bonding layer 33. The metal block 11, the heat spreader 12, and the heat spreader 22 are made of, for example, copper. The bonding layer 31, the bonding layer 32, and the bonding layer 33 are made of, for example, solder.

放熱板１３は、半導体素子Ｄ側から見て、順に、金属層１３ａ、絶縁基板１３ｂ、および、金属層１３ｃが積層された構成である。放熱板２３は、半導体素子Ｄ側から見て、順に、金属層２３ａ、絶縁基板２３ｂ、および、金属層２３ｃが積層された構成である。絶縁基板１３ｂおよび絶縁基板２３ｂはセラミックスからなる。   The heat sink 13 has a configuration in which a metal layer 13a, an insulating substrate 13b, and a metal layer 13c are stacked in this order as viewed from the semiconductor element D side. The heat sink 23 has a configuration in which a metal layer 23a, an insulating substrate 23b, and a metal layer 23c are stacked in this order as viewed from the semiconductor element D side. The insulating substrate 13b and the insulating substrate 23b are made of ceramics.

また、絶縁基板１３ｂの外周端面をなす側面Ｅ１上に、当該側面Ｅ１を覆う金属被膜Ｍ１が設けられている。絶縁基板２３ｂの外周端面をなす側面Ｅ２上に、当該側面Ｅ２を覆う金属被膜Ｍ２が設けられている。   A metal film M1 that covers the side surface E1 is provided on the side surface E1 that forms the outer peripheral end surface of the insulating substrate 13b. On the side surface E2 that forms the outer peripheral end surface of the insulating substrate 23b, a metal coating M2 that covers the side surface E2 is provided.

半導体素子Ｄより上側の積層物はＩＧＢＴのエミッタ側の放熱経路を構成している。半導体素子Ｄより下側の積層物はＩＧＢＴのコレクタ側の放熱経路を構成している。   The laminate above the semiconductor element D constitutes a heat dissipation path on the emitter side of the IGBT. The laminate below the semiconductor element D forms a heat dissipation path on the collector side of the IGBT.

半導体素子Ｄと半導体素子Ｄの上下の積層物とからなる積層体の全体は、モールド樹脂（封止樹脂）４１によって封止されている。金属層１３ｃおよび金属層２３ｃの、半導体素子Ｄ側とは反対側の面は、モールド樹脂４１の外側に露出している。   The entire laminate including the semiconductor element D and the upper and lower laminates of the semiconductor element D is sealed with a mold resin (sealing resin) 41. The surfaces of the metal layer 13 c and the metal layer 23 c opposite to the semiconductor element D side are exposed to the outside of the mold resin 41.

[半導体装置のめっき工程について]
次に、図２を参照して、上述の金属被膜Ｍ１および金属被膜Ｍ２を形成する工程例を説明する。ここでは、金属被膜Ｍ１および金属被膜Ｍ２をニッケルなどからなるめっき層により構成する場合の工程例を説明する。 [About plating process of semiconductor devices]
Next, with reference to FIG. 2, an example process for forming the metal coating M1 and the metal coating M2 will be described. Here, an example of a process in the case where the metal coating M1 and the metal coating M2 are formed of a plating layer made of nickel or the like will be described.

図２（ａ）に示すように、窒化ケイ素の粉末を焼結および緻密化する工程により、窒化ケイ素（Ｓｉ３Ｎ４）のセラミックス膜５１を形成する。次いで、図２（ｂ）に示すように、酸化イットリウムガスの雰囲気中で、エキシマレーザなどのレーザ装置６１により、セラミックス膜５１を絶縁基板１３ｂおよび絶縁基板２３ｂの寸法に合せて切断加工する。これにより、図２（ｃ）に示すように、絶縁基板１３ｂの側面Ｅ１および絶縁基板２３ｂの側面Ｅ２となる切断面には、窒化ケイ素の表面が改質されて生じるＳｉ３Ｎ４・Ｙ２Ｏ３からなる改質膜５１ａが形成される。 As shown in FIG. 2A, a silicon nitride (Si 3 N 4 ) ceramic film 51 is formed by sintering and densifying silicon nitride powder. Next, as shown in FIG. 2B, the ceramic film 51 is cut in accordance with the dimensions of the insulating substrate 13b and the insulating substrate 23b by a laser device 61 such as an excimer laser in an atmosphere of yttrium oxide gas. As a result, as shown in FIG. 2C, Si 3 N 4 .Y 2 generated by modifying the surface of the silicon nitride on the cut surface that becomes the side surface E1 of the insulating substrate 13b and the side surface E2 of the insulating substrate 23b. A modified film 51a made of O 3 is formed.

そして、図２（ｄ）に示すように、図２（ｃ）で得られたセラミックス膜の全体をめっき工程に曝すことにより、改質膜５１ａのみがめっきされる。こうして、側面Ｅ１および側面Ｅ２に窒化ケイ素の表面改質を導入することにより、側面Ｅ１および側面Ｅ２に選択的に、めっき層からなる金属被膜Ｍ１および金属被膜Ｍ２が形成される。この後、絶縁基板１３ｂの両面に金属層１３ａおよび金属層１３ｃが接合されることにより放熱板１３が作成される。また、絶縁基板２３ｂの両面に金属層２３ａおよび金属層２３ｃが接合されることにより放熱板２３が作成される。放熱板１３および放熱板２３が、半導体素子Ｄを含む前述の積層体に組み上げられた後は、モールド樹脂４１による積層体の封止が行われる。この封止工程の前に、金属被膜Ｍ１上および金属被膜Ｍ２上にプライマーなどの密着性強化材を塗布してもよい。   Then, as shown in FIG. 2D, only the modified film 51a is plated by exposing the entire ceramic film obtained in FIG. 2C to a plating process. Thus, by introducing the surface modification of silicon nitride into the side surface E1 and the side surface E2, the metal coating M1 and the metal coating M2 made of plating layers are selectively formed on the side surface E1 and the side surface E2. Then, the heat sink 13 is created by joining the metal layer 13a and the metal layer 13c to both surfaces of the insulating substrate 13b. Moreover, the heat sink 23 is produced by joining the metal layer 23a and the metal layer 23c on both surfaces of the insulating substrate 23b. After the heat radiating plate 13 and the heat radiating plate 23 are assembled in the above-described laminated body including the semiconductor element D, the laminated body is sealed with the mold resin 41. Prior to this sealing step, an adhesion reinforcing material such as a primer may be applied on the metal coating M1 and the metal coating M2.

なお、金属被膜Ｍ１および金属被膜Ｍ２を、スパッタリングなどの堆積法により側面Ｅ１および側面Ｅ２上に形成するようにしてもよい。   Note that the metal coating M1 and the metal coating M2 may be formed on the side surface E1 and the side surface E2 by a deposition method such as sputtering.

［実施の形態の効果等］
本実施形態の半導体装置１では、絶縁基板１３ｂの側面Ｅ１に金属被膜Ｍ１が設けられている。また、絶縁基板２３ｂの側面Ｅ２に金属被膜Ｍ２が設けられている。金属被膜Ｍ１および金属被膜Ｍ２とモールド樹脂４１との密着性は良好である。したがって、絶縁基板１３ｂおよび絶縁基板２３ｂに対するモールド樹脂４１の密着性は、当該金属被膜が設けられない場合と比較して向上する。また、これら金属被膜上に密着性強化材を塗布することにより、金属被膜とモールド樹脂４１との密着性、したがって絶縁基板１３ｂおよび絶縁基板２３ｂに対するモールド樹脂４１の密着性は、さらに向上する。 [Effects of the embodiment, etc.]
In the semiconductor device 1 of this embodiment, the metal coating M1 is provided on the side surface E1 of the insulating substrate 13b. A metal film M2 is provided on the side surface E2 of the insulating substrate 23b. The adhesion between the metal coating M1 and the metal coating M2 and the mold resin 41 is good. Therefore, the adhesion of the mold resin 41 to the insulating substrate 13b and the insulating substrate 23b is improved as compared with the case where the metal coating is not provided. Further, by applying an adhesion reinforcing material on these metal coatings, the adhesion between the metal coating and the mold resin 41, and hence the adhesion of the mold resin 41 to the insulating substrate 13b and the insulating substrate 23b, is further improved.

側面Ｅ１および側面Ｅ２に金属被膜が形成されない場合には、半導体装置１に備えられたモールド樹脂４１のせん断耐性を示すシェア強度は、例えば８ＭＰａといった小さい値である。これに対して、側面Ｅ１および側面Ｅ２に金属被膜が形成され、さらに金属被膜にプライマーが塗布される場合には、当該シェア強度は、例えば２５ＭＰａといった大きな値となる。金属被膜が形成される場合の当該シェア強度は、側面Ｅ１および側面Ｅ２にプライマーが塗布されたのみの場合の１５ＭＰａ程度のシェア強度と比較しても、大きな値である。   When the metal film is not formed on the side surface E1 and the side surface E2, the shear strength indicating the shear resistance of the mold resin 41 provided in the semiconductor device 1 is a small value, for example, 8 MPa. On the other hand, when a metal film is formed on the side surface E1 and the side surface E2, and further a primer is applied to the metal film, the shear strength is a large value, for example, 25 MPa. The shear strength when the metal coating is formed is a large value even when compared with the shear strength of about 15 MPa when only the primer is applied to the side surface E1 and the side surface E2.

このように、半導体装置１によれば、冷熱サイクル時に側面Ｅ１および側面Ｅ２の周辺に応力が集中しても、絶縁基板１３ｂおよび絶縁基板２３ｂに対するモールド樹脂４１の密着性が向上することにより、モールド樹脂４１が剥離することを抑制することができる。また、当該密着性が向上することにより、モールド樹脂４１に割れが発生することを抑制することができる。   As described above, according to the semiconductor device 1, even when stress is concentrated around the side surface E1 and the side surface E2 during the cooling / heating cycle, the adhesion of the mold resin 41 to the insulating substrate 13b and the insulating substrate 23b is improved. It can suppress that resin 41 peels. Moreover, it can suppress that a crack generate | occur | produces in the mold resin 41 by the said adhesiveness improving.

本発明は、パワー半導体素子などの放熱構造を有する半導体素子を有する半導体装置などに適用可能である。   The present invention is applicable to a semiconductor device having a semiconductor element having a heat dissipation structure such as a power semiconductor element.

１ 半導体装置
１１ 金属ブロック
１２、２２ ヒートスプレッダ
１３、２３ 放熱板
１３ａ、１３ｃ、２３ａ、２３ｃ 金属層
１３ｂ、２３ｂ 絶縁基板
３１、３２、３３ 接合層
４１ モールド樹脂
５１ セラミックス膜
５１ａ 改質膜
６１ レーザ装置
Ｄ 半導体素子
Ｅ１、Ｅ２ 側面
Ｍ１、Ｍ２ 金属被膜 DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Metal block 12, 22 Heat spreader 13, 23 Heat sink 13a, 13c, 23a, 23c Metal layer 13b, 23b Insulating substrate 31, 32, 33 Bonding layer 41 Mold resin 51 Ceramic film 51a Modified film 61 Laser apparatus D Semiconductor element E1, E2 Side surface M1, M2 Metal coating

Claims (1)

半導体素子と、
前記半導体素子からの熱を放熱する放熱板と、
前記半導体素子および前記放熱板の周囲を封止する封止樹脂とを備え、
前記放熱板は、
セラミックスよりなる絶縁基板と、
前記絶縁基板の両面に積層された金属層とを有し、
前記絶縁基板の側面に金属被膜が設けられている、
ことを特徴とする半導体装置。 A semiconductor element;
A heat sink for radiating heat from the semiconductor element;
A sealing resin for sealing the periphery of the semiconductor element and the heat sink;
The heat sink is
An insulating substrate made of ceramics;
A metal layer laminated on both sides of the insulating substrate;
A metal coating is provided on the side surface of the insulating substrate,
A semiconductor device.
JP2014253272A 2014-12-15 2014-12-15 Semiconductor device Active JP6299578B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014253272A JP6299578B2 (en) 2014-12-15 2014-12-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014253272A JP6299578B2 (en) 2014-12-15 2014-12-15 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2016115806A JP2016115806A (en) 2016-06-23
JP6299578B2 true JP6299578B2 (en) 2018-03-28

Family

ID=56140223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014253272A Active JP6299578B2 (en) 2014-12-15 2014-12-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JP6299578B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7309127B2 (en) 2019-10-11 2023-07-18 Toto株式会社 Automatic faucet device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6988345B2 (en) * 2017-10-02 2022-01-05 株式会社デンソー Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001093924A (en) * 1999-09-24 2001-04-06 Kyocera Corp Ceramic circuit board and manufacturing method for electronic device using the same
JP4591362B2 (en) * 2006-01-25 2010-12-01 株式会社デンソー Manufacturing method of electronic device
JP2008041752A (en) * 2006-08-02 2008-02-21 Hitachi Metals Ltd Semiconductor module, and radiation board for it
DE112009005537B3 (en) * 2008-04-09 2022-05-12 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7309127B2 (en) 2019-10-11 2023-07-18 Toto株式会社 Automatic faucet device

Also Published As

Publication number Publication date
JP2016115806A (en) 2016-06-23

Similar Documents

Publication Publication Date Title
US9397017B2 (en) Substrate structures and methods of manufacture
CN107112316B (en) Semiconductor module
US9984951B2 (en) Sintered multilayer heat sinks for microelectronic packages and methods for the production thereof
US8987875B2 (en) Balanced stress assembly for semiconductor devices
WO2015064430A1 (en) Laminate body, insulating cooling plate, power module, and production method for laminate body
US9230889B2 (en) Chip arrangement with low temperature co-fired ceramic and a method for forming a chip arrangement with low temperature co-fired ceramic
JP2013093631A (en) Power module manufacturing method
JP2011216564A (en) Power module and method of manufacturing the same
JP6094533B2 (en) Semiconductor device
JP2018049938A (en) Semiconductor device
JP6435711B2 (en) Power module substrate with heat sink and power module
JPWO2015132969A1 (en) Insulating substrate and semiconductor device
US10141199B2 (en) Selecting a substrate to be soldered to a carrier
JP6299578B2 (en) Semiconductor device
JP6183166B2 (en) Power module substrate with heat sink and manufacturing method thereof
JP2011054889A (en) Resin sealing semiconductor device, and method of manufacturing the same
TW201415683A (en) Mrthod for bonding heat-conducting substraye and metal layer
JP2017174875A (en) Circuit board and semiconductor module, manufacturing method of circuit board
JP6380076B2 (en) Semiconductor device
JP2014143342A (en) Semiconductor module and manufacturing method of the same
US9408301B2 (en) Substrate structures and methods of manufacture
JP2011198864A (en) Power semiconductor device and method of manufacturing the same
JP2016162888A (en) Electronic device
US20230154811A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP2018018932A (en) Semiconductor module

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170413

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180122

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180130

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180212

R151 Written notification of patent or utility model registration

Ref document number: 6299578

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250