JP6298746B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a GaN-based field effect transistor.

  Unlike Si-based field effect transistors, GaN-based field effect transistors use a two-dimensional electron gas generated by piezoelectric polarization and spontaneous polarization as a carrier at a heterojunction portion between an AlGaN layer and a GaN layer. Therefore, when a stress due to the transistor structure is generated, the piezoelectric polarization effect changes at the stress generation location, and as a result, the two-dimensional electron gas concentration changes.

  In addition, the stress causes distortion in the AlGaN layer, the GaN layer, the insulating film formed on the AlGaN layer, the upper portion thereof, and the insulating film interface, and the trap state density increases.

  Therefore, due to the above-described change in the two-dimensional electron gas concentration and increase in trap level density, there are problems such as non-uniformity of on-resistance, dielectric breakdown near the drain electrode or the drain electrode due to electric field concentration, and fluctuation of on-resistance. Will occur.

  As described above, a stress is not a problem in the Si field effect transistor, but a problem is caused in the GaN field effect transistor. Therefore, a device structure for relaxing the stress is required.

  Conventionally, as a Si-based field effect transistor, there is a semiconductor device disclosed in Japanese Patent Laid-Open No. 2010-219504 (Patent Document 1). In this semiconductor device, a plurality of via holes are provided on a metal wiring, and the number of the via holes is adjusted, so that the propagation speed of a surge or the like is made uniform throughout the entire multi-finger.

  However, in the semiconductor device, the stress relaxation is not considered at all.

  As a GaN-based field effect transistor for reducing parasitic capacitance, there is a field effect transistor disclosed in WO2014 / 073295 (Patent Document 2). In this field effect transistor, the source electrode pad formed on the source electrode and electrically connected to the source electrode is provided with a notch for reducing parasitic capacitance with the drain electrode. The drain electrode pad formed on the drain electrode and electrically connected to the drain electrode is provided with a notch for reducing parasitic capacitance between the drain electrode pad and the source electrode. At that time, via holes for electrically connecting the source electrode pad to the source electrode and via holes for electrically connecting the drain electrode pad to the drain electrode are provided at both longitudinal ends of each pad. To improve the current collection efficiency.

  However, in the field effect transistor having the above structure, the via hole is connected to only two places per one finger-shaped drain electrode or finger-shaped source electrode. Therefore, there is a problem that the stress generated by the insulating film in which the via holes on both the finger-like electrodes are formed cannot be sufficiently relaxed.

JP 2010-219504 A WO2014 / 073295

  Accordingly, an object of the present invention is to provide a highly reliable field effect transistor that can prevent electric field concentration on a drain electrode or a gate electrode when a high voltage is applied by relaxing stress concentration on a finger electrode. is there.

In order to solve the above problems, the field effect transistor of the present invention is
A GaN-based laminate having a heterojunction;
A drain electrode formed on the GaN-based laminate and extending in a finger shape;
It is formed on the GaN-based laminate so as to extend in a finger shape and is arranged so as to be adjacent to the drain electrode in a direction intersecting with the longitudinal direction which is the extending direction of the drain electrode. A source electrode extending to
A gate electrode formed between the drain electrode and the source electrode;
An insulating film formed on the drain electrode and the source electrode;
A drain electrode pad formed on the insulating film;
A drain-side via hole that is formed in the insulating film and electrically connects the drain electrode and the drain electrode pad;
A source electrode pad formed on the insulating film;
A source-side via hole that is formed in the insulating film and electrically connects the source electrode and the source electrode pad;
A hole having a space for relieving stress on the drain electrode and the source electrode is provided in the insulating film on the drain electrode and the source electrode.

In the field effect transistor of one embodiment,
The drain side via-hole Le has an opening within 50μm from the edge of the drain electrode,
The source side via-hole Le has an opening within 50μm from the edge of the source electrode.

In the field effect transistor of one embodiment,
An interval between the drain side via hole and the hole having a space for relaxing the stress, and an interval between the source side via hole and the hole having the space for relaxing the stress are equal.

  As apparent from the above, the field effect transistor according to the present invention has holes for relaxing stress on the drain electrode and the source electrode at locations on the drain electrode and the source electrode in the insulating film. It has been.

  As described above, in addition to the drain-side via hole and the source-side via hole for improving the current collection efficiency, holes for relaxing stress due to the insulating film on the finger-shaped drain electrode and the source electrode are arranged. By this, in addition to the change in material from the insulating film to the metal in the via holes, the internal stress generated by the insulating film can be divided by the change in material from the insulating film to the hole space. it can.

  Therefore, stress on the finger-shaped drain electrode and source electrode can be relieved, and when high voltage is applied, dielectric breakdown or characteristic fluctuation hardly occurs in the drain electrode or source electrode or the gate electrode in the vicinity of both electrodes. A highly reliable field effect transistor can be provided.

  Here, even if the number of the drain-side via holes and the source-side via holes is increased, the stress generated by the insulating film can be further relaxed. However, the change from the insulating film to the space of the hole is more excellent in the function of dividing internal stress than the change from the insulating film to the metal in the via holes. Therefore, the internal stress can be more effectively divided by providing the stress relaxation holes than by increasing the number of via holes.

It is a schematic diagram which shows the planar structure in the field effect transistor of this invention. It is AA 'arrow sectional drawing in FIG. It is a schematic diagram which shows the planar structure of the field effect transistor different from FIG.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a schematic diagram showing a planar structure of a field effect transistor according to the first embodiment. 2 is a cross-sectional view taken along the line AA ′ in FIG. The field effect transistor of the first embodiment is a GaN HFET (heterojunction field effect transistor).

  As shown in FIG. 2, in this embodiment, an undoped GaN layer 2 and an undoped AlGaN layer 3 are formed in order on the Si substrate 1. The undoped GaN layer 2 and the undoped AlGaN layer 3 constitute a GaN-based laminate that forms a heterojunction. Here, 2DEG (two-dimensional electron gas) 4 is generated at the interface between the undoped GaN layer 2 and the undoped AlGaN layer 3.

A protective film 5 and an interlayer insulating film 6 are sequentially formed on the GaN-based laminate. As the material of the protective film 5, although in this embodiment uses a SiN, it may be used SiO _2, Al ₂ O ₃ or the like. In the present embodiment, the thickness of the SiN protective film 5 is 150 nm, but may be set to other values within the range of 20 nm to 250 nm. As the material of the interlayer insulating film 6, an SiN film is used in the present embodiment, but an SiO ₂ film or a laminated structure of an SiN film and an SiO ₂ film may be used.

  At that time, a recess reaching the undoped GaN layer 2 is formed in the GaN-based laminate and the protective film 5 formed thereon, and a drain electrode base portion 7 forming an ohmic electrode is formed in the recess. Yes. Further, a recess reaching the undoped GaN layer 2 is similarly formed in the protective film 5, and a source electrode base portion 8 forming an ohmic electrode is formed in the recess. In this embodiment, the drain electrode base 7 and the source electrode base 8 are Ti / Al / TiN electrodes in which a Ti layer, an Al layer, and a TiN layer are sequentially stacked.

  A drain electrode 9 is formed on the drain electrode base 7 with the same material as the drain electrode base 7. A source electrode 10 is formed on the source electrode base 8 with the same material as the source electrode base 8.

  An opening is formed in the protective film 5, and a gate electrode 11 is formed in the opening. The gate electrode 11 is made of TiN in the present embodiment, and forms a Schottky electrode that forms a Schottky junction with the undoped AlGaN layer 3.

  Here, a plurality of the drain electrodes 9 and the source electrodes 10 exist, and as shown in FIG. 1, they are arranged in parallel to form a finger shape. The source electrodes 10 and the drain electrodes 9 are alternately arranged in a direction intersecting the longitudinal direction that is the finger-like extending direction.

  As shown in FIGS. 1 and 2, the drain electrode pad 12 and the source electrode pad 13 extend on the interlayer insulating film 6 in a direction crossing the longitudinal direction and are parallel to the longitudinal direction. Is formed.

  The drain electrode pad 12 and the drain electrode 9 are electrically connected through a drain side via hole 14 opened in the interlayer insulating film 6 (see FIG. 2) between them. Similarly, the source electrode pad 13 and the source electrode 10 are electrically connected through a source-side via hole 15 opened in the interlayer insulating film 6 (see FIG. 2) between them. Here, the drain side via hole 14 and the source side via hole 15 are formed by filling a metal such as Ti / Al / TiN into a through hole formed in the interlayer insulating film 6. Here, the metal filled in the through hole may be Ti / Al, Hf / Al, Ti / AlCu / TiN, or Ti / AlSi / TiN. Although not shown in FIG. 1, the gate electrode 11 is connected to the gate electrode pad by a gate electrode connection wiring.

  The GaN HFET of the present embodiment having the above configuration is a normally-on type, and is turned off by applying a negative voltage to the gate electrode 11.

  As shown in FIG. 1, the drain side via hole 14 is formed in two places on one drain electrode 9 in this embodiment, but it may be formed in two or more places. An opening is provided on the drain electrode 9 in the interlayer insulating film 6 between the drain-side via holes 14 arranged at two or more locations to form a stress relief hole 16. One or more holes 16 are provided for each drain electrode 9.

  The hole 16 is for separating stress on the drain electrode 9 caused by the interlayer insulating film 6. Therefore, the hole 16 does not need to be formed by completely opening the interlayer insulating film 6 up to the surface of the drain electrode 9, and may have a depth that can divide the stress.

  Further, in the present embodiment, the source side via hole 15 is formed in two places on one source electrode 10, but it may be formed in two or more places. An opening is provided on the source electrode 10 in the interlayer insulating film 6 between the source-side via holes 15 arranged at two or more locations to form a hole 17 for relaxing stress. One or more holes 17 are provided for each source electrode 10.

  The hole 17 is for dividing the stress applied to the source electrode 10 by the interlayer insulating film 6. Therefore, the hole 17 does not need to be formed by completely opening the interlayer insulating film 6 up to the surface of the source electrode 10, and may have a depth that can divide the stress.

  As described above, according to the present embodiment, the interlayer insulating film 6 is formed at the positions of the drain electrode pad 12 and the source electrode pad 13 in the interlayer insulating film 6 formed on the drain electrode 9 and the source electrode 10. Holes 16 and 17 for relaxing stress are formed between the plurality of drain-side via holes 14 and between the plurality of source-side via holes 15.

  Therefore, by arranging the stress relaxation holes 16 and 17 as described above, in addition to the change in the material of the metal and the interlayer insulating film 6 of the drain side via hole 14 and the source side via hole 15, the stress relaxation hole. The internal stress generated by the interlayer insulating film 6 with respect to the drain electrode 9 and the source electrode 10 can be divided and relaxed by changing the material of the spaces 16 and 17 and the interlayer insulating film 6. An increase in the two-dimensional electron gas concentration in the finger portion made of the electrode 10 can be suppressed.

  Therefore, when a high voltage is applied, electric field concentration on the drain electrode 9 or the source electrode 10, or the gate electrode 11 near the drain electrode 9 or the gate electrode 11 near the source electrode 10 can be suppressed. A highly reliable field effect transistor capable of preventing dielectric breakdown and characteristic fluctuation can be formed.

  Here, even if the number of the drain side via holes 14 and the source side via holes 15 is increased, the stress generated by the interlayer insulating film 6 can be further relaxed. However, the change from the interlayer insulating film 6 to the space of the holes 16 and 17 is superior in the function of dividing internal stress than the change from the interlayer insulating film 6 to the metal in the via holes 14 and 15. Therefore, the internal stress can be more effectively divided by providing the stress relaxation holes 16 and 17 than by increasing the number of the via holes 14 and 15.

  In the embodiment described above, the holes 16 and 17 are formed between the plurality of drain side via holes 14 and between the plurality of source side via holes 15 to relieve stress. The location of the hole for relieving the stress is not limited between the via holes 14 and 15, and may be formed at the end of the drain electrode 9 or the end of the source electrode 10.

Second Embodiment The field effect transistor according to the second embodiment is the same as the GaN HFET according to the first embodiment, in which the electrode pad and the electrode are electrically connected to the stress dividing hole (for stress relaxation). The function of the via hole to be connected is provided.

  The basic structure of the GaN HFET in the second embodiment is the same as that of the GaN HFET in the first embodiment. Therefore, the same members as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Hereinafter, a configuration unique to the present embodiment will be described.

  That is, in the GaN HFET according to the present embodiment, the stress dividing (stress relaxation) hole 16 also serves as a via hole for electrically connecting the drain electrode pad 12 and the drain electrode 9. The hole 17 for stress separation (for stress relaxation) also serves as a via hole for electrically connecting the source electrode pad 13 and the source electrode 10.

  In this embodiment, the stress dividing holes 16 and 17 are filled with a metal such as Ti / Al / TiN, as in the case of the drain side via hole 14 and the source side via hole 15. ing. Therefore, it is possible to have both the function of dividing the stress on the electrodes 9 and 10 and the function of electrically connecting the electrode pads 12 and 13 and the electrodes 9 and 10.

  Therefore, in the present embodiment, the stress relaxation hole 16 and the hole 17 functioning as the via hole can be formed simultaneously with the through hole of the drain side via hole 14 and the source side via hole 15. Therefore, the internal stress generated by the interlayer insulating film 6 with respect to the drain electrode 9 or the source electrode 10 can be relieved without increasing the number of steps, and the two-dimensional electron gas concentration in the finger portion composed of the drain electrode 9 and the source electrode 10 can be reduced. Can be suppressed.

  Therefore, when a high voltage is applied, electric field concentration on the drain electrode 9 or the source electrode 10, or the gate electrode 11 near the drain electrode 9 or the gate electrode 11 near the source electrode 10 can be suppressed. A highly reliable field effect transistor capable of preventing dielectric breakdown and characteristic fluctuation can be formed.

  Further, depending on the use environment, a load short-circuit tolerance may be required. When the load is short-circuited, a high-voltage and high-current state stress is applied to the transistor, and when there is a non-uniform operation in the transistor, a problem occurs that a hot spot is generated and the short-circuit tolerance is reduced. As a result of the load short-circuit experiment, it was found that the dielectric breakdown at the time of the load short-circuit was thermal breakdown in the vicinity of the drain electrode 9. Therefore, in order to improve the short-circuit tolerance, it is effective to suppress the heat generation near the drain electrode 9 or improve the heat dissipation.

  In particular, in a GaN HFET using a Si substrate, a buffer layer (superlattice layer) may be provided at the boundary between Si and GaN. In that case, since the thermal resistance of the superlattice layer is about 10 times higher than the thermal resistance of GaN, the heat dissipation in the extending direction of the Si substrate is extremely poor. Therefore, the heat dissipation toward the metal made of the drain electrode pad 12 through the drain side via hole 14 is important.

  In the present embodiment, since the electric field concentration at the location of the drain electrode 9 can be suppressed, the amount of heat expressed by local “voltage × current” is suppressed. Furthermore, by making the stress dividing hole 16 function as a via hole in addition to the drain-side via hole 14, the heat dissipation near the drain electrode 9 can also be improved, so that a large short-circuit withstanding improvement effect is expected.

Third Embodiment The field effect transistor of the third embodiment defines the distance from the end of the corresponding electrode of the via hole located on the end side of both electrodes in the GaN HFET of the first embodiment. To do.

  FIG. 3 is a schematic diagram showing a planar structure of the GaN HFET of the third embodiment. The basic structure of the GaN HFET in this embodiment is the same as that of the GaN HFET in the first embodiment. Therefore, the same members as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Hereinafter, a configuration unique to the present embodiment will be described.

  That is, in the GaN HFET in the present embodiment, the distance L1 from the end of the drain electrode 9 at least a part of the via hole opening portion in the drain side via hole 14a located on the end side of the drain electrode 9 is set within 50 μm. To do. On the other hand, the distance L2 from the end of the source electrode 10 at least part of the via hole opening in the source side via hole 15a located on the end side of the source electrode 10 is set within 50 μm.

  As described above, in the present embodiment, at least one of the via-hole openings in the drain-side via hole 14a and the source-side via hole 15a is within 50 μm from the end of the drain electrode 9 where stress is likely to concentrate and within 50 μm from the end of the source electrode 10. The part is set. Therefore, the stress on the end of the drain electrode 9 and the end of the source electrode 10 where stress tends to concentrate can be divided by the drain side via hole 14a and the source side via hole 15a.

  As a result, the concentration of internal stress on the end of the drain electrode 9 and the end of the source electrode 10 can be alleviated, and a highly reliable field effect transistor that is less prone to dielectric breakdown and characteristic variation is formed. Can do it.

  In the present embodiment, via hole openings are formed in all drain side via holes 14a located on the end side of the drain electrode 9 and all source side via holes 15a located on the end side of the source electrode 10. At least a part of the portion is set within 50 μm from the end of the drain electrode 9 or the source electrode 10.

  However, the present invention is not limited to this. In the GaN HFET according to the second embodiment, at least one of the drain-side via hole 14 or the via hole formed of the stress relieving hole 16 is formed on the drain electrode 9. It is only necessary that at least one of the source-side via hole 15 or the via hole composed of the hole 17 for relaxing stress is located within 50 μm from the end of the source electrode 10.

  Therefore, the via hole formed by the hole 16 for relaxing the stress positioned at the extreme end of the drain electrode 9 and the via hole formed by the hole 17 for relaxing the stress positioned at the extreme end of the source electrode 10 are formed on the electrodes 9 and 10. It may be located within 50 μm from the end. Further, the drain side via hole 14a located at the extreme end of the drain electrode 9 and the via hole formed by the hole 16 adjacent to the drain side via hole 14a and the source side via hole 15a located at the extreme end of the source electrode 10 are adjacent to the via hole. There may be a case where the via hole formed of the hole 17 for relaxing the stress is located within 50 μm from the end of each electrode 9, 10.

  In each of the above embodiments, the distance between the drain side via hole 14 and the hole 16 for relaxing the stress, or the distance between the drain side via hole 14 and the hole for relaxing the stress functioning as the drain side via hole. And the interval between the source side via hole 15 and the hole 17 for relaxing the stress and the interval between the source side via hole 15 and the hole for relaxing the stress functioning as the source side via hole are set at equal intervals. Is desirable.

  As described above, the via holes 14 and 15, the holes 16 and 17, and the holes functioning as the via holes having a function of dividing the stress caused by the interlayer insulating film 6 are arranged substantially evenly in the interlayer insulating film 6. Even if the stress on the finger-shaped drain electrode 9 and the finger-shaped source electrode 10 is generated at any location in the interlayer insulating film 6, it can be effectively divided.

  In each of the above embodiments, the GaN HFET in which the GaN layer and the AlGaN layer are sequentially stacked on the Si substrate has been described as an example. However, the following effects can be obtained even in the following modifications. This corresponds to the present invention.

  That is, a sapphire substrate or SiC substrate may be used as the substrate, and a nitride semiconductor layer may be grown on the sapphire substrate or SiC substrate. Further, a nitride semiconductor layer may be grown on a nitride semiconductor substrate using a substrate made of a nitride semiconductor, such as growing an AlGaN layer on a GaN substrate. Further, a buffer layer may be formed between the substrate and each layer as appropriate. A hetero improvement layer may be formed of AlN between the undoped GaN layer 2 and the undoped AlGaN layer 3. Further, a GaN cap layer may be formed on the undoped AlGaN layer 3.

  In each of the above embodiments, a finger type HFET having a plurality of drain electrodes 9 and source electrodes 10 has been described. However, the field effect transistor of the present invention is not limited to this. For example, the present invention may be applied to a field effect transistor having one set of a gate electrode, a source electrode, and a drain electrode.

  In each of the above embodiments, a recess reaching the undoped GaN layer 2 is formed, and the drain electrode 9 and the source electrode 10 are formed as ohmic electrodes in the recess. However, the present invention is not limited to this. For example, without forming the recess, the layer thickness of the undoped AlGaN layer 3 on the undoped GaN layer 2 is reduced, and the drain electrode and the source electrode are directly formed on the thin undoped AlGaN layer 3. The drain electrode and the source electrode may be ohmic electrodes.

  In each of the above embodiments, the gate electrode 11 is formed of TiN. However, the gate electrode 11 may be formed of WN, Ti / Au, or Ni / Au. Furthermore, although the drain electrode 9 and the source electrode 10 are formed of Ti / Al / TiN, they may be formed of Ti / Al, Hf / Al, Ti / AlCu / TiN, or Ti / AlSi / TiN. It may be formed. Further, the drain electrode 9 and the source electrode 10 may be formed by stacking Ni / Au on Ti / Al or Hf / Al, or by stacking Pt / Au on Ti / Al or Hf / Al. Alternatively, Au may be laminated on Ti / Al or Hf / Al.

In each of the above embodiments, the protective film 5 is made of SiN. However, the protective film 5 may be made of SiO ₂ , Al ₂ O ₃ or the like, and a laminated film in which an SiO ₂ film is laminated on the SiN film. It is good.

In each of the above embodiments, the GaN-based laminate is composed of Al _X Ga _1-X N (0 ≦ X <1), but Al _X In _Y Ga _1-XY N (X ≧ It may be a GaN-based semiconductor layer represented by 0, Y ≧ 0, 0 ≦ X + Y <1). That is, the GaN-based laminate may include AlGaN, GaN, InGaN, or the like.

  In each of the above embodiments, a normally-on type HFET has been described. However, the present invention may be applied to a normally-off type HFET.

  Although specific embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. Various modifications can be made within the scope of the present invention.

Hereinafter, when this invention is summarized, the field effect transistor of this invention is:
GaN-based laminates 2 and 3 having heterojunctions;
A drain electrode 9 formed on the GaN-based laminates 2 and 3 and extending in a finger shape;
It is formed on the GaN-based laminates 2 and 3 so as to extend in a finger shape, and is arranged so as to be adjacent to the drain electrode 9 in a direction crossing the longitudinal direction which is the extending direction of the drain electrode 9. A source electrode 10 extending in the longitudinal direction,
A gate electrode 11 formed between the drain electrode 9 and the source electrode 10;
An insulating film 6 formed on the drain electrode 9 and the source electrode 10;
A drain electrode pad 12 formed on the insulating film 6;
A drain-side via hole 14 formed in the insulating film 6 and electrically connecting the drain electrode 9 and the drain electrode pad 12;
A source electrode pad 13 formed on the insulating film 6;
A source-side via hole 15 formed in the insulating film 6 and electrically connecting the source electrode 10 and the source electrode pad 13;
Holes 16 and 17 for relaxing stress on the drain electrode 9 and the source electrode 10 are provided at locations on the drain electrode 9 and the source electrode 10 in the insulating film 6.

  According to the above configuration, the holes 16 and 17 for relieving stress on the drain electrode 9 and the source electrode 10 are provided on the insulating film 6 on the drain electrode 9 and the source electrode 10. ing. Thus, in addition to the drain side via hole 14 and the source side via hole 15, holes 16 and 17 for relaxing stress due to the insulating film 6 to the finger-shaped drain electrode 9 and the source electrode 10 are arranged. Thus, in addition to the change in material from the insulating film 6 to the metal in the via holes 14 and 15, the change in material from the insulating film 6 to the space of the holes 16 and 17 causes the insulating film 6 to change. The internal stress caused by can be cut off.

  Therefore, it is possible to relieve stress on the finger-shaped drain electrode 9 and the source electrode 10 and to provide a highly reliable field effect transistor that hardly causes dielectric breakdown or characteristic variation.

In the field effect transistor of one embodiment,
The holes 16 and 17 for relaxing the stress are a via hole that electrically connects the drain electrode 9 and the drain electrode pad 12, and a via hole that electrically connects the source electrode 10 and the source electrode pad 13. Function as.

  According to this embodiment, since the holes 16 and 17 that relieve stress due to the insulating film 6 to the finger-shaped drain electrode 9 and the source electrode 10 function as the via hole, the stress that functions as the via hole. The relaxation holes 16 and 17 can be formed when the through holes of the via holes 14 and 15 are formed. Therefore, it is possible to form a hole that relaxes the stress that functions as the via hole without increasing the number of steps.

In the field effect transistor of one embodiment,
At least one of the drain side via hole 14 and the hole for relaxing the stress functioning as the drain side via hole has an opening within 50 μm from the end of the drain electrode 9,
At least one of the source side via hole 15 and the hole for relaxing the stress functioning as the source side via hole has an opening within 50 μm from the end of the source electrode 10.

  According to this embodiment, the drain-side via hole can divide the stress at a position close to the ends of the finger-shaped drain electrode 9 and the source electrode 10 where stress due to the insulating film 6 is likely to concentrate. 14 or a hole that relaxes the stress that functions as the via hole on the drain side, and a hole that relaxes the stress that functions as the source side via hole 15 or the via hole on the source side. Therefore, the stress to the end of the drain electrode 9 and the end of the source electrode 10 where stress tends to concentrate can be divided by the via holes 14 and 15 or the hole that relaxes the stress that functions as the via hole.

  As a result, it is possible to further relieve the stress on the finger-shaped drain electrode 9 and the source electrode 10 and to provide a field effect transistor that is less prone to dielectric breakdown and characteristic variation.

In the field effect transistor of one embodiment,
An interval between the drain side via hole 14 and the hole 16 for relaxing the stress or the hole for relaxing the stress functioning as the drain side via hole, and the source side via hole 15 and the hole 17 for relaxing the stress or The intervals between the stress relief holes functioning as the source-side via holes are equally spaced.

  According to this embodiment, the via holes 14 and 15, the holes 16 and 17, and the holes functioning as the via holes having a function of dividing the stress caused by the insulating film 6 are substantially formed in the insulating film 6. It can be evenly arranged.

  Therefore, even if the stress on the finger-shaped drain electrode 9 and the finger-shaped source electrode 10 is generated at any location in the insulating film 6, it can be effectively divided.

DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Undoped GaN layer 3 ... Undoped AlGaN layer 4 ... 2DEG
DESCRIPTION OF SYMBOLS 5 ... Protective film 6 ... Interlayer insulating film 7 ... Drain electrode base 8 ... Source electrode base 9 ... Drain electrode 10 ... Source electrode 11 ... Gate electrode 12 ... Drain electrode pad 13 ... Source electrode pad 14 ... Drain side via hole 15 ... Source side Via holes 16, 17 ... holes for stress relaxation

Claims (3)

A GaN-based laminate having a heterojunction;
A drain electrode formed on the GaN-based laminate and extending in a finger shape;
It is formed on the GaN-based laminate so as to extend in a finger shape and is arranged so as to be adjacent to the drain electrode in a direction intersecting with the longitudinal direction which is the extending direction of the drain electrode. A source electrode extending to
A gate electrode formed between the drain electrode and the source electrode;
An insulating film formed on the drain electrode and the source electrode;
A drain electrode pad formed on the insulating film;
A drain-side via hole that is formed in the insulating film and electrically connects the drain electrode and the drain electrode pad;
A source electrode pad formed on the insulating film;
A source-side via hole that is formed in the insulating film and electrically connects the source electrode and the source electrode pad;
A field effect transistor , wherein a hole having a space for relieving stress on the drain electrode and the source electrode is provided at a position on the drain electrode and the source electrode in the insulating film. The field effect transistor according to claim 1 .
The drain side via-hole Le has an opening within 50μm from the edge of the drain electrode,
The source side via-hole Le, the field effect transistor and having an opening within 50μm from the edge of the source electrode. The field effect transistor according to claim 1 or 2 ,
An interval between the drain-side via hole and the hole having a space for relaxing the stress, and an interval between the source-side via hole and the hole having a space for relaxing the stress are equal. Field effect transistor.

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