JP6287277B2 - 3-phase rectifier - Google Patents

Description

  The present invention relates to a three-phase rectifier.

  In Patent Document 1, in a three-phase rectifier, a bidirectional switch circuit that turns on / off each phase input from a three-phase AC power source to a full-wave rectifier circuit is controlled based on a switching pattern of a predetermined switching cycle. Is described. Thereby, according to patent document 1, it is supposed that the alternating current input can be made into the sine wave from which the harmonic was reduced, and the output DC voltage can be made constant.

JP 2011-30409 A

  However, as a result of investigation by the present inventor, it has been found that the technique described in Patent Document 1 may increase the harmonics included in the input AC current or cause the output DC voltage to pulsate.

  This invention is made | formed in view of the above, Comprising: It aims at obtaining the three-phase rectifier which can reduce the harmonic contained in an input alternating current, and can suppress the pulsation of an output DC voltage.

In order to solve the above-described problems and achieve the object, the three-phase rectifier according to the first aspect of the present invention is a three-phase rectifier that converts three-phase AC power input from a three-phase AC power source into DC power. And a full-wave rectifier circuit that rectifies the three-phase alternating current power into direct-current power, and a plurality of switching elements that turn on / off each phase supply from the three-phase alternating current power source to the full-wave rectifier circuit. In accordance with a reference signal corresponding to the switch circuit and the three-phase AC power, a switching pattern of each phase for turning on / off the bidirectional switch circuit is generated, and the both are generated based on the generated switching pattern. Control means for switching control of a direction switch circuit, the control means according to the reference signal, a carrier generation unit for generating a carrier signal, and according to the reference signal, A generation unit that generates a control signal corresponding to a phase voltage; a switching pattern generation unit that generates a switching pattern of the bidirectional switch circuit using the generated carrier signal and the generated control signal; And the generator generates the control signal such that Pe / Pc <1, where Pe is the absolute value of the maximum amplitude of the control signal and Pc is the absolute value of the maximum amplitude of the carrier signal. And the control means generates a switching pattern for each phase so that an on / off pattern considering each fall time of the plurality of switching elements is included , and the control means includes the three-phase AC power. The timing of the zero crossing of the phase voltage is detected, and the timing of the zero crossing of at least one of the detected phase voltage or line voltage is detected. A zero-cross detection unit that generates a zero-cross signal as the reference signal, and the generation unit determines the voltage of each phase based on the generated zero-cross signal so that the absolute value of the maximum amplitude is smaller than 1. A standardized signal is generated as the control signal, and the generation unit estimates the voltage of each phase using a sine wave table in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is 1. Then, the control signal is generated by multiplying the estimated voltage of each phase by a coefficient larger than 0 and smaller than 1 .

A three-phase rectifier according to the second aspect of the present invention is a three-phase rectifier that converts three-phase AC power input from a three-phase AC power source into DC power, and converts the three-phase AC power into DC power. Corresponding to the three-phase AC power, a full-wave rectifier circuit for rectification, a bidirectional switch circuit having a plurality of switching elements for turning on / off each phase supply from the three-phase AC power source to the full-wave rectifier circuit Control means for generating a switching pattern of each phase for turning the bidirectional switch circuit on and off according to a reference signal, and controlling the switching of the bidirectional switch circuit based on the generated switching pattern; The control means generates a carrier signal that generates a carrier signal according to the reference signal, and generates a control signal corresponding to the voltage of each phase according to the reference signal. And a switching pattern generation unit that generates a switching pattern of the bidirectional switch circuit using the generated carrier signal and the generated control signal, and the generation unit includes: When the absolute value of the maximum amplitude of the control signal is Pe and the absolute value of the maximum amplitude of the carrier signal is Pc, the control signal is generated so that Pe / Pc <1, and the control means A switching pattern for each phase is generated so as to include an on / off pattern in consideration of the fall time of each of the plurality of switching elements, and the control means detects the zero-crossing timing of the phase voltage in the three-phase AC power. The zero cross signal indicating the zero cross timing of at least one detected phase voltage or line voltage is used as the reference signal. A zero-cross detection unit for generating, wherein the generation unit controls the signal in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1 based on the generated zero-cross signal; The signal is generated as a signal, and the generation unit estimates the voltage of each phase using a sine wave table in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1. A control signal is generated .

Further, the three-phase rectifier according to the third aspect of the present invention is the three-phase rectifier according to the second aspect of the present invention, wherein the generator is a plurality of sine wave tables corresponding to a plurality of different cumulative operating times. The control signal is generated by selecting a sine wave table corresponding to the accumulated operation time of the three-phase rectifier from the above and estimating the voltage of each phase using the selected sine wave table .

Further, the three-phase rectifier according to the fourth aspect of the present invention is the three-phase rectifier according to any one of the first to third aspects of the present invention, wherein the control means is a time from an on instruction to an off instruction. The switching pattern of each phase is generated so that an on / off pattern shortened by a length considering the fall time from a target on time is included .

  According to the present invention, in the three-phase rectifier, harmonics included in the input AC current can be reduced, and the pulsation of the output DC voltage can be suppressed.

FIG. 1 is a diagram illustrating a configuration of a three-phase rectifier according to a basic form. FIG. 2 is a circuit diagram showing a configuration example of the bidirectional switch circuit in the basic form. FIG. 3 is a diagram showing the operation of the PLL circuit in the basic mode. FIG. 4 is a diagram showing the configuration of the generation unit in the basic form. FIG. 5 is a diagram showing the control voltage in the basic form and in the first embodiment. FIG. 6 is a diagram showing the configuration of the pattern signal generator in the basic form. FIG. 7 is a diagram showing a waveform example of the sawtooth waves 1 and 2 in the basic form. FIG. 8 is a circuit diagram showing a configuration example of the pattern signal generator in the basic form. FIG. 9 is a diagram illustrating a configuration example of the phase voltage discriminator in the basic form. FIG. 10 is a diagram illustrating an example of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the section I in the basic mode and the first embodiment. FIG. 11 is a diagram illustrating an example of the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the basic mode and section II in the first embodiment. FIG. 12 is a diagram illustrating an example of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the basic mode and section III in the first embodiment. FIG. 13 is a diagram illustrating an example of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the section IV in the basic mode and the first embodiment. FIG. 14 is a diagram illustrating an example of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the section V in the basic mode and the first embodiment. FIG. 15 is a diagram illustrating an example of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the section VI in the basic mode and the first embodiment. FIG. 16 is a diagram showing an input AC current and an output DC voltage of the three-phase rectifier in the basic form. FIG. 17 is a diagram showing a configuration of the generation unit in the first embodiment. FIG. 18 is a diagram illustrating an input AC current and an output DC voltage of the three-phase rectifier according to the first embodiment. FIG. 19 is a diagram illustrating a configuration of a generation unit in a modification of the first embodiment. FIG. 20 is a diagram showing a configuration of a generation unit in another modification of the first embodiment. FIG. 21 is a diagram showing a configuration of the generation unit in another modification of the first embodiment. FIG. 22 is a diagram illustrating a configuration of a control unit in the second embodiment. FIG. 23 is a diagram showing a configuration of the phase voltage discriminator in the second embodiment. FIG. 24 is a diagram showing the configuration of the pattern signal generator in the second embodiment. FIG. 25 is a diagram illustrating an example of control voltages for each phase, sawtooth waves 1 and 2 and pulses for each phase in sections II and V in the second embodiment. FIG. 26 is a diagram illustrating an example of control voltages for each phase, sawtooth waves 1 and 2 and pulses for each phase in sections I and IV in the second embodiment. FIG. 27 is a diagram illustrating an example of control voltages for each phase, sawtooth waves 1 and 2 and pulses for each phase in sections III and VI in the second embodiment.

  Embodiments of a three-phase rectifier according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
Before describing the three-phase rectifier 1i according to the embodiment, the three-phase rectifier 1 according to the basic embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of the three-phase rectifier 1.

  The three-phase rectifier 1 converts the three-phase AC power input from the three-phase AC power source PS via the input terminals IT-r to IT-t into DC power, and outputs the load LD from the output terminals OT-p and OT-n. Output to. The three-phase AC power includes, for example, R-phase AC power, S-phase AC power, and T-phase AC power.

  Specifically, the three-phase rectifier 1 includes a three-phase reactor 8, an input capacitor 9, a full-wave rectifier circuit 4, a bidirectional switch circuit 3, a DC reactor 2, a capacitor 10, and a control unit 11.

  The three-phase reactor 8 is connected between the input terminals IT-r to IT-t and the bidirectional switch circuit 3. The input capacitor 9 is connected between the input terminals IT-r to IT-t and the bidirectional switch circuit 3.

  The full-wave rectifier circuit 4 is connected between the bidirectional switch circuit 3 and the output terminals OT-p and OT-n. The full-wave rectifier circuit 4 has, for example, six diodes connected in a bridge, and full-wave rectifies the three-phase AC power supplied via the bidirectional switch circuit 3 using the six diodes to generate DC power. Is generated.

  The bidirectional switch circuit 3 turns ON / OFF the connection between the input terminals IT-r to IT-t and the input node of each phase of the full-wave rectifier circuit 4. That is, the bidirectional switch circuit 3 includes a plurality of switching elements SW-r, SW-s, and SW-t that turn on / off the supply of AC power of each phase from the three-phase AC power source PS to the full-wave rectifier circuit 4. Have. Each switching element SW is, for example, a semiconductor transistor such as an IGBT (Insulated Gate Bipolar Transistor) or an FET (Field Effect Transistor). As shown in FIG. 2 (a), one phase bidirectional switch together with a plurality of diodes. It is comprised so that.

  Note that the bidirectional switch circuit 3 and the full-wave rectifier circuit 4 may be configured by connecting the circuit shown in FIG. 2B to FIGS.

  The DC reactor 2 shown in FIG. 1 is connected between the full-wave rectifier circuit 4 and the output terminal OT-p. The DC reactor 2 is inserted in series in a P line between the full-wave rectifier circuit 4 and the output terminal OT-p, for example.

  The capacitor 10 is connected between the full-wave rectifier circuit 4 and the output terminals OT-p and OT-n. For example, the capacitor 10 has one electrode connected to the P line between the full-wave rectifier circuit 4 and the output terminal OT-p, and the other electrode connected between the full-wave rectifier circuit 4 and the output terminal OT-n. Are connected to the N line.

  The control unit 11 performs switching control of the bidirectional switch circuit 3 based on the voltage of each phase corresponding to the three-phase AC power input from the three-phase AC power source PS.

  Specifically, the control unit 11 includes a zero cross detection unit 12, a PLL circuit 13, a generation unit 14, a switching pattern generator 5, and a drive circuit 6.

  The zero cross detector 12 detects the zero cross timing of the phase voltage in the three-phase AC power. For example, in the case illustrated in FIG. 1, the zero-cross detector 12 detects the timing at which the R-phase voltage zero-crosses. For example, the zero-cross detection unit 12 includes a comparator, and detects the zero-cross timing of the phase voltage by detecting inversion of the polarity of the phase voltage using the comparator or the like. The zero cross detection unit 12 outputs the detection result to the PLL circuit 13. Hereinafter, this detection result is referred to as a phase voltage zero-cross signal. That is, the phase voltage zero-cross signal is, for example, a signal indicating the timing at which the phase voltage zero-crosses in the rising direction, and is, for example, a pulse-like signal having the frequency of the phase voltage.

  The zero cross detection unit 12 may detect the zero cross timing of the line voltage instead of detecting the zero cross timing of the phase voltage. For example, although not shown, the zero cross detector 12 may detect the timing at which the R-phase and S-phase line voltages zero-cross. In this case, the zero cross detection unit 12 generates a zero cross signal of the line voltage as a detection result. The zero-cross signal of the line voltage is, for example, a signal indicating the timing at which the line voltage zero-crosses in the rising direction, and is, for example, a pulse signal having a phase voltage frequency. At this time, the zero-cross detection unit 12 considers that the zero-cross signal of the line voltage is approximately 30 degrees ahead of the zero-cross signal of the phase voltage, and the generated zero-cross signal of the line voltage is approximately 30 degrees. The phase-delayed signal is output to the PLL circuit 13 as a signal corresponding to the zero-cross signal of the line voltage. That is, the zero-cross detection unit 12 generates a signal corresponding to the zero-cross signal of the phase voltage according to the generated zero-cross signal of the line voltage, and outputs the signal to the PLL circuit 13.

  The PLL circuit 13 receives the zero cross signal as a reference signal corresponding to the three-phase AC power from the three-phase AC power source PS. The PLL circuit 13 grasps the frequency of the phase voltage according to a reference signal (for example, a zero cross signal) corresponding to the three-phase AC power. For example, since the zero cross signal has the frequency of the phase voltage, the PLL circuit 13 can grasp the frequency of the phase voltage from the frequency of the zero cross signal. The PLL circuit 13 generates a carrier clock having a frequency obtained by multiplying the grasped frequency of the phase voltage by an integer multiple of 6. The PLL circuit 13 outputs the generated carrier clock to the carrier generation unit 5b (see FIG. 6). Thereby, the carrier generation unit 5b generates a carrier in synchronization with a carrier clock having a frequency obtained by multiplying the frequency of the phase voltage by an integer multiple of 6.

  In addition, the PLL circuit 13 generates a section period clock having an equal period in each of the six sections I to VI according to a reference signal (for example, a zero cross signal) corresponding to the three-phase AC power. That is, the PLL circuit 13 divides a plurality of carrier clocks to generate a carrier cycle clock, and divides a plurality of carrier cycle clocks to generate an interval cycle clock. The PLL circuit 13 outputs the generated carrier cycle clock, the interval cycle clock, and a divided clock (hereinafter referred to as an intermediate divided clock) in the middle stage from the carrier cycle clock to the interval cycle clock to the generation unit 14. The halfway divided clock may include divided clocks at a plurality of stages when the carrier cycle clock is repeatedly divided by two to generate the interval cycle clock.

  Further, the PLL circuit 13 divides the interval cycle clock by two to generate a first divided clock (see FIG. 3). The PLL circuit 13 divides the first frequency-divided clock by two to generate a second frequency-divided clock (see FIG. 3). The PLL circuit 13 generates a third divided clock (also called a follow-up signal, see FIG. 3) obtained by dividing the second divided clock by two. At this time, the PLL circuit 13 resets the levels of the first divided clock, the second divided clock, and the third divided clock at the timing tc shown in FIG. For example, at the timing tc, the broken line level shown in FIG. 3 is reset to the solid line level. Thereby, since the period of the third frequency-divided clock is 6 clocks of the section cycle clock, the third frequency-divided clock can be a follow-up signal obtained by dividing the section-cycle clock by 6. FIG. 3 is a waveform diagram showing the operation of the PLL circuit 13.

  The generation unit 14 illustrated in FIG. 1 receives from the PLL circuit 13 a carrier cycle clock, an intermediate divided clock, an interval cycle clock, a first divided clock, a second divided clock, and a third divided clock. The generation unit 14 estimates which of the six sections I to VI is the current section according to the combination of the first divided clock, the second divided clock, and the third divided clock. (See FIG. 3). Furthermore, the generation unit 14 has the current timing at which time position in the current section (that is, the position on the horizontal axis in FIG. 5) according to the combination of the carrier cycle clock, the halfway divided clock, and the section cycle clock. Estimate. Then, the generation unit 14 estimates the voltage of each phase as indicated by a solid line in FIG. 5 according to the estimation result, and estimates the voltage of each phase (for example, the R phase voltage a, the S phase voltage b, The T-phase voltage c) is output to the switching pattern generator 5.

  Specifically, as illustrated in FIG. 4, the generation unit 14 includes a storage unit (ROM) 14a and a control signal generator 14b. FIG. 4 is a diagram illustrating a configuration of the generation unit 14. The storage unit (ROM) 14a stores a sine wave table 14a1 in which time position data in a sine wave whose peak value is normalized to “1” and the normalized amplitude are associated with each other. As described above, the control signal generator 14b estimates time positions in the current sections I to VI and the current sections I to VI.

  For example, the control signal generator 14b generates first data indicating the current section by collecting the bit values of the first divided clock, the second divided clock, and the third divided clock. The control signal generator 14b generates second data indicating the current timing by combining the bit values of the carrier clock, the halfway divided clock, and the interval cycle clock. The control signal generator 14b combines the first data and the second data to generate time position data. Then, the control signal generator 14b refers to the sine wave table 14a1 stored in the storage unit (ROM) 14a, identifies the normalized amplitude of each phase corresponding to the generated time position data, and identifies each identified Let the normalized amplitude of the phase be the estimation result of the voltage of each phase. Thereby, compared with the case where the phase voltage of each phase in the three-phase AC power from the three-phase AC power source PS is used as it is, each phase (R phase, A phase voltage of S phase and T phase can be obtained.

  The switching pattern generator 5 shown in FIG. 1 generates a switching pattern of the bidirectional switch circuit 3 based on the voltage of each phase (for example, R phase, S phase, T phase). The drive circuit 6 performs switching control of the switching elements SW-r, SW-s, and SW-t of the bidirectional switch circuit 3 based on the switching pattern generated by the switching pattern generator 5. At this time, the switching pattern generator 5 has the bidirectional switch circuit 3 in accordance with six sections I to VI in which one cycle of the phase voltage is divided according to the magnitude relationship of the voltages of the phases in the three-phase AC power. A switching pattern is generated (see FIGS. 10 to 15).

  Next, the six sections I to VI will be described with reference to FIG. FIG. 5 is a diagram illustrating six sections I to VI.

  The control unit 11 recognizes, for example, six sections I to VI as shown in FIG. 5 according to the magnitude relationship of the AC voltage of each phase (R phase, S phase, T phase).

  In section I, the R phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the R phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the T phase is the intermediate voltage phase, it recognizes that the current mode is the section I. .

  In section II, the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase, it recognizes that the current mode is the section II. .

  In section III, the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase, the control unit 11 recognizes that the current mode is the section III. .

  In section IV, the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase, it recognizes that the current mode is the section IV. .

  In section V, the T phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the T phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the S phase is the intermediate voltage phase, it recognizes that the current mode is the section V. .

  In the section VI, the T phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. For example, when the control unit 11 recognizes that the T phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the R phase is the intermediate voltage phase, the control unit 11 recognizes that the current mode is the section VI. .

  Next, a configuration example of the switching pattern generator will be described with reference to FIGS. FIG. 6 is a block diagram showing an example of the switching pattern generator 5. FIG. 7 is a diagram showing waveform examples of sawtooth waves 1 and 2 used when the switching pattern generator 5 generates a switching pattern. FIG. 8 is a circuit diagram showing a configuration example of the pattern signal generator 511 of the switching pattern generator 5. FIG. 9 is a diagram illustrating a configuration example of the phase voltage discriminator 513 of the switching pattern generator 5.

  The switching pattern generator 5 switches the switching patterns (R, S, T phase pulses) of the bidirectional switch circuit 3 for each phase as described below in order to suppress the pulsation of the DC voltage and the harmonics of the input current. Is generated. The switching pattern generator 5 recognizes the maximum potential phase, the intermediate potential phase, and the minimum potential phase of the voltage of each phase of the three-phase AC power supply 1 at a predetermined timing such as the rise of the switching cycle, and In the case of the minimum potential phase, a switching pattern is generated in which the time is proportional to each potential, and at least one of them is ON within the switching cycle T. In the case of the intermediate potential phase, the switching is always ON. A pattern is generated (see FIGS. 10 to 15). Note that the switching period T is determined to be a sufficiently short period (for example, 1/100 kHz = 10 μsec) with respect to the power supply frequency (for example, 50 Hz).

  As shown in FIG. 6, the switching pattern generator 5 includes a carrier generation unit 5b and a switching pattern generation unit 5a. The carrier generator 5b generates a carrier in synchronization with the carrier clock. The switching pattern generator 5a generates the switching pattern of the bidirectional switch circuit 3 using the generated carrier.

  The carrier generator 5bj includes a sawtooth wave generator 54. The switching pattern generator 5a includes a pattern signal generator 511, a voltage setter 512, a phase voltage discriminator 513, comparators 514R, 514S and 514T, comparators 515R, 515S and 515T, and AND circuits 516R, 516S and 516T. AND circuits 517R, 517S, 517T, AND circuits 518R, 518S, 518T, and OR circuits 519R, 519S, 519T.

  The voltage setting unit 512 sets a DC voltage setting gain k (where k = 0.5 to 1) determined in accordance with the DC voltage setting value (target voltage to be stepped down) in the pattern signal generator 511.

  The pattern signal generator 511 receives R, S, and T phase voltages a, b, and c normalized from −1 to +1, respectively, from the generation unit 14. The pattern signal generator 511 calculates the product of the R, S, T phase voltages a, b, c and the DC voltage setting gain k (0.5 to 1) input from the voltage setting unit 512 to obtain the R phase. , S phase, T phase control voltages ka, kb, kc.

  The sawtooth wave generator 54 outputs the sawtooth wave 1 and the sawtooth wave 2. The phase voltage discriminator 513 compares the R, S, and T phase voltages a, b, and c to determine which phase voltage is the maximum, minimum, and intermediate, and determines the maximum determination signal for the R, S, and T phases ( “1” for maximum, “0” for non-maximum), minimum determination signal (“1” for minimum, “0” for non-minimum), intermediate determination signal (“1” for intermediate, “0” for non-intermediate) )) Respectively.

  Comparators 514R to 514T compare R-phase, S-phase, and T-phase control voltages ka, kb, and kc with sawtooth wave 1 (see FIG. 7), respectively, and output a comparison signal. Comparators 515R to 515T compare R-phase, S-phase, and T-phase control voltages ka, kb, and kc with sawtooth wave 2 (see FIG. 7), respectively, and output a comparison signal.

  Here, as shown in FIG. 7, the sawtooth wave 1 has a period of the switching period T, and its peak value is Pc. Pc is a value substantially equal to 1. The sawtooth wave 2 has a switching period T and its peak value is -Pc. The absolute value of the peak value of the sawtooth wave 1 and the absolute value of the peak value of the sawtooth wave 2 are both Pc.

  AND circuits 516R to 516T shown in FIG. 6 perform AND operations on the comparison signals of the comparators 514R to 514T and the R, S, and T phase maximum determination signals, respectively. AND circuits 517R to 517T perform AND operations on the comparison signals of comparators 515R to 515T and the R, S, and T phase minimum determination signals, respectively. The AND circuits 518R to 518T perform AND operations on the fixed value “1” and the R, S, and T phase intermediate determination signals, respectively. The OR circuits 519R to 519T perform an OR operation on the outputs of the AND circuits 516R to 518R, the outputs of the AND circuits 516S to 518S, and the outputs of the AND circuits 516T to 518T, respectively, as final R, S, and T phase pulses (switching patterns). Output to the drive circuit 6.

  The operation related to the R phase will be described. The comparator 514R compares the R-phase control voltage ka input from the pattern signal generator 511 with the sawtooth wave 1, and compares the comparison signal (“1” when the R-phase control voltage ka> sawtooth wave 1). When the control voltage ka ≦ sawtooth wave 1, “0”) is output to the AND circuit 516 R. AND circuit 516R performs an AND operation on the comparison signal input from comparator 514R and the R-phase maximum determination signal, and outputs the result to OR circuit 519R.

  The comparator 515R compares the sawtooth wave 2 with the R phase control voltage ka input from the pattern signal generator 511, and compares the comparison signal (“1” when the sawtooth wave 2> R phase control voltage ka, sawtooth When wave 2 ≦ R phase control voltage ka, “0”) is output to AND circuit 517R. The AND circuit 517R performs an AND operation on the comparison signal input from the comparator 515R and the R-phase minimum determination signal, and outputs the result to the OR circuit 519R.

  The AND circuit 518R performs an AND operation on the fixed signal “1” and the R-phase intermediate determination signal and outputs the result to the OR circuit 519R. The OR circuit 519R performs an OR operation on the outputs of the AND circuits 516R to 518R and outputs the result as the final R-phase pulse.

  The operation relating to the S phase will be described. The comparator 514S compares the S phase control voltage kb input from the pattern signal generator 511 with the sawtooth wave 1 and compares the comparison signal (“1” when the S phase control voltage kb> sawtooth wave 1), When the control voltage ka ≦ sawtooth wave 1, “0”) is output to the AND circuit 516 </ b> S. AND circuit 516S performs an AND operation on the comparison signal input from comparator 514S and the S-phase maximum determination signal, and outputs the result to OR circuit 519S.

  The comparator 515S compares the sawtooth wave 2 with the S phase control voltage kb input from the pattern signal generator 511, and compares the comparison signal (“1” when the sawtooth wave 2> S phase control voltage kb, sawtooth When wave 2 ≦ S phase control voltage kb, “0”) is output to AND circuit 517S. AND circuit 517S performs an AND operation on the comparison signal input from comparator 515S and the S-phase minimum determination signal, and outputs the result to OR circuit 519S.

  The AND circuit 518S performs an AND operation on the fixed signal “1” and the S-phase intermediate determination signal and outputs the result to the OR circuit 519S. The OR circuit 519S performs an OR operation on the outputs of the AND circuits 516S to 518S and outputs the result as the final S-phase pulse.

  The operation related to the T phase will be described. The comparator 514T compares the T-phase control voltage kc input from the pattern signal generator 511 with the sawtooth wave 1, and compares the comparison signal (“1” when the T-phase control voltage kc> sawtooth wave 1). When the control voltage kc ≦ sawtooth wave 1, “0”) is output to the AND circuit 516 T. The AND circuit 516T performs an AND operation on the comparison signal input from the comparator 514T and the T-phase maximum determination signal, and outputs the result to the OR circuit 519T.

  The comparator 515T compares the sawtooth wave 2 with the T-phase control voltage kc input from the pattern signal generator 511, and compares the comparison signal (“1” when the sawtooth wave 2> the S-phase control voltage kc. When the wave 2 ≦ T phase control voltage kc, “0”) is output to the AND circuit 517T. The AND circuit 517T performs an AND operation on the comparison signal input from the comparator 515T and the T-phase minimum determination signal, and outputs the result to the OR circuit 519T.

  The AND circuit 518T performs an AND operation on the fixed signal “1” and the T-phase intermediate determination signal and outputs the result to the OR circuit 519T. The OR circuit 519T performs an OR operation on the outputs of the AND circuits 516T to 518T and outputs the result as the final T-phase pulse.

  As shown in FIG. 8, the pattern signal generator 511 multiplies the R, S, and T phase voltages a, b, and c by the DC voltage control gain k output from the voltage setting unit 512, respectively. Multipliers 30R, 30S, and 30T that respectively output S-phase and T-phase control patterns ka, kb, and kc are provided.

  As shown in FIG. 9, the phase voltage discriminator 513 includes comparators 40R, 40S, and 40T, AND circuits 41R, 41S, and 41T, AND circuits 42R, 42S, and 42T, and NOR circuits 43R, 43S, and 43T. ing.

  The comparator 40R compares the R-phase voltage a and the S-phase voltage b, and compares the comparison signal (“1” when R-phase voltage a> S-phase voltage b, and R-phase voltage a ≦ S-phase voltage b. "0") is output to the AND circuits 41R, 42S, 41T, and 42T. The comparator 40S compares the S-phase voltage b and the T-phase voltage c, and compares the comparison signal (“1” when S-phase voltage b> T-phase voltage c, and R-phase voltage a ≦ T-phase voltage c. "0") is output to the AND circuits 41R, 42R, 41S, and 42T. The comparator 40T compares the T-phase voltage c with the R-phase voltage a and compares the comparison signal (“1” when T-phase voltage c> R-phase voltage a, and T-phase voltage c ≦ R-phase voltage a. "0") is output to the AND circuits 42R, 41S, 42S, 41T.

  The AND circuit 41R outputs an AND operation result of the comparison signal of the comparator 40R and the comparison signal of the comparator 40S as the R-phase maximum determination signal. The AND circuit 42R outputs an AND operation result of the comparison signal of the comparator 40S and the comparison signal of the comparator 40T as an R-phase minimum determination signal. The AND circuit 41S outputs an AND operation result of the comparison signal of the comparator 40S and the comparison signal of the comparator 40T as an S-phase maximum determination signal. The AND circuit 42S outputs an AND operation result of the comparison signal of the comparator 40T and the comparison signal of the comparator 40R as an S-phase minimum determination signal. The AND circuit 41T outputs an AND operation result of the comparison signal of the comparator 40T and the comparison signal of the comparator 40R as a T-phase maximum determination signal. The AND circuit 42T outputs an AND operation result of the comparison signal of the comparator 40R and the comparison signal of the comparator 40S as a T-phase minimum determination signal.

  The NOR circuit 43R outputs the NOR calculation result of the R-phase maximum determination signal and the R-phase minimum determination signal as the R-phase intermediate determination signal. The NOR circuit 43S outputs the NOR calculation result of the S-phase maximum determination signal and the S-phase minimum determination signal as an S-phase intermediate determination signal. The NOR circuit 43T outputs the NOR calculation result of the T-phase maximum determination signal and the T-phase minimum determination signal as a T-phase intermediate determination signal.

[Reduction principle of DC voltage pulsation and input current harmonics]
Next, the principle of reducing the pulsation of the DC voltage and the harmonics of the input current in the basic form will be described. In the basic form, the switching pattern generator 5 and the drive circuit 6 are used to switch the bidirectional switch circuit 3 as follows, thereby reducing DC voltage pulsations and input current harmonics. With reference to FIGS. 10-15, the DC voltage and the electric current of each phase by switching operation in each section I-VI are demonstrated. 10 to 15 are diagrams illustrating examples of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the sections I to VI, respectively. 10 to 15, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the basic form are shown by solid lines.

<Section I>
The case where the R phase is the maximum, the middle of the T phase, and the minimum of the S phase in section I will be described with reference to FIG. FIG. 10 is a diagram illustrating an example of R, S, and T phase control voltages ka, kb, and kc, sawtooth waves 1 and 2, and R, S, and T phase pulses in section I. As described above, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”. As described above, the DC voltage setting gain k is a gain determined in accordance with the DC voltage setting value in the voltage setting unit 512, and is a constant between 0.5 and 1. The DC voltage setting gain k is multiplied by the R phase voltage a, the S phase voltage b, and the T phase voltage c in the pattern signal generator 511, and the multiplied R phase control voltage ka, S phase control voltage kb, and T phase control are multiplied. The voltage kc has a waveform that cuts between the sawtooth waves 1 and 2 (see FIG. 10).

  In FIG. 10, the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the basic form are shown by solid lines. T is the switching period, x is the R-phase pulse width, y is the S-phase pulse width, and z is the T-phase pulse width. The DC voltages in sections 1, 2, and 3 are section 1 voltage = inter-TS voltage = c−b, section 2 voltage = inter-RS voltage = ab, and section 3 voltage = inter-RT voltage = ac. . The width of section 1 is T−x, the width of section 2 is x− (T−y) = x + y−T, and the width of section 3 is T−y. On the other hand, the R-phase pulse width x is T = x = 1: ka and x = kaT, and the S-phase pulse width y is T: y = 1: −kb and y = −kbT. Accordingly, the width of the section 1 is T−x = T−kaT = T (1−ka), the width of the section 3 is T−y = T − (− kbT) = T (1 + kb), and the width of the section 2 is X + y−T = kaT + (− kbT) −T = T (ka−kb−1).

  The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average voltage of switching period T = {(c−b) × T × (1−ka) + (a−b) × T × (ka−kb−1) + (ac−c) × T × (1 + kb) } / T
= K (a ² + b ² ) −kb (a + b)

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

From AC theory, a ² + b ² + c ² = 3/2
= K x 3/2

  In addition, the average of the voltage of the said switching period T is represented based on the phase voltage.

  Therefore, the average value of the DC voltage switching interval is constant, becomes the DC voltage setting gain k × 3/2, and is proportional to the DC voltage setting gain k to be compared with the sawtooth waves 1 and 2. For this reason, by selecting the DC voltage setting gain k, the magnitude of the DC voltage obtained by stepping down can be controlled. Here, since both the R-phase pulse and the S-phase pulse are turned ON in the switching cycle T, the minimum value of the DC voltage setting gain k is 0.5, and the R-phase control voltage ka, the S-phase control voltage kb, Since the T-phase control voltage kc does not exceed the sawtooth waves 1 and 2, the maximum value of the DC voltage setting gain k is 1. Therefore, the settable range of k is in the range of 0.5-1.

  Next, the input current will be described. As the R-phase input current, a positive current proportional to the time of the R-phase control voltage ka flows. As the S-phase input current, a negative current proportional to the absolute value | kb | of the S-phase control voltage kb, that is, a current proportional to the S-phase control voltage kb flows. In the T-phase input current, a positive current flows in section 1 = T × (1−ka), and a negative current flows in section 3 = T × (1 + kb). Accordingly, the positive current that flows is T × (1−ka) −T × (1 + kb) = T × (−ka−kb) = T × k × (−a−b) = T × k × c. When the average of the period T is divided by T, a T-phase control voltage kc is obtained. As described above, currents proportional to the R-phase control voltage ka, S-phase control voltage kb, and T-phase control voltage kc flow through the R-phase, S-phase, and T-phase currents, and the current is proportional to the input voltage. Will flow on average.

<Section II>
The case of R phase maximum, S phase middle, and T phase minimum in Section II will be described with reference to FIG. FIG. 11 is a diagram illustrating an example of R, S, and T phase control voltages ka, kb, and kc, sawtooth waves 1 and 2, and R, S, and T phase pulses in section II. As described above, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”. As described above, the DC voltage setting gain k is a gain determined in accordance with the DC voltage setting value in the voltage setting unit 512, and is a constant between 0.5 and 1. The DC voltage setting gain k is multiplied by the R phase voltage a, the S phase voltage b, and the T phase voltage c in the pattern signal generator 511, and the multiplied R phase control voltage ka, S phase control voltage kb, and T phase control are multiplied. The voltage kc has a waveform that cuts between the sawtooth waves 1 and 2 (see FIG. 11).

  In FIG. 11, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the basic form are shown by solid lines. T is the switching period, x is the R-phase pulse width, y is the S-phase pulse width, and z is the T-phase pulse width. The DC voltages in sections 1, 2, and 3 are section 1 voltage = inter-ST voltage = bc, section 2 voltage = RT voltage = ac, and section 3 voltage = RS voltage = ab. . The width of section 1 is Tx, the width of section 2 is x- (Tz) = x + z-T, and the width of section 3 is Tz. On the other hand, the R-phase pulse width x is T = x = 1: ka and x = kaT, and the T-phase pulse width z is T: z = 1: −kc and z = −kcT. Therefore, the width of section 1 is Tx = T-kaT = T (1-ka), the width of section 3 is Tz = T-(-kcT) = T (1 + kc), and the width of section 2 is X + z−T = kaT + (− kcT) −T = T (ka−kc−1).

  The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average voltage of switching period T = {(b−c) × T × (1−ka) + (a−c) × T × (ka−kc−1) + (a−b) × T × (1 + kc) } / T
= K (a ² + c ² ) −kb (a + c)

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

From AC theory, a ² + b ² + c ² = 3/2
= K x 3/2

  In addition, the average of the voltage of the said switching period T is represented based on the phase voltage.

  Therefore, the average value of the DC voltage switching interval is constant, becomes the DC voltage setting gain k × 3/2, and is proportional to the DC voltage setting gain k to be compared with the sawtooth waves 1 and 2. For this reason, by selecting the DC voltage setting gain k, the magnitude of the DC voltage obtained by stepping down can be controlled. Here, since both the R-phase pulse and the T-phase pulse are turned on in the switching cycle T, the minimum value of the DC voltage setting gain k is 0.5, and the R-phase control voltage ka, the S-phase control voltage kb, Since the T-phase control voltage kc does not exceed the sawtooth waves 1 and 2, the maximum value of the DC voltage setting gain k is 1. Therefore, the settable range of k is in the range of 0.5-1.

  Next, the input current will be described. As the R-phase input current, a positive current proportional to the time of the R-phase control voltage ka flows. As the T-phase input current, a negative current proportional to the absolute value | kc | of the T-phase control voltage kc, that is, a current proportional to the T-phase control voltage kc flows. In the S-phase input current, a positive current flows in section 1 = T × (1−ka), and a negative current flows in section 3 = T × (1 + kc). Accordingly, the positive current that flows is T × (1−ka) −T × (1 + kc) = T × (−ka−kc) = T × k × (−a−c) = T × k × b. When the average of the period T is divided by T, the S-phase control voltage kb is obtained. As described above, currents proportional to the R-phase control voltage ka, S-phase control voltage kb, and T-phase control voltage kc flow through the R-phase, S-phase, and T-phase currents, and the current is proportional to the input voltage. Will flow on average.

<Section III>
The case of the S phase maximum, R phase middle, and T phase minimum of the section III will be described with reference to FIG. FIG. 12 is a diagram illustrating an example of R, S, and T phase control voltages ka, kb, and kc, sawtooth waves 1 and 2, and R, S, and T phase pulses in section III. As described above, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”. As described above, the DC voltage setting gain k is a gain determined in accordance with the DC voltage setting value in the voltage setting unit 512, and is a constant between 0.5 and 1. The DC voltage setting gain k is multiplied by the R phase voltage a, the S phase voltage b, and the T phase voltage c in the pattern signal generator 511, and the multiplied R phase control voltage ka, S phase control voltage kb, and T phase control are multiplied. The voltage kc has a waveform that cuts between the sawtooth waves 1 and 2 (see FIG. 12).

  In FIG. 12, the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the basic form are shown by solid lines. T is the switching period, x is the R-phase pulse width, y is the S-phase pulse width, and z is the T-phase pulse width. The DC voltages in sections 1, 2, and 3 are section 1 voltage = RT voltage = ac, section 2 voltage = ST voltage = bc, section 3 voltage = RS voltage = ba, respectively. . The width of section 1 is T−y, the width of section 2 is y− (T−z) = y + z−T, and the width of section 3 is T−z. On the other hand, the S-phase pulse width y is Y = kbT from T: y = 1: kb, and the T-phase pulse width z is z = −kcT from T: z = 1: −kc. Therefore, the width of section 1 is T−y = T−kbT = T (1−kb), the width of section 3 is T−z = T − (− kcT) = T (1 + kc), and the width of section 2 is , Y + z−T = kbT + (− kcT) −T = T (kb−kc−1).

  The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average voltage of switching period T = {(ac) * T * (1-kb) + (bc) * T * (kb-kc-1) + (ba) * T * (1 + kc) } / T
= K (b ² + c ² ) −kb (b + c)

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

From AC theory, a ² + b ² + c ² = 3/2
= K x 3/2

  In addition, the average of the voltage of the said switching period T is represented based on the phase voltage.

  Therefore, the average value of the DC voltage switching interval is constant, becomes the DC voltage setting gain k × 3/2, and is proportional to the DC voltage setting gain k to be compared with the sawtooth waves 1 and 2. For this reason, by selecting the DC voltage setting gain k, the magnitude of the DC voltage obtained by stepping down can be controlled. Here, since both the S-phase pulse and the T-phase pulse are turned ON during the switching cycle T, the minimum value of the DC voltage setting gain k is 0.5, and the R-phase control voltage ka, the S-phase control voltage kb, Since the T-phase control voltage kc does not exceed the sawtooth waves 1 and 2, the maximum value of the DC voltage setting gain k is 1. Therefore, the settable range of k is in the range of 0.5-1.

  Next, the input current will be described. As the S-phase input current, a positive current proportional to the time of the S-phase control voltage kb flows. As the T-phase input current, a negative current proportional to the absolute value | kc | of the T-phase control voltage kc, that is, a current proportional to the T-phase control voltage kc flows. As for the R-phase input current, a positive current flows in section 1 = T × (1−kb), and a negative current flows in section 3 = T × (1 + kc). Accordingly, the positive current that flows is T × (1−kb) −T × (1 + kc) = T × (−kb−kc) = T × k × (−b−c) = T × k × a When the average of the period T is divided by T, an R-phase control voltage ka is obtained. As described above, currents proportional to the R-phase control voltage ka, S-phase control voltage kb, and T-phase control voltage kc flow through the R-phase, S-phase, and T-phase currents, and the current is proportional to the input voltage. Will flow on average.

<Section IV>
The case where the S phase is maximum, the T phase is intermediate, and the R phase is minimum in the section IV will be described with reference to FIG. FIG. 13 is a diagram illustrating an example of R, S, and T phase control voltages ka, kb, and kc, sawtooth waves 1 and 2 and R, S, and T phase pulses in section IV. As described above, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”. As described above, the DC voltage setting gain k is a gain determined in accordance with the DC voltage setting value in the voltage setting unit 512, and is a constant between 0.5 and 1. The DC voltage setting gain k is multiplied by the R phase voltage a, the S phase voltage b, and the T phase voltage c in the pattern signal generator 511, and the multiplied R phase control voltage ka, S phase control voltage kb, and T phase control are multiplied. The voltage kc has a waveform that cuts between the sawtooth waves 1 and 2 (see FIG. 13).

  In FIG. 13, the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the basic form are shown by solid lines. T is the switching period, x is the R-phase pulse width, y is the S-phase pulse width, and z is the T-phase pulse width. The DC voltages in sections 1, 2, and 3 are section 1 voltage = inter-TR voltage = ca, section 2 voltage = SR voltage = ba, and section 3 voltage = ST voltage = bc. . The width of section 1 is T−y, the width of section 2 is y− (T−x) = y + x−T, and the width of section 3 is T−x. On the other hand, the S-phase pulse width y is T = y = 1: kb and y = kbT, and the R-phase pulse width x is T: x = 1: −ka and x = −kaT. Therefore, the width of section 1 is T−y = T−kbT = T (1−kb), the width of section 3 is T−x = T − (− kaT) = T (1 + ka), and the width of section 2 is Y + x−T = kbT + (− kaT) −T = T (kb−ka−1).

  The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average voltage of switching period T = {(c−a) × T × (1−kb) + (b−a) × T × (kb−ka−1) + (b−c) × T × (1 + ka) } / T
= K (b ² + a ² ) −kb (b + a)

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

From AC theory, a ² + b ² + c ² = 3/2
= K x 3/2

  In addition, the average of the voltage of the said switching period T is represented based on the phase voltage.

  Therefore, the average value of the DC voltage switching interval is constant, becomes the DC voltage setting gain k × 3/2, and is proportional to the DC voltage setting gain k to be compared with the sawtooth waves 1 and 2. For this reason, by selecting the DC voltage setting gain k, the magnitude of the DC voltage obtained by stepping down can be controlled. Here, since both the S-phase pulse and the R-phase pulse are turned ON in the switching cycle T, the minimum value of the DC voltage setting gain k is 0.5, and the R-phase control voltage ka, the S-phase control voltage kb, Since the T-phase control voltage kc does not exceed the sawtooth waves 1 and 2, the maximum value of the DC voltage setting gain k is 1. Therefore, the settable range of k is in the range of 0.5-1.

  Next, the input current will be described. As the S-phase input current, a positive current proportional to the time of the S-phase control voltage kb flows. As the R-phase input current, a negative current proportional to the absolute value | ka | of the R-phase control voltage ka, that is, a current proportional to the R-phase control voltage ka flows. In the T-phase input current, a positive current flows in section 1 = T × (1−kb), and a negative current flows in section 3 = T × (1 + ka). Therefore, the positive current that flows is T × (1−kb) −T × (1 + ka) = T × (−kb−ka) = T × k × (−b−a) = T × k × c. When the average of the period T is divided by T, a T-phase control voltage kc is obtained. As described above, currents proportional to the R-phase control voltage ka, S-phase control voltage kb, and T-phase control voltage kc flow through the R-phase, S-phase, and T-phase currents, and the current is proportional to the input voltage. Will flow on average.

<Section V>
A case where the T-phase is maximum, the S-phase intermediate, and the R-phase minimum in the section V will be described with reference to FIG. FIG. 14 is a diagram illustrating an example of R, S, and T phase control voltages ka, kb, and kc, sawtooth waves 1 and 2, and R, S, and T phase pulses in section VI. As described above, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”. As described above, the DC voltage setting gain k is a gain determined in accordance with the DC voltage setting value in the voltage setting unit 512, and is a constant between 0.5 and 1. The DC voltage setting gain k is multiplied by the R phase voltage a, the S phase voltage b, and the T phase voltage c in the pattern signal generator 511, and the multiplied R phase control voltage ka, S phase control voltage kb, and T phase control are multiplied. The voltage kc has a waveform that cuts between the sawtooth waves 1 and 2 (see FIG. 14).

  In FIG. 14, the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the basic form are indicated by solid lines. T is the switching period, x is the R-phase pulse width, y is the S-phase pulse width, and z is the T-phase pulse width. The DC voltages of the sections 1, 2, and 3 are section 1 voltage = SR voltage = ba, section 2 voltage = TR voltage = ca, section 3 voltage = TS voltage = c−b, respectively. . The width of section 1 is T−z, the width of section 2 is z− (T−x) = z + x−T, and the width of section 3 is T−x. On the other hand, the T-phase pulse width z is z = kcT from T: z = 1: kc, and the R-phase pulse width x is x = −kaT from T: x = 1: −ka. Therefore, the width of section 1 is Tz = T-kcT = T (1-kc), the width of section 3 is Tx = T-(-kaT) = T (1 + ka), and the width of section 2 is Z + x−T = kcT + (− kaT) −T = T (kc−ka−1).

  The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average of switching period T = {(b−a) × T × (1−kc) + (c−a) × T × (kc−ka−1) + (c−b) × T × (1 + ka) } / T
= K (c ² + a ² ) −kb (c + a)

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

From AC theory, a ² + b ² + c ² = 3/2
= K x 3/2

  In addition, the average of the voltage of the said switching period T is represented based on the phase voltage.

  Therefore, the average value of the DC voltage switching interval is constant, becomes the DC voltage setting gain k × 3/2, and is proportional to the DC voltage setting gain k to be compared with the sawtooth waves 1 and 2. For this reason, by selecting the DC voltage setting gain k, the magnitude of the DC voltage obtained by stepping down can be controlled. Here, since both the T-phase pulse and the R-phase pulse are turned ON during the switching cycle T, the minimum value of the DC voltage setting gain k is 0.5, and the R-phase control voltage ka, the S-phase control voltage kb, Since the T-phase control voltage kc does not exceed the sawtooth waves 1 and 2, the maximum value of the DC voltage setting gain k is 1. Therefore, the settable range of k is in the range of 0.5-1.

  Next, the input current will be described. As the T-phase input current, a positive current proportional to the time of the T-phase control voltage kc flows. As the R-phase input current, a negative current proportional to the absolute value | ka | of the R-phase control voltage ka, that is, a current proportional to the R-phase control voltage ka flows. In the S-phase input current, a positive current flows in section 1 = T × (1−kc), and a negative current flows in section 3 = T × (1 + ka). Therefore, the positive current that flows is T × (1−kc) −T × (1 + ka) = T × (−kc−ka) = T × k × (−c−a) = T × k × b. When the average of the period T is divided by T, the S-phase control voltage kb is obtained. As described above, currents proportional to the R-phase control voltage ka, S-phase control voltage kb, and T-phase control voltage kc flow through the R-phase, S-phase, and T-phase currents, and the current is proportional to the input voltage. Will flow on average.

<Section VI>
The case of T phase maximum, R phase middle, and S phase minimum of the section VI will be described with reference to FIG. FIG. 15 is a diagram illustrating an example of R, S, and T phase control voltages ka, kb, and kc, sawtooth waves 1 and 2, and R, S, and T phase pulses in section VI. As described above, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”. As described above, the DC voltage setting gain k is a gain determined in accordance with the DC voltage setting value in the voltage setting unit 512, and is a constant between 0.5 and 1. The DC voltage setting gain k is multiplied by the R phase voltage a, the S phase voltage b, and the T phase voltage c in the pattern signal generator 511, and the multiplied R phase control voltage ka, S phase control voltage kb, and T phase control are multiplied. The voltage kc has a waveform that cuts between the sawtooth waves 1 and 2 (see FIG. 14).

  In FIG. 15, the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the basic form are shown by solid lines. T is the switching period, x is the R-phase pulse width, y is the S-phase pulse width, and z is the T-phase pulse width. The DC voltages in sections 1, 2, and 3 are section 1 voltage = voltage between RSs = a−b, section 2 voltage = voltage between TS = c−b, and section 3 voltage = voltage between TR = c−a, respectively. . The width of section 1 is T−z, the width of section 2 is z− (T−y) = z + y−T, and the width of section 3 is T−y. On the other hand, the T-phase pulse width z is z = kcT from T: z = 1: kc, and the S-phase pulse width y is y = −kbT from T: y = 1: −kb. Therefore, the width of section 1 is Tz = T-kcT = T (1-kc), the width of section 3 is Ty = T-(-kbT) = T (1 + kb), and the width of section 2 is Z + y−T = kcT + (− kbT) −T = T (kc−kb−1).

  The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average voltage of switching period T = {(ab) × T × (1−kc) + (c−b) × T × (kc−kb−1) + (c−a) × T × (1 + kb) } / T
= K (c ² + b ² ) −kb (c + b)

Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

From AC theory, a ² + b ² + c ² = 3/2
= K x 3/2

  In addition, the average of the voltage of the said switching period T is represented based on the phase voltage.

  Therefore, the average value of the DC voltage switching interval is constant, becomes the DC voltage setting gain k × 3/2, and is proportional to the DC voltage setting gain k to be compared with the sawtooth waves 1 and 2. For this reason, by selecting the DC voltage setting gain k, the magnitude of the DC voltage obtained by stepping down can be controlled. Here, since both the T-phase pulse and the S-phase pulse are turned ON in the switching cycle T, the minimum value of the DC voltage setting gain k is 0.5, and the R-phase control voltage ka, the S-phase control voltage kb, Since the T-phase control voltage kc does not exceed the sawtooth waves 1 and 2, the maximum value of the DC voltage setting gain k is 1. Therefore, the settable range of k is in the range of 0.5-1.

  Next, the input current will be described. As the T-phase input current, a positive current proportional to the time of the T-phase control voltage kc flows. As the S-phase input current, a negative current proportional to the absolute value | kb | of the S-phase control voltage kb, that is, a current proportional to the S-phase control voltage kb flows. As for the R-phase input current, a positive current flows in section 1 = T × (1−kc), and a negative current flows in section 3 = T × (1 + kb). Accordingly, the positive current that flows is T × (1−kc) −T × (1 + kb) = T × (−kc−kb) = T × k × (−c−b) = T × k × a When the average of the period T is divided by T, an R-phase control voltage ka is obtained. As described above, currents proportional to the R-phase control voltage ka, S-phase control voltage kb, and T-phase control voltage kc flow through the R-phase, S-phase, and T-phase currents, and the current is proportional to the input voltage. Will flow on average.

  The DC voltage and input current by this switching are summarized as follows.

(1) The average value of the DC voltage in the switching period T becomes a constant voltage value that is stepped down.

(2) The average value of the input current in the switching period T is distributed to the input voltage ratio.

Next, it will be described that the input current becomes a sine wave. The R-phase voltage of the three-phase AC voltage is Vsin (ωt), the S-phase voltage is Vsin (ωt + 120), and the T-phase voltage is Vsin (ωt + 240). From (2) above, the input current is generally R (phase) current I (t) sin (ωt), S phase current I (t) sin (ωt + 120), and T phase current I (t) sin (ωt + 240). Can be written. However, I (t) is the amplitude of the input current.
The input power P at this time can be expressed as follows.

P = Vsin (ωt) × I (t) sin (ωt) + Vsin (ωt + 120) × I (t) sin (ωt + 120) Vsin (ωt + 240) + I (t) sin (ωt + 240)
= V × I (t) sin ² (ωt) + V × I (t) sin ² (ωt + 120) + V × I (t) sin ² (ωt + 240)
= V × I (t) {sin ² (ωt) + sin ² (ωt + 120) + sin ² (ωt + 240)}

When calculating in {}, since {} is a constant 3/2,
By transforming P = V × I (t) × 3/2, I (t) = P / V × 2/3

  Here, when P is constant, V is constant, so I (t) is a constant value that does not depend on time. That is, the input current is a sine wave.

(3) When the power is constant under the above condition (2), the input current is a sine wave.

  In the circuit of FIG. 1, the switching pattern generator 5 and the drive circuit 6 perform the above switching, and can be considered as a DC reactor that removes fluctuations in DC voltage within the switching period T.

  However, when the present inventors made a prototype of the three-phase rectifier 1 and evaluated it, the result shown in FIG. 16 was obtained. FIG. 16 is a diagram showing characteristics evaluated for the input AC current and the output DC voltage of the three-phase rectifier 1 in the basic mode. As shown in FIG. 16, the input AC current of each phase of R, S, and T includes harmonics and has a waveform distorted from an ideal sine wave. Further, in the output DC voltage, pulsation is generated with a period of about 60 ° (period equivalent to the sections I to VI), similarly to the output voltage when the three-phase AC voltage is full-wave rectified.

  The inventor further investigated the cause of the evaluation characteristics as shown in FIG. As a result, it has been found that such evaluation characteristics are generated depending on the turn-off characteristics of each switching element SW (for example, a semiconductor transistor).

That is, even if an off instruction is issued to turn off each switching element SW, current continues to flow through the switching element SW during the fall time from the timing of the off instruction until the switching element SW is turned off. Thereby, the time during which the current flows through the switching element SW, that is, the time during which the switching element SW is actually turned on (actual on time) is longer than the time from the on instruction to the off instruction (indicated on time). It becomes longer by the fall time of SW. For this reason, when the instruction on time is made equal to the time corresponding to the theoretical pulse width (target on time), the actual on time becomes longer than the target on time by the falling time of the switching element SW. As a result, in the three-phase rectifier 1 in the basic form, the actual ON time in the switching pattern of each phase of R, S, and T becomes longer than the time corresponding to the theoretical pulse width (target ON time), and the output DC voltage As the output voltage when full-wave rectification is applied to the three-phase AC voltage, pulsation occurs with a period of about 60 ° (period equivalent to the sections I to VI) because of the superfluous voltage superimposed on it is conceivable that.
When this is expressed by an equation, the following equation 1 is established.

(Actual on time) ≒ (indicated on time) + (fall time of switching element SW)
... Formula 1

  If (indicated on time) = (target on time: time corresponding to the theoretical pulse width) in equation 1, the following equation 2 is established.

(Actual ON time) ≒ (Target ON time) + (Falling time of switching element SW)
... Formula 2
That is, the following expression 3 is established.
(Actual on time)> (target on time)...

  Therefore, in the first embodiment, in the three-phase rectifier 1i, the control circuit generates the switching pattern of each phase so that the on / off pattern considering the falling time of each switching element SW is included. Aiming to approach the target on-time. Below, it demonstrates centering on a different part from a basic form.

  The control unit 11i of the three-phase rectifier 1i according to the first embodiment includes a generation unit 14i as illustrated in FIG. 17 instead of the generation unit 14 (see FIG. 4). FIG. 17 is a diagram illustrating a configuration of the generation unit 14i.

  The generation unit 14i determines which time position in the current interval (that is, the position on the horizontal axis in FIG. 5) the current timing is in accordance with the combination of the carrier cycle clock, the halfway divided clock, and the interval cycle clock. presume. And the production | generation part 14i estimates the voltage of each phase as shown with a dashed-dotted line in FIG. 5 according to an estimation result. That is, the generation unit 14i generates, as a control signal, a signal in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1 according to the zero cross signal. For example, the generation unit 14i controls a signal in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is 0.98 or less (for example, 0.97 or 0.95) according to the zero cross signal. Generate as a signal. The generation unit 14 i outputs the estimated voltage of each phase, that is, the control signal of each phase (for example, the R phase voltage a ′, the S phase voltage b ′, and the T phase voltage c ′) to the switching pattern generator 5. The absolute value of the maximum amplitude is determined according to the fall time of the switching element. For example, the absolute value of the maximum amplitude can be set to 0.98 when the fall time of the switching element is relatively short, and the absolute value of the maximum amplitude can be set to 0.95 when the fall time of the switching element is relatively long. it can.

  Specifically, the generation unit 14i includes a storage unit (ROM) 14ai instead of the storage unit (ROM) 14a (see FIG. 4). The storage unit (ROM) 14ai stores a sine wave table 14a1i in which time position data in a sine wave whose peak values are normalized to Pe and -Pe and the normalized amplitude are associated with each other. The peak value Pe is, for example, a positive value smaller than 1, for example, a positive value of 0.98 or less (for example, 0.97 or 0.95). As described above, the control signal generator 14b estimates time positions in the current sections I to VI and the current sections I to VI.

  For example, the control signal generator 14b generates first data indicating the current section by collecting the bit values of the first divided clock, the second divided clock, and the third divided clock. The control signal generator 14b generates second data indicating the current timing by combining the bit values of the carrier clock, the halfway divided clock, and the interval cycle clock. The control signal generator 14b combines the first data and the second data to generate time position data. Then, the control signal generator 14b refers to the sine wave table 14a1i stored in the storage unit (ROM) 14ai, identifies the normalized amplitude of each phase corresponding to the generated time position data, and identifies each identified Let the normalized amplitude of the phase be the estimation result of the voltage of each phase. Thereby, the phase voltage of each phase (R phase, S phase, T phase) as shown by the alternate long and short dash line in FIG. 5 can be obtained as a standardized control signal whose absolute value of the maximum amplitude is smaller than 1.

  That is, the generation unit 14i generates the control signal such that Pe / Pc <1 when the absolute value of the maximum amplitude of the control signal is Pe and the absolute value of the maximum amplitude of the carrier signal is Pc. The control signal includes, for example, an estimation result of the phase voltage of each phase (R phase, S phase, T phase). Pe is a positive value smaller than 1, for example, a positive value of 0.98 or less (for example, 0.97 or 0.95). The carrier signal includes, for example, a sawtooth wave 1 and a sawtooth wave 2 (see FIG. 7). Pc is a value substantially equal to 1.

  Thus, since the peak values of the voltages (control signals for each phase) a ′, b ′, and c ′ output from the generation unit 14 i to the switching pattern generator 5 are smaller than 1, the pattern signal The control voltages ka ′, kb ′, and kc ′ of each phase generated by the generator 511 (see FIG. 6) can be made smaller in amplitude than the theoretical value. As a result, the switching pattern generation unit 5a (see FIG. 6) shortens the instruction on-time of the maximum voltage phase pulse and the minimum voltage phase pulse by the falling time of the switching element SW in each of the sections I to VI. Can do. As a result, the actual on time can be brought close to the target on time.

When this is expressed by an equation, (instruction on time) = (target on time) − (falling time of the switching element SW) is substituted into equation 1, and the following equation 4 is obtained.
(Actual on-time) ≒ (target on-time) ... Equation 4

  Next, the operation of the switching pattern generator 5 in the first embodiment will be described with reference to FIGS. 10 to 15 are diagrams illustrating examples of the control voltage of each phase, the sawtooth waves 1 and 2 and the pulse of each phase in the sections I to VI, respectively. 10 to 15, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the first embodiment are indicated by a one-dot chain line.

<Section I>
The case where the R phase is the maximum, the middle of the T phase, and the minimum of the S phase in section I will be described with reference to FIG. In FIG. 10, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the first embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are standardized so that the absolute value of the maximum amplitude becomes Pe. The R-phase control voltage ka ′, the S-phase control voltage kb ′, and the T-phase control voltage kc ′ obtained by multiplying this by the DC voltage setting gain k are the control voltages (ka for each phase in the basic form indicated by the solid line. , Kb, kc), the amplitude is reduced.

  Accordingly, the R-phase pulse width x ′, which is the maximum voltage phase, is shorter than the R-phase pulse width x in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 5 holds, the characteristic of expression 4 can be obtained.

      (Time according to R-phase pulse width x ') ≈ (Time according to R-phase pulse width x)-(Falling time of switching element SW-r) Equation 5

  Similarly, the pulse width y ′ of the S phase, which is the minimum voltage phase, is shorter than the pulse width y of the S phase in the basic form by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 6 holds, the characteristic of expression 4 can be obtained.

      (Time according to S-phase pulse width y ′) ≈ (Time according to S-phase pulse width y) − (Falling time of switching element SW-s) Expression 6

<Section II>
The case of R phase maximum, S phase middle, and T phase minimum in Section II will be described with reference to FIG. In FIG. 11, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the first embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are standardized so that the absolute value of the maximum amplitude becomes Pe. The R-phase control voltage ka ′, the S-phase control voltage kb ′, and the T-phase control voltage kc ′, which are multiplied by the DC voltage setting gain k, are attenuated in amplitude compared to the basic form.

  Accordingly, the R-phase pulse width x ′, which is the maximum voltage phase, is shorter than the R-phase pulse width x in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 7 holds, the characteristic of expression 4 can be obtained.

      (Time according to R-phase pulse width x ') ≈ (Time according to R-phase pulse width x)-(Falling time of switching element SW-r)

  Similarly, the T-phase pulse width z ′, which is the minimum voltage phase, is shorter than the T-phase pulse width z in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 8 is established, the characteristic of expression 4 can be obtained.

      (Time according to T-phase pulse width z ′) ≈ (Time according to T-phase pulse width z) − (Falling time of switching element SW-t) Expression 8

<Section III>
The case of the S phase maximum, R phase middle, and T phase minimum of the section III will be described with reference to FIG. In FIG. 12, the control voltage of each phase, sawtooth waves 1 and 2 and the pulse of each phase in the first embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are standardized so that the absolute value of the maximum amplitude becomes Pe. The R-phase control voltage ka ′, the S-phase control voltage kb ′, and the T-phase control voltage kc ′, which are multiplied by the DC voltage setting gain k, are attenuated in amplitude compared to the basic form.

  Accordingly, the S-phase pulse width y ′, which is the maximum voltage phase, is shorter than the S-phase pulse width y in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following formula 9 holds, the characteristic of formula 4 can be obtained.

      (Time corresponding to S-phase pulse width y ′) ≈ (Time corresponding to S-phase pulse width y) − (Falling time of switching element SW-s) Equation 9

  Similarly, the T-phase pulse width z ′, which is the minimum voltage phase, is shorter than the T-phase pulse width z in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 10 holds, the characteristic of expression 4 can be obtained.

      (Time according to T-phase pulse width z ′) ≈ (Time according to T-phase pulse width z) − (Falling time of switching element SW-t)

<Section IV>
The case where the S phase is maximum, the T phase is intermediate, and the R phase is minimum in the section IV will be described with reference to FIG. In FIG. 13, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the first embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are standardized so that the absolute value of the maximum amplitude becomes Pe. The R-phase control voltage ka ′, the S-phase control voltage kb ′, and the T-phase control voltage kc ′, which are multiplied by the DC voltage setting gain k, are attenuated in amplitude compared to the basic form.

  Accordingly, the S-phase pulse width y ′, which is the maximum voltage phase, is shorter than the S-phase pulse width y in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 11 holds, the characteristic of expression 4 can be obtained.

      (Time corresponding to S-phase pulse width y ′) ≈ (Time corresponding to S-phase pulse width y) − (Falling time of switching element SW-s)

  Similarly, the R-phase pulse width x ′, which is the minimum voltage phase, is shorter than the R-phase pulse width x in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 12 holds, the characteristic of expression 4 can be obtained.

      (Time according to R-phase pulse width x ′) ≈ (Time according to R-phase pulse width x) − (Falling time of switching element SW-r) Equation 12

<Section V>
A case where the T-phase is maximum, the S-phase intermediate, and the R-phase minimum in the section V will be described with reference to FIG. In FIG. 14, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the first embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are standardized so that the absolute value of the maximum amplitude becomes Pe. The R-phase control voltage ka ′, the S-phase control voltage kb ′, and the T-phase control voltage kc ′, which are multiplied by the DC voltage setting gain k, are attenuated in amplitude compared to the basic form.

  Accordingly, the T-phase pulse width z ′, which is the maximum voltage phase, is shortened by the amount corresponding to the fall time of the switching element SW, compared with the T-phase pulse width z in the basic configuration. That is, since the following expression 13 holds, the characteristic of expression 4 can be obtained.

      (Time according to T-phase pulse width z ′) ≈ (Time according to T-phase pulse width z) − (Falling time of switching element SW-t) Expression 13

  Similarly, the R-phase pulse width x ′, which is the minimum voltage phase, is shorter than the R-phase pulse width x in the basic configuration by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 14 holds, the characteristic of expression 4 can be obtained.

      (Time according to R-phase pulse width x ′) ≈ (Time according to R-phase pulse width x) − (Falling time of switching element SW-r) Equation 14

<Section VI>
A case where the T phase is the maximum, the R phase middle, and the S phase minimum in the section V will be described with reference to FIG. In FIG. 15, the control voltage of each phase, the sawtooth waves 1 and 2, and the pulse of each phase in the first embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are standardized so that the absolute value of the maximum amplitude becomes Pe. The R-phase control voltage ka ′, the S-phase control voltage kb ′, and the T-phase control voltage kc ′, which are multiplied by the DC voltage setting gain k, are attenuated in amplitude compared to the basic form.

  Accordingly, the T-phase pulse width z ′, which is the maximum voltage phase, is shortened by the amount corresponding to the fall time of the switching element SW, compared with the T-phase pulse width z in the basic configuration. That is, since the following expression 15 holds, the characteristic of expression 4 can be obtained.

      (Time according to T-phase pulse width z ′) ≈ (Time according to T-phase pulse width z) − (Falling time of switching element SW-t) Equation 15

  Similarly, the pulse width y ′ of the S phase, which is the minimum voltage phase, is shorter than the pulse width y of the S phase in the basic form by an amount corresponding to the fall time of the switching element SW. That is, since the following equation 16 holds, the characteristic of equation 4 can be obtained.

      (Time corresponding to S-phase pulse width y ′) ≈ (Time corresponding to S-phase pulse width y) − (Falling time of switching element SW-s)

  When such a three-phase rectifier 1i was prototyped and evaluated, the results shown in FIG. 18 were obtained. FIG. 18 is a diagram showing characteristics evaluated for the input AC current and the output DC voltage of the three-phase rectifier 1i in the first embodiment. As shown in FIG. 18, harmonics are reduced in the input AC current of each phase of R, S, and T, and the waveform is close to an ideal sine wave compared to the basic form (see FIG. 16). It has become. Further, in the output DC voltage, pulsation is suppressed as compared with the basic form (see FIG. 16).

  As described above, in the first embodiment, in the three-phase rectifier 1i, the control unit 11i includes an on / off pattern in which the fall times of the plurality of switching elements SW-r, SW-s, and SW-t are considered. As described above, a switching pattern for each phase is generated. For example, the control unit 11i generates a switching pattern for each phase so that the on-off pattern in which the time from the on instruction to the off instruction is shortened by considering the falling time from the target on time is included. As a result, the time during which the switching element SW is actually turned on (actual on-time) can be brought close to the time corresponding to the theoretical pulse width (target on-time), so that the harmonics included in the input AC current can be reduced. This can reduce the pulsation of the output DC voltage.

  In the first embodiment, in the control unit 11i of the three-phase rectifier 1i, when the generation unit 14i sets Pe as the absolute value of the maximum amplitude of the control signal and Pc as the absolute value of the maximum amplitude of the carrier signal, Pe A control signal is generated according to the reference signal so that / Pc <1. The switching pattern generator 5a generates the switching pattern of the bidirectional switch circuit 3 using the carrier signal and its control signal. Thereby, the switching pattern of each phase can be generated so that the on-off pattern in which the time from the on instruction to the off instruction is shortened by the length considering the fall time from the target on time is included.

  In the first embodiment, in the control unit 11i of the three-phase rectifier 1i, the zero cross detection unit 12 detects the zero cross timing of the phase voltage in the three-phase AC power, and detects at least one of the detected phase voltages or A zero cross signal indicating the zero cross timing of the line voltage is generated as a reference signal. The generation unit 14i generates, as a control signal, a signal in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1 based on the generated zero cross signal. As a result, a control signal corresponding to the phase voltage timing can be generated based on the reference signal, and the phase voltage of each phase (R phase, S phase, T phase) is normalized to a value whose absolute value of the maximum amplitude is smaller than 1. Can be obtained as a control signal.

  In the first embodiment, in the control unit 11i of the three-phase rectifier 1i, the generation unit 14i has a sine wave table 14a1i in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1. A control signal is generated by estimating the voltage of each phase using. Thereby, the phase voltage of each phase (R phase, S phase, T phase) can be obtained as a control signal that is standardized with an absolute value of the maximum amplitude smaller than 1 with a simple configuration.

  As illustrated in FIG. 19, the generation unit 14 i may generate a control signal by multiplying the voltage of each phase estimated using the same sine wave table 14 a 1 as in the basic form by a coefficient. For example, the generation unit 14i illustrated in FIG. 19 may include a storage unit (ROM) 14a that stores the same sine wave table 14a1 as in the basic form, and may further include a multiplier 14ci. In this case, the control signal generator 14b uses the normalized amplitude of each phase whose absolute value of the maximum amplitude is normalized to 1 as the estimated result of the voltage of each phase, and the estimated result of the voltage of each phase to the multiplier 14ci. Output. The multiplier 14ci multiplies the estimation result of the voltage of each phase by a coefficient K smaller than 1, and outputs the multiplication result to the switching pattern generator 5 as a control signal. The coefficient K is, for example, a positive value smaller than 1, for example, a positive value of 0.98 or less (for example, 0.97 or 0.95). Also by this, the phase voltage of each phase (R phase, S phase, T phase) can be obtained as a standardized control signal whose absolute value of the maximum amplitude is smaller than 1 with a simple configuration.

  Alternatively, as illustrated in FIG. 20, the generation unit 14i selects a sine wave table corresponding to the cumulative operation time of the three-phase rectifier 1i from a plurality of sine wave tables having different absolute values of the maximum amplitude, and the selected sine wave The control signal may be generated by estimating the voltage of each phase using a table. The fall time of each switching element SW may become longer as it deteriorates over time. Therefore, a plurality of sine wave tables corresponding to a plurality of different accumulated operating times are prepared, and the plurality of sine wave tables have different absolute values of maximum amplitudes corresponding to the plurality of accumulated operating times.

  For example, the generation unit 14i illustrated in FIG. 20 includes a storage unit (ROM) 14ai that stores a plurality of sine wave tables 14a1i-1 to 14a1i-n, and further includes a selection unit 14di. In each of the plurality of sine wave tables 14a1i-1 to 14a1i-n, the voltage of each phase is standardized so that the absolute value of the maximum amplitude becomes a value smaller than 1. For example, when the absolute values of the maximum amplitudes in the sine wave tables 14a1i-1 to 14a1i-n are Pe-1 to Pe-n, the following Expression 17 holds.

      1> (Pe-1)> (Pe-2)>...> (Pe-n).

  For example, in the three-phase rectifier 1i, a timer (not shown) counts the cumulative operation time of the three-phase rectifier 1i, and the selection unit 14di acquires information on the cumulative operation time of the three-phase rectifier 1i from the timer. The selection unit 14di selects the sine wave table corresponding to the accumulated operation time of the three-phase rectifier 1i among the plurality of sine wave tables 14a1i-1 to 14a1i-n according to the acquired information of the accumulated operation time of the three-phase rectifier 1i. Select.

For example, a plurality of threshold values TH-2 to TH-n for determining the cumulative operation time of the three-phase rectifier 1i are set in the selection unit 14di, and it is assumed that the following Expression 18 holds.
(TH-2) <... <(TH-n) ... Equation 18

  At this time, the selection unit 14di selects the sine wave table 14a1i-1 when the cumulative operation time of the three-phase rectifier 1i does not exceed the threshold value TH-2. The selection unit 14di selects the sine wave table 14a1i-2 when the cumulative operation time of the three-phase rectifier 1i exceeds the threshold value TH-2. ... the selection unit 14di selects the sine wave table 14a1i-n when the cumulative operating time of the three-phase rectifier 1i exceeds the threshold value TH-n. Thereby, the control signal generator 14b estimates the voltage of each phase using the sine wave table selected by the selection unit 14di.

  As described above, the sine wave table corresponding to the cumulative operation time of the three-phase rectifier 1i is selected from the plurality of sine wave tables having different absolute values of the maximum amplitude corresponding to the plurality of different cumulative operation times. The voltage of each phase is estimated using a sine wave table. Thereby, the fall of each switching element SW-r, SW-s, SW-t is considered, considering the lengthening of the fall time due to aged deterioration of each switching element SW-r, SW-s, SW-t. The switching pattern of each phase can be generated so as to include an on / off pattern in consideration of time. As a result, when the switching element SW (for example, a semiconductor transistor) has deteriorated over time, the time during which the switching element SW is actually turned on (actual on time) corresponds to the theoretical pulse width (target on time). Can be approached.

  Alternatively, as illustrated in FIG. 21, the generation unit 14 i selects a coefficient corresponding to the cumulative operation time of the three-phase rectifier 1 i from a plurality of coefficients, and estimates each using the same sine wave table 14 a 1 as the basic form. The control signal may be generated by multiplying the phase voltage by the selected coefficient. For example, the generation unit 14i illustrated in FIG. 21 may include a storage unit (ROM) 14a that stores the same sine wave table 14a1 as in the basic form, and may further include a coefficient selection unit 14ei and a multiplier 14ci. Each of the plurality of coefficients K-1 to K-n is a value smaller than 1, and the following Expression 19 is satisfied.

      1> (K-1)> (K-2)>...> (Kn).

  For example, in the three-phase rectifier 1i, a timer (not shown) counts the cumulative operation time of the three-phase rectifier 1i, and the coefficient selection unit 14ei acquires information on the cumulative operation time of the three-phase rectifier 1i from the timer. The coefficient selection unit 14ei generates a sine wave table corresponding to the accumulated operation time of the three-phase rectifier 1i among the plurality of coefficients K-1 to Kn according to the acquired information on the accumulated operation time of the three-phase rectifier 1i. select.

For example, a plurality of threshold values TH-2 to TH-n for determining the cumulative operating time of the three-phase rectifier 1i are set in the coefficient selection unit 14ei, and the following Expression 20 is satisfied.
(TH-2) <... <(TH-n) ... Equation 20

  At this time, the coefficient selection unit 14ei selects the coefficient K-1 when the cumulative operation time of the three-phase rectifier 1i does not exceed the threshold value TH-2. The coefficient selection unit 14ei selects the coefficient K-2 when the cumulative operation time of the three-phase rectifier 1i exceeds the threshold value TH-2. ... The coefficient selection unit 14ei selects the coefficient Kn when the cumulative operating time of the three-phase rectifier 1i exceeds the threshold value TH-n. Thereby, the multiplier 14ci receives the estimation result of the voltage of each phase from the control signal generator 14b, receives the selected coefficient K from the coefficient selection unit 14ei, and receives the selected coefficient K as the estimation result of the voltage of each phase. Multiply by. The multiplier 14ci outputs the multiplication result to the switching pattern generator 5 as a control signal.

  In this way, a coefficient corresponding to the cumulative operation time of the three-phase rectifier 1i is selected from a plurality of different coefficients, and a control signal is generated by multiplying the voltage of each phase by the selected coefficient. As a result, an on / off pattern in which the fall time of each switching element SW-r, SW-s, SW-t is taken into consideration while considering the aging of each switching element SW-r, SW-s, SW-t is included. As described above, a switching pattern of each phase can be generated. As a result, when the switching element SW (for example, a semiconductor transistor) has deteriorated over time, the time during which the switching element SW is actually turned on (actual on time) corresponds to the theoretical pulse width (target on time). Can be approached.

Embodiment 2. FIG.
Next, a three-phase rectifier 1j according to the second embodiment will be described. Below, it demonstrates focusing on a different part from Embodiment 1. FIG.

  In the second embodiment, when an improved switching pattern is used in order to reduce DC voltage pulsation and input current harmonics while using a capacitor or reactor having a smaller capacity, With the same concept, we aim to bring the actual on-time closer to the target on-time. In the second embodiment, for example, the switching pattern is improved by the following guidelines.

(1) Step-down is performed by turning off the bidirectional switch circuit in at least two phases (R phase, T phase, S phase) and providing a switching section in which no current flows in all phases (intermediate phase) The voltage is dropped without widening the conduction width.

(2) The input capacitor is regularly charged and discharged by making the pulse order of the interval voltages in all modes I to VI regular (the same phase in all modes has the same regular switching pattern). .

  According to the above (1), the DC voltage can be lowered without increasing the conduction width of the intermediate phase, so that the voltage fluctuation of the input capacitor of the intermediate phase can be prevented from increasing. According to the above (2), charging / discharging of the input capacitor of each phase can be balanced by making the pulse order of the section voltage in each mode I to VI regular. As a result, it is possible to prevent spike-like current waveforms during charging / discharging of the input capacitor without increasing the switching frequency. In addition, since the voltage fluctuation of the intermediate phase input capacitor does not increase, it is possible to use an input capacitor having a small capacity.

  Specifically, the control unit 11j of the three-phase rectifier 1j includes a switching pattern generator 5j as shown in FIGS. FIG. 22 is a block diagram showing an example of the switching pattern generator 5j. FIG. 23 is a diagram illustrating a configuration example of the phase voltage discriminator 52 of the switching pattern generator 5j. FIG. 24 is a circuit diagram showing a configuration example of the pattern signal generator 51 of the switching pattern generator 5j.

  The switching pattern generator 5j generates switching patterns (R, S, T phase pulses) as shown in FIGS. 25 to 27, for example, depending on which of the six sections I to VI is present. . The switching pattern generator 5j detects which phase of the three-phase AC power from the three-phase AC power source PS is an intermediate potential phase at a predetermined timing such as the rise of the switching cycle, and generates a modulation waveform according to the detection result. The switching pattern is generated by obtaining the ON / OFF timing of the switching pattern by the sawtooth wave.

  For example, the switching pattern generator 5j includes a carrier generator 5bj and a switching pattern generator 5aj as shown in FIG. The carrier generator 5bj generates a carrier in synchronization with the carrier clock. The switching pattern generator 5aj generates the switching pattern of the bidirectional switch circuit 3 using the generated carrier.

  The carrier generator 5bj includes a DC voltage setter 53 and a sawtooth generator 54. The switching pattern generator 5aj includes a pattern signal generator 51, a phase voltage discriminator 52, comparators 55-1 to 55-3, NOT circuits 56-1 and 56-2, OR circuits 57-1 and 57-2, and a NOT circuit. 58-1, 58-2, AND circuits 59-1, 59-2, AND circuits 60R, 60T, OR circuit 60S, NAND circuits 61R-61T, AND circuits 62R-62T, OR circuits 63R-63T, and AND circuit 64 Have

  The pattern signal generator 51 includes an R-phase voltage normalized signal a, an S-phase voltage normalized signal b, and a T-phase in which the peak value of the input phase voltage is normalized to “Pe” and “−Pe” (0 <Pe <1). The voltage normalization signal c is received from the generation unit 14i. The pattern signal generator 51 generates an R-phase voltage normalized signal a, an S-phase voltage normalized signal b, and a T-phase voltage normalized signal c in order to make the pulse order of the interval voltages in all intervals I to VI regular. Calculation is performed to output a modulation waveform 1, a modulation waveform 2A, a modulation waveform 2B, and a modulation waveform 3.

  The DC voltage setting unit 53 sets a DC voltage setting gain k (where k ≦ 1) in the sawtooth wave generator 54. The sawtooth wave generator 54 outputs the sawtooth wave 1 and the sawtooth wave 2. The phase voltage discriminator 52 compares the potentials of the input R-phase voltage normalized signal a, S-phase voltage normalized signal b, and T-phase voltage normalized signal c, and R-phase middle, S-phase middle, T-phase An intermediate determination signal (“1” for intermediate, “0” for non-intermediate) is output, respectively. Specifically, in the middle of the S phase, modulation waveforms 1 and 3 are output, and sawtooth waves 1 and 2 are output (see FIG. 25). In the middle of the T phase, the modulation waveforms 1 and 2A are output, and the sawtooth wave 1 is output (see FIG. 26). In the middle of the R phase, the modulation waveforms 3 and 2B are output, and the sawtooth wave 2 is output (see FIG. 27). Thus, in the switching pattern generator 5j, the switching pattern generation method is changed according to which phase the intermediate phase is. Thereby, the same regularity is given to the switching pattern of the same phase in all modes.

  The comparison signal obtained by comparing the modulation waveform 1 and the sawtooth wave 1 by the comparator 55-1 and the output obtained by performing the NOT operation on the R-phase intermediate signal by the NOT circuit 58-1 are ANDed by the AND circuit 60R. Output as a non-intermediate phase pulse.

  The comparison signal obtained by comparing the modulation waveform 3 and the sawtooth wave 2 by the comparator 55-3 and the output obtained by performing NOT operation on the T-phase intermediate signal by the NOT circuit 58-2 are ANDed by the AND circuit 60T. Output as a non-intermediate phase pulse.

  The comparison signal obtained by comparing the modulation waveform 2A and the sawtooth wave 1 by the comparator 55-2A and the output obtained by performing NOT operation on the comparison signal of the comparator 55-1 by the NOT circuit 56-1 are ORed by the OR circuit 57-1. Calculated. The comparison signal obtained by comparing the modulation waveform 2B and the sawtooth wave 2 by the comparator 55-2B and the output obtained by performing the NOT operation on the comparison output of the comparator 55-3 by the NOT circuit 56-2 are ORed by the OR circuit 57-2. The

  An AND circuit 59-1 performs an AND operation on the OR circuit 57-1 and an T-phase intermediate signal, and an OR circuit 57-2 performs an OR operation on the R-phase intermediate signal. The output of the AND operation in 2 is ORed by the OR circuit 60S, and an S-phase non-intermediate pulse is output.

  The NAND circuit 61R performs an NAND operation on the S-phase non-intermediate time pulse and the T-phase non-intermediate time pulse and the R-phase intermediate signal, and the AND circuit 62R performs an AND operation to output an R-phase intermediate time pulse.

  The NAND circuit 61S performs an NAND operation on the R-phase non-intermediate pulse and the T-phase non-intermediate pulse, and the S-phase intermediate signal is AND-operated by the AND circuit 62S, and is output as an S-phase intermediate pulse.

  The NAND circuit 61T performs an NAND operation on the R-phase non-intermediate time pulse and the S-phase non-intermediate time pulse and the T-phase intermediate signal, and the AND circuit 62T performs an AND operation to output it as a T-phase intermediate time pulse.

  The comparator 65 compares the sawtooth wave 1 with the “0” input, and outputs a comparison signal as a zero voltage insertion lock signal.

  The OR circuit 63R performs an OR operation on the R-phase non-intermediate time pulse and the R-phase intermediate time pulse, and the 0 voltage insertion signal is ANDed by the AND circuit 64 and is output as an R-phase pulse. Thereby, a switching pattern (section 4 in each section I to VI) for turning off the bidirectional switch is introduced into the R-phase pulse.

  In the OR circuit 63T, the T-phase non-intermediate time pulse and the T-phase intermediate time pulse are ORed and output as a T-phase pulse. Since the output of the OR circuit 63T is “0” during the zero voltage insertion signal period, the T phase pulse is not calculated with the zero voltage insertion signal.

  In the OR circuit 63S, the S-phase non-intermediate time pulse and the S-phase intermediate time pulse are ORed to output an S-phase pulse. The R-phase pulse and the T-phase pulse are “0” during the zero voltage insertion signal period, and no DC voltage is generated even when the S-phase pulse is ON. For the purpose of not increasing the number of times of T-phase switching, the calculation with the zero voltage insertion signal is not performed.

  The sawtooth wave generator 54 is a straight line connecting (time axis kT, gain axis 0) and (time axis 0, gain axis 1) when the period T is set based on the DC voltage setting gain k of the DC voltage generator 53. To output a sawtooth wave 1. The sawtooth wave generator 54 outputs the sawtooth wave 2 as a straight line connecting (time axis 0, gain axis 0) and (time axis kT, gain axis 1) based on the DC voltage setting gain k.

  As shown in FIG. 23, the phase voltage discriminator 52 includes comparators 70R, 70S, and 70T, AND circuits 71R, 71S, and 71T, AND circuits 72R, 72S, and 72T, and NOR circuits 73R, 73S, and 73T. ing.

  The comparator 70R compares the R-phase voltage normalized signal a and the S-phase voltage normalized signal b, and compares the comparison signal (“1” when R-phase voltage normalized signal a> S-phase voltage normalized signal b, When the R-phase voltage standardized signal a ≦ the S-phase voltage standardized signal b, “0”) is output to the AND circuits 71R, 72S, 71T, and 72T. The comparator 70S compares the S-phase voltage normalized signal b and the T-phase voltage normalized signal c, and compares the comparison signal (“1” when S-phase voltage normalized signal b> T-phase voltage normalized signal c; When the S-phase voltage normalized signal b ≦ T-phase voltage normalized signal c, “0”) is output to the AND circuits 71R, 72R, 71S, and 72T. The comparator 70T compares the T-phase voltage normalized signal c and the R-phase voltage normalized signal a, and compares the comparison signal (“1” when T-phase voltage normalized signal c> R-phase voltage normalized signal a; When the T-phase voltage normalized signal c ≦ the R-phase voltage normalized signal a, “0”) is output to the AND circuits 72R, 71S, 72S, 71T.

  The AND circuit 71R outputs an AND operation result of the comparison signal of the comparator 70R and the comparison signal of the comparator 70S. The AND circuit 72R outputs an AND operation result of the comparison signal of the comparator 70S and the comparison signal of the comparator 70T. The AND circuit 71S outputs an AND operation result of the comparison signal of the comparator 70S and the comparison signal of the comparator 70T. The AND circuit 72S outputs an AND operation result of the comparison signal of the comparator 70T and the comparison signal of the comparator 70R. The AND circuit 71T outputs an AND operation result of the comparison signal of the comparator 70T and the comparison signal of the comparator 70R. The AND circuit 72T outputs an AND operation result of the comparison signal of the comparator 70R and the comparison signal of the comparator 70S.

  The NOR circuit 73R outputs a NOR operation result (“1” in the case of the intermediate and “0” in the case of not the intermediate) between the output of the AND circuit 71R and the output of the AND circuit 72R as the R-phase intermediate signal. The NOR circuit 73S outputs a NOR operation result (“1” when intermediate, “0” when not intermediate) between the output of the AND circuit 71S and the output of the AND circuit 72S as an S-phase intermediate signal. The NOR circuit 73T outputs a NOR operation result (“1” when intermediate, “0” when not intermediate) between the output of the AND circuit 71T and the output of the AND circuit 72T as a T-phase intermediate signal.

  As shown in FIG. 24, the pattern signal generator 51 that forms each modulation waveform includes absolute value circuits 80R, 80S, and 80T, and 3-input adders 81-1 and 81-2. The absolute value circuit 80R calculates the absolute value | a | of the R-phase voltage normalized signal a and outputs a modulation waveform 1. The absolute value circuit 80S calculates and outputs the absolute value | b | of the S-phase voltage normalized signal b. The absolute value circuit 80T calculates the absolute value | c | of the T-phase voltage normalized signal c and outputs the modulation waveform 3.

  The 3-input adder 81-1 adds the modulation waveform 1, the output of the absolute value circuit 80S, and the constant −1, and outputs the modulation waveform 2A. The 3-input adder 81-2 adds the modulation wavelength 3, the output of the absolute value circuit 80S, and the constant −1, and outputs a modulation waveform 2B.

  Next, the operation in each section I to VI of the switching pattern generator 5j will be described with reference to FIGS.

  With reference to FIGS. 25 to 27, the DC voltage and the current of each phase by the switching operation in each section I to VI will be described. In sections I and IV, the T phase is an intermediate phase, in sections II and V, the S phase is an intermediate phase, and in sections III and VI, the R phase is an intermediate phase. , III will be described. FIG. 25 is a diagram illustrating an example of a modulation waveform, a sawtooth wave, and R, S, and T phase pulses in sections II and V. FIG. 26 is a diagram illustrating an example of a modulation waveform, a sawtooth wave, and R, S, and T phase pulses in sections I and IV. FIG. 27 is a diagram illustrating an example of a modulation waveform, a sawtooth wave, and R, S, and T phase pulses in sections III and VI.

  In FIG. 25 to FIG. 27, the modulation waveform, the sawtooth waves 1 and 2 and the pulse of each phase in the second embodiment are indicated by a one-dot chain line. In addition, in FIGS. 25 to 27, for comparison, the control voltage of each phase when the generator 14i shown in FIG. 22 is replaced with the generator 14 in the basic form (basic form), the sawtooth wave 1 2. Pulses of each phase are indicated by solid lines. That is, in FIG. 25 to FIG. 27, a solid line indicates the case where the peak values of the R-phase voltage normalized signal a, the S-phase voltage normalized signal b, and the T-phase voltage normalized signal c are “1”. Has been.

  As shown in FIGS. 25 to 27, in all sections I to VI, the R phase pulse is OFF → ON → OFF, the S phase pulse is ON → OFF → ON, and the T phase pulse is ON → OFF. In addition, the same phase in all the sections I to VI has the same regular pattern in which the ON and OFF changes are regular. In all the sections I to VI, the R phase pulse has a period (section 4) in which the zero voltage insertion signal is inserted. The period in which this zero voltage insertion signal is inserted is A switching pattern for turning off the direction switch circuit is inserted. Accordingly, in section 4, two of the three phases (R phase and T phase) are turned off, so that no current flows in all phases.

<Section II, V>
First, a basic form will be described with reference to FIG. In FIG. 25, the modulation waveform, the sawtooth waves 1 and 2 and the pulses of each phase in the basic form are shown by solid lines.

  The DC voltage will be described with reference to the section II. In FIG. 25, the DC voltages in sections 1, 2, 3, and 4 are ST voltage = bc, RT voltage = ac, RS voltage = ab, and rectifier output short-circuit voltage = 0. . Next, each phase pulse will be described. In section II, the R phase is the maximum phase, the T phase is the minimum phase, and the S phase is the intermediate phase. In the maximum phase and the minimum phase, the pulse is turned on for a time proportional to each potential. Therefore, the R-phase pulse width x = kT | a | and the T-phase pulse width z = kT | c |. Here, the timing (section 2 + section 3) at which the R-phase pulse is turned on is obtained from the intersection of the R-phase voltage | a | and the sawtooth wave 1. Further, the timing (section 1 + section 4) when the R-phase pulse is turned off is obtained from the intersection of the sawtooth wave 1 and the gain axis 0. Thereby, an R-phase pulse is obtained. On the other hand, the timing (section 3 + section 4) at which the T-phase pulse is turned off is obtained from the intersection of the T-phase voltage | c | and the sawtooth wave 2. Thereby, a T-phase pulse is obtained. The intermediate phase pulse is turned ON when either the maximum phase pulse or the minimum phase pulse is OFF. Therefore, the S-phase pulse is obtained from the intersection between the R-phase voltage | a | and the sawtooth wave 1 and the intersection between the T-phase voltage | c | and the sawtooth wave 2. The widths of the sections 1, 2, 3, and 4 are kT × (1− | a |), kT × (| a | + | c | −1), kT × (1− | c |), T, respectively. X (1-k). The average of the DC voltage in the switching period T can be expressed as follows by integrating the DC voltage for each section, adding each, and dividing by the switching period T.

Average of DC voltage in switching period T = {(b−c) × kT × (1−a) + (ac) × kT × (ac−1) + (ab) × kT × (1 + c ) + 0 × T × (1-k)} / T
= K {a ² + c ² −b (a + c)}
Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )
Furthermore, from AC theory, from a ² + b ² + c ² = 3/2,
= K x 3/2
Thus, it becomes a constant voltage proportional to k.

  Next, the input current will be described. As the R-phase input current, a positive current proportional to the time of the R-phase voltage a flows. As the T-phase input current, a negative current proportional to the magnitude of the T-phase voltage | c | flows. As for the S-phase input current, a positive current flows in section 1 and a negative current flows in section 3. Therefore, the flowing current is kT × (1−a) −kT × (1 + c) −kT (−a−c) = kTb, and the interval 4 in which the 0 voltage insertion signal is inserted is excluded from the switching period T. When divided by the period kT, the S-phase voltage b is obtained. Therefore, a current proportional to the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c flows through the R phase, S phase, and T phase, resulting in a sine wave current.

  Next, a second embodiment will be described. In FIG. 25, the modulation waveform, the sawtooth waves 1 and 2 and the pulse of each phase in the second embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are obtained by normalizing the phase voltage between “−Pe” and “Pe” (0 <Pe <1). is there. Each modulated waveform obtained by modulating this has an attenuated amplitude as compared with the basic form.

  Accordingly, the pulse width x ′ of the R phase, which is the maximum voltage phase or the minimum voltage phase, is shortened from the pulse width x of the R phase in the basic form by an amount corresponding to the fall time of the switching element SW. . That is, since the following expression 21 holds, the characteristic of expression 4 can be obtained.

      (Time according to R-phase pulse width x ') ≈ (Time according to R-phase pulse width x)-(Falling time of switching element SW-r) Equation 21

  Similarly, the pulse width z ′ of the T phase that is the minimum voltage phase or the maximum voltage phase is shorter than the pulse width z of the T phase in the basic form by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 22 holds, the characteristic of expression 4 can be obtained.

      (Time according to T-phase pulse width z ′) ≈ (Time according to T-phase pulse width z) − (Falling time of switching element SW-t)

<Sections I and IV>
First, a basic form will be described with reference to FIG. In FIG. 26, the modulation waveform, the sawtooth waves 1 and 2 and the pulses of each phase in the basic form are shown by solid lines.

  The section I will be described as an example. In FIG. 26, the DC voltages in sections 1, 2, 3, and 4 are ST voltage = c−b, RT voltage = ac, RS voltage = ab, and rectifier output short-circuit voltage = 0. . Next, each phase pulse will be described. In section I, the R phase is the maximum phase, the S phase is the minimum phase, and the T phase is the intermediate phase. In order to make the time ON proportional to the respective potentials in the maximum phase and the minimum phase without changing the ON / OFF sequence of the R, S, T phase pulses, in the section I, the modulation waveforms 1, 2A and the sawtooth wave 1 Is used to obtain the ON / OFF timing of each pulse shown in FIG. The widths of the sections 1, 2, 3, and 4 are kT × (1− | a |), kT (1− | b |), kT × (| a | − | b | −1), and T ×, respectively. (1-k). The average of the DC voltage in the switching period T can be expressed as follows.

Average of DC voltage of switching period T = {(c−b) × kT × (1−a) + (ac) × kT × (b + 1) + (ab) × kT × (ab−1) ) + 0 * kT * (1-k)} / T
= K {a ² + b ² −c (a + b)}
Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

Furthermore, from AC theory, from a ² + b ² + c ² = 3/2,
= K x 3/2
Thus, it becomes a constant voltage proportional to k.

  Next, the input current will be described. As in the case of the section II, a positive current proportional to the time of the R phase voltage a flows in the R phase of the maximum phase. A negative current proportional to the time of the S phase voltage b flows in the S phase of the minimum phase. In the T phase, a negative current flows in section 1 and a positive current flows in section 2. For this reason, the flowing current is kT × (1−a) −kT × (1 + b) = kTc, and c when divided by kT. Therefore, a current proportional to the voltage flows in each phase and becomes a sine wave current.

  Next, a second embodiment will be described. In FIG. 26, the modulation waveform, the sawtooth waves 1 and 2 and the pulse of each phase in the second embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are obtained by normalizing the phase voltage between “−Pe” and “Pe” (0 <Pe <1). is there. Each modulated waveform obtained by modulating this has an attenuated amplitude as compared with the basic form.

  Accordingly, the pulse width x ′ of the R phase, which is the maximum voltage phase or the minimum voltage phase, is shortened from the pulse width x of the R phase in the basic form by an amount corresponding to the fall time of the switching element SW. . That is, since the following Expression 23 is established, the characteristic of Expression 4 can be obtained.

      (Time corresponding to R-phase pulse width x ′) ≈ (Time corresponding to R-phase pulse width x) − (Falling time of switching element SW-r) Equation 23

  Similarly, the pulse width y ′ of the S phase that is the minimum voltage phase or the maximum voltage phase is shorter than the pulse width y of the S phase in the basic form by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 24 holds, the characteristic of expression 4 can be obtained.

      (Time according to pulse width y ′ of S phase) ≈ (Time according to pulse width y of S phase) − (Fall time of switching element SW-s) Expression 24

<Sections III and VI>
First, a basic form will be described with reference to FIG. In FIG. 27, the modulation waveform, the sawtooth waves 1 and 2 and the pulses of each phase in the basic form are indicated by solid lines.

  The section III will be exemplarily described. In FIG. 27, the DC voltages in sections 1, 2, 3, and 4 are ST voltage = bc, RT voltage = ac, RS voltage = ba, and rectifier output short-circuit voltage = 0. . Next, each phase pulse will be described. In section III, the S phase is the maximum phase, the T phase is the minimum phase, and the R phase is the intermediate phase. As in the section I, in order to turn on the time proportional to the respective potentials in the maximum phase and the minimum phase without changing the ON / OFF order of the R, S, and T phase pulses, in the section III, the modulation waveform 3, 2B and the sawtooth wave 2 are used to obtain the ON / OFF timing of each phase pulse shown in FIG. The widths of the sections 1, 2, 3, and 4 are kT × (| b | + | c | −1), kT × (1− | b |), kT × (1− | c |), T × (1−k). The average of the DC voltage in the switching period T can be expressed as follows.

Average of DC voltage of switching period T = {(b−c) × kT × (−c + b−1) + (ac) × kT × (−b + 1) + (b−a) × kT × (1 + c) +0 * KT * (1-k)} / T
^{= K {b 2 + c 2} -a (b + c)}
Here, considering a + b + c = 0 (three-phase condition),
= K (a ² + b ² + c ² )

Furthermore, from AC theory, from a ² + b ² + c ² = 3/2,
= K x 3/2
Thus, it becomes a constant voltage proportional to k.

  Next, the input current will be described. In section III, since the S phase is the maximum phase and the T phase is the minimum phase, a positive current that is proportional to the time of the S phase voltage b flows in the S phase, and the T phase is a negative that is proportional to the time of the T phase voltage c. Current flows. In the R phase, a negative current flows in section 2 and a positive current flows in section 3. Therefore, the flowing current is kT × (1−b) −kT × (1 + c) = kTa, which is a when divided by RT. Therefore, a current proportional to the voltage flows in each phase and becomes a sine wave current.

  Next, a second embodiment will be described. In FIG. 27, the modulation waveform, sawtooth waves 1 and 2 and the pulse of each phase in the second embodiment are indicated by alternate long and short dash lines. As described above, the R-phase voltage a ′, the S-phase voltage b ′, and the T-phase voltage c ′ are obtained by normalizing the phase voltage between “−Pe” and “Pe” (0 <Pe <1). is there. Each modulated waveform obtained by modulating this has an attenuated amplitude as compared with the basic form.

  Accordingly, the pulse width y ′ of the S phase, which is the maximum voltage phase or the minimum voltage phase, is shortened by the amount corresponding to the fall time of the switching element SW, compared with the pulse width y of the S phase in the basic form. . That is, since the following expression 25 holds, the characteristic of expression 4 can be obtained.

      (Time according to S-phase pulse width y ′) ≈ (Time according to S-phase pulse width y) − (Falling time of switching element SW-s) Equation 25

  Similarly, the pulse width z ′ of the T phase that is the minimum voltage phase or the maximum voltage phase is shorter than the pulse width z of the T phase in the basic form by an amount corresponding to the fall time of the switching element SW. That is, since the following expression 26 holds, the characteristic of expression 4 can be obtained.

      (Time according to T-phase pulse width z ′) ≈ (Time according to T-phase pulse width z) − (Falling time of switching element SW-t) Equation 26

  As described above, in the second embodiment, in the three-phase rectifier 1j, the control unit 11j includes an on / off pattern that considers the fall times of the plurality of switching elements SW-r, SW-s, and SW-t. As described above, a switching pattern for each phase is generated. For example, the control unit 11j generates a switching pattern for each phase so that an on / off pattern in which the time from the on instruction to the off instruction is shortened by considering the falling time from the target on time is included. As a result, the time during which the switching element SW is actually turned on (actual on-time) can be brought close to the time corresponding to the theoretical pulse width (target on-time), so that the harmonics included in the input AC current can be reduced. This can reduce the pulsation of the output DC voltage.

  As described above, the three-phase rectifier according to the present invention is useful for generating a DC voltage from three-phase AC power.

1, 1i, 1j Three-phase rectifier 3 Bidirectional switch circuit 4 Full-wave rectifier circuit 5 Switching pattern generator 5a Switching pattern generator 5b Carrier generator 6 Drive circuit 8 Three-phase reactor 9 Input capacitor 10 Capacitor 11, 11i, 11j Control Unit 12 zero cross detection unit 13 PLL circuit 14, 14i, 14j generation unit 14a, 14ai storage unit (ROM)
14b control signal generator 14ci multiplier 14di selection unit 14ei coefficient selection unit

Claims (4)

A three-phase rectifier that converts three-phase AC power input from a three-phase AC power source into DC power,
A full-wave rectifier circuit for rectifying the three-phase AC power into DC power;
A bidirectional switch circuit having a plurality of switching elements for turning on / off the supply of each phase from the three-phase AC power source to the full-wave rectifier circuit;
In response to a reference signal corresponding to the three-phase AC power, a switching pattern for each phase for turning the bidirectional switch circuit ON / OFF is generated, and the bidirectional switch circuit is generated based on the generated switching pattern. Control means for switching control;
With
The control means includes
A carrier generator for generating a carrier signal in response to the reference signal;
In accordance with the reference signal, a generation unit that generates a control signal corresponding to the voltage of each phase;
A switching pattern generating unit that generates a switching pattern of the bidirectional switch circuit using the generated carrier signal and the generated control signal;
Have
The generation unit generates the control signal such that Pe / Pc <1 when the absolute value of the maximum amplitude of the control signal is Pe and the absolute value of the maximum amplitude of the carrier signal is Pc,
The control means generates a switching pattern for each phase so as to include an on / off pattern in consideration of a fall time of each of the plurality of switching elements ,
The control means detects a zero-cross timing of the phase voltage in the three-phase AC power, and generates a zero-cross signal indicating the detected zero-cross timing of at least any one phase voltage or line voltage as the reference signal. It further has a zero cross detector,
The generation unit generates, as the control signal, a signal in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1 based on the generated zero-cross signal,
The generation unit estimates the voltage of each phase using a sine wave table in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is 1, and the estimated voltage of each phase is larger than 0. The control signal is generated by multiplying by a coefficient smaller than 1. The three-phase rectifier. A three-phase rectifier that converts three-phase AC power input from a three-phase AC power source into DC power,
A full-wave rectifier circuit for rectifying the three-phase AC power into DC power;
A bidirectional switch circuit having a plurality of switching elements for turning on / off the supply of each phase from the three-phase AC power source to the full-wave rectifier circuit;
In response to a reference signal corresponding to the three-phase AC power, a switching pattern for each phase for turning the bidirectional switch circuit ON / OFF is generated, and the bidirectional switch circuit is generated based on the generated switching pattern. Control means for switching control;
With
The control means includes
A carrier generator for generating a carrier signal in response to the reference signal;
In accordance with the reference signal, a generation unit that generates a control signal corresponding to the voltage of each phase;
A switching pattern generating unit that generates a switching pattern of the bidirectional switch circuit using the generated carrier signal and the generated control signal;
Have
The generation unit generates the control signal such that Pe / Pc <1 when the absolute value of the maximum amplitude of the control signal is Pe and the absolute value of the maximum amplitude of the carrier signal is Pc,
The control means generates a switching pattern for each phase so as to include an on / off pattern in consideration of a fall time of each of the plurality of switching elements,
The control means detects a zero-cross timing of the phase voltage in the three-phase AC power, and generates a zero-cross signal indicating the detected zero-cross timing of at least any one phase voltage or line voltage as the reference signal. It further has a zero cross detector,
The generation unit generates, as the control signal, a signal in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1 based on the generated zero-cross signal,
The generation unit generates the control signal by estimating the voltage of each phase using a sine wave table in which the voltage of each phase is standardized so that the absolute value of the maximum amplitude is smaller than 1. 3-phase rectifier you wherein a. The generation unit selects a sine wave table corresponding to the cumulative operation time of the three-phase rectifier from a plurality of sine wave tables corresponding to a plurality of different cumulative operation times, and uses each sine wave table to select each phase. The three-phase rectifier according to claim 2 , wherein the control signal is generated by estimating a voltage of the three-phase rectifier. The control means generates a switching pattern of each phase so that an on / off pattern in which a time from an on instruction to an off instruction is shortened by a length considering the fall time from a target on time is included. The three-phase rectifier according to any one of claims 1 to 3 .

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