JP6279442B2 - Fault detection system - Google Patents

Description

  The present invention relates to a failure detection system that detects failures in a plurality of cell arrays connected in series.

  For example, in various vehicles such as an electric vehicle (EV) that travels using an electric motor and a hybrid vehicle (HEV) that travels using both an engine and an electric motor, a lithium ion rechargeable battery is used as a power source for the electric motor. And rechargeable batteries such as nickel metal hydride batteries.

  As such a secondary battery, Patent Document 1 describes a battery pack that includes a plurality of battery cells connected in series and in parallel. By connecting battery cells in series, the voltage of the entire secondary battery can be increased, and by connecting them in parallel, the capacity can be increased.

JP 2009-176589 A

  In a secondary battery in which a plurality of battery cells as described in Patent Literature 1 are connected in series and in parallel, if one battery cell fails, the capacity of the entire secondary battery is greatly reduced. In particular, when a plurality of battery cells are connected in parallel to form a cell array and the plurality of cell arrays are connected in series, if the capacity of one set of cell arrays decreases due to a failure of one battery cell, the entire secondary battery Is determined by the capacity of the cell array. Therefore, in order to detect and cope with a decrease in capacity, it is required to detect a failure in each cell array.

  Therefore, when a battery cell fails, current is not supplied and the combined internal resistance of the cell array changes. Therefore, a method of detecting a cell array failure by detecting a change in the combined internal resistance can be considered. When the current I flows through the cell array having the open circuit voltage OCV and the combined internal resistance r, the voltage between both electrodes becomes V = OCV−r · I. If the change in the voltage V is detected, the change in the combined internal resistance is detected. Can be detected.

  However, when the number of battery cell failures is small, the change in the voltage V between the two electrodes due to the failure is small, and if this change is smaller than the measurement accuracy of the measuring instrument, the failure of the cell array cannot be detected.

  An object of the present invention is to provide a failure detection system that can accurately detect a failure of a cell array.

In order to solve the above problems and achieve the object, the invention described in claim 1 is directed to a plurality of failure detection devices provided corresponding to each of a plurality of cell arrays connected in series, and a failure of the cell array. A failure detection system comprising: a failure determination unit for detecting, wherein the failure detection device has a first input terminal and a second input terminal, and inputs to each of the first input terminal and the second input terminal. Differential voltage output means for outputting a differential voltage corresponding to the differential value of the voltage, a changeover switch for exclusively connecting one electrode of the cell array to the first input terminal and the second input terminal, A first voltage holding means capable of holding a voltage between one input terminal and the other electrode of the cell array; and a second voltage capable of holding a voltage between the second input terminal and the other electrode of the cell array. Holding means When the first current flows through the cell array, one electrode of the cell array is connected to the first input terminal, and when a second current having a magnitude different from the first current flows through the cell array, Switching control means for controlling the changeover switch so as to connect one electrode and the second input terminal, and the failure determination means includes the plurality of failure detection devices in each of the plurality of cell arrays. The differential voltage corresponding to the difference value between the voltage between the electrodes when the first current flows and the voltage between the electrodes when the second current flows are output by the differential voltage output means based on a failure detection system characterized and Turkey be determined in a cell array failed each of the plurality of cell arrays and normal cell array.

  According to a second aspect of the present invention, in the first aspect of the present invention, the cell array includes a plurality of battery cells connected in parallel to each other, and the failure determination unit includes the differential voltage of the normal cell array. And estimating the number of battery cell failures in the failed cell array based on the differential voltage of the failed cell array and the number of parallel battery cells in the set of cell arrays. is there.

  The invention described in claim 3 is configured such that, in the invention of claim 1 or 2, the differential voltage output means outputs a voltage obtained by amplifying the differential value with a predetermined amplification factor as the differential voltage. It is characterized by being.

  The invention described in claim 4 is the invention described in any one of claims 1 to 3, wherein the first current and the second current are currents that flow through the cell array during discharge. To do.

  According to the first aspect of the present invention, the differential voltage output means has the first input terminal and the second input terminal, and the difference between the voltages input to the first input terminal and the second input terminal, respectively. The differential voltage corresponding to the value is output. A changeover switch exclusively connects one electrode of the cell array to the first input terminal and the second input terminal. A first voltage holding unit is provided between the first input terminal and the other electrode of the cell array, and holds a voltage between the first input terminal and the other electrode of the cell array. A second voltage holding unit is provided between the second input terminal and the other electrode of the cell array, and holds a voltage between the second input terminal and the other electrode of the cell array. The connection switching control means connects one electrode of the cell array and the first input terminal when the first current flows through the cell array, and connects the one electrode of the cell array and the second input when the second current flows through the cell array. The changeover switch is controlled so as to connect the terminal. Then, the failure determination means determines a normal cell array and a failed cell array based on a voltage difference value in each cell array detected by each failure detection device.

  Thus, the voltage between both electrodes when the first current flows through the cell array is held in the first voltage holding means, and the voltage between both electrodes when the second current flows is stored in the second voltage holding means. The difference value between the two voltages can be held, and the difference voltage output means outputs the difference voltage. On the other hand, for example, when the voltage between both electrodes of the secondary battery is directly measured, the voltage changes only between the lowest usable voltage and the highest usable voltage of the secondary battery, The input range of the measuring instrument (for example, an analog-digital converter) needs to be adjusted to 0 or more and the maximum voltage or less, and the minimum use voltage is included as an offset voltage. That is, only a part of the resolution of the measuring instrument can be used. On the other hand, the differential voltage does not include such an offset voltage and becomes a very small value compared to the absolute voltage, so that the resolution of the measuring instrument can be maximized by appropriately amplifying it to match the input range of the measuring instrument. It is possible to detect with high accuracy by using the limit.

  The failure determination means determines a group in which the differential voltage is a value within a predetermined range among a plurality of cell arrays as a normal cell array, and a cell array in which a difference in the differential voltage from the normal cell array is greater than a predetermined value has failed Is determined. By detecting the differential voltage with high accuracy as described above, the failure can be detected with high accuracy even if the change in the differential voltage due to the failure of the cell array is small.

  According to the invention described in claim 2, the failure determination means is configured to provide battery cells based on the differential voltage of the normal cell array, the differential voltage of the failed cell array, and the parallel number of the battery cells in one set of cell arrays. Estimate the number of failures. For example, the internal resistance r0 of one battery cell is calculated based on the differential voltage ΔV of the normal cell array and the parallel number n of battery cells, and the post-failure parallel number n− obtained by subtracting the failure number k from the parallel number n. The combined internal resistance rk of the cell array for the post-failure parallel number nk is calculated based on k and the internal resistance r0 of the battery cell, and the differential voltage for the post-failure parallel number nk is calculated based on the combined internal resistance rk. The theoretical value ΔVk is calculated. Further, the failure determination means estimates the number of failures by comparing the theoretical value and the actual measurement value of the differential voltage in the failed cell array.

  That is, the theoretical value ΔVk of the differential voltage with respect to the post-failure parallel number n−k is compared with the actual measurement value ΔV, and for example, the theoretical value ΔVk that is closest to the actual measurement value ΔV is determined. The failure number k is estimated from the parallel number n−k. Since it did in this way, not only the presence or absence of a failure of a cell array but the number of battery cell failures in the failed cell array can be estimated.

  According to the invention described in claim 3, the differential voltage output means is configured to output a voltage obtained by amplifying the differential value with a predetermined amplification factor as the differential voltage. As a result, the differential voltage can be obtained as a larger value, and the failure of the cell array can be detected with high accuracy.

  According to the fourth aspect of the present invention, the first current and the second current are currents that flow through the secondary battery during discharging. Since it did in this way, a 1st electric current and a 2nd electric current can be set suitably according to the fluctuation | variation of the magnitude | size of the load connected to the secondary battery. Furthermore, by detecting a failure of the cell array at the time of discharging, if the cell array fails and the capacity of the entire secondary battery is reduced, it is determined that the remaining capacity has decreased, and the timing when charging is required is accurately determined. Can be determined.

It is a schematic block diagram which shows each failure detection apparatus in the failure detection system which concerns on embodiment of this invention. It is a schematic block diagram which shows the failure detection system provided with the failure detection apparatus of FIG. 1, and the secondary battery test | inspected by this failure detection system. It is a flowchart which shows an example of the failure detection process performed by CPU of the microcomputer with which a failure detection system is provided. It is a flowchart which shows an example of the differential voltage detection process performed by CPU of the microcomputer with which a failure detection apparatus is provided.

  Hereinafter, a failure detection system according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a schematic configuration of each failure detection apparatus in the failure detection system of the present embodiment. FIG. 2 is a schematic configuration diagram illustrating a failure detection system including a plurality of the failure detection apparatuses of FIG. 1 and a secondary battery inspected by the failure detection system. FIG. 3 is a flowchart illustrating an example of failure detection processing executed by the CPU of the microcomputer included in the failure detection system. FIG. 4 is a flowchart illustrating an example of the differential voltage detection process executed by the CPU of the microcomputer included in the failure detection apparatus.

  The failure detection system according to the present embodiment includes, for example, a plurality of failure detection devices that are mounted on an electric vehicle and are connected between both electrodes of a plurality of cell arrays that constitute a secondary battery included in the electric vehicle. Failure determination means for determining a failure, and detects a failure of the cell array. Of course, you may apply to the apparatus, system, etc. which were equipped with secondary batteries other than an electric vehicle.

  Such a secondary battery (indicated by symbol B in the figure) includes a plurality of cell arrays CA having a plurality of battery cells BC connected in parallel as shown in FIG. 2, and the plurality of cell arrays CA are connected in series. It is connected. A failure detection device 1 described later is provided for each cell array CA, and the failure detection device 1 is connected to the target cell array CA when a failure is detected. In addition, a charging / discharging unit (not shown) is connected between both electrodes of the secondary battery B, and when charging the secondary battery B, the secondary battery B is connected to a charging unit (not shown) so that a charging current flows. At the time of discharging, it is connected to a load (not shown) (for example, a motor for driving an electric vehicle or an electric heater for heating), and the load current flowing from the secondary battery B to the load is adjustable. It has been. Since the plurality of cell arrays CA are connected in series, the charging current or load current flowing through the secondary battery B is equal to the charging current or load current flowing through each cell array CA.

  As shown in FIG. 1, each battery cell BC included in the cell array CA has an electromotive force part e that generates an open circuit voltage OCV and an internal resistance r0. The cell array CA is a combined internal resistance that is a combined resistance of the internal resistance r0. It has a resistance r. The cell array CA generates a voltage V between both electrodes (positive electrode Bp and negative electrode Bn), and this voltage V is determined by the open circuit voltage OCV and the voltage Vr generated by the current flowing through the combined internal resistance r (V = OCV + Vr). When the failure detection apparatus 1 is connected to the cell array CA, the negative electrode Bn of the cell array CA is connected to the reference potential G.

  As shown in FIG. 2, the failure detection system (denoted by reference numeral 10 in the figure) of the present embodiment includes a plurality of failure detection devices 1 described later and a microcomputer 20 (hereinafter referred to as “μCOM 20”). The CPU of the μCOM 20 functions as a failure determination unit.

  Further, as shown in FIG. 1, the failure detection apparatus (indicated by reference numeral 1 in the figure) of this embodiment includes an amplifier 11, a changeover switch 12, a first capacitor 13 as a first voltage holding means, It has the 2nd capacitor | condenser 14 as 2 voltage holding means, the analog-digital converter 21, and the microcomputer 40 (henceforth "microcom 40"). Hereinafter, a configuration when the failure detection apparatus 1 is connected to the target cell array CA will be described.

  The amplifier 11 is composed of, for example, an operational amplifier, and includes two input terminals (first input terminal In1 and second input terminal In2) and one output terminal (output terminal Out). An amplified voltage Vm obtained by amplifying the difference value of the input voltage with a predetermined amplification factor Av is output from the output terminal. The amplifier 11 corresponds to a differential voltage output unit.

  The change-over switch 12 is, for example, a one-circuit two-contact (SPDT (single pole double throw)) switch constituted by an analog switch or the like. In the changeover switch 12, one of the two changeover terminals a and b is connected to the first input terminal In1 of the amplifier 11, and the other changeover terminal b is connected to the second input terminal In2 of the amplifier 11. It is connected. The changeover switch 12 has a common terminal c connected to the positive electrode Bp (one terminal of the cell array) of the cell array CA. The change-over switch 12 is connected to a later-described μCOM 40, and switches the connection between the two change-over terminals a and b and the common terminal c in accordance with a control signal from the μCOM 40, so that the positive electrode Bp of the cell array CA is a first input. It is exclusively connected to the terminal In1 and the second input terminal In2.

  The first capacitor 13 is connected between the first input terminal In1 of the amplifier 11 and the reference potential G. That is, the first capacitor 13 is connected between the first input terminal In1 and the negative electrode Bn of the cell array CA. Is provided. Thereby, the voltage between the first input terminal In1 and the negative electrode Bn of the cell array CA is held in the first capacitor 13.

  The second capacitor 14 is connected between the second input terminal In2 of the amplifier 11 and the reference potential G. That is, the second capacitor 14 is connected between the second input terminal In2 and the negative electrode Bn of the cell array CA. Is provided. Thereby, the voltage between the second input terminal In2 and the negative electrode Bn of the cell array CA is held in the second capacitor 14.

  The analog-digital converter 21 (hereinafter referred to as “ADC 21”) quantizes the amplified voltage Vm output from the amplifier 11 and outputs a signal indicating a digital value corresponding to the amplified voltage Vm. In the present embodiment, the ADC 21 is mounted as an individual electronic component. However, the ADC 21 is not limited to this. For example, each voltage is set using an analog-digital conversion unit built in the μCOM 40 described later. You may quantize.

  The μCOM 40 includes a CPU, a ROM, a RAM, and the like, and controls the entire failure detection apparatus 1. The ROM stores in advance a control program for causing the CPU to function as connection switching control means, and the CPU functions as connection switching means by executing this control program.

  The μCOM 40 includes an output port PO1 connected to the changeover switch 12. The CPU of the μCOM 40 transmits a control signal to the changeover switch 12 through the output port PO1, and when the first current I1 flows as a charging current or a load current to the cell array CA, the positive electrode Bp of the cell array CA and the first input terminal In1 are connected. The selector switch 12 is controlled so that the positive electrode Bp of the cell array CA and the second input terminal In2 are connected when the second current I2 flows as a charging current or a load current through the cell array CA.

  The μCOM 40 has an input port PI1 to which a signal output from the ADC 21 is input. The signal input to the input port PI1 is converted into information in a format that can be recognized by the CPU of the μCOM 40 and sent to the CPU. The CPU of the μCOM 40 detects the amplified voltage Vm based on the information.

  The μCOM 20 of the failure detection system 10 includes a CPU, a ROM, a RAM, and the like, and controls the entire failure detection system 10. In the ROM, a control program for causing the CPU to function as a failure determination unit is stored in advance, and the CPU controls the CPU of the μCOM 40, which is a subordinate CPU, by executing this control program, as will be described later. Further, by detecting a failure of the cell array CA based on the amplified voltage Vm in each cell array CA, it functions as a failure determination means.

  The μCOM 20 has a communication port (not shown). This communication port is connected to an in-vehicle network (for example, CAN (Controller Area Network)), and is connected to a display device such as a terminal device for vehicle maintenance through the in-vehicle network. The CPU of the μCOM 20 transmits a signal indicating whether or not the battery cell BC in the secondary battery B has failed to the display device through the communication port and the in-vehicle network, and whether or not the battery cell BC has failed in the display device based on the signal. Is displayed. Alternatively, the CPU of the μCOM 20 transmits a signal indicating the presence / absence of a failure of the battery cell BC to a display device such as a combination meter mounted on the vehicle through the communication port and the in-vehicle network. You may make it display the presence or absence of the failure of the cell BC. In addition, the signal which shows not only the presence or absence of a failure but the number of failures may be transmitted, and the number of failures may also be displayed.

  The μCOM 20 has a reception port (not shown). This receiving port is connected to an electronic control device mounted on the vehicle. The electronic control device indicates that the charging / discharging current flows through the secondary battery B at the same time as transmitting the control signal to the charging / discharging means so that the charging / discharging current flows by connecting the entire secondary battery B to the charging unit or the load. The signal is transmitted to μCOM 20 and μCOM 40.

  Next, an example of failure detection processing in the microcomputer included in the failure detection system described above will be described with reference to the flowchart of FIG.

  The CPU of the μCOM 20 (hereinafter simply referred to as “upper CPU”) receives a signal indicating that a load current flows from the electronic control unit to the secondary battery B when the vehicle starts running or accelerates, for example, as shown in FIG. Proceed to the failure detection process shown. The CPU of each μCOM 40 is hereinafter simply referred to as “lower CPU”.

  In the failure detection process, when the discharge of the secondary battery B is started, the upper CPU controls the lower CPU and executes the differential voltage detection process for each cell array CA (S110). The differential voltage detection process in each cell array CA may be performed substantially simultaneously or sequentially.

  In the differential voltage detection process, the lower CPU transmits a control signal for connecting the other switching terminal b and the common terminal c to the changeover switch 12 through the output port PO1 (S210). The changeover switch 12 connects the other changeover terminal b and the common terminal c in accordance with this control signal, thereby connecting the positive electrode Bp of the cell array CA and the second input terminal In2 of the amplifier 11. As a result, the second capacitor 14 is connected between the positive electrode Bp and the negative electrode Bn of the cell array CA, and charge flows from the cell array CA into the second capacitor 14.

  Next, the lower CPU waits until the second current I2 flows through the cell array CA (S220). Then, after a certain amount of time has passed, the second capacitor 14 holds the voltage between both electrodes of the cell array CA when the second current I2 flows. Note that the second current I2 may be measured or estimated from the size of the load. For example, a current measuring unit for measuring the load current is provided and the measurement result is input to the μCOM 40. The lower CPU may determine that the second current I2 has flowed, or the μCOM 40 stores in advance the relationship between the load magnitude and the load current, and when the load magnitude reaches a predetermined value, the second current The lower CPU may determine that I2 has flowed. The magnitude of the second current I2 may not be determined in advance. For example, the lower CPU determines that the load current that flows immediately after the start of discharge of the cell array CA or after a predetermined time has elapsed as the second current I2, and measures the current. The magnitude of this current may be measured by means.

  Next, when the second current I2 flows through the cell array CA and a predetermined time elapses, the lower CPU determines that the charge accumulation in the second capacitor 14 has been completed, and one side of the changeover switch 12 via the output port PO1. A control signal for connecting the switching terminal a and the common terminal c is transmitted (S230). The changeover switch 12 connects the positive electrode Bp of the cell array CA and the first input terminal In1 of the amplifier 11 by connecting one switching terminal a and the common terminal c in accordance with a control signal from the lower CPU. As a result, the first capacitor 13 is connected between the positive electrode Bp and the negative electrode Bn of the cell array CA, and charge flows from the cell array CA into the first capacitor 13.

  Next, the lower CPU waits until a first current I1 having a magnitude different from that of the second current I2 flows through the cell array CA (S240). When a certain amount of time elapses after the first current I1 flows, the first capacitor 13 holds the voltage between both electrodes of the cell array CA when the first current I1 flows. The first current I1 may be measured or estimated from the size of the load in substantially the same manner as the second current I2. Further, the magnitude of the first current I1 may not be determined in advance, and the magnitude of the differential current from the second current I2 may be determined in advance.

  Next, the lower CPU detects the amplified voltage Vm output from the amplifier 11 based on information obtained from the signal input to the input port PI1 (S250).

  Next, the lower CPU divides the detected amplified voltage Vm by the amplification factor Av of the amplifier 11 to thereby obtain a differential voltage between the voltage V1 across the first capacitor 13 and the voltage V2 across the second capacitor 14. ΔV (= V1−V2) is calculated (S260), information on the difference voltage ΔV is transmitted to the μCOM 20, and the difference voltage detection process is terminated.

  When the differential voltage detection processing in each cell array CA is completed as described above, the upper CPU determines a group of normal cell arrays CA and a failed cell array CA based on the differential voltages ΔV in the plurality of cell arrays CA ( S120). That is, among the plurality of cell arrays CA, a group in which the differential voltage ΔV is a value within a predetermined range is determined as a normal cell array CA, and a cell having a difference in the differential voltage ΔV from the normal cell array CA greater than a predetermined value is failed. The cell array CA is determined. Note that a cell array CA having a failure history in the past is previously excluded from the group of normal cell arrays CA.

  Next, the host CPU determines the failure number k of the battery cells BC in the failed cell array CA based on the difference voltage ΔV of the normal cell array CA, the difference voltage ΔV of the failed cell array, and the parallel number n of the battery cells BC. (K = 0 to n-1) is estimated (S130), and the failure detection process is terminated. That is, the internal resistance r0 of one battery cell BC is calculated based on the differential voltage ΔV of the normal cell array CA and the parallel number n of the battery cells BC, and the post-failure parallel is obtained by subtracting the failure number k from the parallel number n. The combined internal resistance rk of the cell array is calculated for the post-failure parallel number nk based on the number nk and the battery cell internal resistance r0, and the post-failure parallel number nk is calculated based on the combined internal resistance rk. The theoretical value ΔVk of the differential voltage with respect to is calculated. Further, the theoretical value ΔVk of the differential voltage with respect to the post-failure parallel number n−k is compared with the actually measured value ΔV, for example, the theoretical value ΔVk that is closest to the actually measured value ΔV is determined, and after the failure that becomes the theoretical value ΔVk The failure number k is estimated from the parallel number n−k. And after completion | finish of a failure detection process, a high-order CPU transmits the signal which shows the presence or absence of the failure of the battery cell BC, and the failure number k to another apparatus etc. through a communication port.

  The upper CPU that executes the processes of steps S120 and S130 in the flowchart of FIG. 3 corresponds to the failure determination means, and the lower CPU that executes the processes of steps S210 and S230 in the flowchart of FIG. 4 corresponds to the connection switching control means. .

  The details of the failure determination process will be described more specifically. For example, 100 cell arrays CA are connected in series to form a secondary battery B. In each cell array CA, the parallel number n of battery cells BC is 33, the first current I1 is 100A, Consider the case where the two currents I2 are 1A.

  It is assumed that there are 99 cell array CAs in which the differential voltage ΔV calculated in step S260 is within 60.00 ± 0.50 mV, and the differential voltage ΔV of the remaining one cell array CA is 61.90 mV. In step S120, the upper CPU determines that the 99 sets of cell arrays CA are a group of normal cell arrays CA, and determines that one set of cell arrays CA is a failed cell array CA. Note that the range of the differential voltage ΔV for determining a group of normal cell arrays CA may be set as appropriate, and the median value may be an average value in a normal group, for example. Further, for example, assuming a failed cell array CA based on the difference from the average value of the differential voltage ΔV in the entire cell array CA, recalculating the average value in the normal population and re-determining the failure of the cell array CA is repeated. What is necessary is just to determine the cell array CA which has failed and to obtain the average value of the differential voltage ΔV in a normal group. In addition, the range of the differential voltage ΔV for determining a group of normal cell arrays CA may be set according to the ambient temperature, the total usage time of the secondary battery B, and the like. In addition, it is possible to cope with an increase in the internal resistance of the battery cell BC due to a temperature rise or a decrease due to deterioration, and the determination system can be further improved.

  When the median value of the range of the differential voltage ΔV in the group of normal cell arrays CA is 60.00 mV, in step S130, the upper CPU uses the differential voltage ΔV as the difference value between the first current I1 and the second current I2. The combined internal resistance r is calculated to be 0.6061 mΩ, and the parallel number 33 is multiplied to calculate that the internal resistance r0 of the battery cell BC is 20.00 mΩ. Further, the host CPU calculates that the combined internal resistance r1 of the cell array for the post-failure parallel number 32 is 0.6250 mΩ based on the post-failure parallel number 32 and the internal resistance r0 of the battery cell. Based on the resistance r1, it is calculated that the theoretical value ΔV1 of the differential voltage for the post-failure parallel number 32 is 61.88 mV. Similarly, when the post-failure parallel number nk is 31 or less, the theoretical value Vk of the differential voltage of the failed cell array CA is calculated. The theoretical value ΔVk may be calculated for all the post-failure parallel numbers nk, or may be calculated by determining the lower limit of the post-failure parallel numbers nk.

  In step S130, the upper CPU compares the measured value ΔV of the differential voltage of the failed cell array CA with the theoretical value ΔVk of the differential voltage with respect to the post-failure parallel number n−k, and is closest to the measured value ΔV among the theoretical values ΔVk. The thing is judged and the number of failures k is estimated. Since the measured value ΔV of the differential voltage of the failed cell array CA is 61.90 mV, the closest theoretical value ΔVk is 61.88 mV when the number of parallels after failure nk is 32, and the number of failures k is 1. It is estimated that

  According to this embodiment, there are the following effects. That is, by obtaining the differential voltage ΔV from the amplified voltage Vm amplified by the amplifier 11, the differential voltage ΔV can be obtained with high accuracy. Based on this differential voltage ΔV, a normal cell array CA and a failed cell array CA are obtained. By determining, even if the change in the differential voltage ΔV due to the failure of the cell array CA is small, the failure can be detected with high accuracy.

  Further, the theoretical value ΔVk of the differential voltage with respect to the parallel number n−k after the failure and the actually measured value ΔV are compared to estimate the number of failures k, so that not only the presence / absence of the failure of the cell array CA but also the battery cells in the cell array CA The number of BC failures k can also be accurately estimated.

  Further, by detecting a failure of the battery cell BC based on the first current I1 and the second current I2 that are load currents at the time of discharging the secondary battery B, the magnitude of the load connected to the secondary battery B can be increased. The first current I1 and the second current I2 can be appropriately set according to the fluctuation. Further, by accurately detecting the failure of the battery cell BC at the time of discharging, when the battery cell BC fails and the capacity of the secondary battery B is reduced, it is determined that the remaining capacity has decreased, and charging is performed. Can accurately determine the necessary timing.

  In addition, this invention is not limited to the said embodiment, Including other structures etc. which can achieve the objective of this invention, the deformation | transformation etc. which are shown below are also contained in this invention.

  For example, in the above-described embodiment, the upper CPU calculates the theoretical value ΔVk of the differential voltage with respect to the post-failure parallel number n−k, and estimates the failure number k of the battery cell BC. Alternatively, it may be possible to detect only the presence or absence of a cell array failure without estimating the number of failures.

  In the embodiment, the failure number k is estimated from the theoretical value ΔVk of the differential voltage that is closest to the actual measurement value ΔV, that is, the average of two theoretical values ΔVk that differ by 1 in the post-failure parallel number n−k. Although the number of failures k is estimated using the value as a boundary, this boundary may be determined based on, for example, a non-linear function representing the relationship between the post-failure parallel number n−k and the theoretical value ΔVk.

  In the embodiment, the differential voltage ΔV is measured based on the first current I1 and the second current I2, which are load currents, and the failure of the battery cell BC is detected. The current flowing through the secondary battery during charging may be used, or the current during discharging and the current during charging may be combined.

  In the embodiment, the CPU of the μCOM 20 provided separately from the μCOM 40 of each failure detection device 1 functions as a failure determination unit. However, the μCOM 20 is omitted and one of the CPUs of the μCOM 40 is representative. Then, failure detection processing may be executed to function as failure determination means.

  In addition, the best configuration, method and the like for carrying out the present invention have been disclosed in the above description, but the present invention is not limited to this. That is, the invention has been illustrated and described primarily with respect to particular embodiments, but may be configured for the above-described embodiments without departing from the scope and spirit of the invention. Various modifications can be made by those skilled in the art in terms of materials, quantity, and other detailed configurations. Therefore, the description limiting the shape, material, etc. disclosed above is an example for easy understanding of the present invention, and does not limit the present invention. The description by the name of the member which remove | excluded the limitation of one part or all of such is included in this invention.

DESCRIPTION OF SYMBOLS 10 Failure detection system 1 Failure detection apparatus 11 Amplifier (differential voltage output means)
12 switch 13 first capacitor (first voltage holding means)
14 Second capacitor (second voltage holding means)
40 Microcomputer (connection switching control means)
20 Microcomputer (Failure judgment means)
CA cell array

Claims (4)

A failure detection system comprising a plurality of failure detection devices provided corresponding to each of a plurality of cell arrays connected in series, and failure determination means for detecting a failure in the cell array,
The failure detection device has a first input terminal and a second input terminal, and outputs a differential voltage corresponding to a difference value between voltages input to the first input terminal and the second input terminal. A voltage between an output means, a changeover switch that exclusively connects one electrode of the cell array to the first input terminal and the second input terminal, and a voltage between the first input terminal and the other electrode of the cell array; A first voltage holding means capable of holding; a second voltage holding means capable of holding a voltage between the second input terminal and the other electrode of the cell array; and a cell array when a first current flows through the cell array. One electrode of the cell array is connected to the first input terminal, and when a second current having a magnitude different from that of the first current flows through the cell array, one electrode of the cell array is connected to the second input terminal. As above Comprising a switching control means for controlling the changeover switch, and
In each of the plurality of cell arrays, the failure determination unit includes a voltage between the electrodes and the second current when the first current output by the differential voltage output unit of each of the plurality of failure detection devices flows. fault on the basis of the differential voltage corresponding to the difference value, characterized by the Turkey be determined in a cell array failed each of the plurality of cell arrays and normal cell array and a voltage between the two electrodes when the flow Detection system. The cell array has a plurality of battery cells connected in parallel to each other;
The battery in the failed cell array is based on the differential voltage of the normal cell array, the differential voltage of the failed cell array, and the parallel number of the battery cells in a set of cell arrays. The failure detection system according to claim 1, wherein the number of cell failures is estimated.   The failure detection system according to claim 1, wherein the differential voltage output unit is configured to output a voltage obtained by amplifying the difference value with a predetermined amplification factor as the differential voltage.   The failure detection system according to claim 1, wherein the first current and the second current are currents that flow through the cell array during discharge.

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