JP6276720B2 - ESD protection circuit - Google Patents

Description

  Embodiments described herein relate generally to an electrostatic breakdown prevention circuit.

  The electrostatic breakdown of a semiconductor device occurs when a discharge current flows in the device due to electrostatic discharge (ESD) and local electric field concentration occurs. Therefore, an electrostatic breakdown preventing circuit that prevents local electric field concentration from occurring in the internal circuit due to ESD is incorporated in the semiconductor device.

  There are HBM (Human Body Model: human body model), MM (Machine Model: machine model), and CDM (Charged Device Model: device charging model) as discharge models in the ESD test of the electrostatic breakdown prevention circuit.

  Advances in automation of equipment assembly processes reduce the chances of human touching semiconductor devices, while semiconductor devices charged by friction and electrostatic induction come into contact with metals in automatic assembly equipment. Therefore, in recent years, ESD failures due to CDM tend to increase more than HBM. This CDM discharge waveform is characterized by a very short discharge time and a pulse width of 1 ns or less as compared with HBM.

  Conventionally, as a countermeasure against electrostatic breakdown with respect to CDM of the input terminal, a second MOS transistor is connected in series between the first MOS transistor connected to the input terminal and the reference potential terminal, and a steep surge is applied to the input terminal. During the current flow, the second MOS transistor is turned off, and the source terminal of the first MOS transistor is disconnected from the reference potential end. This prevents a high potential from being applied between the source and gate.

  In this case, in order to control the conduction of the second MOS transistor, it is necessary to detect a sudden surge current flowing into the input terminal. For this reason, a circuit composed of a resistor and a capacitor is conventionally used. However, the formation of the resistor and the capacitor requires a large area, which causes a problem that the chip area of the semiconductor device increases.

JP 2009-81307 A

  The problem to be solved by the present invention is to provide an electrostatic breakdown prevention circuit capable of protecting an input circuit from ESD of CDM while suppressing an increase in chip area.

The electrostatic breakdown preventing circuit according to the embodiment includes a power supply potential end, a reference potential end, an input terminal to which an external signal is input, a first diode, a second diode, a PMOS transistor, and a first NMOS. A transistor; a second NMOS transistor; a first CMOS inverter; a second CMOS inverter; and a third CMOS inverter. The first diode is connected in the forward direction from the input terminal toward the power supply potential end. The second diode is connected in the reverse direction from the input terminal toward the reference potential end. The PMOS transistor has a gate terminal connected to the input terminal via a protective resistor, a source terminal connected to the power supply potential end, and a drain terminal connected to the output end. The first NMOS transistor has a gate terminal connected to the input terminal via the protective resistor, and a drain terminal connected to the output terminal. The second NMOS transistor has a drain terminal connected to the source terminal of the first NMOS transistor and a source terminal connected to the reference potential terminal. The first CMOS type inverter has an input terminal connected to the reference potential terminal. The second CMOS inverter has an input terminal connected to an output terminal of the first CMOS inverter. The third CMOS inverter has an input terminal connected to the output terminal of the second CMOS inverter, an output terminal connected to the gate terminal of the second NMOS transistor, the output terminal, the power supply potential terminal, A plurality of PMOS transistors are connected in series, and the potential at the output terminal of the third CMOS inverter remains at a low level during a period in which a surge is applied to the input terminal. The number of the plurality of PMOS transistors of the third CMOS inverter is adjusted.

The circuit diagram which shows the example of a structure of the electrostatic breakdown prevention circuit of 1st Embodiment. The wave form diagram which shows the example of operation | movement of the electrostatic breakdown prevention circuit of 1st Embodiment. The figure which shows the example of the CDM countermeasure effect of the electrostatic breakdown prevention circuit of 1st Embodiment. The circuit diagram which shows the example of a structure of the principal part of the electrostatic breakdown prevention circuit of 2nd Embodiment. The circuit diagram which shows the example of a structure of the inverter used with the electrostatic breakdown prevention circuit of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
FIG. 1 is a circuit diagram showing an example of the configuration of the electrostatic breakdown preventing circuit of the first embodiment.

  The electrostatic breakdown prevention circuit of this embodiment is connected in the forward direction from the power supply potential terminal VDD, the reference potential terminal VSS, the input terminal PAD to which an external signal is input, and the input terminal PAD toward the power supply potential terminal VDD. The diode D1, the diode D2 connected in the reverse direction from the input terminal PAD to the reference potential terminal VSS, the gate terminal is connected to the input terminal PAD via the protective resistor R1, and the source terminal is connected to the power supply potential terminal VDD. A PMOS transistor P1 having a drain terminal connected to the output terminal OUT, an NMOS transistor N1 having a gate terminal connected to the input terminal PAD via the protective resistor R1, and a drain terminal connected to the output terminal OUT; NMO whose terminal is connected to the source terminal of the NMOS transistor N1 and whose source terminal is connected to the reference potential terminal VSS The transistor N2, the CMOS inverter IV1 whose input terminal I1 is connected to the reference potential terminal VSS, the CMOS inverter IV2 whose input terminal I2 is connected to the output terminal O1 of the CMOS inverter IV1, and the input terminal I3 are CMOS type A CMOS type inverter IV3 connected to the output terminal O2 of the inverter IV2 and having the output terminal O3 connected to the gate terminal of the NMOS transistor N2.

  Here, the CMOS inverter IV3 has a plurality of PMOS transistors connected in series between the output terminal O3 and the power supply potential terminal VDD. In the present embodiment, an example is shown in which four PMOS transistors P31, P32, P33 and P34 are connected in series. By connecting a plurality of PMOS transistors in series, the rise of the output of the CMOS inverter IV3 becomes gentle, and the propagation delay time at the rise of the output increases.

  The number of PMOS transistors is not limited to four. In the present embodiment, the number of PMOS transistors is adjusted so that the propagation delay time of the total three stages of the CMOS type inverters IV1 to IV3 becomes longer than the CDM surge application period to the input terminal PAD.

  An NMOS transistor N31 is connected between the output terminal O3 of the CMOS inverter IV3 and the reference potential terminal VSS.

  In the present embodiment, the CMOS inverter IV2 has a plurality of NMOS transistors connected in series between the output terminal O2 and the reference potential terminal VSS. FIG. 1 shows an example in which two NMOS transistors N21 and N22 are connected in series. By connecting a plurality of NMOS transistors in series, the fall of the output signal of the CMOS inverter IV2 becomes gentle, and the propagation delay time at the fall of the output increases.

  The number of NMOS transistors is not limited to two. By adjusting the number of NMOS transistors, the total propagation delay time of the CMOS inverters IV1 to IV3 can be set to a desired value.

  A PMOS transistor P21 is connected between the output terminal O2 of the CMOS inverter IV2 and the power supply potential terminal VDD.

  In the present embodiment, the CMOS inverter IV1 is connected between the high-breakdown-voltage type PMOS transistor P11 connected between the output terminal O1 and the power supply potential terminal VDD, and between the output terminal O1 and the reference potential terminal VSS. And a high breakdown voltage type NMOS transistor N11.

  The reason why the high voltage MOS transistor is used is that the reference potential terminal VSS connected to the gate terminal is connected to the external terminal, so that a high voltage surge input may be applied to the gate terminal. By adopting the high breakdown voltage type, the electrostatic breakdown voltage of the gate oxide film of the MOS transistor can be improved.

  Next, with reference to FIG. 2, the operation of the electrostatic breakdown preventing circuit of the present embodiment during the CDM test for the input terminal PAD will be described.

  As shown in FIG. 2A, during the CDM test, a pulsed high voltage waveform (CDM waveform) is input to the input terminal PAD during a surge application period T of about 1 ns.

  Due to the input of the CDM waveform, a current flows through the diode D1 to the open power supply potential VDD during the CDM test, and the potential of the power supply potential VDD rises as shown in FIG. 2B.

  When the potential at the power supply potential VDD rises, the CMOS inverters IV1 to IV3 are in an operating state. At this time, the potential of the reference potential terminal VSS is lower than the potential of the power supply potential terminal VDD.

  Therefore, as shown in FIG. 2C, the potential at the output terminal O1 of the CMOS inverter IV1 changes to a high level.

  In response to a change in the level of the output terminal O1 of the CMOS inverter IV1, the potential of the output terminal O2 of the CMOS inverter IV2 changes from a high level to a low level as shown in FIG. At this time, since the CMOS inverter IV2 has two NMOS transistors (N21, N22) connected in series, it takes time for the output to fall.

In response to the fall of the output of the CMOS inverter IV2, the potential at the output terminal O3 of the CMOS inverter IV3 changes from a low level to a high level as shown in FIG. At this time, since the CMOS inverter IV3 is four P MOS transistor (P31 to P34) are connected in series, it takes time to rise of output. That is, the propagation delay time of the CMOS inverter IV3 at the output rising time is long.

  As described above, in this embodiment, the total three-stage propagation delay time D of the CMOS inverters IV1 to IV3 is designed to be longer than the surge application period T for the input terminal PAD.

  For this reason, during the period when the CDM wave is applied to the input terminal PAD, the potential of the output terminal O3 of the CMOS inverter IV3 remains at a low level. Therefore, during this period, the gate terminal of the NMOS transistor N2 is at a low level, and the NMOS transistor N2 is in an off state.

  Therefore, the source terminal of the NMOS transistor N2 and the reference potential terminal VSS are not conductive, and the source terminal of the NMOS transistor N1 does not become the reference potential (for example, the ground potential).

  This prevents the gate-source voltage Vgs of the NMOS transistor N1 from becoming a high voltage while the CDM wave is applied to the input terminal PAD.

  FIG. 3 shows how the gate-source voltage Vgs of the NMOS transistor N1 changes during the period when the CDM wave is applied to the input terminal PAD.

  The circuit of this embodiment can significantly reduce the peak of the gate-source voltage Vgs of the NMOS transistor N1 as compared with the case where no CDM countermeasure is taken.

  According to the present embodiment as described above, since the circuit is configured only by the CMOS type inverter, the gate-source voltage of the NMOS transistor N1 is applied during the period when the CDM wave is applied to the input terminal PAD without increasing the chip area. The peak of Vgs can be greatly reduced. Thereby, electrostatic breakdown of the gate oxide film of the NMOS transistor N1 can be prevented.

(Second Embodiment)
With the progress of miniaturization of the semiconductor device manufacturing process, the operation speed of the semiconductor device is improved and the propagation delay time per inverter stage tends to be reduced. Therefore, it is conceivable that sufficient delay time cannot be obtained with the three-stage inverter configuration shown in the first embodiment. Therefore, in the present embodiment, an example of a circuit configuration capable of obtaining a desired delay time even when the propagation delay time per inverter stage is small is shown.

  FIG. 3 is a circuit diagram illustrating an example of a configuration of a main part of the electrostatic breakdown preventing circuit according to the second embodiment. Here, only the delay circuit portion constituted by the inverter is shown. Other circuit configurations are the same as those of the first embodiment shown in FIG.

  In the present embodiment, an even number (2n) of inverters IV are cascaded between the output terminal O1 of the CMOS inverter IV1 and the input terminal I2 of the CMOS inverter IV2.

  As shown in FIG. 4, the inverter IV has a configuration in which a PMOS transistor P100 and an NMOS transistor N100 are connected in series between a power supply potential terminal VDD and a reference potential terminal VSS.

  If the propagation delay time per stage of the inverter IV is d, 2n · d delay time is added between the CMOS inverter IV1 and the CMOS inverter IV2 by cascading 2n inverters IV. Can do.

  Therefore, by adjusting the number of inverters IV, the delay time from the application of the CDM wave to the input terminal PAD until the rise of the output of the CMOS inverter IV3 can be set to a desired value.

  According to the present embodiment as described above, even if the propagation delay time per inverter stage is small, the NMOS transistor N2 is turned off during the period when the CDM wave is applied to the input terminal PAD in the configuration of only the inverter. be able to.

  According to the electrostatic breakdown prevention circuit of at least one embodiment described above, the input circuit can be protected from CDM ESD while suppressing an increase in chip area.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

P1, P11, P21, P31 to P34, P100 PMOS transistors N1, N11, N21 to N22, N31, N100 NMOS transistors D1, D2 Diodes IV1, IV2, IV3, IV Inverter R1 Protection resistor PAD Input terminal VDD Power supply potential terminal VSS Reference Potential end

Claims (4)

Power supply potential end,
A reference potential end;
An input terminal to which an external signal is input;
A first diode connected in a forward direction from the input terminal toward the power supply potential end;
A second diode connected in a reverse direction from the input terminal toward the reference potential end;
A PMOS transistor having a gate terminal connected to the input terminal via a protective resistor, a source terminal connected to the power supply potential end, and a drain terminal connected to the output end;
A first NMOS transistor having a gate terminal connected to the input terminal via the protective resistor and a drain terminal connected to the output end;
A second NMOS transistor having a drain terminal connected to the source terminal of the first NMOS transistor and a source terminal connected to the reference potential end;
A first CMOS type inverter having an input terminal connected to the reference potential terminal;
A second CMOS inverter whose input is connected to the output of the first CMOS inverter;
A third CMOS inverter having an input terminal connected to the output terminal of the second CMOS type inverter and an output terminal connected to a gate terminal of the second NMOS transistor;
In the third CMOS inverter, a plurality of PMOS transistors are connected in series between the output terminal and the power supply potential terminal .
The number of the plurality of PMOS transistors of the third CMOS type inverter is set so that the potential at the output terminal of the third CMOS type inverter remains at a low level during a period in which a surge is applied to the input terminal. An electrostatic breakdown prevention circuit characterized by adjusting . The electrostatic breakdown prevention circuit according to claim 1, wherein the second CMOS inverter includes a plurality of NMOS transistors connected in series between the output terminal and the reference potential terminal. 3. The electrostatic breakdown preventing circuit according to claim 1, wherein the first CMOS type inverter includes a high breakdown voltage type PMOS transistor and a high breakdown voltage type NMOS transistor. 4. 4. An even number of inverters are further cascaded between the output terminal of the first CMOS type inverter and the input terminal of the second CMOS type inverter. The electrostatic breakdown prevention circuit according to any one of the preceding claims.