TWI658668B - Esd protection cirtcuit - Google Patents

Esd protection cirtcuit Download PDF

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Publication number
TWI658668B
TWI658668B TW107123467A TW107123467A TWI658668B TW I658668 B TWI658668 B TW I658668B TW 107123467 A TW107123467 A TW 107123467A TW 107123467 A TW107123467 A TW 107123467A TW I658668 B TWI658668 B TW I658668B
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TW
Taiwan
Prior art keywords
nmos transistor
gate
transistor
electrostatic discharge
node
Prior art date
Application number
TW107123467A
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Chinese (zh)
Other versions
TW202007042A (en
Inventor
黃紹璋
陳立凡
林志軒
王裕凱
陳宏維
王靖雯
林庭佑
陳俊智
Original Assignee
世界先進積體電路股份有限公司
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Priority to TW107123467A priority Critical patent/TWI658668B/en
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Publication of TWI658668B publication Critical patent/TWI658668B/en
Publication of TW202007042A publication Critical patent/TW202007042A/en

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Abstract

The invention provides an electrostatic discharge protection circuit for protecting a standard NMOS transistor coupled between an I / O (input / output) bonding pad and a ground. The NMOS transistor includes a first discharge device provided in the I Between the / O bonding pad and the ground, there is a trigger turn-on voltage lower than the breakdown voltage of the NMOS transistor; a discharge NMOS transistor is coupled between the ground and the gate of the target NMOS transistor; a first PMOS transistor The crystal connects the gate of the target NMOS transistor with a connection node; and a first NMOS transistor connects the connection node with the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Description

ESD protection circuit

The invention relates to an electrostatic discharge protection circuit. In particular, a gate voltage control device is used to ground the gate of a standard NMOS transistor to ensure that the NMOS transistor is turned off when an electrostatic discharge event occurs.

With the development of semiconductor process technology, a bipolar transistor, a complementary CMOS transistor, and a diffused DMOS transistor are integrated into a power element In the above-mentioned BCD process, in order to save the area of the electrostatic discharge protection circuit, a PNP or NPN bipolar transistor is usually used as an electrostatic discharge protection element, and the triggering on-voltage of the electrostatic discharge protection circuit ( The trigger-on voltage is lower than the breakdown voltage of the protected component, such as a Lateral Double-Diffused NMOS transistor.

However, when an electrostatic discharge event occurs, the gate voltage of the protected component (such as an LDNMOS transistor) is affected by the electrostatic discharge instead of 0V. When an electrostatic discharge voltage is coupled to the gate of the LDNMOS transistor, the LDNMOS transistor is turned on, so that an electrostatic discharge current directly flows through the LDNMOS transistor, and directly damages the LDNMOS transistor. In the above state, no matter how low the trigger on-voltage of the electrostatic protection circuit is, Protect the turned-on LDNMOS transistor.

In view of this, the present invention discloses an electrostatic discharge protection circuit. When an electrostatic discharge event occurs, the gate of a target NMOS transistor is grounded through a gate voltage control device to ensure that the target NMOS transistor is turned off.

An electrostatic discharge protection circuit according to an embodiment of the present invention is used to protect a standard NMOS transistor coupled between an I / O (input / output) bonding pad and a ground, and includes: a first discharge device; Between the I / O bonding pad and the ground, a triggering turn-on voltage lower than the breakdown voltage of the NOMS transistor; and a gate voltage control device, including: a discharge NMOS transistor, coupled between the ground and the ground A gate of the target NMOS transistor; a first PMOS transistor connected to the gate of the target NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other. When an electrostatic discharge event occurs and an electrostatic discharge voltage is coupled to the gate of the target NMOS transistor, the first PMOS transistor is turned on, so that the electrostatic discharge voltage turns on the discharge NMOS transistor and the gate of the NMOS transistor Ground to ensure that the NMOS transistor is off.

The electrostatic discharge protection circuit described above further includes a trace-high circuit, which includes: a second PMOS transistor connected to a power node and a first output node TH; and a third PMOS circuit A crystal, connected to the gate of the target NMOS transistor and the first output node. Where, the The first output node is coupled to the base electrode of the first PMOS transistor; the gate of the second PMOS transistor is connected to the gate of the target NMOS transistor, and the gate of the third PMOS transistor is connected to the power node.

The electrostatic discharge protection circuit described above further includes a voltage clamping device, at least including a resistor having a first terminal and a second terminal, the first terminal of the resistor is connected to the power node, and the second terminal of the resistor is coupled Connected to the gate of the first PMOS transistor; and a capacitor having a first end and a second end, the first end of the capacitor is directly connected to the second end of the resistor, and the second end of the capacitor is connected to the ground.

The electrostatic discharge protection circuit described above further includes a buffer device formed by an even number of buffers connected in series; wherein the input terminal of the buffer device is connected to the second terminal of the resistor, and the output terminal of the buffer device is connected to the buffer device. Gates of first PMOS and first NMOS transistors. The power input terminal of each buffer in the buffer device is coupled to the first output node of the traceback circuit.

The electrostatic discharge protection circuit described above further includes a transmission gate including a second NMOS transistor connected to a signal node and a second output node; a fourth PMOS transistor connected to the signal A node and the second output node; and an inverter having an input terminal and an output terminal. The second output node is coupled to the gate of the target NMOS transistor; the base of the second NMOS transistor is connected to ground; the base of the fourth PMOS transistor is connected to the power node; the second NMOS transistor The gate of is connected to the input terminal of the inverter, and the gate of the fourth PMOS transistor is connected to the output terminal of the inverter.

100‧‧‧ Electrostatic discharge protection circuit

102‧‧‧I / O bonding pad

104‧‧‧First discharge device

106‧‧‧standard NMOS transistor

108‧‧‧Gate voltage control device

110‧‧‧discharge NMOS transistor

112‧‧‧The first PMOS transistor

114‧‧‧The first NMOS transistor

D1, D2‧‧‧ diodes

G0‧‧‧ Gate of NMOS transistor 106

G1‧‧‧ Gate of discharge NMOS transistor 110

G3‧‧‧Gate of the first PMOS transistor 112

TH‧‧‧First output node

C‧‧‧ connected node

200‧‧‧ Traceback Circuit

202‧‧‧Second PMOS transistor

204‧‧‧Third PMOS transistor

Pr‧‧‧ Power Node

300‧‧‧Voltage clamping device

302 (R1) ‧‧‧Resistor

304 (C1) ‧‧‧Capacitor

306‧‧‧Fifth PMOS transistor

308‧‧‧Third NMOS transistor

310‧‧‧Fourth NMOS transistor

C2‧‧‧Second connection node

D3‧‧‧ Diode

G2‧‧‧node

400‧‧‧ buffer device

402, 404‧‧‧Buffer

500‧‧‧Transmission gate

502‧‧‧Second NMOS transistor

504‧‧‧Fourth PMOS transistor

506‧‧‧ Inverter

S‧‧‧Signal Node

C3‧‧‧ third output node

FIG. 1 is a schematic diagram of an electrostatic discharge protection circuit of the disclosed embodiment; FIG. 2 is a schematic diagram of a trace-high circuit of the electrostatic discharge protection circuit of the disclosed embodiment; and FIG. 3 is an electrostatic discharge protection of the disclosed embodiment A schematic diagram of a voltage clamping device of the circuit; FIG. 4 is a schematic diagram of a buffer device of the electrostatic discharge protection circuit of the embodiment of the disclosure; and FIG. 5 is a schematic diagram of a transmission gate of the electrostatic discharge protection circuit of the embodiment of the disclosure.

FIG. 1 is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the disclosure. As shown in FIG. 1, the electrostatic discharge protection circuit 100 is used to protect a standard NMOS transistor 106 coupled between the I / O bonding pad 102 and a ground. The electrostatic discharge protection circuit 100 includes: the I / O (input / output) bonding pad 102, a first discharge device 104, and a gate voltage control device 108. The gate voltage control device 108 includes a discharge NMOS transistor 110, a first PMOS transistor 112, and a first NMOS transistor 114. Diode D1 is a parasitic diode between the source and the drain of the target NMOS transistor. The first discharge device 104 is disposed between the I / O bonding pad 102 and the ground, and includes a diode D2, where the diode D2 has a triggering turn-on voltage lower than a breakdown voltage of a standard NMOS transistor 106. (trigger-on voltage). When an electrostatic discharge event occurs, static electricity enters the electrostatic discharge protection circuit 100 from the I / O bonding pad 102. If the target NMOS transistor 106 is completely closed, the static electricity It will pass through the first discharge device 104 as a discharge path, so the electrostatic discharge current will not flow through the target NMOS transistor 106. Therefore, the present invention uses the gate voltage control device 108 to ensure that the target NMOS transistor 106 is completely closed during the electrostatic discharge process.

In the gate voltage control device 108, the discharge NMOS transistor 110 is coupled to the ground and the gate of the target NMOS transistor 106 (labeled G0). The first PMOS transistor 112 is coupled to the gate G0 of the target NMOS transistor 106 and a connection node C; and the first NMOS transistor 114 is connected to the connection node C and the ground. The connection node C is connected to the gate of the discharge NMOS transistor 110 (labeled as G1), and the gates of the first PMOS transistor 112 and the gate of the first NMOS transistor 114 are connected to each other (labeled G3). When an electrostatic discharge event occurs and the electrostatic discharge voltage is coupled to the gate (G0) of the target NMOS transistor 106, the first PMOS transistor 112 is turned on, the first NMOS transistor 114 is turned off, and the target NMOS transistor is turned off. The electrostatic discharge voltage coupled to the gate (G0) of the crystal 106 is conducted to the connection node C via the first PMOS transistor 112, and the voltage of the gate (G1) of the discharge NMOS transistor 110 is At a high level, the discharge NMOS transistor 110 is thus turned on, and then the gate (G0) of the target NMOS transistor 106 is grounded, so as to ensure that the target NMOS transistor 106 is closed, and an electrostatic discharge current is prevented from flowing through the target NMOS transistor 106.

FIG. 2 is a schematic diagram of a trace-high circuit according to an embodiment of the disclosure. The electrostatic discharge protection circuit 100 of the embodiment of the present disclosure may further include a traceback circuit 200 as shown in FIG. 2. The traceability circuit 200 includes a second PMOS transistor 202 and a third PMOS transistor 204. The second PMOS The transistor 202 is connected to a power node Pr and a first output node TH; and the third PMOS transistor 204 is connected to the gate (G0) of the target NMOS transistor 106 and the first output node TH. The first output node TH is coupled to the body of the first PMOS transistor 112; the gate of the second PMOS transistor 202 is connected to the gate of the target NMOS transistor 106, and the third PMOS transistor The gate of the crystal 204 is connected to the power node Pr. When an electrostatic discharge event occurs, if the (electrostatic discharge) voltage of the power node Pr coupling is greater than the (electrostatic discharge) voltage of the gate (G0) of the target NMOS transistor 106, the second PMOS voltage of the traceback circuit 200 The crystal 202 is turned on to transmit the voltage of the power node Pr to the first output node TH. If the voltage of the power node Pr is less than the voltage of the gate (G0) of the target NMOS transistor 106, the The third PMOS transistor 204 is turned on to transmit the voltage of the gate (G0) of the target NMOS transistor 106 to the first output node TH. By coupling the first output node TH to the base electrode of the first PMOS transistor 112, the first PMOS transistor 112 can be prevented from being affected by the body effect during an electrostatic discharge event.

FIG. 3 is a schematic diagram of a voltage clamping device according to an embodiment of the disclosure. As shown in FIG. 3, the electrostatic discharge protection circuit 100 of the embodiment of the present disclosure may further include a voltage clamping device 300, including a resistor (R1) 302, a capacitor (C1) 304, a fifth PMOS transistor 306, A third NMOS transistor 308 and a fourth NMOS transistor 310. The resistor 302 has a first terminal and a second terminal, a first terminal of which is connected to the power node Pr, and a second terminal of which is coupled to the gate (G3) of the first PMOS transistor 112 and the first NMOS transistor 114. The capacitor 304 has a first terminal and a second terminal. The first terminal is directly coupled to the second terminal of the resistor 302, and the second terminal is connected to the ground. A fifth PMOS transistor 306 is connected to the power section Point Pr is connected to a second connection node C2; a third NMOS transistor 308 connects the second connection node C2 and the ground; a fourth NMOS transistor 310 is coupled to the ground and the power node Pr. The diode D3 is a parasitic diode between the source and the drain in the fourth NMOS transistor 310. When in the normal working state (when the power node Pr is supplied with voltage), the voltage of the second terminal of the resistor 302 is at a high level, so the fifth PMOS transistor 306 is turned off and the third NMOS transistor 308 is turned on. ), So that the voltage of the node G2 is at a low level, and the fourth NMOS transistor 310 is turned off. Therefore, in the above-mentioned general working state, the voltage clamping device 300 does not affect the normal operation of the circuit. However, when an electrostatic discharge event occurs (such as when the electrostatic discharge voltage appears instantaneously at the power node Pr), the voltage across the capacitor 304 does not change instantly, so the second voltage of the resistor can be maintained at 0V, making the fifth PMOS voltage The crystal 306 is turned on, and the electrostatic discharge voltage coupled on the power node Pr is transmitted to the node G2, so that the voltage of the node G2 is at a high level, the fourth NMOS transistor 310 is turned on, and the electrostatic discharge current is conducted to The ground. In addition, by coupling the second end of the resistor 302 to the gate (G3) of the first PMOS transistor 112, it can be ensured that at the moment when the electrostatic discharge event occurs, the voltage of the gate G3 is 0V, so that the first The first PMOS transistor 112 and the discharge NMOS transistor 110 of FIG. 1 are turned on, and the gate (G0) of the target NMOS transistor 106 is connected to the ground.

FIG. 4 is a schematic diagram of a buffer device according to an embodiment of the disclosure. As shown in FIG. 4, the electrostatic discharge protection circuit 100 of the embodiment of the present disclosure further includes a buffer device 400, which is composed of one buffer or a plurality of buffers connected in series; and each buffer may be composed of an even number The inverters are connected in series. For example, in FIG. 4, the buffer device 400 includes two inverters (402, 404) connected in series. A buffer is formed, but the present invention is not limited to this. The input terminal of the buffer device 400 is connected to the second terminal of the resistor 302 of the voltage clamping device 300 in FIG. 3, and the output terminal of the buffer device 400 is connected to the first PMOS transistor 112 and the first NMOS transistor 114 in FIG. 1. Gate (G3). The power input terminal of the buffer in the buffer device 400 (that is, the power input terminals of the inverters 402 and 404) is coupled to the first output node TH of the traceback circuit 200 in FIG. 2. In the event of an electrostatic discharge, the output voltage of the first output node TH of the traceback circuit 200 can provide the buffer device 400 required for operation. The buffer device 400 is used to increase the slope of the rising or falling edge of the electrostatic discharge voltage of the gate (G3) coupled to the first PMOS transistor 112, so that the gate voltage control device 108 grounds the gate of the target NMOS transistor 106. Control is more responsive.

FIG. 5 is a schematic diagram of a transmission gate according to an embodiment of the disclosure. As shown in FIG. 5, the electrostatic discharge protection circuit 100 of the embodiment of the present disclosure further includes a transmission gate 500 including a second NMOS transistor 502 connected to a signal node (S) and a third output node (C3); A fourth PMOS transistor 504 is connected to the signal node (S) and the third output node (C3); and an inverter 506 has an input terminal and an output terminal. The third output node (C3) is coupled to the gate (end point G0) of the target NMOS transistor 106 in FIG. 1; the base of the fourth PMOS transistor 504 is connected to the power node Pr; the second NMOS The gate of the transistor 502 is connected to the input terminal of the inverter 506, and is connected to the gate (G3) of the first PMOS transistor 112 and the first NMOS transistor 114. In addition, the fourth PMOS transistor 504 The gate is connected to the output terminal of the inverter 506. The transmission gate 500 determines whether the voltage of the gate (G3) of the first PMOS transistor 112 and the first NMOS transistor 114 is high or low to determine whether to cut off the The connection between the signal node (S) and the gate of the target NMOS transistor 106. For example, when in the normal working state, the voltage of the gate G3 is at a logic high level, so the second NMOS transistor 502 is turned on. After the voltage of the gate G3 passes the inverter 506, it becomes a logic low level, so that The fourth PMOS transistor 504 is turned on, so the signal node (S) and the gate of the target NMOS transistor 106 are in a conducting state without affecting normal operation. When an electrostatic discharge event occurs, the gate G3 is at a logic low level, so the second NMOS transistor 502 is turned off. After the voltage of the gate G3 passes the inverter 506, it becomes a logic high level, making the fourth PMOS transistor 504. Closed, so the connection between the signal node (S) and the gate of the target NMOS transistor 106 is cut off to protect the signal node (S) from being coupled to the gate of the target NMOS transistor 106 Influence of electrostatic discharge voltage.

Although the embodiment of the present invention is described as above, we should understand that the above is only an example, not a limitation. Many changes of the above-described exemplary embodiments according to this embodiment can be performed without violating the spirit and scope of the invention. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. More specifically, the scope of the present invention should be defined by the following patent application scopes and their equivalents.

Claims (5)

  1. An electrostatic discharge protection circuit for protecting a standard NMOS transistor coupled between an I / O (input / output) bonding pad and a ground, including: a first discharge device provided at the I / O bonding Between the pad and the ground, having a trigger turn-on voltage lower than the breakdown voltage of the target NOMS transistor; and a gate voltage control device, including: a discharge NMOS transistor, coupled between the ground and the target NMOS transistor A gate; a first PMOS transistor connected to the gate of the target NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground; wherein the connection node is connected to the discharge NMOS transistor And the first PMOS transistor and the gate of the first NMOS transistor are connected to each other; when an electrostatic discharge event occurs and an electrostatic discharge voltage is coupled to the gate of the target NMOS transistor, the first PMOS transistor Turn on to make the electrostatic discharge voltage turn on the discharge NMOS transistor and ground the gate of the target NMOS transistor to ensure that the target NMOS transistor is turned off.
  2. The electrostatic discharge protection circuit according to item 1 of the scope of patent application, further comprising a trace-high circuit, including: a second PMOS transistor connected between a power node and a first output node; and A third PMOS transistor connected to the gate of the target NMOS transistor and the first output node; wherein the first output node is coupled to the base electrode of the first PMOS transistor; the second PMOS transistor The gate is connected to the gate of the target NMOS transistor, and the gate of the third PMOS transistor is connected to the power node.
  3. The electrostatic discharge protection circuit according to item 2 of the scope of patent application, further comprising: a voltage clamping device, at least comprising: a resistor having a first end and a second end, the first end of the resistor being connected to the power node, The second terminal of the resistor is coupled to the gate of the first PMOS transistor and the first NMOS transistor; and a capacitor has a first terminal and a second terminal, and the first terminal of the capacitor is directly connected to the resistor. The second terminal, the second terminal of the capacitor is connected to the ground.
  4. The electrostatic discharge protection circuit as described in item 3 of the scope of patent application, further comprising: a buffer device or a buffer device in which a plurality of buffers are connected in series; wherein the input terminal of the buffer device is connected to the first resistor of the resistor. At two ends, the output terminal of the buffer device is connected to the gates of the first PMOS and the first NMOS transistor; the power input terminal of each buffer in the buffer device is coupled to the first output node of the traceback circuit.
  5. The electrostatic discharge protection circuit according to item 4 of the scope of the patent application, further includes a transmission gate, including: a second NMOS transistor connected between a signal node and a second output node; a fourth PMOS A transistor connected to the signal node and the second output node; and an inverter having an input terminal and an output terminal; wherein the second output node is coupled to the gate of the target NMOS transistor; the first The base electrodes of the two NMOS transistors are connected to ground, and the base electrode of the fourth PMOS transistor is connected to the power node; the gate of the second NMOS transistor is connected to the input terminal of the inverter and is coupled to the first PMOS transistor. The crystal is connected to the gate of the first NMOS transistor, and the gate of the fourth PMOS transistor is connected to the output terminal of the inverter.
TW107123467A 2018-07-06 2018-07-06 Esd protection cirtcuit TWI658668B (en)

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Application Number Priority Date Filing Date Title
TW107123467A TWI658668B (en) 2018-07-06 2018-07-06 Esd protection cirtcuit

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Application Number Priority Date Filing Date Title
TW107123467A TWI658668B (en) 2018-07-06 2018-07-06 Esd protection cirtcuit

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TW202007042A TW202007042A (en) 2020-02-01

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200425459A (en) * 2003-05-02 2004-11-16 Ind Tech Res Inst ESD protection circuits for mixed-voltage buffers
US20060114047A1 (en) * 2004-11-26 2006-06-01 Nec Electronics Corporation Semiconductor unit
TW200719464A (en) * 2005-11-11 2007-05-16 Silicon Integrated Sys Corp High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique
US20080055805A1 (en) * 2006-05-30 2008-03-06 Samsung Electronics Co., Ltd. Semiconductor device having electro static discharge detection circuit
CN100508322C (en) * 2003-06-30 2009-07-01 Nxp股份有限公司 Protection circuit for an integrated circuit device
CN103646944A (en) * 2013-12-03 2014-03-19 北京中电华大电子设计有限责任公司 Double-mode electro-static discharge protection IO circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200425459A (en) * 2003-05-02 2004-11-16 Ind Tech Res Inst ESD protection circuits for mixed-voltage buffers
CN100508322C (en) * 2003-06-30 2009-07-01 Nxp股份有限公司 Protection circuit for an integrated circuit device
US20060114047A1 (en) * 2004-11-26 2006-06-01 Nec Electronics Corporation Semiconductor unit
TW200719464A (en) * 2005-11-11 2007-05-16 Silicon Integrated Sys Corp High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique
US20080055805A1 (en) * 2006-05-30 2008-03-06 Samsung Electronics Co., Ltd. Semiconductor device having electro static discharge detection circuit
CN103646944A (en) * 2013-12-03 2014-03-19 北京中电华大电子设计有限责任公司 Double-mode electro-static discharge protection IO circuit

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