JP6268939B2 - 3-level power converter - Google Patents

Description

  The present invention relates to a main circuit wiring structure of a three-level power converter.

  FIG. 5 is a circuit diagram for one phase of the three-level power converter (A-NPC type). In the three-phase power converter, the circuit in FIG. 5 is configured in three parallels, and in the single-phase inverter, the circuit in FIG. 5 is configured in two parallels. When expanding the current capacity, as shown in FIG. 6, the necessary number of elements shown in FIG. 5 are arranged in parallel.

Japanese Patent Application Laid-Open No. 2011-254672

  However, since the three-level power conversion device has a larger number of semiconductor elements than the two-level power conversion device, the number of wirings also increases. Moreover, it is necessary to suppress the surge voltage at the time of interruption of current as one element to be used by increasing the reliability of the element. One of the causes of the surge voltage is the impedance of the wiring. In order to suppress the surge voltage, it is necessary to reduce the impedance of the wiring.

  As described above, in the three-level power conversion device, there is a problem of providing a simple wiring structure with low inductance.

  The present invention has been devised in view of the above-described conventional problems. One aspect of the present invention is connected in series between the positive and negative electrodes of a DC power source, and divides the DC voltage between both electrodes by half. A plurality of DC capacitors having a neutral point, first and fourth semiconductor switching elements parallel to the DC capacitor and connected in series between positive and negative electrodes of a DC power source, and the neutral point P is connected between the bidirectional switch connected to the common connection point of the first and fourth semiconductor switching elements, the positive electrode of the DC capacitor connected to the positive electrode of the DC power supply, and the first semiconductor switching element. An N-side conductor connecting a side conductor, a negative electrode of a DC capacitor connected to the negative electrode of the DC power source, and a fourth semiconductor switching element; the neutral point; and an M-point conductor connecting a bidirectional switch; 3 level power converter with The P-side conductor, the N-side conductor and the M-point conductor flat conductor are laminated in three layers, the P-side conductor and the N-side conductor are arranged in adjacent layers, and the first and fourth semiconductor switching elements are It is arranged next to the DC capacitor.

  According to the present invention, a three-level power converter can have a simple wiring structure with low inductance.

The circuit block diagram which shows the main circuit of the 3 level power converter device in embodiment. The figure which shows the wiring structure of the 3 level power converter device in embodiment. Schematic which shows the circuit and terminal position of a module which consist of semiconductor switching elements T1, T4. The circuit block diagram which connected the load resistance to the output terminal of U and V phase. The circuit block diagram which shows an example of the conventional 3 level power converter device. The circuit block diagram which shows the other examples of the conventional 3 level power converter device.

  Hereinafter, the three-level power converter according to the present embodiment will be described in detail with reference to FIGS.

[Embodiment]
Fig.1 (a) is a circuit block diagram which shows the basic circuit for 1 phase of the 3 level power converter device in this invention. The three-level power converter performs three-level conversion from direct current to alternating current or from alternating current to direct current.

  As shown in FIG. 1A, DC capacitors C1 and C2 are sequentially connected in series between a positive electrode P (P-side conductor) and a negative electrode (N-side conductor) N of a DC power supply. The DC capacitors C1 and C2 divide the DC voltage between the positive electrode P and the negative electrode N by half, and this voltage dividing point is set as a neutral point. In the present embodiment, two DC capacitors C1 and C2 are provided. However, a configuration in which two or more DC capacitors C1 and C2 are connected in series may be used.

  Further, between the positive electrode P and the negative electrode N of the DC power supply, semiconductor switching elements T1 and T4 are connected in series in parallel with the DC capacitors C1 and C2. A bidirectional switch is connected between the neutral point (M arm) of the DC capacitors C1 and C2 and the common connection point of the semiconductor switching elements T1 and T4. In this embodiment, the semiconductor switching elements T2 and T3 are connected in reverse series to constitute a bidirectional switch. In FIG. 1, the semiconductor switching element T2 and the semiconductor switching element T3 are connected in common to the emitter, but can also be realized by a structure using a collector common connection or an antiparallel connection of IGBTs having reverse breakdown voltage.

  FIG. 1B shows an A-NPC type three-level power conversion device according to this embodiment, which includes four (2 in 1) modules 1a to 1d of semiconductor switching elements T1 and T4, and an M-arm semiconductor switching element T2. Two (1in1) modules T2a and T2b, two (1in1) modules T3a and T3b of the M-arm semiconductor switching element T3, and DC capacitors C1a, C1b, C2a and C2b are provided separately.

  FIG. 2 is a diagram showing a wiring structure of the three-level power converter according to this embodiment. 2A is a plan view, FIG. 2B is a side view (exploded view), and FIG. 2C is a side view (completed view).

  As shown in FIG. 2A, the modules 1a → 1b → 1c → 1d of the semiconductor switching elements T1 and T4 are arranged in the X direction in the order of the modules T2a → T3a → T2b → T3b of the M-arm semiconductor switching elements. They are arranged in the X direction in order, arranged in the X direction in the order of DC capacitors C1a → C1b, and arranged in the X direction in the order of DC capacitors C2a → C2b.

  Further, the modules T2a, T2b, T3a, and T3b of the M-arm semiconductor switching elements are arranged in the Y direction in the order of modules 1a to 1d including the semiconductor switching elements T1 and T2, DC capacitors C1a, C1b, and DC capacitors C2a and C2b.

  FIG. 3 is a schematic diagram showing circuits and terminal positions of the modules 1a to 1d including the semiconductor switching elements T1 and T4. As shown in FIG. 3, the modules 1a to 1d include a collector terminal c1 of the semiconductor switching element T1, a common connection point c2e1 of the emitter terminal of the semiconductor switching element T1 and a collector terminal of the semiconductor switching element T4, and an emitter of the semiconductor switching element T4. It has a terminal e2. The common connection point e1c2 → the emitter terminal e2 → the collector terminal c1 is arranged in the Y direction in this order.

  Next, a method for connecting conductors will be described with reference to FIG. In the present embodiment, the conductors are stacked in three layers. Here, the first layer, the second layer, and the third layer are referred to in order from the side closer to the element. The P-side conductor P, the N-side conductor N, the M point conductor M, the AC conductor AC, and the conductor 2 are flat conductors.

  First, the conductor 2 and the M point conductor M are arranged in the first layer. The conductor 2 connects the emitter terminals e of the modules T2a, T3a, T3b, and T2b of the semiconductor switching element. The M point conductor connects the semiconductor switching element modules T2a and T2b to the negative terminals of the DC capacitors C1a and C1b and the positive terminal (neutral point) of the collector terminals c of the DC capacitors C2a and C2b.

  Next to the first layer, the second layer is disposed via the insulator 3a. In the second layer, an AC conductor AC and an N-side conductor N are arranged. The AC conductor AC connects the collector terminals c of the modules T3a and T3b of the semiconductor switching element and the common connection point c2e1 of the modules 1a to 1d. The N-side conductor N connects the emitter terminals e2 of the modules 1a to 1d and the negative terminals of the DC capacitors C2a and C2b.

  Next to the second layer, the third layer is laminated via the insulator 3b. The P-side conductor P is disposed on the third layer. The P-side conductor P is connected to the collector terminals c1 of the modules 1a to 1d and the positive terminals of the DC capacitors C1a and C1b.

  The object of the present embodiment is to suppress surge voltage when current is interrupted and to simplify wiring. The voltage surge is generated by the circuit inductance and the cut-off current value. Low inductance can be achieved by reducing the area of the current loop from the voltage source. The current value of each part of the circuit in this embodiment is different.

  FIG. 4 is a diagram showing a circuit in which a resistive load R is connected to U-phase and V-phase AC conductors AC. In FIG. 4, the elements are simplified and represented as not being connected in parallel. The current duties in FIG. 4 are as follows. The current flowing in the P-side conductor P is I1, the current flowing in the M point conductor M is I2 (right direction), I3 (left direction), and the current flowing in the N-side conductor N is I4. Assume that a resistive load R is connected. T2U, T3U and T2V, T3V are regarded as one-way bidirectional switches. Focusing on the U phase as the basic current mode, the current duties are the following two types.

1. T1U and T4Y are turned on. A current of I1 = I4 = 2E / R flows through the P-side conductor P, the N-side conductor N, and the semiconductor switching elements T1U and T4Y.

2. T1U, T2V, and T3V are turned on. A current of I1 = I2 = E / R flows through the P-side conductor P and the M point conductor M, and T1U, T2V, and T3V.

  From the viewpoint of the current duty of the semiconductor switching element, the current duty of the semiconductor switching elements T2U, T3U, T2V, and T3V is E / R, and the U-phase, V-phase, W-phase, X-phase, Y-phase, and Z-phase Since the semiconductor switching elements T1U, T1V, T1W, T4X, T4Y, and T4Z have a current duty of 2E / R, the semiconductor switching elements T1U, T1V, T1W, T4X, T4Y, and T4Z are doubled. Also, the current duty of the conductor is the M point conductor M, the current duty is E / R, and the P side conductor P, N side conductor N is 2E / R, so the P side conductor P, N side conductor N is doubled.

  In the present embodiment, the P-side conductor P and the N-side conductor N are brought close to each other by being arranged in adjacent layers, and the current flowing in the P-side conductor P and the N-side conductor N is utilized by utilizing the difference in the direction of the current. The generated magnetic field is canceled and the inductance is suppressed. As a result, the inductance of the wiring is reduced, and the impedance and surge voltage of the wiring are reduced.

  Further, modules 1a to 1d composed of semiconductor switching elements T1 and T4 having a greater current duty than the modules T2a, T3a, T3b and T2b of the semiconductor switching elements are arranged at positions close to the DC capacitors C1a, C1b, C2a and C2b. By reducing the distance, inductance is reduced, wiring impedance is reduced, and surge voltage is suppressed.

  By adopting a three-layer wiring structure as in the present embodiment, a simple wiring structure with low inductance can be achieved, and surge voltage can be suppressed, downsized, and cost can be reduced.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  For example, in the embodiment, the wiring structure of the three-level power conversion device having a specific configuration has been described. However, the P-side conductor P, the N-side conductor N, and the M-point conductor M flat plate conductors are stacked in three layers, and the P-side If the conductor P and the N-side conductor N are arranged in adjacent layers, and the modules 1a to 1d composed of the first and fourth semiconductor switching elements T1 and T4 are arranged next to the DC capacitors C1 and C2, the other configuration is obtained. May be.

C1, C2 ... DC capacitors T1-T4 ... Semiconductor switching elements 1a-1d ... Modules composed of semiconductor switching elements T1, T4 P ... P-side conductor N ... N-side conductor M ... M-point conductor AC ... AC conductor 2 ... Conductor

Claims (1)

A plurality of DC capacitors connected in series between the positive and negative electrodes of the DC power source, dividing the DC voltage between the two electrodes in half, and having this voltage dividing point as a neutral point;
First and fourth semiconductor switching elements connected in series to the DC capacitor and sequentially connected in series between the positive and negative terminals of a DC power source;
A bidirectional switch connected between the neutral point and a common connection point of the first and fourth semiconductor switching elements;
A P-side conductor connecting the positive electrode of the DC capacitor connected to the positive electrode of the DC power supply and the first semiconductor switching element;
An N-side conductor connecting the negative electrode of the DC capacitor connected to the negative electrode of the DC power supply and the fourth semiconductor switching element;
The neutral point and the M point conductor connecting the bidirectional switch;
An AC conductor connecting the bidirectional switch and the first and fourth semiconductor switching elements;
A three-level power conversion device comprising:
The P-side conductor, the N-side conductor and the M-point conductor are laminated in three layers, the P-side conductor and the N-side conductor are arranged in adjacent layers, and the first and fourth semiconductor switching elements are adjacent to the DC capacitor. The M-point conductor and the AC conductor are arranged in adjacent layers, and the M-point conductor and the AC conductor overlap each other.

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