JP2019134543A - Power supply device - Google Patents

Abstract

To provide a power supply device capable of reducing influence of current sharing and voltage drop due to inductance variation by reducing inductance.SOLUTION: A first phase output conductor plate 11 and a second phase output conductor plate 12 are arranged so as to be mutually overlapped and spaced apart from each other so as to cover a semiconductor device row L1 (L2) configured by arranging a first phase semiconductor device UX1 (UX2) and a second phase semiconductor device VY1 (VY2) in parallel. The first phase output conductor plate and the second phase output conductor plate include: a wide plate portion 21 in which openings 23a to 23d are formed at positions facing the first phase semiconductor device and the second phase semiconductor device; and a narrow plate portion 22 connected to the wide plate portion and serving as an output terminal. The first phase output conductor plate includes a first terminal 26 connected to an AC output terminal of the first phase semiconductor device on the side opposite to the narrow plate portion of the opening facing the first phase semiconductor device. The second phase output conductor plate includes a second terminal 27 connected to the AC output terminal of the second phase semiconductor device on the side opposite to the narrow plate portion of the opening facing the second phase semiconductor device.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply device that outputs AC power of a single phase or three or more phases.

As this type of power supply device, a power converter that outputs single-phase or three-phase or more AC power is provided. In this inverter device, two or three or more legs in which a first semiconductor element constituting an upper arm and a second semiconductor element forming a lower arm are connected in series between a positive electrode line and a negative electrode line are connected in parallel. The bridge circuit is configured. Then, one phase of AC power is output from the connection point between the first semiconductor element and the second semiconductor element.
For example, in a 3-phase 2-level power converter, a U-phase output is output from the U-phase leg, a V-phase output is output from the V-phase leg, and a W-phase output is output from the W-phase leg.

By the way, in a three-phase two-level power converter, when a necessary amount of current increases, in order to secure this amount of current, a plurality of legs are connected in parallel to each of the U-phase leg, the V-phase leg, and the W-phase leg. (For example, refer patent document 1).
In such a power conversion device, a plurality of legs composed of a positive-side IGBT and a negative-side IGBT are arranged in parallel for each phase, and an AC-side output terminal is provided for each of the U-phase, V-phase, and W-phase as a flat-plate AC They are connected by side conductors. Therefore, the AC side conductors for three phases are arranged in parallel for three phases.

JP 2000-60126 A

By the way, in the prior art described in Patent Document 1 described above, a flat AC output side conductor is connected for each phase. For this reason, the inductance from the output end of the AC output side conductor to the connection point of the first semiconductor element and the second semiconductor element varies in structure.
Here, for the sake of simplicity, for example, as shown in FIG. 12, a single-phase power conversion device is considered, and a 2-in-1 semiconductor device UX1 in which one leg is constituted by a U-phase arm and an X-phase arm, and Consider a case where UX2 and two VY1 and VY2 are arranged in parallel and the AC output terminals ACu1 and ACu2 and ACv1 and ACv2 are connected by flat output conductor plates Cu and Cv.

At this time, in a power converter having a low fundamental frequency, for example, a commercial AC frequency of about 60 Hz, the inductance from the AC output terminals ACu1, ACu2, and ACv1, ACv2 to the output terminals Ue and Ve of each element of the output conductor plates Cu and Cv is set. When the total of each phase (U or V) is about 0.5 μH, the voltage drop ΔVL ′ (= ωL × I = 2πf × I) of the output conductor plates Cu and Cv is calculated as follows. Here, when the output current of one device of the semiconductor devices UX1, UX2, and VY1, VY2 is 200A, the two semiconductor devices UX1, UX2, and VY1, VY2 are connected in parallel. It becomes 400A in the V phase.
ΔVL ′ == 2 × π × 60 Hz × 0.5 × 10 ⁻⁶ × 400 A≈0.075 V
This voltage drop ΔVL′≈0.075 V is not particularly significant for a power converter having an output of several hundred volts.

On the other hand, in the power conversion device with a high output current of 10000 Hz at the fundamental frequency, the voltage drop of the output conductor plates Cu and Cv is expressed by the following equation.
ΔVL ′ = 2 × π × 10000 Hz × 0.5 × 10 ⁻⁶ × 400 A = 12.6V
This voltage drop ΔVL ′ = 12.6 V is about 5% for a power converter having an output voltage of about 300 V, resulting in a decrease in the voltage utilization rate of the power converter and a factor in reducing the capacity of the power converter. Yes.

Next, as shown in FIG. 13, current sharing when the three semiconductor devices UX1 to UX3 and the semiconductor devices VY1 to VY3 are connected in parallel in the U phase and the V phase will be described.
In this case, in a power conversion device with an output current having a fundamental frequency of, for example, a commercial frequency of about 60 Hz, even if a difference of 0.05 μH occurs in the inductances Lu1 to Lu3 between the parallel devices on the output conductor plates Cu and Cv, for example, On the other hand, the ON voltage 1V (200 V / semiconductor element) when the semiconductor elements constituting the semiconductor devices UX1 to 3 and the semiconductor devices VY1 to 3 are IGBTs is sufficiently large with respect to the voltage drop ΔVL calculated below in FIG.
ΔVL = 2 × π × 60 Hz × 0.05 × 10 ⁻⁶ × 200 A = 3.8 mV << ON voltage For this reason, the variation in inductance of the output conductor plates Cu and Cv with respect to each parallel semiconductor device is different from that of the parallel semiconductor device. There is no problem with current sharing.

On the other hand, in a power conversion device with an output current as high as 10000 Hz, for example, when a difference of 0.05 μH occurs between the inductances Lu1 to Lu3 between the parallel semiconductor devices on the output conductor plates Cu and Cv, the semiconductor devices UX1 to 3 and The voltage drop ΔVL in this portion is calculated as follows with respect to the on-voltage 1 V (200 A / semiconductor element) when the semiconductor elements constituting the semiconductor devices VY 1 to 3 are IGBTs.
ΔVL = 2 × π × 10000 Hz × 0.05 × 10 ⁻⁶ × 200 A = 0.63V
This voltage drop ΔVL = 0.63V is 50% or more with respect to the on-voltage 1V of the semiconductor element, and has a great influence.
For this reason, conventionally, there is a problem that the element acquisition current must be examined by the current sharing of the parallel semiconductor device in consideration of the voltage drop ΔVL of the output conductor plates Cu and Cv.
Therefore, the present invention has been made paying attention to the problems of the above-described prior art, and an object thereof is to provide a power supply apparatus capable of reducing the inductance and reducing the current sharing and the voltage drop due to the inductance variation. .

  In order to achieve the above object, one aspect of a power supply device according to the present invention provides a first phase output so as to cover a semiconductor device row configured by arranging a first phase semiconductor device and a second phase semiconductor device in parallel. The conductor plate and the second phase output conductor plate are arranged to be spaced apart from each other, and the first phase output conductor plate and the second phase output conductor plate are located at positions facing the first phase semiconductor device and the second phase semiconductor device. A wide plate portion having an opening portion and a narrow plate portion connected to the wide plate portion and serving as an output terminal, a current path is formed between the openings of the wide plate portion, and the first phase output conductor plate is The first terminal portion connected to the first phase AC output terminal of the first phase semiconductor device is provided on the opposite side of the narrow plate portion of the opening facing the one phase semiconductor device, and the second phase output conductor plate is The second phase AC output terminal of the second phase semiconductor device is connected to the opposite side of the narrow plate portion of the opening facing the two phase semiconductor device. And a second terminal.

  According to one aspect of the present invention, the first-phase semiconductor device and the second-phase semiconductor device are arranged in parallel and the first-phase output conductor plate and the second-phase output conductor plate are arranged so as to cover them. By doing so, the inductance can be canceled by the mutual induction effect between the first phase output conductor plate and the second phase output conductor plate. Therefore, it is possible to reduce the influence of voltage drop and current sharing in the first phase output conductor plate and the second phase output conductor plate portion, and improve the utilization factor of the power converter.

It is a top view which shows one Embodiment of the power supply device which concerns on this invention. It is a left side surface of FIG. It is a rear view of FIG. It is sectional drawing on the IV-IV line of FIG. It is sectional drawing on the VV line of FIG. It is a top view which shows a 1st phase output conductor plate. It is a top view which shows a 2nd phase output conductor plate. It is a circuit which shows the circuit structure of the power supply device of FIG. It is explanatory drawing with which it uses for description of operation | movement of the power supply device which concerns on this invention. It is a top view which shows the modification of a power supply device. It is a rear view which shows the other modification of a power supply device. It is a top view which shows the conventional output conductor board. It is a top view which shows the other example of the conventional output conductor board.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention. The technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the component parts as follows. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

Hereinafter, an embodiment of a power supply device according to the present invention will be described with reference to the drawings, taking as an example a case where a single-phase power conversion device is provided.
As illustrated in FIG. 1, the power supply device 10 includes a first phase semiconductor device UX that forms a U phase and a second phase semiconductor device VY that forms a V phase. The first phase semiconductor device UX has two semiconductor devices UX1 and UX2. Similarly, the second phase semiconductor device VY also includes two semiconductor devices VY1 and VY2.
In these semiconductor devices UX1, UX2 and VY1, VY2, a power semiconductor element composed of, for example, an IGBT constituting an upper arm and a power semiconductor element composed of an IGBT, which similarly constitutes a lower arm, are connected in series by a totem pole. It has a so-called 2-in-1 configuration built in. As shown in FIGS. 1 to 3, the semiconductor devices UX1, UX2, and VY1, VY2 have AC output terminals ACu1, ACu2, ACv1, ACv2, a positive terminal DCp, and a negative terminal DCn on the upper surface at predetermined intervals in this order. It is formed so as to protrude in a row.

The semiconductor device UX1 of the first phase semiconductor device UX and the semiconductor device VY1 of the second phase semiconductor device VY are arranged in parallel with their upper surfaces facing upward and maintaining a preset insulation distance. Is configured. Similarly, the semiconductor device row L2 is configured by arranging the semiconductor device UX2 of the first phase semiconductor device UX and the semiconductor device VY2 of the second phase semiconductor device VY in parallel while maintaining a predetermined insulation distance.
The semiconductor device rows L1 and L2 are arranged in parallel with an insulation distance equal to the insulation distance between the semiconductor devices UX1 and VY1. Therefore, the semiconductor devices UX1, VY1, UX2, and VY2 are aligned in that order in the direction orthogonal to the arrangement direction of the AC output terminals ACu1 to ACv2, the positive electrode terminal DCp, and the negative electrode terminal DCn of each semiconductor device. .

Above the semiconductor device rows L1 and L2, a first phase output conductor plate 11 and a second phase output conductor plate 12 are, for example, a first phase output conductor plate 11 facing the terminals ACu1 to ACv2, DCp and DCn. Is arranged with the insulation distance set in advance so that the second phase output conductor plate 12 is the lower side.
As shown in FIGS. 6 and 7, each of the first phase output conductor plate 11 and the second phase output conductor plate 12 includes a wide plate portion 21 set to a size covering the semiconductor device rows L1 and L2, and this A narrow plate portion 22 serving as an output terminal connected to the central portion of the wide plate portion 21 is formed in a T shape. In the wide plate portion 21, openings 23a to 23d having substantially the same shape as the top surfaces of the semiconductor devices UX1, VY1, UX2, and VY2 are formed so as to pass through the positions facing the semiconductor devices UX1, VY1, UX2, and VY2. Has been. A current path 24a is formed between the openings 23a and 23b, a current path 24b is formed between the openings 23b and 23c, and a current path 24c is formed between the openings 23c and 23d.

The wide plate portion 21 is formed with current suppressing portions 25a and 25b at both ends in the alignment direction of the openings 23a to 23d. These current suppressing portions 25a and 25b are set to have a cross-sectional area that is sufficiently small as about 1/6 as compared with the cross-sectional areas of the current passages 24a to 24c, and limit the flowing current.
The current suppressing portions 25a and 25b are not limited to the narrow strip-shaped regions, but are formed as wide strip-shaped regions on the side edges facing the openings 23a and 23d from the outer peripheral side toward the openings 23a and 23d. You may make it provide the notch which goes to a reverse direction. Furthermore, a cutting part may be provided at an arbitrary position facing the openings 23a and 23d to open the circuit, thereby interrupting the current.

The first phase output conductor plate 11 extends into the openings 23a and 23c from the central portion on the opposite side of the narrow plate portion 22 of the openings 23a and 23c facing the semiconductor devices UX1 and UX2, and A first terminal 26 extending downward is formed so as to contact the AC output terminals ACu1 and ACu2 of the semiconductor devices UX1 and UX2.
Further, the second phase output conductor plate 12 extends from the central portion on the opposite side of the narrow plate portion 22 of the openings 23b and 23d facing the semiconductor devices VY1 and VY2 into the openings 23b and 23d, and A second terminal 27 extending downward is formed so as to contact the AC output terminals ACv1 and ACv2 of the semiconductor devices VY1 and VY2.
Then, the first terminal 26 of the first phase output conductor plate 11 is connected to the AC output terminals ACu1 and ACu2 of the semiconductor devices UX1 and UX2 through the openings 23a and 23c of the first phase output conductor plate 11, as shown in FIG. Joined with screws.
Further, as shown in FIG. 5, the second terminal 27 of the second phase output conductor plate 12 is directly joined to the AC output terminals ACv1 and ACv2 of the semiconductor devices VY1 and VY2 by screws.

Next, the electrical connection relationship of the above embodiment will be described with reference to FIGS.
As shown in FIG. 8, the semiconductor devices UX1, UX2, and VY1, VY2 are, for example, a power switching semiconductor element Q1 formed of an IGBT forming an upper arm and a power switching semiconductor element formed of an IGBT forming a lower arm. Q2 is totem-pole connected in series. Free wheeling diodes D1 and D2 are connected in reverse direction to the power switching semiconductor elements Q1 and Q2, respectively.
The semiconductor device UX1 will be described as a representative. The connection point of the power switching semiconductor elements Q1 and Q2 is connected to the AC output terminal ACu1, the collector of the power switching semiconductor element Q1 is connected to the positive terminal DCp, and the power switching semiconductor element Q2 Are connected to the negative terminal DCn.

The AC output terminal ACu1 is connected to the first phase output conductor plate 11, and the positive electrode terminal DCp and the negative electrode terminal DCn are individually connected to the positive electrode line Lp and the negative electrode line Ln to which DC power is supplied.
Similarly, the positive electrode terminal DCp and the negative electrode terminal DCn of the semiconductor devices UX2 and VY1, VY2 are connected in parallel with the semiconductor device UX1 between the positive electrode line Lp and the negative electrode line Ln, and the AC output terminal ACu2 of the semiconductor device UX2 is the first phase output. An inverter device as a power converter is configured by connecting to the conductor plate 11 and connecting the AC output terminals ACv1 and ACv2 of the semiconductor devices VY1 and VY2 to the second phase output conductor plate 12.

Next, the operation of the above embodiment will be described.
A PWM signal is input to the gate terminals of the upper arms of the semiconductor devices UX1 and UX2, and an ON signal is input to the gate terminals of the lower arms of the semiconductor devices VY1 and VY2, and a positive AC output is output from the first phase output conductor plate 11. Output half cycle. Next, a PWM signal is input to the gate terminals of the lower arms of the semiconductor devices UX1 and UX2, and an ON signal is input to the gate terminals of the upper arms of the semiconductor devices VY1 and VY2 to output an AC output from the second phase output conductor plate 12. Output negative half cycle.

At this time, the first phase output conductor plate 11 and the second phase output conductor plate 12 having different output polarities are arranged in parallel while maintaining a predetermined insulation distance, and the first phase output conductor plate 11 and the second phase Openings 23a to 23d corresponding to the semiconductor devices UX1, VY1, UX2, and VY2 are formed in the output conductor plate 12. For this reason, the current paths 24 a to 24 c formed between the openings of the first phase output conductor plate 11 overlap with the current paths 24 a to 24 c formed between the openings of the second phase output conductor plate 12 in the vertical direction.
The first terminal 26 and the second terminal 27 connected to the semiconductor devices UX1, UX2, and VY1, VY2 of the first phase output conductor plate 11 and the second phase output conductor plate 12 are narrow plates having openings 23a to 23d. It is formed on the side opposite to the portion 22. Therefore, the current flowing through the first phase output conductor plate 11 and the second phase output conductor plate 12 passes through the current paths 24a to 24c from the first terminal 26 and the second terminal 27 as shown in FIG. They are merged at the plate portion 22 and output from the narrow plate portion 22.

  At this time, in the simple substance of the first phase output conductor plate 11 and the second phase output conductor plate 12, the current passing through the current path 24b flows in the shortest distance to the narrow plate portion 22, but the current passing through the current paths 24a and 24b is The distance through the current path 24b is increased with respect to the current. For this reason, since the inductance is proportional to the length of the current path, the inductances La and Lc of the current passing through the current paths 24a and 24c are larger than the inductance Lb of the current passing through the central current path 24b, and the inductance varies. This is the same as in the conventional example.

However, in this embodiment, since the first phase output conductor plate 11 and the second phase output conductor plate 12 are overlapped, the inductance can be reduced by the mutual induction effect. That is, as shown in FIG. 9, the inductance La for the current flowing through the current path 24 a having a large inductance alone is Lu1 as the inductance of the current path of the first phase output conductor plate 11, and the second phase output conductor plate 12. If the inductance of the current path is Lv1,
La = Lu1 + Lv1-2Mu1v1
It is represented by Here, Mu1v1 is a mutual inductance caused by mutual induction. For this reason, the inductance La is reduced to substantially zero by canceling out the inductances Lu1 and Lv1 by the mutual inductance Mu1v1.

Similarly, the inductance Lc for the current flowing through the current path 24c having a large inductance alone is represented by Lu2 as the inductance of the current path of the first phase output conductor plate 11, and the inductance of the current path of the second phase output conductor plate 12 by Lv2. Then,
Lc = Lu2 + Lv2-2Mu2v2
It is represented by Here, Mu2v2 is a mutual inductance generated by mutual induction. For this reason, the inductance Lc is reduced to substantially zero by canceling out the inductances Lu2 and Lv2 by the mutual inductance Mu2v2.

Further, the inductance Ld of the current flowing through the narrow plate portion 22 to the output end is set to Lu as the inductance of the narrow plate portion 22 of the first phase output conductor plate 11 and the second phase output conductor plate 12 is narrow. If the inductance of the plate portion 22 is Lv,
Ld = Lu + Lv-2Muv
It is represented by Here, Muv is a mutual inductance caused by mutual induction. For this reason, the inductance Ld in the narrow plate portion 22 is canceled by the mutual inductance Muv and reduced to substantially zero.

As described above, the single output conductor plates 11 and 12 exhibit the mutual induction effect in the current paths 24a and 24b and the narrow plate portion 22 in which the inductance is increased, and the inductance can be reduced to substantially zero. Also, the inductance of the current path 24b is reduced to substantially zero by the mutual induction effect.
As described above, in the above embodiment, the semiconductor devices constituting different phases are arranged in parallel, and the output conductor plates of the respective phases are overlapped. Inductance can be canceled out. For this reason, the voltage drop by the inductance from each semiconductor device to the output end of the output conductor plate can be reduced.

Even in an inverter device with an output current having a high fundamental frequency (for example, a frequency of 10000 Hz), the inductance in the first phase output conductor plate 11 and the second phase output conductor plate 12 becomes substantially zero, so that the voltage drop ΔVL = ωL × I The influence of can be made small. Therefore, the current sharing of the semiconductor devices connected in parallel is improved.
Therefore, the current sharing of the semiconductor devices connected in parallel can be improved, and the voltage drop at the output conductor plate of the power conversion device constituted by the inverter device can be improved, thereby improving the utilization rate of the power conversion device. Can do.

Further, since the current suppressing portions 25a and 25b are formed outside the openings 23a and 23d outside the phase output conductor plates 11 and 12, the current flowing to both ends of the wide plate portion 21 in the alignment direction of the semiconductor device is suppressed. Thus, the current path can be limited, and the generation of a large inductance due to a longer distance can be suppressed.
In addition, although the case where this invention was applied to the single phase inverter apparatus was demonstrated in the said embodiment, it is not limited to this, This invention can be applied also to the three phase inverter apparatus shown in FIG. .

That is, the first-phase semiconductor device UX, the second-phase semiconductor device VY, and the third-phase semiconductor device WZ are configured by two semiconductor devices UX1, UX2, VY1, VY2, WZ1, and WZ2 each having, for example, a 2-in-1 configuration. . Then, semiconductor devices having different phases are arranged in parallel to form a semiconductor device row, and the semiconductor device rows are arranged in parallel.
On these semiconductor device rows, a first phase output conductor plate 11, a second phase output conductor plate 12, and a third phase output conductor plate 13 are arranged in order from the top while maintaining a predetermined insulation distance. Each of the phase output conductor plates 11, 12, and 13 includes a wide plate portion 21 that covers all of the semiconductor devices UX1, VY1, WZ1, UX2, VY2, and WZ2, and a narrow plate that is connected to the wide plate portion 21 and serves as an output terminal. The portion 22 is formed in a T shape.

  In the wide plate portion 21, openings 23a to 23f are formed at positions facing the semiconductor devices UX1, VY1, WZ1, UX2, VY2, and WZ2. In the first phase output conductor plate 11, a first terminal 26 connected to the AC output terminals ACu1 and ACu2 of the semiconductor devices UX1 and UX2 is formed on the side opposite to the narrow plate portion 22 of the openings 23a and 23d. . The second phase output conductor plate 12 is formed with a second terminal 27 connected to the AC output terminals ACv1 and ACv2 of the semiconductor devices VY1 and VY2 on the opposite side to the narrow plate portion 22 of the openings 23b and 23e. . The third phase output conductor plate 13 is formed with a third terminal 28 connected to the AC output terminals ACw1 and ACw2 of the semiconductor devices WZ1 and WZ2 on the side opposite to the narrow plate portion 22 of the openings 23c and 23f. .

Further, current suppressing portions 25 a and 25 b are formed outside the openings 23 a and 23 f of the wide plate portion 21.
Even in the power supply device having the three-phase inverter device, the first phase output conductor plate 11 and the second phase are arranged so as to cover the semiconductor device rows formed by arranging the semiconductor devices having different phases in parallel. The output conductor plate 12 and the third phase output conductor plate 13 are arranged so as to overlap each other. For this reason, when alternating currents having a phase difference of 120 degrees flow through the respective phase output conductor plates 11, 12, and 13, the mutual induction effect can be exhibited and the inductance can be canceled and reduced. Therefore, the voltage drop due to the inductance from each semiconductor device to the output end of the output conductor plate can be reduced, and the current sharing of the semiconductor devices connected in parallel is improved. Therefore, the utilization efficiency of the power converter device comprised with a three-phase inverter apparatus can be improved.

Moreover, since the current suppressing portions 25a and 25b are provided at both ends of the wide plate portion 21 in the alignment direction of the semiconductor device, it is possible to suppress the generation of large inductance due to the current flowing through both ends of the wide plate portion 21. The present invention can also be applied to a power supply device having an inverter device having four or more phases.
In the above embodiment, the case where the first phase semiconductor device UX and the second phase semiconductor device VY are arranged in a row has been described. However, the present invention is not limited to this, and as shown in FIG. A semiconductor device in which the phase output conductor plate 11 and the two-phase output conductor plate 12 are arranged to face each other while maintaining a predetermined insulation distance, and the first phase semiconductor device UX is configured to face the first phase output conductor plate 11. UX1 and UX2 may be arranged, and the semiconductor devices VY1 and VY2 constituting the second phase semiconductor device VY may be arranged so as to face the second phase output conductor plate 12.

  Further, in the above embodiment, the case where the first phase semiconductor device UX and the second phase semiconductor device VY are connected to the two semiconductor devices XU1, XU2, VY1, and VY2 in parallel has been described. However, the present invention is not limited to the above-described configuration, and the first phase semiconductor device UX and the second phase semiconductor device VY are configured by one semiconductor device, or three or more semiconductor devices are connected in parallel. Even in this case, the present invention can be applied.

In the above embodiment, the first phase semiconductor device UX is formed by sequentially arranging the semiconductor device rows in which the semiconductor devices constituting the first phase semiconductor device UX and the semiconductor devices constituting the second phase semiconductor device VY are arranged in parallel. The case where the semiconductor device constituting the semiconductor device and the semiconductor device constituting the second phase semiconductor device are alternately arranged has been described. However, the present invention is not limited to the above configuration, and for example, a semiconductor device row in which the semiconductor device UX1 and the semiconductor device VY1 are arranged in order, and conversely, a semiconductor device row in which the semiconductor device VY2 and the semiconductor device UX2 are arranged in order. May be arranged in parallel.
Moreover, although the case where the semiconductor device of 2in1 structure was applied as the semiconductor devices UX1-VY2 was demonstrated in the said embodiment, it is not limited to this, The semiconductor device of 1in1 structure which contains one switching semiconductor element is not limited to this. You may make it connect in series.

  DESCRIPTION OF SYMBOLS 10 ... Power supply device, UX ... First phase semiconductor device, UX1, UX2 ... Semiconductor device, VY ... Second phase semiconductor device, VY1, VY2 ... Semiconductor device, WZ ... Third phase semiconductor device, WZ1, WZ2 ... Semiconductor device, L1, L2 ... Semiconductor device row, ACu1-ACv2 ... AC output terminal, DCp ... Positive electrode terminal, DCn ... Negative electrode terminal, 11 ... First phase output conductor plate, 12 ... Second phase output conductor plate, 13 ... Third phase output Conductor plate, 21: Wide plate portion, 22: Narrow plate portion, 23a-23f ... Opening portion, 24a-24e ... Current path, 25a, 25b ... Current suppression portion, 26 ... First terminal, 27 ... Second terminal, 28 ... Third terminal

Claims (7)

The first phase output conductor plate and the second phase output conductor plate are arranged so as to be spaced apart from each other so as to cover a semiconductor device row configured by arranging the first phase semiconductor device and the second phase semiconductor device in parallel.
The first phase output conductor plate and the second phase output conductor plate include a wide plate portion in which an opening is formed at a position facing the first phase semiconductor device and the second phase semiconductor device, and the wide plate portion. It has a narrow plate portion that is connected and becomes an output terminal, and a current path is formed between the openings of the wide plate portion
The first phase output conductor plate is connected to a first phase AC output terminal of the first phase semiconductor device on a side opposite to the narrow plate portion of the opening facing the first phase semiconductor device. With a terminal,
The second phase output conductor plate is connected to a second phase AC output terminal of the second phase semiconductor device on a side opposite to the narrow plate portion of the opening facing the second phase semiconductor device. A power supply with terminals.   2. The power supply device according to claim 1, wherein the first-phase output conductor plate and the second-phase output conductor plate are formed with a current suppressing portion that suppresses a passing current outside the opening on the outer side in the arrangement direction. .   3. The power supply device according to claim 2, wherein the current suppression unit is configured such that a cross-sectional area of at least a part of an outer current passage in the opening on the outer side in the arrangement direction is set smaller than a cross-sectional area of a current passage between the openings. .   The power supply device according to claim 2, wherein the current suppressing portion has an outer current passage in the opening on the outer side in the arrangement direction.   5. The semiconductor device array according to claim 1, wherein the semiconductor device array includes a plurality of semiconductor device arrays in which an alignment order of the first phase semiconductor device and the second phase semiconductor device is set to be the same. The power supply described.   The said semiconductor device row | line | column is comprised with the some semiconductor device row | line | column set so that the order of alignment of the said 1st phase semiconductor device and the said 2nd phase semiconductor device may differ. The power supply device described in 1.   The first-phase output conductor plate and the second-phase output conductor plate are arranged in a state of being separated from each other, the first-phase semiconductor device is arranged to face the first-phase output conductor plate, The power supply device according to any one of claims 1 to 6, wherein a phase semiconductor device is arranged to face the second phase output conductor plate.

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