JP6266908B2 - Manufacturing method of electronic component built-in substrate - Google Patents

Description

  The present invention relates to a method of manufacturing an electronic component built-in substrate.

  With the recent development of electronic devices, wiring boards for electronic component devices used in electronic devices are required to be smaller and have higher performance. In order to cope with this, an electronic component built-in board in which an electronic component is built in a wiring board has been put into practical use.

  In such an electronic component built-in substrate, the electronic component is disposed in the opening of the core substrate, and build-up wiring is formed on both sides of the core substrate.

  As a first method for fixing the electronic component to the opening of the core substrate, there is a method in which a protrusion is provided on the inner wall of the opening of the core substrate, and the electronic component is press-fitted into the opening and fixed to the protrusion.

  As a second method, there is a method of fixing the side surface of the electronic component to the inner wall of the opening of the core substrate with an adhesive.

  As a third method, a core substrate provided with an opening is placed on a temporary fixing tape, an electronic component is temporarily fixed on the temporary fixing tape in the opening, and then the opening is filled with resin. There is a way to do it.

JP 2001-332437 A JP 2005-203457 A JP 2007-258541 A JP 2011-216740 A JP 2012-79994 A

  In the first method of fixing the electronic component to the opening of the core substrate described above, the inner wall of the opening of the substrate is deformed, so that the insulating reliability of the substrate may not be obtained. In addition, since variations in the outer shape of the electronic component and variations in the size of the opening of the core substrate occur, it is difficult to fix the electronic component to the opening of the substrate with high accuracy and stability.

  Further, in the second method described above, since an adhesive having a different material from the resin that embeds the electronic component remains on the inner wall of the opening of the core substrate, peeling or residual stress due to the difference in physical properties between the two tends to occur. . Furthermore, the adhesive may be pushed out onto the electrode pad on the surface of the core substrate, which may reduce the reliability of via connection on the electrode pad.

  Further, in the third method described above, since the temporary fixing tape is specially used, there is a problem in that the cost is increased, the manufacturing process becomes complicated, and the manufacturing efficiency is lowered.

  An object of the present invention is to provide a novel method that does not cause a problem in a method for manufacturing an electronic component built-in substrate in which an electronic component is disposed in an opening of a substrate and the electronic component is sealed with an insulating layer.

According to one aspect of the disclosure below, a step of preparing a substrate provided with an opening, a semi-cured first insulating resin layer, and the first insulating resin layer are formed on the first insulating resin layer. A step of preparing a first resin base material comprising a resin that is the same as the resin layer and a solvent that dissolves the resin, and a liquid adhesive resin layer having a boiling point of the solvent of 35 ° C. or higher and lower than 180 ° C . ; A step of disposing an adhesive resin layer of the first resin base material on one surface of the substrate to close one of the openings of the substrate; and an electron in the adhesive resin layer in the opening of the substrate. A step of adhering the components at room temperature, a second resin base material including a semi-cured second insulating resin layer on the other surface of the substrate, and thermocompression bonding from both sides of the substrate, a temperature of 180 ° C. or higher heat treatment by volatilizing the solvent contained in the adhesive resin layer, wherein the group Method of manufacturing an electronic component-embedded substrate and a step of forming an insulating layer which seals the electronic component on both sides is provided.

  According to the following disclosure, in the method for manufacturing an electronic component built-in substrate, a first resin base material in which an adhesive resin layer made of the same resin is formed on an insulating resin layer is used as an interlayer insulating material. And the resin layer for adhesion | attachment of a 1st resin base material is arrange | positioned on one side of the board | substrate with which the opening part was provided.

  Subsequently, the electronic component is bonded to the bonding resin layer in the opening of the substrate. Furthermore, the 2nd resin base material is arrange | positioned on the other surface of a board | substrate, and the insulating layer which seals an electronic component is formed by carrying out the thermocompression bonding from the both sides of a board | substrate.

  As described above, the electronic component is bonded to the surface of the first resin base material for obtaining the insulating layer with tackiness. For this reason, since the adhesive of a material different from an insulating layer does not exist around an electronic component, the peeling | exfoliation by the difference in physical property and generation | occurrence | production of a residual stress are suppressed.

  Further, when the electronic component is arranged in the opening of the substrate, the inner wall of the opening of the substrate is not deformed, so that the reliability of insulation of the substrate is not lowered.

  Furthermore, since the temporary fixing tape is not used when the electronic component is arranged in the opening of the substrate, the cost can be reduced and the manufacturing process is simplified.

1A to 1D are sectional views (No. 1) showing a method for manufacturing an electronic component built-in substrate according to an embodiment. 2A to 2D are sectional views (No. 2) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. 3A and 3B are sectional views (No. 3) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. 4A and 4B are sectional views (No. 4) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. 5A to 5C are sectional views (No. 5) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. 6A to 6C are sectional views (No. 6) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. 7A to 7C are sectional views (No. 7) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. FIG. 8 is a sectional view (No. 8) showing the method for manufacturing the electronic component built-in substrate according to the embodiment. FIG. 9 is a cross-sectional view showing a state in which a semiconductor chip is mounted on the electronic component built-in substrate of FIG.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  1-8 is a figure which shows the manufacturing method of the electronic component built-in board | substrate of embodiment.

  In the method for manufacturing an electronic component built-in substrate according to the embodiment, first, a core substrate 10 formed of an insulating material such as glass epoxy resin is prepared. The thickness of the core substrate 10 is, for example, about 100 μm to 400 μm.

  Next, as shown in FIG. 1B, through-holes TH are formed by penetrating the core substrate 10 in the thickness direction with a laser or a drill. The diameter of the through hole TH is set to, for example, about 100 μm to 200 μm.

  After that, as shown in FIG. 1C, a through-hole plating layer 20a made of copper or the like is formed on both sides of the core substrate 10 and the inner surface of the through-hole TH by electroless plating and electrolytic plating. Further, as shown in FIG. 1D, the remaining holes of the through holes TH are filled with a resin body R such as an epoxy resin.

  Subsequently, as shown in FIG. 2A, a metal plating layer 20b made of copper or the like is formed on the through-hole plating layer 20a on both sides of the core substrate 10 and the resin body R by electroless plating and electrolytic plating, respectively. To do.

  Next, as shown in FIG. 2B, the resist layers 12 are patterned on the metal plating layers 20b on both sides of the core substrate 10 by photolithography. Further, on both sides of the core substrate 10, the metal plating layer 20b and the through-hole plating layer 20a are removed by wet etching using the resist layer 12 as a mask.

  Thereby, as shown in FIG. 2C, the first wiring layers 20 are formed on both sides of the core substrate 10, respectively. The thickness of the first wiring layer 20 is set to, for example, about 18 μm to 33 μm.

  2C, the first wiring layer 20 is formed by laminating a through-hole plating layer 20a and a metal plating layer 20b in order from the bottom. The first wiring layers 20 on both sides are interconnected via a through-hole plating layer 20a.

  As described above, the core wiring board 2 used in the present embodiment is obtained.

  In the example of FIG. 2C, the resin body R is filled in the hole in the through hole TH, but the entire inside of the through hole TH may be embedded with a metal plating layer such as copper.

  Further, a multilayer wiring may be built in the core substrate 10. In this case, for example, a copper-clad laminate with copper foil affixed on both sides of the core material is used, a copper layer on both sides is patterned to form a wiring layer, and a prepreg with a copper foil affixed on one side After being laminated, the substrate is manufactured based on a method of forming a through hole in the entire substrate.

  Next, a method for incorporating electronic components in the core wiring board 2 will be described. As shown in FIG. 2D, first, an opening 2a penetrating from the upper surface to the lower surface is formed in the central portion of the core wiring board 2 in FIG. 2C by press working using a mold. Instead of pressing using a mold, the opening 2a may be formed by router processing, laser processing, or the like. The opening 2a is also called a cavity.

  The opening 2a of the core wiring board 2 is formed in, for example, a square shape in plan view, and an electronic component is disposed in the opening 2a as described later. When a large core wiring board 2 for multi-sided use is used, the openings 2a are respectively arranged in a plurality of product areas defined.

  Before or after the opening 2a is formed in the core wiring board 2, the surface of the first wiring layer 20 is roughened by blackening or the like. By making the surface of the first wiring layer 20 a roughened surface, the insulating resin layer can be formed on the first wiring layer 20 with good adhesion by the anchor effect.

  As described above, the core wiring board 2 provided with the opening 2a is prepared.

  Next, the 1st resin base material used as an interlayer insulation material is prepared. 3A and 3B show a first method for producing the first resin base material.

  In the first production method of the first resin base material, as shown in FIG. 3A, a semi-cured (B stage) insulating resin layer 32 having a copper foil 34 attached to one side is prepared. A prepreg is preferably used as the insulating resin layer 32. The prepreg is a sheet-like intermediate material made of a resin in a semi-cured state (B stage) in which a fiber reinforced material such as glass cloth is impregnated with a thermosetting resin such as an epoxy resin.

  Then, as shown in FIG. 3B, a liquid resin (varnish) obtained by dissolving the same resin as the resin of the insulating resin layer 32 in a solvent is applied on the insulating resin layer 32 to form an adhesive resin layer 36. To do. When the insulating resin layer 32 is formed from a prepreg, an adhesive resin layer 36 made of the same resin as the resin contained in the prepreg is formed.

  The thickness of the adhesive resin layer 36 is preferably set to about 2 μm to 3 μm, but may be increased to about 15 μm to 20 μm.

  As described above, by forming the adhesive resin layer 36 made of the same resin on the semi-cured insulating resin layer 32, the surface of the insulating resin layer 32 can be provided with tackiness (adhesiveness). .

  Thus, the 1st resin base material 5 which has tack property provided with the insulating resin layer 32, the copper foil 34 formed in the one surface, and the adhesive resin layer 36 formed in the other surface. Create

  In addition, although the prepreg was illustrated as the insulating resin layer 32, you may use the resin sheet of a semi-hardened state (B stage), such as an epoxy resin which does not contain fiber reinforcements, such as a glass cloth. When using a resin sheet as the insulating resin layer 32, the copper foil does not need to be stuck on one side. In this case, a liquid resin (varnish) obtained by dissolving the same resin as the resin sheet in a solvent is applied on the resin sheet to form the adhesive resin layer 36.

  In addition, various thermosetting resins can be used as the insulating resin layer 32.

  Suitable examples of the solution for forming the liquid resin (varnish) include methanol, methyl ethyl ketone (MEK), methyl isobutyl ketone (MBK), dimethylformamide, dimethyl cellosolve, acetone, and a composite thereof. Selected.

  The above-mentioned solvents have boiling points at relatively low temperatures, and their boiling points are in the range of 35 ° C. or more and less than 180 ° C. In the liquid resin (varnish), it functions as an adhesive that does not volatilize at room temperature (25 ° C) and is adhesive, and the solvent is completely removed when cured at a temperature of 180 ° C or higher to form an interlayer insulating layer. This is because it preferably has the property of volatilizing.

  FIG. 4 shows a second method for creating the first resin base material. In the second method for producing the first resin substrate, as shown in FIG. 4A, first, as in FIG. 3A described above, insulation in a semi-cured state in which a copper foil 34 is pasted on one side is performed. A resin layer 32 is prepared. And the solvent S is apply | coated to the surface of the insulating resin layer 32 from the multi nozzle 14 of a spray apparatus.

  As a result, as shown in FIG. 4B, the resin on the surface of the insulating resin layer 32 is dissolved in the solvent S to form the adhesive resin layer 36. When the insulating resin layer 32 is made of a prepreg, the resin contained in the prepreg is dissolved in the solvent S, and the adhesive resin layer 36 is obtained.

  Also in the second preparation method, the solvent S for dissolving the resin is preferably the same as that described in the first preparation method, and the boiling point of the solvent is set in the same range. .

  As described above, even when the second production method is used, the adhesive resin layer 36 formed of the same resin as that on the insulating resin layer 32 can be similarly formed.

  Thus, by the second preparation method, the tackiness provided with the insulating resin layer 32, the copper foil 34 formed on one surface thereof, and the adhesive resin layer 36 formed on the other surface is provided. The 1st resin base material 5a which has is obtained.

  The first resin member 5a shown in FIG. 4B created by the second creation method has substantially the same structure as the first resin substrate 5 shown in FIG. 3B created by the first creation method. Have.

  Next, as shown in FIG. 5A, the above-described adhesive resin layer 36 of the first resin base material 5 is disposed on one surface of the core wiring board 2 provided with the opening 2a in FIG. To do. As a result, one opening of the opening 2a of the core wiring board 2 is closed.

  In this step, the core wiring board 2 may be attached to the first resin base material 5 fixed on the stage (not shown). Conversely, the first resin is applied to the core wiring board 5 fixed on the stage. The substrate 5 may be pasted. Thereby, the adhesive resin layer 36 of the first resin base material 5 is exposed in the opening 2 a of the core wiring board 2.

  Further, as shown in FIG. 5B, the chip capacitor 40 is bonded and disposed on the bonding resin layer 36 in the opening 2 of the core wiring board 2. As described above, the solvent contained in the adhesive resin layer 36 has a boiling point of 35 ° C. or higher, and thus functions as an adhesive having viscosity at room temperature (25 ° C.).

  The area of the opening 2a of the core wiring substrate 2 is formed to be slightly larger than the area of the built-in chip capacitor 40.

  The chip capacitor 40 includes a pair of connection terminals 42 at both ends in the lateral direction, and the pair of connection terminals 42 are arranged in a horizontal direction parallel to the surface of the core wiring board 2.

  The connection terminal 42 of the chip capacitor 40 is formed to extend from both side surfaces to the end portions of the upper and lower surfaces. In the example of FIG. 5B, the entire thickness of the core wiring board 2 is set to be the same as the entire thickness including the connection terminals 42 of the chip capacitor 40. Alternatively, the entire thickness of the core wiring board 2 may be set to be thicker than the entire thickness of the chip capacitor 40.

  At this time, a gap C is generated between the inner wall of the opening 2 a of the core wiring board 2 and the side surface of the chip capacitor 40. The width of the gap C is, for example, about 40 μm to 60 μm.

  As an example of the chip capacitor 40, there is a ceramic chip capacitor in which electrodes are provided at both ends in the longitudinal direction of a capacitor body made of a rectangular parallelepiped.

  Although the chip capacitor 40 is illustrated as an electronic component, various electronic components provided with connection terminals, such as a semiconductor chip, a resistance element, and an inductor element, can be used. A plurality of electronic components may be arranged in one opening 2 a of the core wiring board 2.

  Next, as shown in FIG. 5 (c), a second resin base material 6 is prepared in which a copper foil 34a is attached to one side of a semi-cured insulating resin layer 32a. The insulating resin layer 32 a of the second resin base 6 is formed from the same resin as the insulating resin layer 32 of the first resin base 5.

  As with the first resin base material 5, the insulating resin layer 32a is preferably formed from a prepreg.

  Alternatively, a semi-cured resin sheet such as an epoxy resin may be used as the insulating resin layer 32a. In this case, the copper foil 34a may be omitted and the resin sheet may be used as a single layer.

  The second resin base material 6 is an interlayer insulating material for forming an insulating layer on the upper surface side of the core wiring board 2. For this reason, unlike the 1st resin base material 5, the 2nd resin base material 6 does not need to have tackiness on the surface, and does not need to be provided with the resin layer for adhesion. However, the same structure as the first resin substrate 5 may be used as the second resin substrate 6.

  And the surface of the insulating resin layer 32a of the 2nd resin base material 6 is arrange | positioned facing the upper surface side of the core wiring board 2 with the vacuum laminator provided with the thermocompression bonding function.

  At this time, first, the adhesive resin layer 36 and the insulating resin layer 32 of the first resin substrate 5 are fluidized from the lower surface side of the core wiring base 2 by thermocompression bonding at a temperature of 130 ° C. to 150 ° C. to open the openings. It flows into the part 2a. At the same time, the insulating resin layer 32a of the second resin base 6 is fluidized from the upper surface side of the core wiring base 2 and flows into the opening 2a. Thereafter, the cured resin is fully cured at a temperature of 180 ° C. to 200 ° C.

  As a result, as shown in FIG. 6A, first interlayer insulating layers 50 that cover the first wiring layer 20 and seal the chip capacitor 40 are formed on both sides of the core wiring board 2. As described above, the boiling point of the solvent contained in the adhesive resin layer 36 of the first resin substrate 5 is less than 180 ° C.

  For this reason, the solvent in the adhesive resin layer 36 is completely volatilized by curing when the first interlayer insulating layer 50 is formed, and the adhesive resin layer 36 is formed as a part of the first interlayer insulating layer 50.

  A gap C (FIG. 5B) between the side surface of the chip capacitor 40 and the inner wall of the opening 2 a of the core wiring board 2 is buried with the filling insulating portion 50 x of the first interlayer insulating layer 50. As a result, the entire periphery of both sides and all side surfaces of the chip capacitor 40 is sealed by the first interlayer insulating layer 52. The first interlayer insulating layers 50 on both sides are formed in a state where the copper foils 34 and 34a are adhered to the respective outer surfaces.

  In the present embodiment, the adhesive resin layer 36 and the insulating resin layer 32 of the first resin base material 5 are formed from the same resin. Further, the second resin base 6 is also made of the same resin as the insulating resin layer 32 of the first resin base 5. For this reason, the chip capacitor 40 is sealed with the same resin including the gaps on the side surfaces thereof.

  As described above, since there is no adhesive of a material different from that of the first interlayer insulating layer 50 for filling around the chip capacitor 40, the occurrence of peeling and residual stress due to the difference in physical properties is suppressed. Further, an adhesive having different physical properties from the first interlayer insulating layer 50 is not pushed out onto the first wiring layer 20.

  Further, when the chip capacitor 40 is disposed in the opening 2a of the core wiring board 2, the inner wall of the opening 2a of the core wiring board 2 is not deformed, so that the insulation reliability of the core board 10 is lowered. There is nothing.

  Further, the chip capacitor 40 is bonded to the first resin base material 5 for obtaining the first interlayer insulating layer 50 with tackiness without using a temporary fixing tape. For this reason, while being able to reduce the cost of a temporary fix | stop tape, since a manufacturing process is simplified, production efficiency can be improved.

  Further, since the chip capacitor 40 is temporarily fixed to the adhesive resin layer 36 of the first resin base material 5 with sufficient adhesive force, the first and second resin base materials 5 and 6 are provided on both sides of the core wiring board 2. There is no possibility that the chip capacitor 40 is displaced during thermocompression bonding. For this reason, all the side surfaces of the chip capacitor 40 are reliably sealed with the filling resin portion 50x.

  In addition, since the first interlayer insulating layers 50 are symmetrically arranged on both sides of the core wiring board 2, even if thermal stress is generated during the heat treatment, the occurrence of warpage is suppressed.

  When the chip capacitor 40 is bonded to the bonding resin layer 36 more strongly in order to prevent the displacement of the chip capacitor 40, the bonding is performed by preheating at a temperature of about 100 ° C. in the process of FIG. 5B. May be.

  Next, as shown in FIG. 6B, the copper foils 34 and 34 a and the first interlayer insulating layer 50 are processed with a laser or the like on both sides of the core wiring board 2. Thus, the first via holes VH1 reaching the connection terminals 42 of the chip capacitors 40 and the connection portions of the first wiring layers 20 are formed on both sides of the core wiring board 2, respectively. Alternatively, the first interlayer insulating layer 50 may be formed from a photosensitive resin, and the first via hole VH1 may be formed by photolithography.

  As described above, in the present embodiment, the technique of fixing the side surface of the chip capacitor 40 to the inner wall of the opening 2 of the core wiring board 2 with an adhesive is not used. For this reason, an adhesive having different physical properties from the first interlayer insulating layer 50 is not pushed onto the first wiring layer 20, so that the first via hole VH 1 can be formed with high reliability.

Subsequently, as shown in FIG. 6 (c), copper foils 34, 34 are formed on both sides of the core wiring board 2.
A seed layer 22a made of copper or the like is formed by electroless plating on a and on the inner surface of the first via hole VH1.

  Next, as shown in FIG. 7A, on both sides of the core wiring board 2, a plating resist layer 16 provided with openings 16a in portions where the second wiring layer is disposed is formed by photolithography. Further, on both sides of the core wiring board 2, a metal plating layer 22 b is formed in the opening 16 a of the plating resist layer 16 by electrolytic plating using the seed layer 22 a as a plating power feeding path.

  Thereafter, the plating resist layer 16 is peeled off. Subsequently, on both sides of the core wiring board 2, the seed layer 22a and the copper foils 34 and 34a are removed by wet etching using the metal plating layer 22b as a mask.

  As a result, as shown in FIG. 7B, the second wiring layers 22 are formed on the first interlayer insulating layers 50 on both sides of the core substrate 10, respectively. As shown in the partial cross-sectional view of FIG. 7B, the second wiring layer 22 on the upper surface side is formed by laminating a copper foil 34a, a seed layer 22a, and a metal plating layer 22b in order from the bottom.

  The second wiring layers 22 on both sides are connected to the connection terminal 42 of the chip capacitor 40 and the first wiring layer 20 via via conductors in the first via hole VH1. In the present embodiment, since there is no possibility that the adhesive remains in the first via hole VH1, the connection terminal 42 of the chip capacitor 40 and the second wiring layer 22 can be electrically connected reliably.

  Next, as shown in FIG. 7C, the second interlayer insulating layer 52 covering the second wiring layer 22 is formed on the first interlayer insulating layer 50 on both sides. The second interlayer insulating layer 52 is formed, for example, by thermocompression bonding a semi-cured resin sheet such as an epoxy resin. Further, second via holes VH2 reaching the second wiring layer 22 are formed in the second interlayer insulating layers 52 on both sides by laser processing or the like.

  Thereafter, the third wiring layers 24 connected to the second wiring layer 22 through the via conductors in the second via holes VH2 are respectively formed on the second interlayer insulating layers 52 on both sides. The third wiring layer 24 is formed by, for example, a semi-additive method.

  Next, as shown in FIG. 8, solder resist layers 54 each having an opening 54 a on the connection portion of the third wiring layer 24 are formed on the second interlayer insulating layers 52 on both sides. Further, a contact layer (not shown) is formed by forming a nickel / gold plating layer at the connection portion of the third wiring layer 24.

  Thus, the electronic component built-in substrate 1 of the embodiment is obtained. In addition, when using the large core wiring board 2 for multi-surface drawing, it divides | segments so that each board | substrate 1 with a built-in electronic component may be obtained from each product area | region.

  FIG. 9 shows a state in which a semiconductor chip is mounted on the electronic component built-in substrate 1 of FIG. As shown in FIG. 9, the connecting portion of the semiconductor chip 60 is flip-chip connected to the third wiring layer 24 on the upper surface side of the electronic component built-in substrate 1 of FIG. 8 via bump electrodes 62 such as solder.

  Thereafter, the underfill resin 64 is filled in the gap between the semiconductor chip 60 and the electronic component built-in substrate 1.

  Further, external connection terminals 66 are formed by mounting solder balls on the connection portions of the third wiring layer 24 on the lower surface side of the electronic component built-in substrate 1.

  In the example of FIG. 9, the chip capacitor 40 of the electronic component built-in substrate 1 is disposed as a decoupling capacitor between the power supply line and the ground line for the purpose of stabilizing the power supply voltage of the semiconductor chip 60 and reducing high frequency noise. The

  In the present embodiment, the combination in which the chip capacitor 40 is built in the core wiring board 2 and the semiconductor chip 60 is mounted on the surface is illustrated, but the present invention can be applied to combinations of various electronic components.

DESCRIPTION OF SYMBOLS 1 ... Electronic component built-in board, 2 ... Core wiring board, 2a, 16a, 54a ... Opening part, 5, 5a ... 1st resin base material, 6 ... 2nd resin base material, 10 ... Core substrate, 12 ... Resist layer, DESCRIPTION OF SYMBOLS 14 ... Multi nozzle, 16 ... Plating resist layer, 20 ... 1st wiring layer, 20a ... Through-hole plating layer, 20b, 22b ... Metal plating layer, 22 ... 2nd wiring layer, 22a ... Seed layer, 24 ... 3rd wiring Layer 32, insulating resin layer 34, 34a copper foil 36 adhesive resin layer 40 chip capacitor 42 connection terminal 50 first interlayer insulating layer 50x filling resin portion 52 second Interlayer insulating layer 54... Solder resist layer 60. Semiconductor chip 62 62 Bump electrode 64. Underfill resin 66. External connection terminal C Crevice R Resin body S Solvent TH Through hole VH1 ... first via hole, VH2 ... second via hole.

Claims (7)

Preparing a substrate provided with an opening;
A semi-cured first insulating resin layer;
A liquid adhesive resin formed on the first insulating resin layer, comprising the same resin as the first insulating resin layer and a solvent for dissolving the resin, wherein the solvent has a boiling point of 35 ° C. or higher and lower than 180 ° C. Preparing a first resin base material including a layer;
Disposing an adhesive resin layer of the first resin base on one surface of the substrate and closing one opening of the opening of the substrate;
Bonding an electronic component to the adhesive resin layer in the opening of the substrate at room temperature ;
A second resin base material including a semi-cured second insulating resin layer is disposed on the other surface of the substrate, heat-pressed from both sides of the substrate, and the adhesive resin layer by heat treatment at a temperature of 180 ° C. or higher. And a step of forming an insulating layer for sealing the electronic component on both sides of the substrate by volatilizing the solvent contained in the substrate. In the process of thermocompression bonding from both sides of the substrate,
2. The electronic component according to claim 1, wherein the adhesive resin layer , the first insulating resin layer, and the second insulating resin layer flow into the opening of the substrate to seal the electronic component. A method for manufacturing a built-in substrate. In the step of preparing the first resin base material,
The adhesive resin layer of the first resin substrate is
3. The method according to claim 1, wherein the first insulating resin layer is obtained by applying a liquid resin in which the same resin as the first insulating resin layer is dissolved in the solvent on the semi-cured first insulating resin layer. The manufacturing method of the electronic component built-in board of description. In the step of preparing the first resin base material,
The adhesive resin layer of the first resin substrate is
The solvent is applied on the semi-cured first insulating resin layer, and the resin on the surface of the first insulating resin layer is obtained by dissolving in the solvent. Manufacturing method for electronic component embedded substrate.   5. The solvent according to claim 1, wherein the solvent is any one of methanol, methyl ethyl ketone, methyl isobutyl ketone, dimethylformamide, dimethyl cellosolve, acetone, and a composite thereof. Manufacturing method of electronic component built-in substrate. In the step of preparing the first resin base material,
The first insulating resin layer of the first resin base is formed from a prepreg, and a copper foil is pasted on the surface of the first insulating resin layer opposite to the surface on which the adhesive resin layer is formed. The manufacturing method of the electronic component built-in substrate as described in any one of Claims 1 thru | or 5 . The substrate is a wiring substrate having a first wiring layer on both sides;
The electronic component is a chip capacitor,
After the step of forming the insulating layer,
Forming via holes reaching the connection terminals of the chip capacitors and the first wiring layers in the insulating layers on both sides of the substrate;
And forming a second wiring layer connected to the connection terminal and the first wiring layer through the via hole on the insulating layers on both sides of the substrate, respectively. The method for manufacturing an electronic component built-in substrate according to claim 6 .

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