JP6266424B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to an oscillation circuit, and more particularly to an oscillation circuit that oscillates by using charge / discharge of a capacitive element.

  In an oscillation circuit used for a clock source in an IC or the like, there is a technique described in JP 2005-217762 A (Patent Document 1) in order to obtain an oscillation period that does not depend on a power supply voltage and temperature. According to this publicity, “the voltage at one end of the capacitive element C 1 is a constant voltage (V I H −V th, V th −V I) that is not influenced by the power supply voltage and temperature, centering on the threshold voltage V th. L 1), and at one end of the capacitive element C 1, the constant currents I p and I n that are not influenced by the power supply voltage and temperature flow in and out, so that charging and discharging are performed for a certain time. The voltage at one end of the capacitive element C 1 changes at a constant cycle without being affected by the power supply voltage and temperature. ”

JP 2005-217762 A

  As described above, if the voltage amplitude of the charge / discharge capacitance is shaken at a constant voltage, an oscillation period that does not depend on the power supply voltage can be obtained, but if the power supply voltage range required for the oscillation circuit is wide, the required minimum power supply voltage Therefore, it is necessary to design the voltage amplitude to be small so that it can be shaken with a constant amplitude even under the above conditions.

  However, when the voltage amplitude for charging / discharging is set to a small amplitude, the charging / discharging voltage continues to fluctuate in the vicinity of the threshold value of the comparator circuit under the condition that the power supply voltage is high.

  In Patent Document 1, “the threshold voltage is determined by the resistance ratio between the source and the drain of the internal N-channel transistor and the P-channel transistor.” Therefore, when the through-current is large near the threshold voltage and the power supply voltage is particularly high. The increase in current consumption was remarkable.

Accordingly, an object of the present invention is to provide an oscillation circuit that reduces through current and has low temperature and voltage dependency.

In order to solve the above problems, one of the typical circuit configurations of the present invention is to eliminate a through current by using a comparator circuit that limits a current for threshold judgment in an oscillation circuit that uses charge and discharge of a capacitive element. In addition, a voltage limit circuit is used for setting the charge / discharge voltage, and the power supply voltage dependency is suppressed.

  According to the present invention, it is possible to obtain a clock source in which through current is suppressed and temperature and power supply voltage dependence is small.

Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

1 is a block diagram illustrating a configuration example of an oscillation circuit according to a first embodiment. 2 is a timing chart showing an oscillation operation with the configuration of FIG. 1. A circuit diagram showing an example of composition of an oscillation circuit by a 2nd embodiment. The circuit diagram which shows the structural example of the current source used for an oscillation circuit. A circuit diagram showing an example of composition of an oscillation circuit by a 3rd embodiment. The circuit diagram which shows the structural example of the oscillation circuit by 4th Embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of an oscillation circuit according to a fifth embodiment. The block diagram which shows the structural example of the oscillation circuit by 6th Embodiment. A circuit diagram showing an example of composition of an oscillation circuit by a 6th embodiment. The block diagram which shows the structural example of the oscillation circuit by 7th Embodiment. A circuit diagram showing an example of composition of an oscillation circuit by a 7th embodiment. The block diagram which shows the structural example of the oscillation circuit by 8th Embodiment. The block diagram which shows another structural example of the oscillation circuit by 8th Embodiment.

  Hereinafter, examples will be described with reference to the drawings.

(Minimum configuration block diagram)
The configuration of the oscillation circuit 1 according to this embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram illustrating a configuration example of the oscillation circuit 1.

  The oscillation circuit 1 compares the voltage at the node A with an arbitrary threshold value and outputs the result to the node B. The comparator circuit 1 that is current limited by the current source 2 receives the voltage at the node B, A voltage limit circuit 3 that outputs to the node C with a constant voltage amplitude regardless of temperature, a capacitive element 7 having one end connected to the node A and the other end connected to the node C, and a power source for the capacitive element The voltage level of the node C includes a current source 4 for supplying a constant charging current IC1 independent of voltage and temperature, a current source 5 for supplying a constant discharge current IC2 independent of power supply voltage and temperature to the capacitive element, and A switch circuit 6 is provided for connecting the current source 4 and the node A when the level is low, and for connecting the current source 5 and the node A when the voltage level of the node C is high.

  The operation of the above-described oscillation circuit 1 will be described with reference to FIG.

  FIG. 2 is a timing chart showing the operation of the oscillation circuit.

  If the voltage at the node A is higher than the threshold voltage (VTH) of the comparator 1, the comparator 1 outputs a low level (VL1) to the node B, and the voltage limit circuit receives this and is limited in amplitude to the node C. A high level (VH2) is output. When the potential of the node C rises from the low level (VL2) to the high level (VH2), the potential of the node A increases to VTH + (VH2−VL2) via the capacitor 7, and the switch circuit 6 indicates that the node C is high. In the case of the level (VH2), the node A is connected to the current source 5 through which the discharge current flows, so that the voltage level of the node A decreases with a constant slope determined by the discharge current and the capacitive element 7, and the threshold voltage of the comparator 1 (VTH) is reached.

  When the voltage level of the node A falls below the threshold voltage (VTH), the comparator 1 outputs a high level (VH1) to the node B, and the voltage limit circuit receives this and the low level (VL2) whose amplitude is limited to the node C. Is output. When the potential of the node C is lowered from the high level (VH2) to the low level (VL2), the potential of the node A is decreased to VTH− (VH2−VL2) through the capacitor element 7, and the switch circuit 6 In the case of the low level (VL2), since the node A is connected to the current source 4 through which the charging current flows, the voltage level of the node A increases with a constant slope determined by the charging current and the capacitor element 7, and the threshold value of the comparator 1 The voltage (VTH) is reached.

  The above operation is repeated to oscillate.

  Here, in the comparator circuit 1, since the current source 2 is connected in series between the power supply and GND, the maximum current consumption is limited. For example, when the comparator circuit 1 is composed of a switch connected in series between the power source and the current source 2, the current consumption of the comparator circuit 1 is consumed by the current limited by the current source 2 when the output is at a high level. When the output is low level, no current flows. In the figure, the effect of reducing the current consumption can be seen in comparison with the through current when the CMOS inverter indicated by the broken line is used. If a constant current source that does not depend on the power source voltage is selected as the current source 2, even if the power source voltage is high, current consumption does not increase.

  According to this embodiment, it is possible to reduce current consumption as compared with a comparator using a CMOS inverter.

Note that the high-level and low-level polarities of the signal at the node B shown in the timing chart of FIG. 2 are examples, and a configuration in which signals are output with inverted polarities can be included in the embodiments.

(Minimum configuration MOS level circuit)
The configuration of the oscillation circuit 1 according to this embodiment will be described with reference to FIGS.

  FIG. 3 is a circuit diagram showing a configuration example of the oscillation circuit 1 of the present embodiment.

  The oscillation circuit includes a PMOS transistor (MP) 1 having a gate terminal connected to a node A, a source terminal connected to a power supply, a drain terminal connected to a node B, one end connected to the node B, and the other end connected to the node B. An NMOS having a current source 2 connected to the GND potential, a gate terminal connected to the node B, a source terminal connected to the other end of the current source 11 having one end connected to the GND potential, and a drain terminal connected to the node C. A transistor (MN) 1; a resistance element R1 having one end connected to the node C and the other end connected to the power supply potential VDD; an inverter 10 that receives the node B as an input and outputs the inverted signal to the node C2, and a gate terminal; Connected to the node C2, has a source terminal connected to the other end of the current source 4 whose one end is connected to the power supply potential VDD, MP2 whose drain terminal is connected to the node A, and a gate. The terminal is connected to the node C2, the source terminal is connected to the other end of the current source 5 having one end connected to the GND potential, the drain terminal is connected to the node A, and one end is connected to the node A. And a capacitive element 7 having the other end connected to the node C.

  The PMOS transistor MP1 constitutes a comparator circuit whose input is connected to the node A. The PMOS transistor MP1 is turned off when the potential of the node A is higher than the threshold voltage VTH (MP1) specific to MP1, and the reference voltage GND is output to the node B. If the voltage is lower than the threshold voltage VTH (MP1), the signal is turned on, and the power supply voltage VDD is output to the node B.

  The NMOS transistor MN1 has a source terminal connected to a current source 11 for passing a current inversely proportional to the resistance value of R1, and the potential of the node B connected to the gate terminal is higher than the threshold voltage VTH (MN1) unique to MN1. If the power supply voltage is VDD and the charging current is IC1, the low level (VL2) that is (VL2 = VDD−R1 × (IR1−IC1)) is output to the node C. If it is lower than the threshold voltage VTH (MN1), it is turned OFF. Here, assuming that the discharge current is IC2, a high level (VH2) of (VH2 = VDD−R1 × IC2) is output to the node C.

  If the current value is selected so that IC1 = IC2 << IR1, the voltage amplitude output to the node C is expressed as VH2-VL2 = R1 × IR1, and IR1 is controlled to be inversely proportional to R1. Therefore, a constant voltage amplitude that is not affected by the power supply voltage of R1 and temperature fluctuation can be obtained.

  On the other hand, since the inverter 10 inverts and outputs the voltage level of the node B to the node C2, when the node C is at the high level (VH2), the inverter 10 outputs VDD to the node C2, and the node C is at the low level (VL2). Sometimes GND is output to the node C2.

  MP2 and MN2 constitute a switch for switching the charging / discharging current. When the node C2 is VDD, MP2 is turned off and MN2 is turned on. Therefore, the potential of the node A to which one end of the capacitive element 7 is connected is When discharged by the discharge current IC2 and the node C2 is GND, MP2 is turned on and MN2 is turned off, so that the potential of the node A is charged by the charge current IC1.

  FIG. 4 is a circuit diagram illustrating a configuration example of a current source of the oscillation circuit 1.

  The current source has a specific accuracy as compared with the operational amplifier OPA, a constant reference voltage VREF not affected by power supply voltage / temperature, a resistance element RREF1 not affected by power supply voltage / temperature, and the resistance element R1 shown in FIG. The resistor element RREF2 arranged in such a manner, a current mirror circuit composed of a PMOS transistor PM, and a current mirror circuit composed of an NMOS transistor NM are provided.

  MP20 has a source terminal connected to the power supply voltage and a drain terminal connected to RREF1. The OPA1 controls the gate voltage of the MP20 so that the terminal voltage of the RREF1 becomes equal to the VREF1, and a current of VREF1 / RREF1 flows through the MP20. MP21 and MP22 constitute a current mirror circuit in which MP20 and a gate terminal are connected in common, and MP22 is used as the charging current source 4 which is not affected by the power supply voltage and temperature. MN20, M21, and MN22 also constitute a current mirror circuit. MN20 mirrors the current received from MP21, and uses MN21 and M22 as discharge current source 5 and current source 2.

  With the same configuration, the MN 24 is used as a current source that is inversely proportional to RREF2, which is VREF2 / RREF2.

According to this embodiment, the through current can be limited by an oscillation circuit that is not affected by the power supply voltage and temperature with a simple circuit configuration.

(Resistance temperature dependence reduction effect due to charge current cancellation in minimum configuration)
The configuration of the oscillation circuit 1 of this embodiment will be described with reference to FIG.

  FIG. 5 is a circuit diagram showing a configuration example of the oscillation circuit 1 of the present embodiment.

  In this embodiment, a current source 21 is further connected to the source terminal of MN1 with respect to the circuit diagram shown in the second embodiment. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 3 and have not been described.

  Here, the current value of the current source 21 is set to the sum of the current value (IC1) of the charging current source 4 and the current value (IC2) of the discharge current source 5. At this time, the low level voltage (VL2) output to the node C is VL2 = VDD−R1 × (IR1 + IC1 + IC2−IC2), while the high level voltage (VH2) is VH2 = VDD−R1 × IC1. Therefore, the voltage amplitude of the node C is (VH2−VL2) = R1 × IR1, and the influence of the charge / discharge currents IC1 and IC2 can be canceled.

According to this embodiment, the current consumption of the voltage limiter circuit is reduced by canceling the influence of the charging / discharging current at the node C, and the accuracy of the voltage amplitude is improved.

(Minimum configuration with reduced output impedance)
The configuration of the oscillation circuit 1 of this embodiment will be described with reference to FIG.

  FIG. 6 is a circuit diagram showing a configuration example of the oscillation circuit 1 of the present embodiment.

  In this embodiment, a source follower circuit composed of MN3 and a current source 31 is added to the circuit diagram shown in the second embodiment. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 3 and have not been described.

  In the circuit of FIG. 3 described above, the output resistance viewed from the node C of the voltage limit circuit composed of R1, MN1, and current source 11 is R1 when the output resistance of the current source is sufficiently larger than R1. Therefore, the voltage transition speed of the node C is limited by the time constant that is the product of R1 and the capacitive element 7. In particular, when the current of the current source 11 is reduced, the resistance value of R1 must be increased in order to ensure a constant voltage amplitude, so that the speed decreases and it is difficult to obtain a relatively high oscillation frequency. Become.

  In the circuit of FIG. 6, the output resistance of the voltage limit circuit output composed of MN3 and the current source 31 viewed from the node C is as follows. From the characteristics of the source follower circuit, when the transconductance of MN3 is gm (MN3), the output resistance = It is mainly determined by 1 / gm (MN3), and the potential of the node C is determined from the potential of the node D. Since gm (MN3) can be changed depending on the aspect ratio of the MOS, the output resistance value can be lowered than the resistance for the same voltage amplitude and current value. Therefore, the oscillation frequency can be increased as compared with the circuit of FIG.

According to this embodiment, the source follower circuit makes the voltage waveform of the node C steep and a relatively high oscillation frequency can be obtained.

(Minimum output impedance reduction + current cancellation effect)
The configuration of the oscillation circuit 1 of this embodiment will be described with reference to FIG.

  FIG. 7 is a circuit diagram showing a configuration example of the oscillation circuit 1 of the present embodiment.

  In this embodiment, a switch composed of MP3 and MN4 and an inverter 33 are added to the circuit diagram shown in the fourth embodiment. Other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 6 and have not been described.

  The inverter 33 is added to invert the voltage level of the node C2. Therefore, when the node C2 is at a low level, MP2 and MN4 are turned on, and MN2 and MP3 are turned off. Therefore, the charging current IC1 flows into the capacitive element 7 through MP2 and further flows into the discharge current source 5 through MN4. . On the other hand, when node C2 is at a high level, MP3 and MN2 are turned on, and MP2 and MN4 are turned off. Therefore, discharge current IC2 draws current from capacitive element 7 through MN2, and further draws from charge current source 4 through MP3. Take a route. At this time, if IC1 = IC2 is set, the influence of the charge / discharge current flowing into the source terminal of MN3 can be canceled.

According to this embodiment, it is possible to further improve the accuracy of the voltage amplitude while making the voltage waveform steep by the source follower circuit.

(Charging single differential configuration, no threshold voltage difference and no delay between paths + speed improvement)
The configuration of the oscillation circuit 1 of the present embodiment will be described with reference to FIGS.

  FIG. 8 is a block diagram illustrating a configuration example of the oscillation circuit 1 of the present embodiment.

  The oscillation circuit 1 compares the voltage at the node A with an arbitrary threshold value, and outputs a differential voltage to the node B1 and the node B2. The comparator circuit 52 is current-limited by the current source 2, and the node B1. And the voltage limit circuit 53 that receives the differential voltage of B2 and drives the node C1 with a constant voltage amplitude regardless of the power supply voltage and temperature, and outputs the differential voltage to the nodes C1 and C2, and the node C1. And a single output charge / discharge current switching circuit 51 that receives the differential voltage of the node C2 and outputs a current to the node A.

  FIG. 9 is a circuit diagram showing a configuration example of FIG.

  The charge / discharge current switching circuit 51 includes PMOS transistors MP50 to MN51, NMOS transistors MN50 to MN51, and a current source 5 that is not affected by temperature and power supply voltage. Here, the potential of the node C1 is set to VC1, If the potential of the node C2 is VC2 and the differential voltage between the nodes C1-C2 is VC_DIFF = (VC1-VC2), if VC_DIFF> 0, the MN50 is turned on, the MN51 is turned off, and the MN51 is turned off. As a result, MP51 and MP50 constituting the current mirror are also turned OFF, and the node A is discharged by the current of the current source 5. If VC_DIFF <0, MN50 is turned off, MN51 is turned on, and when MN51 is turned on, MP51 and MP50 mirror the current flowing in MN51 to MP50, and node A is charged with the mirror current.

  The comparator circuit 52 includes a differential pair including resistors R50 to R51, NMOS transistors MN52 to MN53, and a current source 2, and a voltage source VTH50. Here, the potential of the node B1 is set to VB1, and the node If the potential of B2 is VB2, and the differential voltage between the nodes B1 and B2 is (VB_DIFF) = (VB1−VB2), if the voltage of the node A is higher than VTH50, VB_DIFF <0 is output, and the node A If the voltage is lower than VTH50, VB_DIFF> 0 is output. Further, since the current consumption is limited by the current source 2, the current consumption is always set by the current source 2 regardless of the power supply voltage, and a large through current does not flow.

  The voltage limit circuit 53 includes resistors R52 to R53, NMOS transistors MN54 to MN55, a current source 11 that passes a current IR1 that is inversely proportional to the resistors R52 to R53, and a current source 21 that is the sum of the charging and discharging currents. If VB_DIFF <0, VC_DIFF> 0, and if VB_DIFF> 0, VC_DIFF <0. In particular, the voltage amplitude of the node C1 is (R52 × IR1) due to the same effect as in the third embodiment, and is a constant voltage amplitude determined by R52 and IR1.

  When the voltage of the node C is fixed to a small amplitude in order to eliminate the influence of the power supply voltage in the circuit described in Patent Document 1 or the single input / output circuit configuration as shown in FIG. Since the voltage amplitude enough to switch between MP2 and MN2 shown in FIG. 2 cannot be obtained, buffering by the inverter 10 is necessary. In this case, the oscillation operation is performed by two paths, that is, the feedback path 1 that is node B → C → A → B and the feedback path 2 that is node B → C2 → A → B. Since the signal switching timing differs depending on the difference between the voltage threshold value of the inverter 10 and the voltage threshold value of the MN1 in the drawing as well as the delay time difference between the paths, it is necessary to adjust the delay time between the paths and the threshold voltage.

  Therefore, by setting the charge / discharge current switching circuit 51 and the voltage limit circuit 53 as differential inputs, the voltage amplitude required for the switching operation can be smaller than that of the single input, so the output of the voltage limit circuit is directly charged / discharged. It can be input to the switching circuit, and there is no need to consider the delay between paths due to the threshold voltage difference. In addition, since the output voltage of the comparator circuit may be a small amplitude, it is possible to increase the speed by a relatively small amplitude voltage input as compared with the case where the output is fully swung up to VDD-GND.

  According to this embodiment, the delay time between paths due to the threshold voltage difference can be eliminated, so that the design is simplified and a high oscillation frequency can be obtained by small amplitude signal transmission.

Note that the circuit configuration of the comparator circuit 52 illustrated in FIG. 9 is an example, and the resistors R50 to R51 may include an active load using transistors. Moreover, any of the said Examples 3-5 can be included as the cancellation method of the charging / discharging electric current of a voltage limit circuit. The active loads MP50 and MP51 of the charge / discharge current switching circuit 51 can also include a current source load.

(Fully differential configuration, noise removal capability UP effect)
The configuration of the oscillation circuit 1 of this embodiment will be described with reference to FIGS.

  FIG. 10 is a block diagram illustrating a configuration example of the oscillation circuit 1 according to the present embodiment.

  In the present embodiment, a single output charge / discharge current switching circuit 51 is replaced with a fully differential input / output charge / discharge current switching circuit 61 in FIG. Is replaced with a fully differential input / output comparator circuit 62, and a capacitive element 64 is further added. Other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 8 described above, and thus the description thereof is omitted.

  FIG. 11 is a circuit diagram showing a configuration example of FIG.

  The charge / discharge current switching circuit 61 includes current sources 65 and 66 that allow a constant current to flow regardless of the power supply voltage and temperature, the MN51, MN50, and the current source 5. Here, the current sources 65 and 66 are provided. If VC_DIFF <0, the MN50 is turned off, the MN51 is turned on, and the node A1, which is one end of the capacitor element 7, is set to be the current value of the current source 5 (IC1). The battery is charged with a constant current of (IC / 2), and the node A2 which is one end of the capacitor 64 is discharged with a constant current of (IC−IC / 2) = IC / 2. If VC_DIFF> 0, MN50 is turned on, MN51 is turned off, node A1 is discharged with a constant current of (IC−IC / 2) = IC / 2, and node A2 is discharged with a constant current of IC / 2. Charge.

  The capacitive element 64 has the same capacitance value as the capacitive element 7.

  The comparator circuit 62 is obtained by removing the voltage source VTH50 from the comparator circuit 52 of FIG. 9, and connects the gate terminal of the MN53 to the node A2 instead of the voltage source VTH50. The potential of the node A1 is VA1, and the node A2 Is A2 and the differential voltage between nodes A1-A2 is VA_DIFF = (VA1-VA2), VA_DIFF> 0 is output if VA_DIFF <0, and VB_DIFF <0 if VA_DIFF> 0. 0 is output.

  The voltage limit circuit 63 sets the resistance values of the resistors R52 and R53 to R52 = R53 = RD, the current value of the current source 11 to IR1, the potential of the node C1 to VC1, the potential of the node C2 to VC2, and the node C1- If the differential voltage between C2 is VC_DIFF = (VC1-VC2), the same effect as in the third embodiment is obtained. If VB_DIFF <0, a constant voltage VC_DIFF = RD × IR1 is output, and VB_DIFF> If 0, a constant voltage of VC_DIFF = −RD × IR1 is output.

  According to this embodiment, since all the feedback loops are transmitted as differential signals, high resistance to external noise can be obtained.

Note that the circuit configuration of the comparator circuit 62 illustrated in FIG. 11 is an example, and the resistors R50 to R51 may include an active load using transistors. Moreover, any of the said Examples 3-5 can be included as the cancellation method of the charging / discharging electric current of a voltage limit circuit.

(When incorporating the oscillation circuit of the present invention into a system)
The configuration of the integrated circuit including the oscillation circuit 1 according to this embodiment will be described with reference to FIGS.

  FIG. 12 is a block diagram illustrating a configuration example of an integrated circuit.

  The integrated circuit includes a regulator circuit that receives a battery voltage and controls a power supply voltage of the internal circuit, an internal circuit that operates according to an output voltage of the regulator circuit, and the oscillation circuit 1.

  FIG. 13 is a block diagram illustrating another configuration example of the integrated circuit.

  The integrated circuit includes a regulator circuit that receives a battery voltage and controls a power supply voltage of the internal circuit, an internal circuit that operates according to an output voltage of the regulator circuit, and the oscillation circuit 1 that operates when the battery voltage is input. Prepare.

  In the oscillation circuit 1, since the accuracy of the oscillation frequency is mainly determined by the reference voltage and the reference current, and the consumption current is limited by the current value of the current source, the characteristics viewed from the outside of the circuit are shown in FIGS. Both are equivalent.

Therefore, according to the oscillation circuit 1, the regulator circuit is not required to have relatively high accuracy, and may not be required. In particular, in the configuration example of FIG. 13, the regulator circuit can be used as a backup clock that operates even when a normal voltage cannot be output.

In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.

1 ... Comparator circuit,
2, 4, 5, 11, 21, 31, 65, 66 ... current source,
3 ... Voltage limit circuit,
6 ... Switch circuit,
7, 64 ... capacitive element,
10: Inverter circuit,
51. Charge / discharge current switching circuit,
52. Differential output comparator circuit,
53. Fully differential input / output voltage limit circuit,
MN1-3, MN20-24, MN50-55 ... NMOS transistors,
MP1-3, MP20-24, MP50-51 ... PMOS transistor,
OPA1-2 ... inverting amplifier,
R1, R50 to 53, RREF1-2, resistance element,
VREF1-2 ... reference voltage VTH50 ... voltage source

Claims (7)

In an oscillation circuit that is driven by a battery voltage and oscillates using charge / discharge of a capacitive element,
A differential comparator circuit that outputs a result obtained by comparing a voltage at one end of the capacitive element with a threshold voltage, the current consumption of which is limited by a current source;
In accordance with the voltage output from the comparator circuit, the voltage limit circuit that drives the other end of the capacitive element with a constant voltage amplitude without being affected by the power supply voltage and temperature;
A constant current source that flows into one end of the capacitive element or flows out from one end of the capacitive element according to a voltage output from the comparator, a constant current that is not affected by a power supply voltage and temperature. An oscillation circuit characterized by. The voltage limit circuit includes a current source that is connected in parallel with the other current source that supplies a current inversely proportional to the resistive load, and that supplies a sum of current flowing into and out of the capacitive element. The oscillation circuit according to claim 1 . 2. The oscillation circuit according to claim 1 , wherein the voltage limit circuit includes a source follower circuit having one end of the resistive load and the drain of the transistor as inputs and the other end of the capacitive element as an output. . A constant current source circuit that flows into or out of one end of the capacitive element includes a current source 1 having one end connected to the power source and the other end connected to the source of the PMOS transistor 1;
A current source 2 having one end grounded and the other end connected to the source of the NMOS transistor 1;
The PMOS transistor 1 has a source connected to the current source 1, a drain connected to one end of the capacitive element and the drain of the NMOS transistor 1, a source connected to the other end of the current source 2, and a gate connected to the PMOS transistor. The NMOS transistor 1 is connected to the gate of No. 1, the switch voltage having the same phase as the output polarity of the voltage limit circuit, the source is connected to the other end of the current source 1, and the drain is the other end of the capacitive element. And the PMOS transistor 2 connected to the drain of the NMOS transistor 2, the source is connected to the other end of the current source 2, the gate is connected to the gate of the PMOS transistor 2, and the output polarity of the voltage limit circuit is opposite to that of the PMOS transistor 2. and the NMOS transistor 2 switch voltage is input, according to claim 1, characterized in that it comprises a Fukairo. The comparator circuit has one input terminal for detecting a voltage at one end of the capacitive element, and a differential output terminal,
The voltage limit circuit has a differential input terminal and a differential output terminal,
Constant current source circuit into or out to one end of said capacitive element has an input terminal of the differential, and one current output terminal, claim 2, characterized in that it comprises a to any one of claims 4 The oscillation circuit described. The comparator circuit has a differential input terminal and a differential output terminal, and the voltage limit circuit has a differential input terminal and a differential output terminal,
A constant current source circuit that flows into or out of one end of the capacitive element has a differential input terminal and a differential output terminal,
The capacitive element has one end connected to the differential output terminal of the voltage limit circuit, and the other end connected to the differential input terminal of the comparator circuit having the same polarity as the differential output terminal. the oscillator circuit as claimed in any one of the preceding claims 2, characterized in that it comprises two capacitive elements forming a pair, the. 7. The oscillator circuit according to claim 1, wherein the oscillator circuit is applied to an integrated circuit driven by a battery voltage, and a regulator circuit may or may not be used for a power supply voltage of the oscillator circuit . The oscillation circuit according to item 1 .

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