JP6266248B2 - Semiconductor device, discharge control system, and control method - Google Patents

Description

  The present invention relates to a semiconductor device, a discharge control system, and a control method.

  Conventionally, a secondary battery that can be repeatedly used by charging is known. In a system that requires a high DC voltage, an assembled battery including a plurality of secondary batteries connected in series is used. Each secondary battery included in the assembled battery is called a single cell or a battery cell. A discharge circuit having a resistor and a transistor is connected in parallel to each of the plurality of battery cells included in the assembled battery. The transistor is on / off controlled according to the voltage of each battery cell (battery cell terminal voltage). Thereby, the voltage of each battery cell is adjusted (for example, refer patent documents 1-3).

JP 2007-218680 A JP 2006-53120 A JP 2004-248348 A

  By the way, in the case of a battery cell having a low voltage, it may be impossible to turn on the transistor of the discharge circuit to discharge the battery cell to a desired voltage.

  According to an aspect of the present invention, there is provided a semiconductor device connected to control terminals of a plurality of discharge transistors for discharging each battery cell of a battery pack in which a plurality of battery cells are connected in series, and a plurality of drive signals And a plurality of drive circuits for outputting a drive voltage for driving the plurality of discharge transistors, each of the plurality of drive circuits having an output terminal connected to an external output terminal to which a control terminal of the discharge transistor is connected A buffer circuit to which the drive signal is supplied, and a first switch circuit for supplying the buffer circuit with a first voltage at a first external input terminal to which a positive electrode of the corresponding battery cell is connected. And a second switch circuit for supplying a second voltage higher than the first voltage to the buffer circuit, and based on the first voltage or the second voltage Generating the driving voltage.

  According to one aspect of the present invention, a battery cell can be discharged.

It is a schematic explanatory drawing of a discharge control system. It is a partial circuit diagram of a discharge control device. It is a flowchart which shows discharge control. It is a wave form diagram which shows operation | movement of a discharge control system. It is a wave form diagram which shows operation | movement of a discharge control system.

Hereinafter, an embodiment will be described.
As shown in FIG. 1, a discharge circuit 20 is connected to the assembled battery 10, and the assembled battery 10 and the discharge circuit 20 are connected to a discharge control system 30. The discharge control system 30 includes a monitoring device 31 and a host device 32. The monitoring device 31 is an example of a semiconductor device, and the host device 32 is an example of a discharge control device.

  The assembled battery 10 includes n (five in FIG. 1) battery cells BC1 to BC5. Battery cells BC1 to BC5 are connected in series. The battery cells BC1 to BC5 are, for example, lithium ion batteries. The assembled battery 10 has (n + 1) (six in FIG. 1) external terminals P11 to P16 corresponding to the battery cells BC1 to BC5. The external terminal P11 is connected to the negative electrode of the battery cell BC1, and the external terminal P12 is connected to the positive electrode of the battery cell BC1 and the negative electrode of the battery cell BC2. Similarly, the external terminals P12 to P15 are connected to the positive electrodes of the battery cells BC2 to BC4 and the negative electrodes of the battery cells BC3 to BC5. The external terminal P16 is connected to the positive electrode of the battery cell BC5.

  The potential difference between the external terminal P11 and the external terminal P12 is the voltage of the battery cell BC1 (the voltage between the negative electrode and the positive electrode, which is the cell voltage). Similarly, the potential difference between the external terminals P12 to P15 and the external terminals P13 to P16 is the voltage of the battery cells BC2 to BC5. The potential difference between the external terminal P11 and the external terminal P16 is the voltage of the assembled battery 10.

The external terminals P <b> 11 to P <b> 16 of the assembled battery 10 are connected to the discharge circuit 20.
The discharge circuit 20 includes n (five) discharge circuits 21 to 25 in accordance with the battery cells BC1 to BC5 included in the assembled battery 10.

  The discharge circuit 21 is connected between the external terminal P12 and the external terminal P11. The discharge circuit 21 includes a discharge resistor R1 and a discharge transistor T1. The discharge transistor T1 is an N-channel MOS transistor. The first terminal of the discharge resistor R1 is connected to the positive electrode of the battery cell BC1 via the external terminal P12. A second terminal of the discharge resistor R1 is connected to a first terminal (for example, a drain terminal) of the discharge transistor T1. A second terminal (for example, a source terminal) of the discharge transistor T1 is connected to the negative electrode of the battery cell BC1 via the external terminal P11. That is, the discharge resistor R1 and the discharge transistor T1 are connected in series with each other. The discharge circuit 21 including the discharge resistor R1 and the discharge transistor T1 is connected in parallel to the battery cell BC1.

  Similarly, the discharge circuit 22 connected between the external terminal P12 and the external terminal P12 includes a discharge resistor R2 and a discharge transistor T2 connected in series with each other. The discharge circuit 22 is connected in parallel to the battery cell BC2. The discharge circuit 23 connected between the external terminal P13 and the external terminal P13 includes a discharge resistor R3 and a discharge transistor T3 connected in series with each other. The discharge circuit 23 is connected in parallel to the battery cell BC3. The discharge circuit 24 connected between the external terminal P15 and the external terminal P14 includes a discharge resistor R4 and a discharge transistor T4 connected in series with each other. The discharge circuit 24 is connected in parallel to the battery cell BC4. The discharge circuit 25 connected between the external terminal P16 and the external terminal P15 includes a discharge resistor R5 and a discharge transistor T5 connected in series with each other. The discharge circuit 25 is connected in parallel to the battery cell BC5.

External terminals P <b> 11 to P <b> 16 of the assembled battery 10 are connected to the monitoring device 31.
The control terminals (for example, gate terminals) of the discharge transistors T1 to T5 included in the discharge circuit 20 are connected to the monitoring device 31.

  The monitoring device 31 has (n + 1) (six in FIG. 1) external input terminals P21 to P26 and n (five in FIG. 1) external output terminals P31 to P35. The external input terminals P21 to P26 are connected to the external terminals P11 to P16 of the assembled battery 10, respectively. Therefore, the voltages at the terminals of the battery cells BC1 to BC5 included in the assembled battery 10 are applied to the external input terminals P21 to P26.

The monitoring device 31 includes a multiplexer 41, an AD conversion circuit 42, an interface circuit 43, and a control circuit 44.
The input terminal of the multiplexer 41 is connected to each external input terminal P21-P26. The multiplexer 41 selects an input terminal corresponding to the selection signal SL supplied from the control circuit 44, that is, an external input. For example, when the external input terminal P21 is selected, a voltage equal to the terminal voltage VT1 at the external input terminal P21 is output. Similarly, when the external input terminals P22 to P26 are selected, voltages equal to the terminal voltages VT2 to VT6 at the external input terminals P22 to P26 are output. The output voltage of the multiplexer 41 is Tx (x = 1 to 6). The multiplexer 41 outputs a voltage VTx equal to the voltage supplied from the selected input terminal (external input terminal). The multiplexer 41 is an example of a selection circuit.

  The output terminal of the multiplexer 41 is connected to the input terminal of the AD conversion circuit 42. The AD conversion circuit 42 is activated / deactivated in response to the control signal EN1 supplied from the control circuit 44. The activated AD conversion circuit 42 outputs a voltage value generated by digitally converting the output voltage VTx of the multiplexer 41. A voltage value obtained by converting the terminal voltage VT1 is defined as DT1. Similarly, voltage values obtained by converting the terminal voltages VT2 to VT6 are defined as DT2 to DT6. That is, the AD conversion circuit 42 outputs the voltage value DTx (x = 1 to 6).

  The interface circuit 43 is activated / deactivated in response to the control signal EN2 supplied from the control circuit 44. The output terminal of the interface circuit 43 is connected to the external output terminal PH1, and the host device 32 is connected to the external output terminal PH1. The activated interface circuit 43 outputs the voltage value DTx output from the AD conversion circuit 42. Note that the voltage value from the interface circuit 43 uses the same sign as the voltage value from the AD conversion circuit 42 for convenience. The voltage value DTx is supplied to the host device 32 via the external output terminal PH1.

  The host device 32 is connected to the control terminal PH <b> 2 of the monitoring device 31, and the control terminal PH <b> 2 is connected to the control circuit 44. The host device 32 outputs a command CMD for controlling the monitoring device 31, and the command CMD is supplied to the control circuit 44 via the control terminal PH2. The control circuit 44 generates the selection signal SL and the control signals EN1, EN2 according to the command CMD.

  For example, the host device 32 outputs a predetermined command CMD, and the control circuit 44 generates a selection signal SL according to the command CMD. The multiplexer 41 selects the external input terminals P21 to P26 according to the selection signal SL, and outputs the voltage supplied to those external input terminals P21 to P26. The AD conversion circuit 42 outputs a voltage value DTx obtained by converting the output voltage VTx (x = 1 to 6) of the multiplexer 41. The voltage value DTx is output to the host device 32 by the interface circuit 43. Thus, the host device 32 receives the voltage DT1 of the voltage at the external input terminal P21, that is, the voltage at the external terminal P11 of the assembled battery 10. Similarly, the host device 32 receives voltage values DT2 to DT6 at the external terminals P12 to P16 of the assembled battery 10. As described above, the monitoring device 31 converts the terminal voltages VT1 to VT6 applied to the external input terminals P21 to P26 into digital values, and outputs the converted values (voltage values) to the host device 32.

  The host device 32 calculates cell voltages VC1 to VC5 of the battery cells BC1 to BC5 based on the received voltage values DT1 to DT6. For example, the host device 32 calculates the cell voltage VC1 by subtracting the voltage value DT1 from the voltage value DT2. Similarly, the host device 32 calculates the cell voltages VC2 to VC5 by subtracting the voltage values DT2 to DT5 from the voltage values DT3 to DT6.

  For example, the host device 32 is set with a reference voltage Vcr1 and a reference voltage Vcr2. The reference voltage Vcr1 is set according to each battery cell BC1 to BC5. The reference voltage Vcr1 is a target value for equalizing the cell voltages VC1 to VC5 of the battery cells BC1 to BC5.

  The reference voltage Vcr2 is set according to the discharge transistors T1 to T5 for discharging the battery cells BC1 to BC5. For example, the reference voltage Vcr2 is set according to the threshold voltages of the discharge transistors T1 to T5.

  The host device 32 generates a command CMD for controlling the monitoring device 31 to equalize the cell voltages VC1 to VC5 based on the cell voltages VC1 to VC5 of the battery cells BC1 to BC5 and the reference voltages Vcr1 and Vcr2. To do.

In addition, the monitoring device 31 includes a level conversion unit 45 and a drive unit 46 for controlling the discharge circuit 20.
The control circuit 44 generates the drive signals SK11 to SK15 based on the command CMD output from the host device 32. The drive signals SK11 to SK15 are supplied to the level converter 45.

The level conversion unit 45 includes n (5) level converters (denoted as “LVC”) 51 to 55.
The level converter 51 operates based on, for example, the operating voltage of the control circuit 44 and the voltage input via the external input terminals P21 and P22. Then, the level converter 51 converts the level of the drive signal SK11 output from the control circuit 44 into a level in the voltage range of the external input terminals P21 and P22, and outputs the converted drive signal SK21.

  Similarly, the level converters 52 to 55 convert the level of the drive signals SK12 to SK15 output from the control circuit 44 into the level of the voltage range at the corresponding external input terminal, and convert the converted drive signals SK22 to SK25. Output. The drive signals SK21 to SK25 are supplied to the drive unit 46.

The drive unit 46 includes n (five in FIG. 1) drive circuits 61 to 65.
A drive signal SK21 is supplied to the drive circuit 61. The output terminal of the drive circuit 61 is connected to the external output terminal P31, and the external output terminal P31 is connected to the control terminal of the discharge transistor T1 of the discharge circuit 20. The drive circuit 61 outputs a drive voltage VK1 for driving the discharge transistor T1 based on the drive signal SK21. The discharge transistor T1 is turned on / off based on the drive voltage VK1.

  Similarly, the output terminals of the drive circuits 62 to 65 are connected to the control terminals of the discharge transistors T2 to T5 via the external output terminals P32 to P35, respectively. The drive circuits 62 to 65 output drive voltages VK2 to VK5 based on the drive signals SK22 to SK25. The discharge transistors T2 to T5 are turned on / off based on the drive voltages VK2 to VK5.

As shown in FIG. 2, the drive circuit 61 includes a buffer circuit 71, an inverter circuit 81, switch circuits SW1a and SW1b, and a resistor R11.
Based on the drive signal SK21, the buffer circuit 71 outputs a signal SK31 having a level equal to the level of the drive signal SK21.

  The inverter circuit 81 includes transistors TP1 and TN1. The transistor TP1 is, for example, a P channel MOS transistor, and the transistor TN1 is, for example, an N channel MOS transistor.

  A signal SK31 is supplied to the gate terminals of the transistors TP1 and TN1. The source terminal of the transistor TP1 is connected to the switch circuits SW1a and SW1b. The drain terminal of the transistor TP1 is connected to the drain terminal of the transistor TN1, and the source terminal of the transistor TN1 is connected to the external input terminal P21. A node between the drain terminal of the transistor TP1 and the drain terminal of the transistor TN1 is an output terminal of the inverter circuit 81, and this output terminal is connected to the external output terminal P31. The external output terminal P31 is connected to the control terminal of the discharge transistor T1 of the discharge circuit 20. A resistor R11 is connected between the external output terminal P31 and the external input terminal P21.

  The first terminal of the switch circuit SW1a is connected to the external input terminal P22, and the second terminal of the switch circuit SW1a is connected to the source terminal of the transistor TP1. The first terminal of the switch circuit SW1b is connected to a terminal to which a higher voltage than the external input terminal P22 is supplied, for example, the external input terminal P23. The second terminal of the switch circuit SW1b is connected to the source terminal of the transistor TP1.

  A control signal SS1a output from the control circuit 44 is supplied to the control terminal of the switch circuit SW1a. The switch circuit SW1a is turned on / off in response to the control signal SS1a. For example, the switch circuit SW1a is turned on in response to the control signal SS1a at the H level and turned off in response to the control signal SS1a at the L level. A control signal SS1b output from the control circuit 44 is supplied to the control terminal of the switch circuit SW1b. The switch circuit SW1b is turned on / off in response to the control signal SS1b. For example, the switch circuit SW1b is turned on in response to the H level control signal SS1b and turned off in response to the L level control signal SS1b.

  When the switch circuit SW1a is turned on, the terminal voltage VT2 at the external input terminal P22 is supplied to the source terminal of the transistor TP1, that is, the high potential side power supply terminal of the inverter circuit 81. The inverter circuit 81 supplies the drive voltage VK1 having a level corresponding to the positive terminal level of the battery cell BC1 to the gate terminal of the discharge transistor T1. A terminal voltage VT1 is supplied to the source terminal of the discharge transistor T1. Therefore, the gate-source voltage Vgs of the discharge transistor T1 is equal to the terminal voltage of the corresponding battery cell BC1, that is, the cell voltage.

  On the other hand, when the switch circuit SW1b is turned on, the terminal voltage VT3 at the external input terminal P23 is supplied to the source terminal of the transistor TP1, that is, the high potential side power supply terminal of the inverter circuit 81. The inverter circuit 81 supplies the drive voltage VK1 having a level corresponding to the positive terminal level of the battery cell BC2 to the gate terminal of the discharge transistor T1. Therefore, the gate-source voltage Vgs of the discharge transistor T1 is between the voltage at the positive electrode of the battery cell BC2 higher than the corresponding battery cell BC1 (the higher voltage side) and the voltage at the negative electrode of the corresponding battery cell BC1. Equal to the voltage.

Similarly, the drive circuit 62 includes a buffer circuit 72, an inverter circuit 82, switch circuits SW2a and SW2b, and a resistor R12.
Based on the drive signal SK22, the buffer circuit 72 outputs a signal SK32 having a level equal to the level of the drive signal SK22.

  The inverter circuit 82 includes transistors TP2 and TN2. The transistor TP2 is, for example, a P channel MOS transistor, and the transistor TN2 is, for example, an N channel MOS transistor. A signal SK32 is supplied to the gate terminals of the transistors TP2 and TN2. The source terminal of the transistor TP2 is connected to the external input terminal P23 via the switch circuit SW2a. The source terminal of the transistor TP2 is connected to the external input terminal P24 through the switch circuit SW2b. A resistor R12 is connected between the external output terminal P32 and the external input terminal P22.

  The switch circuit SW2a is turned on / off in response to the control signal SS2a output from the control circuit 44. The switch circuit SW2b is turned on / off in response to the control signal SS2b output from the control circuit 44. When the switch circuit SW2a is turned on, the inverter circuit 82 supplies the drive voltage VK2 having a level corresponding to the positive terminal level of the battery cell BC2 to the gate terminal of the discharge transistor T2. Therefore, the gate-source voltage Vgs of the discharge transistor T2 becomes the voltage between the terminals of the corresponding battery cell BC2, that is, the cell voltage. On the other hand, when the switch circuit SW2b is turned on, the inverter circuit 82 supplies the drive voltage VK2 having a level corresponding to the positive terminal level of the battery cell BC3 to the gate terminal of the discharge transistor T2. Therefore, the gate-source voltage Vgs of the discharge transistor T2 is between the voltage at the positive electrode of the battery cell BC3 higher than the corresponding battery cell BC2 (the higher voltage side) and the voltage at the negative electrode of the corresponding battery cell BC2. Voltage.

The drive circuit 63 includes a buffer circuit 73, an inverter circuit 83, switch circuits SW3a and SW3b, and a resistor R13.
The buffer circuit 73 outputs a signal SK33 having a level equal to the level of the drive signal SK23 based on the drive signal SK23.

  The inverter circuit 83 includes transistors TP3 and TN3. The transistor TP3 is, for example, a P-channel MOS transistor, and the transistor TN3 is, for example, an N-channel MOS transistor. A signal SK33 is supplied to the gate terminals of the transistors TP3 and TN3. The source terminal of the transistor TP3 is connected to the external input terminal P24 via the switch circuit SW3a. The source terminal of the transistor TP3 is connected to the external input terminal P25 to which a voltage higher than that of the external input terminal P24 is supplied via the switch circuit SW3b. A resistor R13 is connected between the external output terminal P33 and the external input terminal P23.

  The switch circuit SW3a is turned on / off in response to the control signal SS3a output from the control circuit 44. The switch circuit SW3b is turned on / off in response to the control signal SS3b output from the control circuit 44. When the switch circuit SW3a is turned on, the inverter circuit 83 supplies the drive voltage VK3 having a level corresponding to the positive terminal level of the battery cell BC3 to the gate terminal of the discharge transistor T3. Therefore, the gate-source voltage Vgs of the discharge transistor T3 becomes the voltage between the terminals of the corresponding battery cell BC3, that is, the cell voltage. On the other hand, when the switch circuit SW3b is turned on, the inverter circuit 83 supplies the drive voltage VK3 having a level corresponding to the positive terminal level of the battery cell BC4 to the gate terminal of the discharge transistor T3. Accordingly, the gate-source voltage Vgs of the discharge transistor T3 is between the voltage at the positive electrode of the battery cell BC4 higher than the corresponding battery cell BC3 (the higher voltage side) and the voltage at the negative electrode of the corresponding battery cell BC3. Voltage.

The drive circuit 64 includes a buffer circuit 74, an inverter circuit 84, switch circuits SW4a and SW4b, and a resistor R14.
Based on the drive signal SK24, the buffer circuit 74 outputs a signal SK34 having a level equal to the level of the drive signal SK24.

  The inverter circuit 84 includes transistors TP4 and TN4. The transistor TP4 is, for example, a P-channel MOS transistor, and the transistor TN4 is, for example, an N-channel MOS transistor. A signal SK34 is supplied to the gate terminals of the transistors TP4 and TN4. The source terminal of the transistor TP4 is connected to the external input terminal P25 via the switch circuit SW4a. The source terminal of the transistor TP4 is connected to the external input terminal P26 to which a voltage higher than that of the external input terminal P25 is supplied via the switch circuit SW4b. A resistor R14 is connected between the external output terminal P34 and the external input terminal P24.

  The switch circuit SW4a is turned on / off in response to the control signal SS4a output from the control circuit 44. The switch circuit SW4b is turned on / off in response to the control signal SS4b output from the control circuit 44. When the switch circuit SW4a is turned on, the inverter circuit 84 supplies the drive voltage VK4 having a level corresponding to the positive terminal level of the battery cell BC4 to the gate terminal of the discharge transistor T4. Therefore, the gate-source voltage Vgs of the discharge transistor T4 becomes the voltage between the terminals of the corresponding battery cell BC4, that is, the cell voltage. On the other hand, when the switch circuit SW4b is turned on, the inverter circuit 84 supplies the drive voltage VK4 having a level corresponding to the positive terminal level of the battery cell BC5 to the gate terminal of the discharge transistor T4. Therefore, the gate-source voltage Vgs of the discharge transistor T4 is between the voltage at the positive electrode of the battery cell BC5 higher than the corresponding battery cell BC4 (the higher voltage side) and the voltage at the negative electrode of the corresponding battery cell BC4. Voltage.

The drive circuit 65 includes a buffer circuit 75, an inverter circuit 85, switch circuits SW5a and SW5b, and a resistor R15.
The buffer circuit 75 outputs a signal SK35 having a level equal to the level of the drive signal SK25 based on the drive signal SK25.

  The inverter circuit 85 includes transistors TP5 and TN5. The transistor TP5 is, for example, a P channel MOS transistor, and the transistor TN5 is, for example, an N channel MOS transistor. A signal SK35 is supplied to the gate terminals of the transistors TP5 and TN5. The source terminal of the transistor TP5 is connected to the external input terminal P26 through the switch circuit SW5a. A resistor R15 is connected between the external output terminal P35 and the external input terminal P25. The source terminal of the transistor TP5 is connected to the charge pump circuit 47 through the switch circuit SW5b.

  The input terminal of the charge pump circuit 47 is connected to the external input terminal P41, and the external input terminal P41 is connected to the external terminal P16 of the assembled battery 10. Accordingly, the voltage at the positive electrode of the battery cell BC5 is supplied to the charge pump circuit 47. The voltage at the positive electrode of battery cell BC5 is terminal voltage VT6. For this reason, the voltage supplied to the charge pump is VT6. The output terminal of the charge pump circuit 47 is connected to the external terminal P42, and the capacitor C11 is connected to the external terminal P42. The charge pump circuit 47 is activated / deactivated in response to the control signal EN3 supplied from the control circuit 44. The control circuit 44 generates a control signal EN3 according to the command CMD from the host device 32. The activated charge pump circuit 47 generates a voltage VCP higher than the voltage VT6 based on the voltage VT6 supplied via the external input terminal P41. The charge pump circuit 47 is an example of a booster circuit.

  The switch circuit SW5a is turned on / off in response to the control signal SS5a output from the control circuit 44. The switch circuit SW5b is turned on / off in response to the control signal SS5b output from the control circuit 44. When the switch circuit SW5a is turned on, the inverter circuit 85 supplies the drive voltage VK5 having a level corresponding to the positive terminal level of the battery cell BC5 to the gate terminal of the discharge transistor T5. Therefore, the gate-source voltage Vgs of the discharge transistor T5 becomes the voltage between the terminals of the corresponding battery cell BC5, that is, the cell voltage. On the other hand, when the switch circuit SW5b is turned on, the inverter circuit 85 supplies the drive voltage VK5 at a level corresponding to the voltage generated by the charge pump circuit 47 to the gate terminal of the discharge transistor T5. Therefore, the gate-source voltage Vgs of the discharge transistor T5 is a voltage between the voltage VCP higher than the corresponding battery cell BC5 (the higher voltage side) and the voltage at the negative electrode of the corresponding battery cell BC5.

  FIG. 2 shows a resistor R21 connected between the external input terminal P21 of the monitoring device 31 and the external terminal P11 of the assembled battery 10, and a capacitor C21 connected between the external input terminal P21 and the ground. Yes. Similarly, resistors R22 to R26 connected between the external input terminals P22 to P26 of the monitoring device 31 and the external terminals P12 to P16 of the assembled battery 10, and a capacitor connected between the external input terminals P22 to P26 and the ground. C22 to C26 are shown. The resistors R21 to R26 and the capacitors C21 to C26 remove, for example, stabilization of voltage supplied to the external input terminals P21 to P26 of the monitoring device 31 and noise.

Next, the discharge process in the discharge control system 30 will be described.
As shown in FIG. 3, the discharge process includes steps 101 to 106.
The discharge process is periodically performed according to time measurement such as a timer. In addition, you may implement with a predetermined signal as a trigger.

First, in step 101, the cell voltages of all the battery cells BC1 to BC5 are measured.
For example, the host device 32 shown in FIG. 1 outputs a plurality of commands CMD so as to sequentially select the external input terminals P21 to P26 of the monitoring device 31. The control circuit 44 of the monitoring device 31 generates a selection signal SL according to the command CMD, and the multiplexer 41 selects an input terminal according to the selection signal SL, and outputs according to the terminal voltage supplied to the input terminal. The voltage VTx (x = 1 to 6) is output. The AD conversion circuit 42 outputs a voltage value DTx (x = 1 to 6) obtained by converting the output voltage VTx of the multiplexer 41. When the host device 32 receives all the voltage values DT1 to DT6, the host device 32 calculates the cell voltages VC1 to VC5 of the battery cells BC1 to BC5 based on the voltage values DT1 to DT6.

Next, in step 102, a battery cell that needs to be discharged is determined.
The host device 32 compares the cell voltages VC1 to VC5 of the battery cells BC1 to BC5 calculated in Step 101 with the reference voltage Vcr1 set for discharging, and based on the comparison result, the battery cells BC1 to BC1. In BC5, it is determined whether or not a discharge is necessary. The host device 32 determines that the battery cell having a cell voltage higher than the reference voltage Vcr1 needs to be discharged. And let the battery cell determined to be the discharge be discharge object. When it is determined that there is a battery cell that needs to be discharged (determination: YES), the process proceeds to the next step 103, and when it is determined that there is no battery cell that needs to be discharged (determination: No), the process proceeds to step 101.

Next, in step 103, it is determined whether or not the discharge drive voltage is sufficient.
The host device 32 compares the cell voltage of the battery cell to be discharged set in step 102 with the reference voltage Vcr2 set for voltage control, and whether or not the discharge drive voltage is sufficient based on the comparison result. Determine. The discharge drive voltage is a voltage for turning on the discharge transistors T1 to T5 shown in FIG. 2, and the reference voltage Vcr2 is set according to the threshold voltage of the discharge transistors T1 to T5 shown in FIG. The host device 32 determines that the discharge drive voltage is sufficient when the cell voltage of the battery cell to be discharged is higher than the reference voltage Vcr2. On the other hand, when the cell voltage of the battery cell to be discharged is lower than the reference voltage Vcr2, it is determined that the discharge drive voltage is insufficient. When it is determined that the discharge drive voltage is sufficient (determination: YES), the process proceeds to the next step 104.

  In step 104, voltage is supplied from the battery cell to be discharged. The host device 32 outputs a command CMD generated from the battery cell to be discharged so as to supply a voltage to the drive circuit that drives the discharge transistor.

  For example, the battery cell to be discharged is a battery cell BC1 shown in FIG. The host device 32 outputs a command CMD generated so as to supply a voltage from the battery cell BC1 to the drive circuit 61. In response to the command CMD, the control circuit 44 outputs an H level control signal SS1a. The switch circuit SW1a is turned on by the control signal SS1a, and a voltage is supplied from the battery cell BC1 to the inverter circuit 81 via the external input terminal P22.

In step 105, the battery cell to be discharged is discharged for a predetermined time.
The host device 32 outputs a command CMD generated to turn on the discharge transistor corresponding to the battery cell to be discharged. The control circuit 44 outputs a drive signal corresponding to the command CMD.

  For example, the battery cell to be discharged is a battery cell BC1 shown in FIG. The host device 32 outputs a command CMD generated so as to discharge the battery cell BC1. The control circuit 44 outputs a drive signal SK11 corresponding to the command CMD. The drive signal SK11 is level-converted by the level converter 51 shown in FIG. The inverter circuit 81 of the drive circuit 61 outputs the drive voltage VK1 based on the drive signal SK21 of the level converter 51. At this time, the cell voltage of the battery cell BC1 to be discharged is supplied to the inverter circuit 81 via the switch circuit SW1a. The inverter circuit 81 outputs a drive voltage VK1 that is equal to the cell voltage. This drive voltage VK1 is higher than the reference voltage Vcr1 set according to the discharge transistor T1. Therefore, the discharge transistor T1 is turned on according to the drive voltage VK1. Thereby, the battery cell BC1 to be discharged is discharged.

  The host device 32 outputs a command CMD for turning off the discharge transistor T1 when a predetermined time elapses after outputting the command CMD for turning on the discharge transistor T1. In response to this command CMD, the control circuit 44 outputs a drive signal SK11, and based on the drive signal SK11, the inverter circuit 81 of the drive circuit 61 outputs a drive voltage VK1 of L level (potential level of the external input terminal P21). The discharge transistor T1 is turned off.

If it is determined in step 103 that the discharge drive voltage is insufficient (determination: NO), the process proceeds to step 106.
In step 106, a voltage higher than the battery cell to be discharged is supplied. The host device 32 generates the voltage of the external connection terminal higher (high potential side) than the external connection terminal to which the battery cell to be discharged is connected to the drive circuit corresponding to the battery cell to be discharged. Command CMD is output.

  For example, the battery cell to be discharged is a battery cell BC1 shown in FIG. The host device 32 outputs a command CMD generated to supply voltage to the drive circuit 61 from the battery cell BC2 higher than the battery cell BC1. That is, the host device 32 generates the voltage supplied to the external input terminal P23 higher (high potential side) than the external input terminal P22 to which the battery cell BC1 to be discharged is connected to the drive circuit 61. Command CMD is output. In response to the command CMD, the control circuit 44 outputs an H level control signal SS1b. The switch circuit SW1b is turned on by the control signal SS1b, and a voltage is supplied from the battery cell BC2 to the inverter circuit 81 via the external input terminal P23.

In step 105, the battery cell to be discharged is discharged for a predetermined time.
At this time, voltage is supplied to the inverter circuit 81 from the battery cell BC2 higher than the battery cell BC1 to be discharged via the switch circuit SW1b. That is, the inverter circuit 81 is supplied with the terminal voltage VT3 at the external input terminal P23 to which the positive electrode of the battery cell BC2 is connected. Inverter circuit 81 outputs drive voltage VK1 equal to terminal voltage VT3. Therefore, a drive voltage VK1 that is a voltage obtained by adding the cell voltage VC2 of the upper battery cell BC2 to the cell voltage VC1 of the battery cell BC1 to be discharged is supplied between the source and gate terminals of the discharge transistor T1. The drive voltage VK1 is higher than the reference voltage Vcr1 set according to the discharge transistor T1. Therefore, the discharge transistor T1 is turned on according to the drive voltage VK1. Thereby, the battery cell BC1 to be discharged is discharged.

[When discharge target is top battery cell BC5]
In step 106, the host device 32 outputs a command CMD so as to activate the charge pump circuit 47. The control circuit 44 outputs a control signal EN3 in response to the command CMD, and activates the charge pump circuit 47. Then, the host device 32 outputs a command CMD so as to supply the output voltage VCP of the charge pump circuit 47 to the drive circuit 65 corresponding to the battery cell BC5 to be discharged. In response to the command CMD, the control circuit 44 outputs an H level control signal SS5b. The switch circuit SW5b is turned on by the control signal SS5b, and the output voltage VCP of the charge pump circuit 47 is supplied to the inverter circuit 85. This output voltage VCP is generated by boosting the terminal voltage VT6 based on the cell voltage VC5 of the battery cell BC5 to be discharged.

  In step 105, the battery cell to be discharged is discharged for a predetermined time. At this time, the output voltage VCP of the charge pump circuit 47 is supplied to the inverter circuit 85 via the switch circuit SW5b. Inverter circuit 85 outputs drive voltage VK5 equal to output voltage VCP. Accordingly, the gate voltage of the discharge transistor T5 is supplied with a drive voltage VK5 that is a voltage obtained by adding the output voltage VCP of the charge pump circuit 47 to the cell voltage VC5 of the battery cell BC5 to be discharged. The drive voltage VK5 is higher than the reference voltage Vcr1 set according to the discharge transistor T5. Therefore, the discharge transistor T5 is turned on according to the drive voltage VK5. Thereby, the battery cell BC5 to be discharged is discharged.

  When the processing in step 105 is completed, the routine proceeds to step 101. In step 101, the voltages of all the battery cells BC1 to BC5 are measured. In step 102, it is determined whether or not the battery cell to be discharged needs to be discharged. When the cell voltage of the battery cell to be discharged becomes equal to or lower than the reference voltage Vcr1, the two switch circuits included in the drive circuit corresponding to the battery cell are turned off, and the discharge process for the battery cell to be discharged is completed. When it is determined that another battery cell needs to be discharged, the battery cell determined to be necessary is set as a discharge target, and a discharge process is performed on the discharge target battery cell.

Next, the operation of the above discharge control system will be described.
For example, the battery cell BC1 shown in FIG. The processes of steps 101 to 106 shown in FIG. 3 are appropriately performed on the battery cell BC1 to be discharged.

  As shown in FIG. 4, since the cell voltage VC1 is higher than the reference voltage Vcr2, an H level control signal SS1a and an L level control signal SS1b are output from the control circuit 44 shown in FIG. The switch circuit SW1a is turned on in response to the H level control signal SS1a, and the drive voltage VK1 equal to the cell voltage VC1 is supplied to the discharge transistor T1. The discharge transistor T1 is turned on according to the drive voltage VK1, and the battery cell BC1 is discharged.

  As shown in FIG. 4, the cell voltage VC1 of the battery cell BC1 is reduced by the discharge process. Then, according to the cell voltage VC1, the drive voltage VK1 supplied to the gate terminal of the discharge transistor T1 corresponding to the battery cell BC1 decreases.

  When the cell voltage VC1 becomes lower than the reference voltage Vcr2, an L level control signal SS1a and an H level control signal SS1b are output from the control circuit 44 shown in FIG. In response to the H level control signal SS1b, the switch circuit SW1b is turned on. As a result, the drive voltage VK1 is a voltage obtained by adding the cell voltage VC2 to the cell voltage VC1. Since the drive voltage VK1 is higher than the reference voltage Vcr2, the discharge transistor T1 is turned on, and the discharge to the battery cell BC1 is continued. When the cell voltage VC1 becomes equal to the reference voltage Vcr1, the discharge process for the battery cell BC1 ends.

  Thus, even when the cell voltage VC1 of the battery cell BC1 to be discharged becomes lower than the reference voltage Vcr2 set according to the discharge transistor T1, the discharge transistor T1 is turned on by adjusting the drive voltage VK1. . The reference voltage Vcr2 is set according to the threshold voltage and on-resistance value of the discharge transistor T1. When the size of the discharge transistor T1 is reduced, the on-resistance value increases and the threshold voltage increases. Then, the discharge transistor cannot be turned on with the cell voltage supplied from the low-voltage battery cell.

  The discharge control system 30 shown in FIG. 1 supplies a driving voltage VK1 based on the cell voltage VC1 to the discharge transistor T1 when the cell voltage VC1 is higher than a reference voltage Vcr2 set according to the discharge transistor T1, and causes the discharge transistor T1 to be supplied. Turns on and discharges the battery cell BC1. When the cell voltage VC1 becomes lower than the reference voltage Vcr2, the drive voltage VK1 is generated based on the cell voltage VC2 higher than the cell voltage VC1. The discharge transistor T1 is turned on by this drive voltage VK1, and the discharge process for the battery cell BC1 is continued. Thus, even when the cell voltage VC1 is lower than the reference voltage Vcr2, the discharge transistor T1 can be turned on to discharge the battery cell BC1.

In addition, about battery cell BC2-BC4, since it is the same as that of battery cell BC1, description is abbreviate | omitted.
Next, the case where the battery cell BC5 shown in FIG.

  As shown in FIG. 5, since the cell voltage VC5 is higher than the reference voltage Vcr2, an H level control signal SS5a and an L level control signal SS5b are output from the control circuit 44 shown in FIG. The switch circuit SW5a is turned on in response to the H level control signal SS5a, and the drive voltage VK5 equal to the cell voltage VC5 is supplied to the discharge transistor T5. The discharge transistor T5 is turned on according to the drive voltage VK5, and the battery cell BC5 is discharged.

  As shown in FIG. 5, the cell voltage VC5 of the battery cell BC5 is reduced by the discharge process. Then, according to the cell voltage VC5, the drive voltage VK5 supplied to the gate terminal of the discharge transistor T5 corresponding to the battery cell BC5 decreases.

  When the cell voltage VC5 becomes lower than the reference voltage Vcr2, an L level control signal SS5a and an H level control signal SS5b are output from the control circuit 44 shown in FIG. In response to this H level control signal SS5b, the switch circuit SW5b is turned on. As a result, the drive voltage VK5 is a voltage obtained by adding the output voltage VCP of the charge pump circuit 47 to the cell voltage VC5. Since the drive voltage VK5 is higher than the reference voltage Vcr2, the discharge transistor T5 is turned on, and the discharge to the battery cell BC5 is continued. When the cell voltage VC5 becomes equal to the reference voltage Vcr1, the discharge process for the battery cell BC5 is completed.

  Thus, even when the cell voltage VC5 of the battery cell BC5 to be discharged becomes lower than the reference voltage Vcr2, the discharge transistor T5 is turned on by adjusting the drive voltage VK5, and the discharge process for the battery cell BC5 is continued. . Thus, even when the cell voltage VC5 is lower than the reference voltage Vcr2, the discharge transistor T5 can be turned on to discharge the battery cell BC5.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The drive circuit 61 includes a buffer circuit 71, an inverter circuit 81, switch circuits SW1a and SW1b, and a resistor R11. The inverter circuit 81 includes transistors TP1 and TN1. The first terminal of the switch circuit SW1a is connected to the external input terminal P22, and the second terminal of the switch circuit SW1a is connected to the source terminal of the transistor TP1. The first terminal of the switch circuit SW1b is connected to a terminal to which a higher voltage than the external input terminal P22 is supplied, for example, the external input terminal P23. The second terminal of the switch circuit SW1b is connected to the source terminal of the transistor TP1. The inverter circuit 81 drives the drive voltage VK1 with respect to the discharge transistor T1 that discharges the battery cell BC1 based on the terminal voltage VT2 supplied via the switch circuit SW1a or the terminal voltage VT3 supplied via the switch circuit SW1b. Is output.

  Therefore, when the cell voltage VC1 of the battery cell BC1 is higher than the reference voltage Vcr1, the discharge transistor T1 is turned on by the drive voltage VK1 generated based on the terminal voltage VT2 by the cell voltage VC1, and the battery cell BC1 is discharged. On the other hand, when the cell voltage VC1 of the battery cell BC1 is lower than the reference voltage Vcr1, the drive voltage VK1 is generated based on the upper terminal voltage VT3. The discharge transistor T1 is turned on by the drive voltage VK1, and the battery cell BC1 is discharged. As described above, the driving voltage VK1 is generated based on the terminal voltage VT2 or the terminal voltage VT3 higher than the terminal voltage VT2 in accordance with the cell voltage VC1 of the battery cell BC1, thereby discharging even when the cell voltage VC1 is low. The battery cell BC1 can be discharged by turning on the transistor T1.

  (2) The output voltage VCP of the charge pump circuit 47 is supplied to the inverter circuit 85 of the drive circuit 65 corresponding to the uppermost battery cell BC5 via the switch circuit SW5b. The charge pump circuit 47 generates an output voltage VCP higher than the terminal voltage VT6 based on the terminal voltage VT6 based on the cell voltage VC5 of the battery cell BC5. Based on the output voltage VCP, a drive voltage VK5 for driving the discharge transistor T5 corresponding to the battery cell BC5 is generated. Accordingly, even when the cell voltage VC5 is low, the discharge transistor T5 can be turned on to discharge the battery cell BC5. Then, the drive voltage VK5 for the discharge transistor T5 is generated using the charge pump circuit 47. Thereby, the transistor of the same electrical characteristic as discharge transistor T1-T4 corresponding to other battery cell BC1-BC4 can be used for discharge transistor T5.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, for example, when the cell voltage of the battery cell BC1 is lower than the reference voltage Vcr2, the drive voltage VK1 supplied to the discharge transistor T1 of the discharge circuit 21 that discharges the battery cell BC1 is determined by the upper battery cell BC2. It was generated based on the terminal voltage VT3. This may be generated based on, for example, the terminal voltage VT4 by the higher-order battery cell BC3.

  For example, n is the number of battery cells included in the assembled battery. For the m-th battery cell in order from the low potential side, the voltage at the (m + 1) -th terminal and the (m + i) -th (2 ≦ i ≦ (n−m + 1)) terminal voltage are switched to supply power to the inverter circuit. Supply to the terminal. As a result, the discharge transistor can be turned on to discharge the low-voltage battery cell. It is preferable to set the terminal voltage for generating the drive voltage supplied to the inverter circuit via the switch circuit according to the electrical characteristics (for example, withstand voltage) of the discharge transistor.

  In the above embodiment, the assembled battery 10 including the five battery cells BC1 to BC5 has been described. However, the number of battery cells included in the assembled battery may be changed to any number of 4 or less or 6 or more. Good.

The switch circuits SW1a, SW1b to SW5a, SW5b included in the drive circuits 61 to 65 may be turned on and off in a complementary manner.
Three or more switch circuits are connected to the power supply terminals of the inverter circuits 81 to 85 of the drive circuits 61 to 65, and each switch circuit is controlled in accordance with the cell voltage of the corresponding battery cell. The discharge transistors T1 to T5 The drive voltages VK1 to VK5 that can be turned on may be generated.

-You may change the circuit structure of the monitoring apparatus 31 suitably.
For example, by reducing the on-resistance value of the discharge transistor, the discharge transistor can be turned on with a low gate voltage. Therefore, by reducing the on-resistance value of the discharge transistor T5 shown in FIG. 2, even when the voltage value of the battery cell BC5 is lower than the reference voltage Vcr2, the discharge transistor T5 is turned on by the cell voltage VC5 of the battery cell BC5. The battery cell BC5 can be discharged. In such a case, the charge pump circuit 47 shown in FIG. 2 can be omitted.

  The reference voltage Vcr1 may be set as appropriate. For example, you may make it set based on cell voltage VC1-VC5 of all the battery cells BC1-BC5 measured in step 101 shown in FIG. For example, the minimum cell voltage is detected, and the reference voltage Vcr1 is set according to the minimum cell voltage. Then, the reference voltage Vcr1 is compared with the cell voltages VC1 to VC5, and a battery cell having a cell voltage higher than the reference voltage Vcr1 is set as a discharge target.

10 assembled battery 20 discharge circuit 21-25 discharge circuit 61-65 drive circuit 71-75 buffer circuit SW1a-SW5a switch circuit SW1b-SW5b switch circuit SS1a-SS5b control signal SK11-SK15 drive signal SK21-SK25 drive signal BC1-BC5 battery Cells T1 to T5 Discharge transistors R1 to R5 Discharge resistors VK1 to VK5 Drive voltages P21 to P26 External input terminals P31 to P35 External output terminals

Claims (10)

A semiconductor device connected to control terminals of a plurality of discharge transistors for discharging each battery cell of a battery pack in which a plurality of battery cells are connected in series,
A plurality of drive circuits for outputting a drive voltage for driving the plurality of discharge transistors based on a plurality of drive signals;
Each of the plurality of drive circuits is
A buffer circuit to which an output terminal is connected to an external output terminal to which a control terminal of the discharge transistor is connected, and to which the drive signal is supplied;
A first switch circuit for supplying the buffer circuit with a first voltage at a first external input terminal to which a positive electrode of the corresponding battery cell is connected;
A second switch circuit for supplying a second voltage higher than the first voltage to the buffer circuit;
Have
Generating the drive voltage based on the first voltage or the second voltage;
A semiconductor device characterized by the above.   The second switch circuit supplies the second voltage at the second external input terminal to which the positive electrode of a battery cell higher than the battery cell to which the positive electrode is connected to the first external input terminal to the buffer circuit. The semiconductor device according to claim 1, wherein the semiconductor device is connected so as to be supplied to the semiconductor device.   3. The semiconductor device according to claim 1, further comprising a booster circuit that boosts the first voltage to generate the second voltage.   The booster circuit supplies the second voltage to a drive circuit that generates the drive voltage with respect to a control terminal of a discharge transistor corresponding to the uppermost battery cell included in the assembled battery. The semiconductor device according to claim 3. A selection circuit that is connected to a plurality of external input terminals to which the plurality of battery cells are connected and outputs a voltage at one external input terminal selected based on a selection signal;
An AD conversion circuit for converting the output voltage of the selection circuit into a digital signal;
An interface circuit for outputting the output of the AD converter circuit to the outside;
A control circuit for generating the selection signal and the drive signal based on an external command;
The semiconductor device according to claim 1, comprising: Wherein the control circuit, the semiconductor device according to claim 5, characterized in that, to generate a control signal for controlling the boost circuit based on a command from outside.   The semiconductor device according to claim 5, wherein the control circuit generates a control signal for controlling the AD converter circuit based on a command from the outside. A discharge control system that discharges the battery cell by driving a plurality of discharge transistors connected to each battery cell of a battery pack in which a plurality of battery cells are connected in series,
A discharge control device for outputting a command;
A monitoring device that outputs a voltage value corresponding to voltages at a plurality of external input terminals to which the plurality of battery cells are connected based on the command, and outputs a driving voltage to control terminals of the plurality of discharge transistors; ,
Have
The monitoring device
A plurality of drive circuits for outputting a drive voltage for driving the plurality of discharge transistors based on a plurality of drive signals;
Each of the plurality of drive circuits is
A buffer circuit to which an output terminal is connected to an external output terminal to which a control terminal of the discharge transistor is connected, and to which the drive signal is supplied;
A first switch circuit for supplying the buffer circuit with a first voltage at a first external input terminal to which a positive electrode of the corresponding battery cell is connected;
A second switch circuit for supplying a second voltage higher than the first voltage to the buffer circuit;
Have
Generating the drive voltage based on the first voltage or the second voltage;
Discharge control system characterized by. The discharge control device comprises:
The cell voltage of each of the plurality of battery cells calculated based on the voltage value output from the monitoring device is compared with a first reference voltage to set a discharge target,
A command is output according to a result of comparing the cell voltage to be discharged with a second reference voltage,
The monitoring device controls the first switch circuit and the second switch circuit based on the command;
The discharge control system according to claim 8. A method for controlling a semiconductor device connected to control terminals of a plurality of discharge transistors for discharging each battery cell of a battery pack in which a plurality of battery cells are connected in series,
The semiconductor device includes:
A plurality of drive circuits for outputting a drive voltage for driving the plurality of discharge transistors based on a plurality of drive signals;
The plurality of drives to generate the drive voltage based on a first voltage at a first external input terminal to which a positive electrode of the corresponding battery cell is connected or a second voltage higher than the first voltage. Controlling the circuit,
A control method characterized by the above.