JP6240950B2 - Game machine - Google Patents

Description

The present invention is related to a gaming machine comprising a plurality of single-level control means for controlling the effect device which is divided into groups, and a plurality of units of the control unit Batch integration that controls the control means.

As a gaming machine that can simplify the wiring between the sub relay board and the electrical decoration board, the top LED central board arranged in the center of the top electrical decoration area is serially connected to the sub relay board,
A gaming machine having a configuration in which a top LED right substrate disposed on the right side of the top illumination area and a top LED left substrate disposed on the left side of the top illumination area are separated from the top LED central substrate and connected by wiring. It has been. Thereby, the number of wirings from the sub relay board to the top illumination area can be reduced to simplify the wiring (for example, see Patent Document 1).

In addition, as a gaming machine that can reduce the number of signal lines and easily detect fraudulent activity, signal transmission between the main board and the sub board is performed by the I2C bus method, Some sub-boards are provided with bidirectional bus buffers. This bidirectional bus buffer is for bifurcating two bidirectional serial lines (SDA, SCL) constituting the I2C bus into two unidirectional serial lines, and is provided on the main board. And the bidirectional bus buffer provided on the sub-board are configured to be connected by four serial lines so that the signal transmission directions of the unidirectional serial lines branched by them coincide with each other (for example, Patent Document 2).

JP 2008-212271 A JP 2006-15036 A

In conventional gaming machines, the wiring could not be reduced sufficiently .

The present invention divides a plurality of effect devices into a plurality of groups, and includes unit control means for controlling the effect devices for each group, and also includes overall control means for comprehensively controlling each of the unit control means. A data line and a timing signal line are connected between the control means and the unit control means to enable data transmission from the overall control means to the unit control means, and the overall control means controls the rendering device. Arithmetic processing means for performing arithmetic processing related to the unit, and connected to the unit control means, based on a command from the arithmetic processing means, each signal of the data line and the timing signal line between the unit control means Signal level control means for controlling the level, and arithmetic processing by the arithmetic processing means and control of each signal level by the signal level control means, respectively The data transmitted by the overall control means defines production mode information that defines the output mode of the rendering device and the timing at which the unit control unit updates the output mode of the rendering device. update defining information to be included, the unit control means as a start address a predetermined address of the storage destination, stores the data transmitted from the integrated control unit, the address of the storage destination for each for storing the data At the timing specified in the update specification information transmitted from the overall control means, the output mode of the rendering device is updated to the output mode defined by the rendering mode information, and the signal The level control unit and the unit control unit include an initialization unit that initializes itself when power supply is started.

According to the present invention, wiring between the overall control unit and the unit control unit can be reduced .

It is explanatory drawing of the game machine of embodiment of this invention. It is a front view of the game board of the embodiment of the present invention. It is a disassembled perspective view of the center case of embodiment of this invention. It is a figure which shows the state before the movable production | presentation apparatus of embodiment of this invention operate | moves. It is a figure which shows the state contact | abutted in the contact part as a result of the movable production | presentation apparatus of embodiment of this invention operating, and operating the 1st production unit and the 2nd production unit. It is a disassembled perspective view of the 1st effect member of embodiment of this invention. It is a disassembled perspective view of the 2nd production member of an embodiment of the invention. It is a figure explaining wiring of the game machine of an embodiment of the invention. It is a block diagram which shows the structure of the game machine of embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of embodiment of this invention. It is a block diagram showing a configuration of the first master IC provided in the effect control device of the embodiment of the present invention and the effect device provided in the game board. It is a block diagram which shows the structure of the production | presentation apparatus with which the 2nd master IC with which the presentation control apparatus of embodiment of this invention was equipped and the front frame was equipped. It is a figure which shows the structure of the game board of embodiment of this invention. It is a figure which shows the structure of the front frame of embodiment of this invention. It is a figure explaining the connection state of the relay control board and decoration control apparatus which are included in the production | presentation control apparatus of embodiment of this invention, and a game board. It is a figure explaining the connection state of the presentation control apparatus of embodiment of this invention, the simple relay board | substrate contained in a front frame, and a decoration control apparatus. It is a block diagram of the decoration control apparatus of embodiment of this invention. It is a block diagram which shows the structure of the I2CI / O expander of embodiment of this invention. It is a circuit diagram around the I2CI / O expander of the decoration control device that controls the decoration device of the embodiment of the present invention. It is a circuit diagram around the I2CI / O expander of the decoration control device according to the embodiment of the present invention, and shows a case where a motor and a solenoid are controlled. It is a circuit diagram of the connection line regarding the input / output of the decoration control device (including the relay board and the simple relay board) of the embodiment of the present invention. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of embodiment of this invention. It is explanatory drawing of the I2CI / O expander address table of embodiment of this invention. It is a figure for demonstrating the work register allocated to the output setting register | resistor with which the I2CI / O expander of embodiment of this invention is equipped. It is explanatory drawing of the start condition and stop condition which the master IC of embodiment of this invention outputs data via the connection line SDA and the connection line SCL. It is a timing chart which the decoration control apparatus into which the data output from the master IC of embodiment of this invention was input outputs a response signal. It is a timing chart of the signal level of the connection line SDA and the connection line SCL when the master IC of the embodiment of the present invention outputs effect control data. The format of data transmitted and received between the master IC and the I2CI / O expander when the master IC of the embodiment of the present invention designates the slave individual address and sets the effect control data in the decoration control device FIG. Effect control data transmitted and received between the master IC and the I2CI / O expander when the master IC according to the embodiment of the present invention specifies the slave individual address and sets the effect control data in the decoration control device. It is the figure which applied the specific numerical value to. It is a figure explaining the order which transmits presentation control data of master IC of an embodiment of the invention. It is a figure explaining the format of the initialization instruction | indication data transmitted to I2CI / O expander from master IC, when the master IC of embodiment of this invention initializes I2CI / O expander. It is a figure explaining the abnormality determination table of the 1st master IC of an embodiment of the invention. It is a figure explaining the abnormality determination table of the 2nd master IC of an embodiment of the invention. It is a figure explaining the information transmitted / received between CPU and master IC (1st master IC or 2nd master IC) at the time of initialization (reset) of each decoration control apparatus (slave) of embodiment of this invention. . The figure explaining the information transmitted / received between CPU and master IC (1st master IC or 2nd master IC), when transmitting presentation control data to each decoration control apparatus (slave) of embodiment of this invention. It is. It is a figure explaining the step which transmits production | presentation control data to the master IC (1st master IC or 2nd master IC) from the production | presentation control apparatus of embodiment of this invention. It is a flowchart which shows the procedure of the process by the presentation control apparatus of embodiment of this invention. It is a flowchart which shows the procedure of the 1st master IC side slave initialization start process and 2nd master IC side slave initialization start process of embodiment of this invention. It is a flowchart which shows the procedure of the slave output start process of embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of transmission interruption interrupt generation by the 1st master IC and 2nd master IC of embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the time-out interruption generation | occurrence | production by the 1st master IC and 2nd master IC of embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the initialization instruction | indication data of embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of presentation control data of embodiment of this invention. It is a figure which shows an example of the transmission process continuation determination table for determining continuation of the transmission restart process of the data of embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process by the master IC of embodiment of this invention. It is a flowchart which shows the procedure of the stop condition output process of embodiment of this invention. It is a flowchart which shows the procedure of the SCL release monitoring process of embodiment of this invention. It is a flowchart which shows the procedure of the SDA release monitoring process of embodiment of this invention. It is a flowchart which shows the procedure of the start condition output process of embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process to the I2CI / O expander by the side of the slave of embodiment of this invention. 6 is a flowchart showing a processing procedure when a reset signal is generated in the slave-side I2CI / O expander according to the embodiment of the present invention. It is a flowchart which shows procedures, such as an address recognition process in the I2CI / O expander by the side of a slave of embodiment of this invention. It is a flowchart which shows the procedure of the data read-out process in the I2CI / O expander by the side of the slave of embodiment of this invention. It is a timing chart which shows the state in which the process by 1st master IC and 2nd master IC is performed in parallel by the instruction | indication from an effect control apparatus at the time of VDP interruption of embodiment of this invention. It is a figure which shows the example of a connection of the decoration control apparatus and decoration apparatus in embodiment of this invention, and is a figure which shows the structure which controls LED for 8 sets by two decoration control apparatuses. It is a figure which shows the timing which the decoration control apparatus in embodiment of this invention receives data, and controls an effect apparatus, and is a figure explaining the case where the data received at the time of outputting a stop condition are reflected. It is a figure explaining the procedure which releases a bus | bath when the self slave occupies the bus | bath in embodiment of this invention. In the embodiment of the present invention, a state where the connection line SDA is occupied for some reason occurs, and the I2CI / O expander that detects the occupation of the connection line SDA resets itself and releases the bus. It is a figure explaining the procedure to try. FIG. 10 is a diagram illustrating a procedure for releasing a bus by a slave I2CI / O expander in response to a command from the master IC when the bus is occupied by the slave I2CI / O expander in the embodiment of the present invention. . In the embodiment of the present invention, when a read mode occurs in the slave I2CI / O expander due to an erroneous command from the master IC and the bus is occupied, the slave requests the bus by the command from the master IC. It is a figure explaining the procedure to release. It is a block diagram which shows the structure of the presentation control apparatus of the 1st modification of embodiment of this invention. It is a flowchart which shows the procedure of the process by the production | presentation control apparatus of the 1st modification of embodiment of this invention. It is a figure explaining the structure of the switch part of the presentation control apparatus of the 2nd modification of embodiment of this invention. It is a figure explaining the structure of the switch part of the presentation control apparatus of the 3rd modification of embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is an explanatory diagram of a gaming machine 1 according to an embodiment of the present invention.

A front frame (game frame) 3 of the gaming machine 1 is assembled to the main body frame (outer frame) 2 via a hinge 4 so as to be openable and closable on the front surface of the gaming machine 1. A game board 10 (see FIG. 2) is accommodated on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 10 is attached to the front frame 3.

Around the cover glass of the glass frame 18, decoration members 9 a and 9 b that emit decoration light are provided. The decoration members 9a and 9b are provided with a decoration device composed of a lamp, an LED, or the like. By causing the decoration device to emit light in a predetermined light emission mode, the decoration member 9a
9b emit light according to a predetermined light emission mode.

Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 11 is provided above the glass frame 18.

In the illumination unit 11, a first movable illumination 13 and a second movable illumination 14 are arranged on the left and right. The first movable illumination 13 and the second movable illumination 14 include an illumination drive first motor (MOT) 13a and an illumination drive second motor (MOT) 14a in addition to an illumination member such as an LED. It is controlled so as to operate according to the contents of the production.

An abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided at the lower right of the lighting unit 11.

The open / close panel 20 below the front frame 3 is provided with an upper plate for supplying a game ball to a ball hitting device (not shown), and the fixed panel 22 is provided with a lower plate 23 and an operation unit 24 of the ball hitting device. Lower plate 2
3 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23.
A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

In addition, an effect button 1 for accepting an operation input from a player is provided on the upper edge of the upper plate 21.
7 is provided. When the player operates the effect button 17, the effect content of the special figure variation display game on the display device 53 (see FIG. 2) provided on the game board 10 is selected,
It is possible to produce an effect in which the player's operation is intervened in the special figure variation display game on the display device 53.

The special figure variation display game is started when the launched game ball wins a start opening 36 (see FIG. 2) provided in the game board 10. In the special figure fluctuation display game, a plurality of pieces of identification information are variably displayed on the display device 53. Then, when the identification information that has been variably displayed is stopped and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (a state where a privilege is granted) Transition to a special gaming state.

In the upper right portion of the upper plate 21, a ball lending button 26 that is operated when a player borrows a game ball and a discharge button 27 that is operated to discharge a prepaid card from a card unit (not shown) are provided. . Further, a balance display unit 28 for displaying the balance of the prepaid card is provided between the ball lending button 26 and the discharge button 27.

  FIG. 2 is a front view of the game board 10 according to the embodiment of the present invention.

The gaming machine 1 shown in FIG. 1 fires a game ball in an internal game area 10a (bounces it) to play a game, and a game area 10a is provided on the back side of the cover glass of the glass frame 18. The game board 10 which comprises is installed.

The game board 10 includes a flat game board main body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and the game area 10 surrounded by a guide rail 32 on the front surface of the game board main body 10b.
a. In addition, on the outside of the guide rail 32 on the front surface of the game board main body 10b,
A front structural member 33 is attached. Then, a game ball (hit ball; game medium) is launched from the launching device into the game area 10a surrounded by the guide rail 32 to play a game.

A center case 51 that forms a window 52 serving as a display area for a special figure variation display game is attached to the approximate center of the game area 10a. Window 52 formed in center case 51
Behind is a display device 53 as an effect display device capable of executing an effect of a special-figure variable display game that variably displays a plurality of identification information. The display device 53 includes, for example, a liquid crystal display, and is arranged so that a display portion 53 a whose display contents can be changed is visible from the front side of the game board 10 through the window portion 52 of the center case 51. Note that the display device 53 is not limited to a device including a liquid crystal display, and may include a display such as an EL or a CRT.

In addition, a reliability notification device 15 that notifies the possibility of jackpot (reliability) is provided on the upper portion of the center case 51. The reliability notification device 15 includes LEDs of a plurality of colors (for example, LEDs of three colors of red, blue, and green) and is controlled to emit light in a color and manner according to the reliability.

Furthermore, on the left side of the center case 51, a ball introduction path (warp flow path) through which game balls can flow down
50 is provided, and the entrance 50a is opened toward the game area 10a.
The ball introduction path 50 communicates with the inside of the center case 51, and the game ball that has flowed from the inlet 50a passes through the back side of the center case 51 and is discharged onto the unit-side stage portion 49b. Further, the game ball that rolls on the unit-side stage portion 49b can flow down onto the base-side stage portion 49a disposed below the unit-side stage portion 49b.

A plurality of ornaments 47 are arranged on the peripheral edge of the center case 51. Center case 5
A decorative lamp 48 is disposed at the lower left portion of 1, and a plurality of decorative pieces 46 are disposed above and below the center case 51 so as to be movable up and down. The decoration tool 47, the decoration lamp 48, and the decoration piece 46 perform an effect operation according to a command from an effect control device 550 described later. The configuration of the center case 51 will be described in more detail with reference to FIG.

Further, in the game area 10a, below the center case 51, a start opening 36 for starting a special figure changing display game that can receive (win) a game ball is arranged. Further, on the side of the center case 51 (on the left side), a general map start gate 34 for starting the general map change display game is arranged.

Further, in the game area 10a, side lamps 45 that perform various decorative displays by light emission are arranged on the lower left and lower right of the center case 51. The side lamp 45 is provided with a general winning opening 44.

Further, a big winning opening 42 is arranged below the start opening 36, and an out opening for collecting the game balls that have flowed down without winning at the lower edge of the gaming area 10a below the big winning opening 42. 43 is established. The special winning opening 42 includes an attacker-type opening / closing door 42a that can be opened by rotating in a direction in which the upper end side is tilted to the near side. Depending on the result of the special figure change display game, the open / close door 42
a is changed from a closed state (a disadvantageous state for the player) to an open state (a state advantageous to the player).

In addition, in the game area 10a excluding attachment portions such as the center case 51, the start port 36, the side lamp 45, etc., there are a windmill (not shown) as a hitting direction changing member, and many No. nails (not shown) are provided. And the center case 51
A longitudinal arc-shaped game ball passage 57 is formed between the center case 51 and the front structural member 33 located on the opposite side of the usual start gate 34.

Further, the game board 10 is provided with a special figure / special figure display 35 for executing a special figure change display game and a normal figure change display game. The special map / special display 35 includes an unprocessed number of special figure change display games (special figure start memory number) and an unprocessed number of special figure change display games (general figure start memory number).
Is displayed. The multi-use / special-purpose display 35 is a game state display LED (not shown) indicating a game state.
In addition, it is provided as a segment LED.

A gate SW 34a (see FIG. 9) for detecting a game ball that has passed through the general chart start gate 34 is provided in the general chart start gate 34. Then, when the game ball that has been driven into the game area 10a passes through the normal figure start gate 34, the normal figure change display game is started.

In addition, when the game ball passes through the general chart start gate 34 in a state where the normal map variable display game cannot be started, if the general chart start memory number is less than the upper limit number, the general chart start memory number is incremented by one, One random number indicating whether or not the normal figure change display game is won is stored as a normal figure start memory.

The state in which the general map change display game cannot be started is, for example, a state in which the general map change display game has already been performed and the normal map change display game has not been completed, Is the state that has been converted to the open state.

It should be noted that the universal map change display game may display the universal map change display game in a part of the display area of the display device 53. In this case, for example, numbers, symbols, character designs, etc. are used as identification symbols. This identification symbol is displayed by variably displaying for a predetermined time and then stopped and displayed.

When the stop display of the normal map change display game becomes a special result mode, the opening / closing member 36a of the start port 36 is opened for a predetermined time (for example, 0.5 seconds) as a win for the normal map change display game. Is done. Thereby, it becomes easy to win a game ball in the start opening 36, and the special figure variation display game can be started easily. The opening / closing member 36a of the start port 36 normally maintains a closed state (a disadvantageous state for the player) with an interval of about the diameter of the game ball. When the stop display mode is entered (when the normal-game fluctuation display game is won), the game ball is opened in the reverse “C” shape by the solenoid (Fuden SOL 36b, see FIG. 9), and the game ball is placed at the start port 36. It is changed to a state that is easy to flow in (a state that is advantageous to the player).

In addition, the gaming machine 1 according to the embodiment of the present invention is based on the result mode of the special figure variation display game.
As the gaming state, it is possible to generate a short time operation state (second operation state) that shortens the variation display time of the special figure variation display game on the display device 53. The short-time operation state (second operation state) is a state in which the opening / closing member 36a of the start port 36 is likely to be open compared to the normal operation state (first operation state).

In the short-time operation state, the execution time of the normal variation display game is controlled to be shorter than the execution time in the normal operation state (for example, 10 seconds is 1 second), and the start port 3 per unit time is controlled.
The number of times of opening 6 is controlled to be substantially increased. Further, in the short-time operation state, when the start port 36 is opened due to the winning of the normal fluctuation display game, the opening time is controlled to be longer than the opening time of the normal operation state (for example, 0 .3 seconds is 1.8 seconds)
. Further, in the short-time operation state, the start port 36 is opened a plurality of times (for example, two times) instead of once for the one-time winning result of the normal map display game. Further, in the short-time operation state, control is performed so that the probability of winning the normal-variation display game is higher than that in the normal operation state. That is, the number of opening of the start port 36 is increased compared to the normal operation state, and the start port 36
This makes it easier for a game ball to win and makes it easier to start a special figure variation display game.

In addition, a start port SW 36 d (see FIG. 9) for detecting a game ball that has passed through the start port 36 is provided inside the start port 36. When a game ball is detected by the start port SW36d,
A start right to start a special figure variation display game as an auxiliary game is generated. At this time, the right to start the special figure variation display game is stored as a special figure start memory within a predetermined upper limit number (for example, 4).

When the special figure fluctuation display game cannot be started immediately, for example, when the special figure fluctuation display game has already been performed and the special figure fluctuation display game has not been completed, or when the special game state has been entered, the start port 36 When the game ball wins, if the special figure start memory number is less than the upper limit number (for example, less than 4), the special figure start memory number is incremented by 1 and extracted at the timing when the game ball wins the start opening 36. One random number is stored as a special figure start memory. When the special figure fluctuation display game is ready to start, the special figure fluctuation display game is started based on the special figure start memory.

The special figure variation display game as an auxiliary game is a general figure / special figure display 3 provided on the game board 10.
This process is executed by stopping and displaying a predetermined result form after a plurality of pieces of identification information are variably displayed. Further, a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) are displayed in a variable manner on the display device 53 in correspondence with the special figure fluctuation display game. And as a result of the special figure variation display game, when the display mode of the general figure / special map display 35 becomes a special result mode, it becomes a big win and becomes a special game state (so-called big hit state). Correspondingly, the display mode of the display device 53 is also a special result mode (for example, any one of the numbers in the flat order such as “7, 7, 7”). In addition, you may comprise so that a special figure fluctuation display game may be performed only with the display apparatus 53 instead of the general figure and special figure display 35. FIG.

Further, the gaming machine 1 according to the embodiment of the present invention can generate a probability variation state (second probability state) as a gaming state based on the result mode of the special figure variation display game. This probability variation state (second probability state) is a state in which the probability of a hit result in the special figure variation display game is higher than the normal probability state (first probability state). Note that the probability variation state and the above-described short-time operation state can be generated independently, and both can be generated at the same time, or only one of them can be generated.

  FIG. 3 is an exploded perspective view of the center case 51 according to the embodiment of the present invention.

The center case 51 includes a frame decoration portion 65 disposed as a front surface configuration portion on the front surface side of the game board main body 10b (game board 10), and a frame base portion 60 disposed as a back surface configuration portion on the back surface side of the game board main body 10b. And are polymerized before and after. The frame decoration portion 65 includes an annular decoration base 66 that is fixed to the surface of the game board main body 10b. On the back side of the decoration base 66, a decoration panel unit 67 is formed which is substantially the same size as the decoration base 66 and is formed in a circular shape.
5 is configured by superposing a decorative base 66 and a decorative panel unit 67 back and forth.

Under the decoration base 66, a base side stage portion 49a capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface, and a decoration lamp is provided between the base side stage portion 49a and the game ball passage 57. 48 is arranged (see FIG. 2). A ball introduction path (warp flow path) 50 through which a game ball can flow is provided on the side opposite to the decorative lamp 48 across the base side stage portion 49a.
Is provided with the inlet 50a of the sphere introduction path 50 open to the outside of the decoration base 66, and the outlet 50b of the sphere introduction path 50 communicates with the back side of the decoration panel unit 67 described later.

The decorative panel unit 67 includes a cover panel portion 69 formed of a substantially circular transparent resin plate, and a plurality of decorative tools 47 are arranged on the peripheral edge of the front side of the cover panel portion 69. When the decorative panel unit 67 and the frame decorative portion 65 are overlapped, the decorative tool 47 is set so as to be arranged along the inner peripheral edge of the decorative base 66 (see FIG. 2). In addition, a reliability notification device 15 is disposed on the upper portion of the cover panel unit 69.

In addition, a unit-side stage portion 49b capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface at the lower portion on the back side of the cover panel portion 69. The unit side stage portion 49b is disposed above the base side stage portion 49a of the decorative base 66.

Further, a sphere inlet 68 is opened at a location where the cover panel portion 69 overlaps with the outlet 50 b of the sphere introduction path 50, and the sphere introduction path 50 and the unit side stage 49 b are connected via the sphere inlet 68.
And communicate with. Therefore, when a game ball flowing down the game area 10a flows into the ball introduction path 50, the ball introduction path 50 is configured so that the game ball can be introduced onto the unit side stage portion 49b.

The frame base portion 60 includes a frame-like base case 61 that is fixed to the back side of the game board 10 in a state where the front side is open, and the inside of the base case 61 (in other words, the inside of the center case 51).
In addition, an opening 62a forms a concave chamber 62 provided on the front side.

In addition, a rectangular window 52 is opened in the front-rear direction behind the concave chamber 62 in the base case 61, and a display device 53 is attached from the rear of the base case 61 to display the display portion of the display device 53. 5
3a is exposed to the front of the center case 51 through the window 52 and the recessed chamber 62.

Further, a plurality of decorative pieces 46 that can be moved up and down by an accessory driving solenoid (not shown) are disposed on the front side of the upper edge of the window 52, and display portions are provided on the left and right edges of the window 52. 53
There is provided a movable effect device 58 that moves to the front of a and performs an effect operation.

Then, when the frame decoration portion 65 is overlapped in front of the frame base portion 60, the opening 62a and the window portion 52 of the concave chamber 62 are covered with the cover panel portion 69 from the front, and the display portion 53a of the display device 53 is covered with the frame decoration portion. It is configured to face the front of the center case 51 from the inside of 65 (where the cover panel portion 69 is exposed).

  4 and 5 are diagrams illustrating the configuration of the movable effect device 58 according to the embodiment of the present invention.

The movable effect device 58 is configured by providing the first effect unit 63 and the second effect unit 64 at positions separated from each other, and the first effect unit 63 and the second effect unit 64 are operated in conjunction with each other. .

FIG. 4 is a diagram illustrating a state before the movable effect device 58 is operated, and FIG. 5 is a result of the movable effect device 58 being operated and the first effect unit 63 and the second effect unit 64 being operated. It is a figure which shows the state contact | abutted in a part (1st contact part 121 and 2nd contact part 122).

The first effect unit 63 is disposed on the left side of the center case 51, that is, on the left side of the peripheral edge of the window portion 52 of the base case 61. Further, the second rendering unit 64 has a center case 51.
It is arranged on the right side. When viewed from the front of the center case 51, the concave chamber 62 and the window 52 are arranged so as to face between the first effect unit 63 and the second effect unit 64.

The first effect unit 63 includes a first effect member 70 that can move forward of the display unit 53a, and an accessory driving first motor (MOT) that serves as a first effect drive source that generates the driving force of the first effect member 70.
) 71 and a first effect transmission mechanism (a first main arm member 73 and a first sub arm member 74) that transmits the driving force (rotational power) generated from the accessory driving first MOT 71 to the first effect member 70. .

Further, an output shaft (first output shaft) 71a of the accessory driving first MOT 71 extends in the front-rear direction of the center case 51, and a first drive gear 76 is rotatably mounted on the first output shaft 71a. Yes.

The first main arm member 73 is formed with a first main arm gear 77 that meshes with the first drive gear 76, and is pivotally mounted above the first drive gear 76. The first sub arm member 74 is formed with a first sub arm gear 78 that meshes with the first drive gear 76, and is pivotally attached to the lower side of the first drive gear 76. The first main arm member 73 and the first sub arm member 74 are axially attached to the first effect member 70 at positions where the end portions opposite to the end portions axially attached to the base case 61 are different from each other. 70 is supported.

When the first effect unit 63 drives the accessory driving first MOT 71 and rotates the first driving gear 76 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving first MOT 71 is generated. The first main arm member 73 is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 is rotated counterclockwise when viewed from the front of the center case 51 by this driving force. To do. The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same counterclockwise direction as the arm member 73. As a result, the first effect member 70 becomes the first main arm member 73.
Ascending while being supported by the first sub arm member 74.

The first main arm member 73 and the first sub arm member 7 are driven by the driving force of the accessory driving first MOT 71.
When 4 is extended upward and set in the vertical orientation, as shown in FIG. 4, the first effect member 70 is placed in a first effect stop state in which the first effect member 70 is positioned away from the front of the display unit 53 a. Is located on the side of the window 52 and hidden behind the frame decoration 65 and behind the game board main body 10b (see FIG. 2).

On the other hand, when the first driving gear MOT 71 is driven from the first effect stop state and the first driving gear 76 is rotated counterclockwise when viewed from the front of the center case 51, the driving force (rotational power) of the first driving gear MOT 71 is rotated. ) Is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 rotates clockwise as viewed from the front of the center case 51 by this drive force. Move.

The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. Arm member 73
Rotate in the same clockwise direction. As a result, the first effect member 70 is lowered while being supported by the first main arm member 73 and the first sub arm member 74.

The first main arm member 73 and the first sub arm member 7 are driven by the driving force of the accessory driving first MOT 71.
When 4 is extended to the front of the display unit 53a and set in the horizontal posture, as shown in FIG. 5, the first effect member 70 is positioned in front of the display unit 53a, and the first effect member is executed. 7
0 is located in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69.

The second effect unit 64 includes a second effect member 80 that can move to the front of the display unit 53a, and an accessory driving second motor (MOT) as a second effect drive source that generates the drive force of the second effect member 80.
) 81 and a second effect transmission mechanism (second main arm member 83 and second sub arm member 84) that transmits the driving force (rotation power) generated from the accessory driving second MOT 81 to the second effect member 80. .

Further, the accessory driving second MOT 81 has an output shaft (second output shaft) 81a extending in the front-rear direction of the center case 51, and a second drive gear 86 is pivotally attached to the second output shaft 81a so as to be able to rotate together. Yes.

The second main arm member 83 is formed with a second main arm gear 87 that meshes with the second drive gear 86, and is pivotally attached to a position closer to the first effect unit 63 than the second drive gear 86. The second sub arm member 84 is formed with a second sub arm gear 88 that meshes with the second drive gear 86, and is pivotally attached to the lower side of the second drive gear 86. The second main arm member 83 and the second sub arm member 84 are pivotally attached to the second effect member 80 at positions where the end portions opposite to the end portions that are axially attached to the base case 61 are different from each other. 80 is supported.

When the second effect unit 64 drives the accessory driving second MOT 81 and rotates the second driving gear 86 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving second MOT 81 is generated. This is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates counterclockwise when viewed from the front of the center case 51 by this driving force. To do. Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same counterclockwise direction as the arm member 83. As a result, the second effect member 80 becomes the second main arm member 83.
And descends while being supported by the second sub-arm member 84.

The second main arm member 83 and the second sub arm member 8 are driven by the driving force of the accessory driving second MOT 81.
4 is rotated to bring the second effect member 80 to the bottom dead center, and the second main arm member 83 and the second
When the sub-arm member 84 is rotated to extend obliquely downward and set in a vertical posture and the second effect member 80 is slightly raised from the bottom dead center, as shown in FIG. Is in a second effect stop state where it is positioned away from the front of the display portion 53a, and the second effect member 80 is hidden behind the frame decoration portion 65 and behind the game board main body 10b (see FIG. 2).

On the other hand, when the accessory driving second MOT 81 is driven from the second effect stop state and the second driving gear 86 is rotated counterclockwise as viewed from the front of the center case 51, the driving force (rotational power) of the accessory driving second MOT 81 is rotated. ) Is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates clockwise as viewed from the front of the center case 51 by this driving force. Move.

Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. Arm member 83
Rotate in the same clockwise direction. As a result, the second effect member 80 rises while being supported by the second main arm member 83 and the second sub arm member 84.

The second main arm member 83 and the second sub arm member 8 are driven by the driving force of the accessory driving second MOT 81.
When 4 is extended to the front of the display unit 53a and set to the horizontal orientation, as shown in FIG. 5, the second effect member 80 is placed in front of the display unit 53a, and the second effect member is executed. 8
0 is located in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69.

  FIG. 6 is an exploded perspective view of the first effect member 70 according to the embodiment of the present invention.

The first effect member 70 is a substantially semicircular member when viewed from the front of the center case 51, and is set in a posture in which an arc surface is disposed on the first effect unit 63 side.

The first effect member 70 is provided with a first effect base 100 serving as a base. The first effect base 100 is formed of a transparent resin. Formed on the upper portion of the first effect base 100 is a first main arm axis attachment portion 101 for axially attaching the first main arm member 73 from the front of the first effect base 100,
A first sub-arm shaft attachment portion 102 that pivotally attaches the first sub-arm member 74 from the rear of the first effect base 100 is formed in the lower portion of the first effect base 100.

On the front surface of the first production base 100, a first light diffusion sheet 10 that can transmit light while diffusing light.
3 is polymerized. Further, a transparent first protective panel 104 is provided on the front surface of the first light diffusion sheet 103.
The first light diffusing sheet 103 is prevented from dropping from the first effect member 70 by polymerizing.

Further, the rear portion of the first production base 100 is recessed forward to form a first substrate storage space portion 105, and a light emitting device such as an LED (decoration device 620, see FIG. 17) is formed in the first substrate storage space portion 105. The mounted first light emitting substrate 106 is accommodated. Further, in this state, the first substrate housing space portion 105 is closed with the first base lid portion 107 to prevent the first light emitting substrate 106 from falling off the first effect member 70.

Then, when light is generated from the light emitting device of the first light emitting substrate 106, this light is transmitted through the first effect base 100, the first light diffusion sheet 103, and the first protective panel 104, and the center case 51.
It is comprised so that it may irradiate ahead.

Further, the first contact portion 121 has a rear portion opened to the first substrate storage space 105 side.
The effect magnet holder 124 is recessed. The first effect magnet holder 124 has a first magnet 125 made of a button-shaped permanent magnet in a posture in which the magnetic pole faces the second effect member 80 side.
The 1st magnet 125 is stored so that it may not drop from the 1st contact part 121 (1st production magnet holder 124).

The first light-emitting substrate 106 is equipped with an I2CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and a control signal (
A data line and a clock line (signal line) for transmission such as an electrical signal are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 108.

  FIG. 7 is an exploded perspective view of the second effect member 80 according to the embodiment of the present invention.

The second effect member 80 has a substantially parallelogram shape with a cutout portion at the top when viewed from the front of the center case 51. In the second effect stop state, the upper and lower side surfaces of the second effect member 80 are inclined downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 4).
In the second effect execution state, the left and right side surfaces of the second effect member 80 are connected to the second effect unit 64.
The posture is set to be inclined downward from the side toward the first effect unit 63 side (see FIG. 5).

The second effect member 80 includes a second effect base 110 that serves as a base. The second effect base 110 is formed of a transparent resin. On the upper part of the second effect base 110, a second main arm shaft attachment portion 111 for attaching the second main arm member 83 from the front of the second effect base 110 is formed.
A second sub-arm shaft attachment portion 112 that pivotally attaches the second sub-arm member 84 from the rear of the second effect base 110 is formed below the second effect base 110.

Further, a second light diffusing sheet 113 that can transmit light while diffusing light is superposed on the front surface of the second effect base 110. A transparent second protective panel 114 on the front surface of the second light diffusion sheet 113
The second light diffusing sheet 113 is prevented from falling off from the second effect member 80 by polymerizing the above.

In addition, the rear portion of the second effect base 110 is recessed forward to form a second substrate storage space 115, and a light emitting device (decoration device 620) such as an LED is mounted in the second substrate storage space 115. The second light emitting substrate 116 is accommodated, and in this state, the second substrate accommodating space 115 is closed by the second base lid portion 117 to prevent the second light emitting substrate 116 from dropping from the second effect member 80. .

When light is generated from the light emitting device of the second light emitting substrate 116, the light passes through the second effect base 110, the second light diffusing sheet 113, and the second protective panel 114 and passes through the center case 51.
It is comprised so that it may irradiate ahead.

Further, the second contact portion 122 has a rear portion opened on the second substrate storage space 115 side.
The effect magnet holder 128 is recessed. In the second effect magnet holder 128, a second magnet 129 made of a button-shaped permanent magnet is stored at a position symmetrical to the first magnet 125 across the first contact portion 121 and the second contact portion 122. Has been.

Similar to the first light-emitting substrate 106, the second light-emitting substrate 116 is equipped with an I2CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and the effect control device 5
A data line and a clock line (signal line) for transmitting a control signal output from 50 are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 118.

The movable effect device 58 includes the first contact member 121 on the first effect member 70 and the second contact member 122 on the second effect member 80. When the first effect unit 63 is converted to the first effect execution state and the second effect unit 64 is converted to the second effect execution state, the first effect unit 63 is converted into the first effect execution state.
The contact portion 121 and the second contact portion 122 are in contact with each other, and the first effect member 70 and the second effect member 80 form one decorative body. At this time, the first magnet 125 and the second magnet 129 are arranged so as to generate an attractive force between the first magnet 125 and the second magnet 129. Further, the decorative body thus formed is configured to be positioned in front of the central portion of the display portion 53a.

  FIG. 8 is a diagram illustrating wiring of the gaming machine 1 according to the embodiment of the present invention.

FIG. 8 shows a state before the center case 51 is attached to the game board main body 10 b and the display device 53 is attached to the center case 51. An effect control device 550 is attached to the back surface of the display device 53. The effect control device 550 includes a connection terminal 90.
Are provided, and control signals are transmitted and electric power is supplied to the rendering device to be controlled via the connection terminal 90. Specifically, it is connected via a cable 91 to a relay board 600 described later.

In addition, a game control device 500 and a control unit 700 including various control boards are arranged at the lower back of the game board main body 10b. The control board mounted on the control unit 700 includes a relay board 600 that relays the control signal transmitted from the effect control apparatus 550 to the decoration control apparatus 610 (see FIG. 11). Although the details will be described later, the decoration control device 610 controls an effect device such as a light emitting device (for example, LED) or a movable object (for example, a motor) for effecting a game. The relay board 600 can be connected to a light emitting device or a movable object, similarly to the decoration control device 610.

The relay board 600 is provided with an upstream connector 601 connected to the effect control device 550 via the cable 91. One connector 91a of the cable 91 is connected to the connection terminal 90 of the effect control device 550 as described above. The other connector 91b of the cable 91 is
It is connected to the upstream connector 601 of the relay board 600. Furthermore, connectors 602a to 602e for connecting to a decoration control device 610 that controls each effect device provided in the gaming machine 1 are provided.

Further, the relay board 600 has a vacant terminal monitor 6 indicating the connection state of the connected cables.
03 is provided. Details of the empty terminal monitor 603 will be described with reference to FIG.

Although illustration is omitted, units constituting the game control device 500 are provided so as to cover the connector mounting surface of the relay board 600. Therefore, the game control apparatus 500 has an arrangement configuration that is attached after attaching necessary cables to the connectors of the relay board 600.

Connected to the front frame 3 is a cable 3b for transmitting signals for controlling the speaker 30 and the decorative members 9a, 9b and the like disposed on the front frame 3. The connector of the cable 3b is connected to the connection terminal 92 of the effect control device 550.

An opening 45b for attaching the side lamp 45 is formed in the game board main body 10b. A cable 45a for transmitting power and signals is connected to the side lamp 45, and is introduced from the opening 45b to the back side of the game board 10. The cable 45a introduced to the back side of the game board 10 is connected to the relay board 600, for example, connected to the connector 602d.

Further, as shown in FIG. 2, a starting port 36 and a special winning port 42 are arranged at the lower part of the game board 10. On the back side of the game board 10 on which the start opening 36 is arranged, there is a general-use solenoid (SOL) 36 for opening and closing an open / close member 36a that is opened when a normal-game variable display game is won.
b is arranged. In addition, a special winning opening SOL 42 b for opening and closing the special winning opening 42 when the special figure variation display game is won is also arranged on the back side of the game board 10. A cable (not shown) for receiving an input of a control signal is connected to the general electric power SOL 36 b and the special winning opening SOL 42 b, and these cables are connected to the game control device 500. Also, cable 42C
Is connected to the relay board 600 as a cable for transmitting power and signals for turning on the LED for presentation provided in the special winning opening 42, and is connected to the connector 602f, for example.

As described above, the center case 51 is attached to the center of the game board 10.
Inside the center case 51, a movable effect device 58 constituted by the first effect member 70 and the second effect member 80 is provided. In FIG. 8, the first effect member 70 and the second effect member 80.
Is in contact with the contact surfaces (121, 122).

Further, as described above, the first effect unit 63 and the second effect unit 64 of the movable effect device 58 include the motor (the accessory driving first motor) for operating the first effect member 70 and the second effect member 80. 71, an accessory driving second motor 81) is provided. Then, a cable 65 for supplying a signal for controlling these motors and electric power for driving the motors.
2 is connected to the movable effect device 58. In addition, the movable rendering device 58 is provided with a motor position detection sensor (not shown) for detecting the operation state of these motors, and a cable 651 for receiving a sensing result is connected. The cable 652 and the cable 651 extend from the opening 51 b of the center case 51 to the back side of the game board 10 and are connected to the relay board 600. For example, the cable 652 is connected to the connector 602C, and the cable 651 is connected to the connector 602e.

Furthermore, a cable 653 is connected to transmit the control signal output from the effect control device 550 to a decoration control device 610 (see FIG. 11) for controlling the effect device such as an LED disposed inside the center case 51. The The cable 653 is connected to the relay board 600 on the back side of the game board 10 through an opening 51a provided in the center case 51, and is connected to, for example, a connector 602a.

  FIG. 9 is a block diagram showing a configuration of the gaming machine 1 according to the embodiment of the present invention.

The gaming machine 1 includes a game control device 500 that controls the game in an integrated manner, an effect control device 550 that controls the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) for paying out game balls. A payout control device 580 for controlling is provided.

First, the configuration of the game control device 500 will be described. The production control device 550 will be described with reference to FIG.

The game control device 500 includes a game microcomputer 501 and an input I / F (Interface) 5.
05, an output I / F (Interface) 506, and an external communication terminal 507.

The gaming microcomputer 501 includes a CPU 502, ROM (Read Only Memory).
503 and RAM (Random Access Memory) 504.

The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game. RO
M503 stores invariant information (program, data, etc.) for game control. R
The AM 504 is used as a work area during game control.

The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects the setting information of the game control device 500.

The CPU 502 receives various input devices (start opening SW36d, general winning openings SW44a to 44n, gate SW34a, count SW42d, glass frame opening SW1 via the input I / F 505.
8a, the front frame opening SW 3a, the ball break SW 54, the vibration sensor 55, and the magnetic sensor 56) are received, and various processes such as a big hit lottery are performed.

The start port SW36d is a switch that detects that a game ball has won the start port 36.
The general winning ports SW 44 a to 44 n are switches that detect that a game ball has won the general winning port 44.

The gate SW 34a is a switch that detects that a game ball has passed through the usual start gate 34. The count SW 42d is a switch that detects that a game ball has won a prize winning opening 42.

The glass frame opening SW 18a is a switch that detects that the glass frame 18 has been opened. The front frame opening SW 3a is a switch for detecting that the front frame 3 is opened.

The ball cut SW 54 is a switch that detects that the number of game balls stored in the gaming machine 1 and used for payout has become a predetermined number or less.

The vibration sensor 55 is a sensor that detects vibration applied to the gaming machine 1 and detects an illegal act such as vibrating the gaming machine 1. The magnetic sensor 56 is a second start winning port of the start port 36,
It is a sensor that is provided in the vicinity of the general winning opening 44, the big winning opening 42, and the usual start gate 34, and detects magnetic force. The magnetic sensor 56 detects a fraud that brings a magnet close to each winning hole and guides the game ball launched to the gaming area 10a to each winning hole.

In addition, the CPU 502 is connected to the ordinary / special-purpose display 35, the ordinary electric SO via the output I / F 506.
A command signal is transmitted to L36b, special winning opening SOL42b, payout control device 580, and effect control device 550 to control the game in an integrated manner.

As described above, the special figure change display game and the universal figure change display game are executed on the special figure / special figure display unit 35. Furthermore, the number of unprocessed times (special figure start memory number) of the special figure change display game and the number of unprocessed times (standard figure start memory number) of the normal figure change display game are displayed. A general chart start memory including a random number indicating whether or not the special figure fluctuation display game is won and a special figure start memory including a random number indicating whether or not the special figure fluctuation display game is a win are stored.

The general electric power SOL 36b opens the opening / closing member 36a when the stop display of the general-purpose variable display game becomes a special result mode, thereby making it easy for the game ball to win the start opening 36.

The special winning opening SOL42b opens the open / close door 42a of the special winning opening 42 when the result of the special figure change display game becomes a special result mode and becomes a special gaming state (a big hit state), and a game ball Is converted to a state where it is easy to win.

The game control device 500 outputs game machine data from the external information terminal 508 to a game hall management device (not shown) via an information collection terminal device (not shown). The gaming hall management device is a computer that collects and manages gaming data of the gaming machines 1 installed in the gaming hall.

The payout control device 580, when the game ball wins the general winning opening 44 or the big winning opening 42,
A payout command for the number of game balls corresponding to the winning winning award is received from the game control device 500. Further, even when the ball lending button 26 is operated, a payout command for paying out a predetermined number of game balls is received from the game control device 500. Based on the received payout command, the payout control device 580
A payout motor (not shown) is controlled to pay out the number of game balls specified in the payout command.

The game control device 500 uses a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like as game data indicating the game situation via the output I / F 506, and the effect control device 550. Send to.

  FIG. 10 is a block diagram showing a configuration of the effect control device 550 according to the embodiment of the present invention.

The effect control device 550 determines the contents of the effect based on the game data input from the game control device 500, controls the display device 53, and controls various effect devices provided in the game board 10 and the front frame 3. To do. The rendering device includes a light emitting device such as an LED and a movable object such as a motor or a solenoid.

The production control device 550 includes a CPU 551, a control ROM 552, a RAM 553, and an image ROM.
554, sound ROM 555, VDP 556, sound LSI 557, input I / F 558b, output I
/ F558a, power-on detection circuit 559, first master IC 570a, second master IC57
0b, a NOR gate circuit 561 and a monitoring timer circuit 562. Furthermore, the production control device 550 includes a connection terminal 90 connected to the game board 10 and a connection terminal 9 connected to the front frame 3.
2 is provided. The functions common to the first master IC 570a and the second master IC 570b will be described simply as “master IC”.

The CPU 551 receives the command signal transmitted from the game control device 500 as an interrupt signal (INT) as a communication interrupt, and controls various effects based on the input command signal.
The CPU 551 receives an interrupt signal (INT) as a master interrupt from the first master IC 570a and the second master IC 570b, and also receives an interrupt signal (INT) as an image update interrupt from the VDP 556. Is done.

Further, the CPU 551 receives an interrupt signal (INT) as a timeout interrupt also from the monitoring timer circuit 562. The monitoring timer circuit 562 includes a plurality of types of monitoring timers. When the monitoring timer value set by the CPU 551 expires, the CPU
An interrupt signal is output to 551. When the CPU 551 receives an input of an interrupt signal, the CPU 551 interrupts the process being executed and executes a process corresponding to the input interrupt signal.

The control ROM 552 stores invariant information (program, data, etc.) for effect control. The RAM 553 is used as a work area during production control.

The image ROM 554 is connected to the VDP 556 and stores image data displayed on the display device 53. The VDP 556 is a processor that controls image output to the display device 53.

In addition, the VDP 556 includes a synchronization signal generating unit that generates a synchronization signal that is synchronized with a cycle (33 ms cycle) for updating an image displayed on the display device 53. Every time the synchronization signal is generated, the synchronization signal generation means inputs the generated synchronization signal to the CPU 551 as an interrupt signal.

The sound ROM 555 is connected to the sound LSI 557 and stores sound data output from the speaker 30 provided in the front frame 3. The sound LSI 557 is a circuit that controls the sound output from the speaker 30.

The input I / F 558b is an interface that receives information input from the outside via the filters 565a and 565b. Specifically, the production button 1 provided on the front frame 3
7 is received, or an input of position information of each motor detected by a motor position detection sensor provided in the game board 10 is received.

The power-on detection circuit 559 generates a reset signal that initializes the registers of the first master IC 570a and the second master IC 570b to a default state (all 0) when the effect control device 550 is powered on, and generates a NOR gate. Output to the circuit 561.

Further, the CPU 551 outputs a reset signal to the output I / F 558a via the bus 563 when a predetermined condition is satisfied. The output I / F 558a outputs the input reset signal to the NOR gate circuit 561, and further from the NOR gate circuit 561 to the first
The reset signal is output to the master IC 570a and the second master IC 570b. The predetermined condition is, for example, a case where an error flag is “ON” in all the decoration control devices 610 (see FIGS. 32 and 33).

Further, the output I / F 558a outputs a control signal to an effect device (an effect device driven by a movable object such as a motor or a solenoid) provided in the game board 10 or the front frame 3 via the driver 564a and the driver 564b. .

Note that the reset signal input from the power-on detection circuit 559 to the NOR gate circuit 561 and the reset signal input from the CPU 551 to the NOR gate circuit 561 via the output I / F 558a are in a LOW level state in any case. It functions as a signal for commanding reset at the time. Therefore, if a reset signal is output from at least one of the power-on detection circuit 559 and the CPU 551 to the NOR gate circuit 561, the NOR gate circuit 56
1 is input to the first master IC 570a and the second master IC 570b.

FIG. 11 shows the first master IC 57 provided in the effect control device 550 according to the embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a rendering device provided in 0a and the game board 10;

The game board 10 includes a relay board 600 connected to the first master IC 570a, the relay board 6
The decorative device substrate 625 connected to 00 and the auxiliary game device unit 12 are provided.

The relay board 600 transmits (relays) the electrical signal transmitted from the first master IC 570 a to the decoration control device 610 provided in the game board 10. In addition, the relay board 600 has a function of controlling the effect device, similarly to the decoration control device 610, and controls the decoration device board 625 directly connected to the relay board 600.

The decoration device 620 includes an I2CI / O expander 615 provided in the decoration control device 610.
(Refer to FIG. 17) is a light-emitting device that produces an effect by flashing light by passing an electric current, such as an LED. The decoration device substrate 625 is provided with a side lamp 45 (FIG. 8).
The light emitting device (LED) of the side lamp 45 is mounted. The light emitting device of the side lamp 45 is directly controlled by an I2CI / O expander 615 provided on the relay board 600.

The auxiliary gaming device unit 12 includes a decoration device 620 that is a light emitting device such as an LED, a first accessory driving first motor (MOT) 71 that is a movable object, and a second accessory driving second MOT 81.
The decoration device 620 in the auxiliary gaming device unit 12 is controlled by the decoration control device 610 included in the auxiliary gaming device unit 12. In the embodiment of the present invention, the accessory driving first M
The OT 71 and the accessory driving second MOT 81 are configured to be controlled by the relay board 600, but are configured to be controlled by the decoration control device 610 included in the auxiliary gaming device unit 12 in the same manner as the decoration device 620. May be.

The first accessory driving MOT 71 and the second accessory driving MOT 81 are driving devices that perform an effect operation by rotating when current flows. The accessory drive first MOT 71 and the accessory drive second
Since the MOT 81 is directly controlled by the driver 564 of the effect control device 550 via the relay board 600, the process of interposing the I2CI / O expander 615 is not performed.

In the embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are included in the movable effect device 58. Specifically, the accessory driving first MOT 71 is the first effect unit 63.
The accessory driving second MOT 81 is included in the second effect unit 64.

The effect control device 550 controls the first and second effect units driving MOT 71 and second MOT 81 to cause the first effect unit 63 and the second effect unit 64 to perform an effect operation.

The first master IC 570a controls the decoration control device 6 that controls the decoration device 620 to be controlled.
The address individually assigned to 10 is designated, and the control content of the decoration device 620 is output to the decoration control device 610 of the designated individual address. It should be noted that the individual address of the decoration control device 610 is precisely the I2CI / O expander 615 (FIG. 1) included in the decoration control device 610.
7).

The first master IC 570a includes a connection line SDA, a connection line SCL, a connection line GND, and a connection line Vc.
c, the connection line Vled, the connection line Vms, and the connection line Vse are connected to the relay board (decoration control device) 600 through seven types of connection lines. These connection lines are connected to the first master IC 570a.
And the relay board 600 are configured by a cable 91 (see FIG. 8).

Connection line SDA is a connection line for communicating data signals between effect control device 550 and decoration control device 610, and functions as a data line in the embodiment of the present invention. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication on the connection line SDA, and functions as a timing signal line in the embodiment of the present invention. Connection line GN
D is a ground of the power supplied by the connection line Vcc, the connection line Vled, the connection line Vms, and the connection line Vse.

The connection line Vcc is a connection line for supplying logic power to the relay board 600 and the decoration control device 610. The connection line Vled is a connection line for supplying power for causing the LED (decoration device 620) to emit light. The connection line Vms is a motor or solenoid included in the auxiliary gaming device unit 12 (specifically, an accessory driving first MOT 71, an accessory driving second MOT).
81) is a connection line for supplying power. The connection line Vse is a connection line for supplying power to various sensors (a state detection sensor that detects the state of the motor included in the rendering device, and specifically corresponds to the motor position detection sensor 560a). is there.

Between the relay board 600 and the auxiliary gaming device unit 12, seven types of connection lines that connect the effect control device 550 and the relay board 600 are connected. In the embodiment of the present invention, the motor position detection sensor 560a, the accessory driving first MOT 71, and the accessory driving second MOT 81 are directly controlled by the relay board 600, and therefore, the connection line Vms among the seven types of connection lines described above.
The five types of connection lines other than the connection line Vse are connected to the decoration control device 610 disposed at the uppermost stream of the auxiliary gaming device unit 12. Specifically, the relay board 600 and the decoration control device 61.
Between 0, the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, and the connection line G
ND is connected.

When the wiring (cable) shown in FIG. 8 is associated with each connection line, the effect control device 550 is provided.
Various connection lines (connection line Vcc, connection line Vled, connection line SDA, connection line SCL, connection line Vms, connection line Vse, and connection line GND) delivered to the relay board 600 are included in the cable 91.

These various connection lines are further branched from the relay board 600 and delivered to another board. The connection line Vcc, the connection line Vled, the connection line SDA, and the connection line SCL branched from the relay board 600 are connected to the cable 653. The connection line Vms is included in the cable 652, and the connection line Vse is included in the cable 651. Further, the connection line GND branched from the relay board 600 is included in all the cables 651 to 653.

The first master IC 570a and the decoration control device 610 perform two-line bidirectional communication using the connection line SDA and the connection SCL. The first master IC 570a functions as a (first) signal level control means for controlling each signal level of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551. To do.

When transmitting data to the relay board 600 and the decoration control device 610, the first master IC 570a first maintains the connection line SDA while keeping the signal level of the connection line SCL at HIGH.
Is changed from HIGH to LOW to establish a start condition for starting data output to the decoration control device 610 (issue (output) a start condition to the decoration control device 610).

Thereafter, the first master IC 570a changes the signal level of the connection line SCL to LOW, and sets the signal level of the connection line SDA to the level of the first bit of the transmission data while the signal level of the connection line SCL is LOW. After a predetermined time, the signal level of the connection line SCL is changed from LOW to HI.
Change to GH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 6
10 acquires the signal level of the connection line SDA and recognizes it as the first bit of the transmission data.
Next, the first master IC 570a returns the signal level of the connection line SCL from HIGH to LOW.

When this procedure is executed once, 1-bit data is transmitted from the first master IC 570a to the decoration control device 610. Finally, this procedure is repeated 8 times, so that the transmission data 8
All the bits are transmitted from the first master IC 570a to the decoration control device 610 (1 byte of data is transmitted).

Then, when the data transmission of the last 8 bits is completed, the first master IC 570a releases the connection line SDA and returns a response from the decoration control device 610 when the signal level of the connection line SCL is returned from HIGH to LOW. A reception standby state in which a signal is received is set.

In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the first master IC 570a via the connection line SDA. Next, the first master IC 570a changes the signal level of the connection line SCL from LOW to HIGH to capture the response signal level, and after a predetermined time, changes the signal level of the connection line SCL from HIGH to LOW.
The decoration control device 610 releases the connection line SDA.

The first master IC 570a alternately repeats such data transmission for 1 byte (transmission of downlink data) and reception of a response signal for 1 bit (reception of uplink data), and outputs the result to the decoration control device 610. Continue until all the data to be output is output. First master IC5
70a sets the signal level of the connection line SCL to H when the output of the data to be output is completed.
The stop condition for terminating the data output to the decoration control device 610 is established by changing the signal level of the connection line SDA from LOW to HIGH while maintaining the IGH (stop condition for the decoration control device 610). Issue).

The input buffer 571 is a storage device that temporarily stores data input from the decoration control device 610 via the connection line SDA.

Specifically, when the first master IC 570a is set to the input mode, the data transmitted from the decoration control device 610 to the first master IC 570a is temporarily removed to the input buffer 571 after the noise is removed by the filter 575a. Is remembered.

The output buffer 572 temporarily stores data output to the decoration control device 610 via the connection line SDA.

The reset register (REG) 573 is connected to the bus 563, receives a command from the CPU 551 of the effect control device 550, and outputs a reset signal to the controller 574. The controller 574 comprehensively controls the first master IC 570a and executes various processes.

The filter 575a removes noise from data input from the connection line SDA. When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage at which the transistor 578a can operate to the transistor 578a.

A predetermined voltage is applied to the connection line SDA by a pull-up resistor R (see FIG. 21), and the connection line SDA is connected to the filter 575a and the transistor 578a.

As the transistor 578a, a field effect transistor (FET) is used in order to suppress power consumption. The gate of the transistor 578a is connected to the driver 576a, the drain is connected to the connection line SDA to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

If the voltage applied to the gate of the transistor 578a is smaller than a predetermined value for operating the transistor 578a, no current flows between the drain and the source.
As a result, the connection line SDA becomes HIGH level. on the other hand,
When the voltage applied to the gate of the transistor 578a is equal to or higher than a predetermined value for operating the transistor 578a, a current flows from the drain to which the predetermined voltage is applied to the grounded source, whereby the voltage of the connection line SDA is reduced. As a result, the connection line SDA is LOW.
Become a level.

Note that the transistor 578a has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. For this reason, the connection line SDA has a normal I2
It is possible to pass a current of about 10 milliamperes that is much larger than the current value used when using the C bus, and the data transmission between the production control device 550 and the decoration control device 610 can withstand a failure due to noise. It has become.

When the driver 576a outputs data from the connection line SDA, the driver 576a
In order to pass a current between the drain and source in a, a voltage having a value that allows the transistor 578a to operate is applied to the gate of the transistor 578a. Then, the driver 576a outputs data from the connection line SDA by setting the voltage of the connection line SDA to the HIGH level or the LOW level.

Further, the filter 575b removes noise from data input from the connection line SCL.
When the driver 576b outputs data from the connection line SCL, the driver 576b
Is applied to the transistor 578b.

A predetermined voltage is applied to the connection line SCL by the pull-up resistor R (see FIG. 21), and the connection line SCL is connected to the filter 575b and the transistor 578b.

A field effect transistor (FET) is used as the transistor 578b in order to reduce power consumption. The gate of the transistor 578b is connected to the driver 576b, the drain is connected to the connection line SCL to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

If the voltage applied to the gate of the transistor 578b is smaller than a predetermined value for operating the transistor 578b, no current flows between the drain and the source.
As a result, the connection line SCL becomes HIGH level. on the other hand,
If the voltage applied to the gate of the transistor 578b is equal to or higher than a predetermined value for operating the transistor 578b, the current flows from the drain to which the predetermined voltage is applied to the grounded source, so that the voltage of the connection line SCL is reduced. As a result, the connection line SCL is LOW.
Become a level.

Note that the transistor 578b has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, the connection line SCL has a normal I2
It is possible to pass a current of about 10 milliamperes that is much larger than the current value used when using the C bus, and the data transmission between the production control device 550 and the decoration control device 610 can withstand a failure due to noise. It has become.

When the driver 576b outputs a clock signal from the connection line SCL, the driver 576b applies a voltage having a value at which the transistor 578b can operate to the gate of the transistor 578b so that a current flows between the drain and the source of the transistor 578b. The driver 576b
A clock signal is output from the connection line SCL by repeatedly changing the voltage of the connection line SCL between a HIGH level and a LOW level.

The power-on reset circuit 577 defaults storage areas such as the input buffer 571 and the output buffer 572 when the first master IC 570a is powered on and the voltage in the power-on reset circuit 577 reaches a predetermined value. A reset signal for setting the state is output to the controller 574. As for the power-on reset circuit 577, the first master IC
It may be provided outside 570a and may be common to a second master IC 570b described later.

The command register (REG) 581 is a register for receiving a command from the CPU 551 of the effect control device 550. In the embodiment of the present invention, the command register 58
1, each bit of STA, STO, SI, and MODE is assigned in advance, and C
The PU 551 can set “0” or “1” for each bit individually.

The STA is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a start condition (start condition). “1” for STA
Is set, the first master IC 570a issues (outputs) a start condition to the decoration control device 610 to be controlled, thereby satisfying the start condition.

The STO is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a stop condition (stop condition). “1” for STO
Is set, the first master IC 570a issues (outputs) a stop condition to the decoration control device 610 to be controlled to establish the stop condition.

SI is a bit that is set when an interrupt is generated in the effect control device 550 from the first master IC 570a. When an interrupt is generated from the first master IC 570a to the CPU 551, the controller 574 sets SI to “1” and an interrupt signal (
INT) is input to the CPU 551. Thereafter, while the SI is set to “1”, the first master IC 570a suspends processing. However, when the CPU 551 sets SI to “0”, the first master IC 570a interrupts. Suspend and resume processing.

MODE is a bit for designating a mode for transmitting data, and “buffer mode” is designated when “1” is set, and “byte mode” is designated when “0” is set. . The buffer mode is a mode for transmitting a plurality of continuous bytes of data at a time and transmitting a maximum of 68 bytes of data. The byte mode is a mode in which only one byte of data can be transmitted in one transmission, and is used for data transmission / reception in units of bytes.

The status register (REG) 582 stores information indicating the status of the first master IC 570a. “0” is always set in the lower 2 bits, and the status code is set in the upper 5 bits.

The own address setting register (REG) 583 indicates that the first master IC 570a is a slave (
It is a register set when functioning as a decoration control device. A commercially available master IC usually has a function as a master and a function as a slave, and is used according to the application. In the own address setting REG 583, an address for specifying itself when the first master IC 570a functions as a slave is set.

FIG. 12 shows the second master IC 57 provided in the effect control device 550 according to the embodiment of the present invention.
It is a block diagram showing the configuration of the effect device provided in 0b and the front frame 3.

The front frame 3 includes a simple relay board 1600 connected to the second master IC 570b, a decoration control device 610 connected to the simple relay board 1600, a speaker 30, a motor position detection sensor 560b, an illumination drive first MOT 13a, and an illumination drive first. 2MOT 14a and the like are included.

The simple relay board 1600 transmits (relays) the electrical signal transmitted from the second master IC 570 b to the decoration control device 610 provided in the front frame 3. Note that, unlike the relay board 600, the simple relay board 1600 does not include the I2CI / O expander 615. Therefore, the electronic components provided in the simple relay board 1600 execute arithmetic processing for controlling the effect device. It does not have a function to do. Therefore, since the illumination driving first MOT 13a and the illumination driving second MOT 14a that are directly connected to the simple relay board 1600 cannot be controlled by their own judgment, the simple relay board 1600 receives the electric signal received from the second master IC 570b. Thus, it plays a role of relaying to the illumination driving first MOT 13a and the illumination driving second MOT 14a.

The illumination drive first MOT 13a and the illumination drive second MOT 14a drive the light emitting member provided inside based on the signal transmitted from the effect control device 550, and execute various effects.

In addition, the effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17 via the simple relay board 1600. Furthermore, the illumination drive first MOT 13a and the illumination drive second MOT 14a detected by the motor position detection sensor 560b.
Is input via the simple relay board 1600.

Further, the simple relay board 1600 receives a signal from the sound LSI 557 of the effect control device 550 and outputs it from the speaker 30.

Since the configuration of the second master IC 570b is the same as that of the first master IC 570a, the same reference numeral is assigned to each configuration of the second master IC 570b, and description thereof is omitted. Also,
Similar to the first master IC 570a, the second master IC 570b controls each signal level of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551 (second Function as signal level control means.

The connection method between the effect control device 550 and the relay board 600 and the connection method between the relay board 600 and the decoration control device 610 other than the relay board 600 will be described in detail later with reference to FIGS. The configuration of the relay board 600 and the decoration control device 610 is shown in FIG.
Details will be described later with reference to FIGS.

The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The decoration device (LED) 620 controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration members 9a and 9b, the illumination unit 11, and the abnormality notification LED 29.
On the other hand, the decoration control device 610 attached to the game board 10 is included in the auxiliary game device unit 12 configured by integrating the center case 51, the display device 53, and the effect control device 550.

In FIG. 13, a configuration and connection form of the decoration control device 610 included in the relay board 600 and the auxiliary game device unit 12 provided in the game board 10 will be described. In FIG. 14, configurations and connection forms of the simple relay board 1600 and the decoration control device 610 provided in the front frame 3 will be described.

  FIG. 13 is a diagram showing a configuration of the game board 10 according to the embodiment of the present invention.

As described above, the center case 51 constituting the auxiliary gaming device unit 12 is configured by combining the frame decoration portion 65 and the frame base portion 60.

The frame decoration unit 65 is provided with a plurality of effect devices for performing auxiliary games such as a variable display game, and a decoration control device 610 for controlling the effect devices. These decoration control devices 610 are connected to each other by a predetermined signal cable, and the effect device controlled by the decoration control device 610 is also connected by a cable, whereby the frame decoration portion 65 is integrally configured.

The frame base 60 is also provided with a plurality of effect devices for performing an auxiliary game such as a variable display game, and a plurality of decoration control devices 610 for controlling the effect devices. By connecting these decoration control devices 610 to each other by a predetermined signal cable, and also connecting the effect device controlled by the decoration control device 610 with a cable, the frame base 60 is integrally configured.

Therefore, the frame decoration part 65 and the frame base 60 constitute an integrated production unit in the present embodiment. On the other hand, since the side lamps 45 and the like are single production devices that are not included in the integrated production unit, they constitute a separate production device.

Note that not all of the effect devices included in the auxiliary gaming device unit 12 need be controlled by the decoration control device 610 inside the auxiliary gaming device unit 12. For example, in the embodiment of the present invention, the movable object arranged in the center case 51 is directly controlled by the effect control device 550 via the relay board 600.

As described above, the decoration control device 610 includes the I2CI / for controlling the decoration device 620.
O expander 615 is mounted, and each I2CI / O expander 615 includes individual I2C
An individual address for identifying the I / O expander 615 is assigned. In the embodiment of the present invention, as described above, the individual address of the I2CI / O expander 615 is
This is used as an individual address of the decoration control device 610.

The effect control device 550 can perform the effect operation by individually controlling the decoration device 620 by designating the individual address of the I2CI / O expander 615 and transmitting the control signal. In principle, each decoration control device 610 has a different individual address (
(Indicated by “ad =” in the figure).

Further, the decoration control device 610 is classified into three types according to a connection form: a branch type (branch substrate), a connection type (connection substrate), and a termination type (termination substrate). The decoration device 620 can be connected to any of the branch type, the connection type, and the terminal type decoration control device 610, and the decoration device 620 connected thereto can be connected.
Can be controlled.

The branch type decoration control device 610 has a plurality of decoration control devices 610 directly connected to the downstream side,
The received control signal is transmitted to the plurality of decoration control devices 610. The connected decoration control device 610 has one decoration control device 610 connected to the downstream side, and the connected decoration control device 6.
10 transmits the received control signal. The terminal-type decoration control device 610 does not connect the decoration control device 610 on the downstream side, and only controls the decoration device 620. Details of the branch type, connected type, and terminal type decoration control device 610 will be described later with reference to FIG.

The upstream side refers to the side that transmits the electrical signal in the configuration in which the electrical signal is transmitted from the effect control device 550 to the terminal decoration control device 610 through the decoration control device 610 on the way. On the other hand, the downstream side is the side that receives this electrical signal.

In short, the decoration control device 6 connected to the side closer to the production control device 550 when the signal cable from the production control device 550 to the terminal decoration control device 610 is traced in order.
10 is the upstream side, and the decoration control device 610 connected to the side closer to the decoration control device 610 at the end is the downstream side. For example, the decoration control devices 610A and 610C are arranged on the upstream side of the decoration control device 610H, and the decoration control devices 610I and 610J are arranged on the downstream side of the decoration control device 610H.

Here, in the embodiment of the present invention, as described above, the decoration control device 610 is arranged on the movable parts of the first effect member 70 and the second effect member 80 that constitute the movable effect device 58. In other words, in FIG. 6, the decoration control device 610 (first light emitting substrate 106) is disposed on the movable part (first effect base 100) of the first effect member 70, and in FIG. 7, the movable part of the second effect member 80. The decoration control device 610 (second light emitting substrate 116) is disposed on the (second effect base 110).

At this time, like the conventional shift register, when each decoration control device 610 is wired in a daisy chain, only one of the decoration control devices 610 at the end of the daisy chain is
You only need to connect the input cable. However, it is necessary to connect an input cable and an output cable to the other decoration control device 610 configured to be connected in the middle of the daisy chain. When a plurality of cables are connected to the movable part, the decoration control device 610 (the first light emitting board 106 and the second light emitting board 116) itself moves together with the movable part, and the cable also moves. It can be difficult. Furthermore, the movement of the cable may cause a disconnection of the connection line constituting the cable, which may affect the production.

In the embodiment of the present invention, the decoration control device 610 disposed on the first effect member 70 and the second effect member 80 is a terminal type, and the branch type decoration control device 610 is disposed upstream of these decoration control devices 610. doing. Therefore, the terminal-type decoration control device 610 (the first light emitting substrate 106,
The second light emitting board 116) has a structure in which a cable that transmits a signal to another decoration control device 610 provided outside the first effect member 70 and the second effect member 80 is not connected. If the decoration control device 610 is arranged in this way, only the input cable needs to be connected to the decoration control device 610 arranged in the movable part. Therefore, the wiring can be easily routed and the possibility of disconnection can be reduced as compared with the case of wiring by daisy chain.

When the destination address of the received control signal is not addressed to itself, the decoration control device 610 transmits the received control signal if the decoration control device 610 is further connected to the downstream side. If there is no transmission destination, the received control signal is discarded.

The decoration control device 610 can control the LEDs corresponding to the 16 ports. The decoration control device 610 includes an LED mounted on the decoration control device 610 and an external decoration device substrate 625 connected to the decoration control device 610. If the total number of mounted LEDs is 16 or less, both LEDs
Can be controlled. In other words, in the integrated decoration control device 610 (corresponding to a main active substrate on which both the I2CI / O expander 615 and the decoration device 620 are arranged), the decoration device substrate 625 (the I2CI / O expander 615 is not arranged) (Corresponding to a driven substrate on which the device 620 is arranged) is further connected to provide a decoration device 62 provided therein.
It is possible to control both 0 and the decoration device 620 connected to the outside.

In this way, the decoration device 620 arranged at a distance is replaced with one decoration control device 610.
And the number of decoration control devices 610 can be minimized.

The relay board 600 has a first master IC 570 mounted on the effect control device 550 on the upstream side.
The control signal transmitted from the first master IC 570a is received. Further, on the downstream side, it is connected to a decoration control device 610A included in the auxiliary gaming device unit 12 (more precisely, a decoration control device 610A included in the frame base 60 which is an integrated production unit). Further, the relay board 600 is connected to a decoration device board 625 (a board provided on the side lamp 45 (see FIG. 8)) which is a separation type effect device provided in the game board 10, and is provided in the relay board 600. The decoration device 620 mounted on the decoration device substrate 625 is controlled by the I2CI / O expander 615.

The auxiliary gaming device unit 12 includes decoration control devices 610A to 610J. The decoration control device 610A is a branch type decoration control device, and transmits the control signal received from the first master IC 570a to the decoration control device 610B and the decoration control device 610C. In addition, a decoration device substrate 625B is connected to the decoration control device 610B, and an effect device (decoration device 620) such as an LED disposed on the decoration device substrate 625B is controlled by the decoration control device 610B.

The decoration control device 610C is a branch type decoration control device 610, and transmits the received control signal to the decoration control device 610D and the decoration control device 610H on the downstream side. Decoration control device 610
D is connected to the branch type decoration control device 610E, and further controls the decoration device 620D included in the decoration device substrate 625D.

The decoration control device 610E is connected to a decoration control device 610F that controls the first effect member 70 and a decoration control device 610G that controls the second effect member 80. The first effect member 70 and the second effect member 80 perform an effect operation in conjunction with each other. The decoration control device 610F is disposed on the first light-emitting substrate 106 included in the first effect member 70 (FIG. 6), and the decoration control device 61.
0G is arrange | positioned at the 2nd light emission board | substrate 116 contained in the 2nd production member 80 (FIG. 7).

The first light emitting substrate 106 itself functions as the decoration control device 610F, and the second light emitting substrate 1
16 itself may function as the decoration control device 610G.

In the embodiment of the present invention, the decoration control device 610F is an LED included in the first effect member 70.
The decoration control device 610G controls the LEDs and the like included in the second effect member 80. In addition, the 1st effect member drive MOT71 and the 2nd effect member drive 2MOT8 for outputting the drive force for moving the 1st effect member 70 and the 2nd effect member 80 to the front of the display part 53a, respectively.
1 is controlled by the relay board 600.

The effect control device 550 controls the first effect unit 63 (the first effect member 70) and the second effect unit 64 (the second effect member 80) when the predetermined condition is satisfied, such as when the variable display game is executed. Perform the action. Specifically, the first accessory driving included in the first effect unit 63
In order to control the accessory driving second MOT 81 included in the MOT 71 and the second rendering unit 64, an individual address (“0000”) of the relay board 600 is designated and a control signal for operating these motors is transmitted. . Furthermore, a control signal for controlling a light emitting device such as an LED included in the first effect member 70 is transmitted by designating the individual address (“0110”) of the decoration control device 610F for controlling the first effect member 70. Similarly, L included in the second effect member 80
A decoration control device 6 for controlling the second effect member 80 with a control signal for controlling the light emitting device such as ED.
A 10G individual address (“0111”) is designated and transmitted. After that, issue a stop condition.

The decoration control device 610H is a connection type decoration control device 610, and is further connected to a connection type decoration control device 610I and a terminal type decoration control device 610J. The terminal-type decoration control device 610J controls the decoration device 620J included in the decoration device substrate 625J.

In the embodiment of the present invention, the decoration control device 610H and the decoration control device 610I control an effect device (LED) included in the reliability notification device 15. When the predetermined condition is satisfied, a control signal for indicating a predetermined mode is transmitted from the first master IC 570a of the production control device 550, and the production is performed in the designated mode.

  FIG. 14 is a diagram showing a configuration of the front frame 3 according to the embodiment of the present invention.

The gaming machine 1 according to the embodiment of the present invention has a plurality of specifications, and there are a normal version gaming machine 1 and an inexpensive version gaming machine 1. The normal version gaming machine 1 includes a front frame 3 (hereinafter, referred to as a normal version front frame 3) having a standard decorative member. The low-priced gaming machine 1 includes a front frame 3 (hereinafter referred to as a low-priced front frame 3 ′) that includes a decorative member that is configured at a lower cost than a standard decorative member. The upper side of FIG. 14 shows the configuration of the normal version front frame 3, and the lower side shows the configuration of the inexpensive version front frame 3 ′. In the gaming machine 1, only the front frame 3 of one of the specifications is shown. Is attached and connected to the production control device 550, so that only one of the normal plate front frame 3 and the inexpensive plate front frame 3 ′ is connected to the second master IC 570b.

The normal plate front frame 3 and the inexpensive plate front frame 3 'are a decoration device 62 included in the decoration members 9a and 9b.
The number of 0 is different, and the number of decoration control devices 610 that control the decoration device 620 is also different. Specifically, the decoration members 9a and 9b of the normal plate front frame 3 are controlled by seven decoration control devices 610, and the decoration members 9a 'and 9b' of the inexpensive plate front frame 3 'are controlled by five decoration control devices 610. Is done. The decorative members 9a and 9b have more LEDs than the decorative members 9a ′ and 9b ′.
Therefore, the normal version front frame 3 becomes brighter than the cheap version front frame 3 ', and it is possible to increase the variation of executable effects. For this reason, the control of the decoration device 620 when the normal plate front frame 3 is attached is different from the control of the decoration device 620 when the inexpensive plate front frame 3 ′ is attached.

For this reason, when the same address is assigned to the individual address of the decoration control device 610 attached to the normal plate front frame 3 and the individual address of the decoration control device 610 attached to the inexpensive plate front frame 3 ′, the effect control device 550 Since the production control data to be transmitted to the decoration control device 610 needs to be different between the case of the normal version front frame 3 and the case of the inexpensive version front frame 3 ′, it is usually determined according to the front frame 3 attached to the gaming machine 1. The production control device 550 for the plate and the production control device 550 for the low cost version must be prepared. Therefore, when the manufacturer ships the gaming machine 1, the effect control device 550 for the normal version and the effect control device 55 for the low-cost version.
0 must be prepared, which increases the manufacturing cost.

Therefore, in the embodiment of the present invention, different addresses are assigned to the individual addresses of the decoration control device 610 whose control is different between the normal plate front frame 3 and the low cost plate front frame 3 ′, and the effect control device 5.
50. The effect control data transmitted from 50 to the decoration control device 610 is configured to be common between the case of the normal version front frame 3 and the case of the inexpensive version front frame 3 ′. The control for the plate and the control for the low cost version can be executed. By doing so, it is not necessary to prepare the production control device 550 for the normal version and the production control device 550 for the low-priced version, and the manufacturing cost can be suppressed. In the embodiment of the present invention, the configuration of the game board 10 is the same regardless of whether it is a normal version or a low-priced version.

  Hereinafter, the configurations of the normal plate front frame 3 and the inexpensive plate front frame 3 'will be described in detail.

The normal plate front frame 3 includes a simple relay board 1600 connected to the second master IC 570b. The simple relay board 1600 includes a branch type decoration control device 610K and an illumination drive motor (
13a, 14a) are connected.

The decoration control device 610K is arranged in the lighting unit 11 and controls the decoration device 620 provided on the decoration device substrate 625K. Specifically, the LED included in the illumination unit 11 and the abnormality notification LED 29 are controlled.

Further, the decoration control device 610K is a branch type decoration control device, and the decoration control device 610L.
The received control signal is transmitted to the decoration control device 610P. Decoration control device 610L-61
0N controls the decorative member 9a on the left side of the normal plate front frame 3. Also, the decoration control device 61
0P to 610R controls the decorative member 9b on the right side portion of the normal plate front frame 3.

The decorative member 9a on the left side of the normal plate front frame 3 is connected to the decorative control devices 610L and 610.
M and a terminal type decoration control device 610N are included. The decoration control device 610L is the production control device 5
The control signal transmitted from the 50 second master ICs 570b is received from the decoration control device 610K and transmitted to the decoration control devices 610M and 610N.

As described above, the decorative member 9b on the right side portion of the normal plate front frame 3 is connected to the decorative decorative control device 6 as described above.
10P, 610Q and terminal type decoration control device 610R. The decoration control device 610P
The control signal transmitted from the second master IC 570b of the effect control device 550 is received from the decoration control device 610K and transmitted to the decoration control devices 610Q and 610R.

Also, different individual addresses are assigned to the decoration control devices 610L to 610R included in the decoration member 9a and the decoration member 9b, and different rendering operations are performed based on the control signals transmitted from the second master IC 570b. Can be executed. Specifically, the individual address of the decoration control device 610K included in the lighting unit 11 is “0000”.
”,“ 0001 ”,“ 0010 ”, and“ 0011 ”for the individual addresses of the decoration control devices 610L, 610M, and 610N included in the decoration member 9a, and the individual addresses of the decoration control devices 610P, 610Q, and 610R included in the decoration member 9b. Are "0100", "0101" and "
“0110” is assigned.

On the other hand, the low-priced front frame 3 ′ is similar to the normal plate front frame 3 in that the simple relay board 1600 connected to the second master IC 570 b and a board having substantially the same function (hereinafter referred to as the low-priced simple relay board 1600). 'And). However, in the low price front frame 3 ′, the simple relay board 160 is used.
Only the branch type decoration control device 610S is connected to 0 ′, and the illumination drive motor (13a,
Cost reduction is achieved without providing 14a).

The decoration control device 610 </ b> S is disposed in the lighting unit 11, and the decoration device substrate 625.
The decoration device 620 provided in S is controlled. Specifically, L included in the lighting unit 11
The ED, the abnormality notification LED 29 and the like are controlled, and are the same as those of the normal plate front frame 3. In addition, the decoration control device 610S is a decoration control device 610K that controls the illumination unit 11 of the normal plate front frame 3.
And the same individual address (“0000”) is assigned. Therefore, the decoration control device 610K for the normal plate front frame 3 and the decoration control device 610 for the inexpensive plate front frame 3 ′.
In S, the same control is executed.

The decoration control device 610S is a branch type decoration control device, and the decoration control device 610T.
The received control signal is transmitted to the decoration control device 610V. Decoration control devices 610T and 6
10 U controls the decorative member 9 a ′ on the left side of the normal plate front frame 3. Further, the decoration control devices 610V and 610W control the decoration member 9b ′ on the right side portion of the normal plate front frame 3.

Further, in the low-priced front frame 3 ′, a decoration control device 610T for controlling the left decoration member 9a ′.
And 610U and decoration control devices 610V and 610W for controlling the decoration member 9b 'on the right side
Is attached. The decoration control device 610T is a decoration control device 610 of the normal plate front frame 3.
The same substrate as L and the same individual address (“0001”) is assigned. Similarly, the decoration control device 610V is the same substrate as the decoration control device 610P of the normal plate front frame 3, and is assigned the same individual address (“0001”). Therefore, the same control is executed in the decoration control device 610L of the normal plate front frame 3 and the decoration control device 610T of the inexpensive plate front frame 3 ′, and the decoration control device 610P of the normal plate front frame 3 and the inexpensive plate front frame 3 are controlled. In the 'decoration control device 610V, the same control is executed.

The same individual address (“0111”) is assigned to the decoration control devices 610U and 610W. Therefore, in the low-priced front frame 3 ′, the decoration control device 61 is composed of left and right decoration members.
The same control is executed at 0 U and 610 W, that is, irradiation by the LED to be controlled is executed at the same timing. In addition, the decoration control devices 610U and 610W are assigned individual addresses that are not assigned to the decoration control device 610 of the normal front frame 3.

The decoration control device included in the decoration members 9a, 9b, 9a ′, and 9b ′ is used from the effect control device 550 regardless of whether the normal version front frame 3 or the inexpensive plate front frame 3 ′ is used. 6
Production control data is transmitted to all the individual addresses assigned to the ten I2CI / O expanders 615.

As described above, the low price front frame 3 'corresponds to the decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means) among the decoration control devices provided. Instead, decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached. The normal plate front frame 3 is equipped with decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means), whereas the inexpensive plate front frame 3 ′ has fewer. A number of decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached.

The decoration control device 610K and the decoration control device 610S, the decoration control device 610L and the decoration control device 610T, and the decoration control device 610V and the decoration control device 610P are common to the normal plate front frame 3 and the inexpensive plate front frame 3 ′. It is configured as a usable substrate.

Therefore, the production control device 550 according to the embodiment of the present invention can share the control for the normal version and the control for the low cost version, and there is no need to change the control for each front frame. The manufacturing cost of the device 550 can be reduced.

In the following description, unless otherwise specified, it is assumed that the normal version front frame is attached to the gaming machine 1 according to the embodiment of the present invention.

In the low price front frame 3 ′, the individual addresses are “0010”, “0011”, “010”.
The I2CI / O expander 615 with “1” and “0110” is not used, and the I2CI / O expander 615 with the individual address “0111” is not used in the normal version front frame 3. Therefore, in any front frame 3, there is an unconnected I2CI / O expander 615 in the abnormality determination table 3300 (see FIG. 33). However, as will be described later, at least one registered in the abnormality determination table 3300
If data transmission is normally performed between the two I2CI / O expanders 615 and the second master IC 570b, it is determined that the data is normally operating, so that the process is not interrupted due to this. .

FIG. 15 is a diagram illustrating a connection state between the effect control device 550 and the relay board 600 and the decoration control device 610 included in the game board 10 according to the embodiment of this invention.

In FIG. 15, the effect control device 550, the relay board 600, and the decoration control devices 610A and 610B.
And 610C will be described. For convenience of explanation, description of the decoration control device 610 is omitted for one relay board 600 and each decoration control device (610D to 610J) connected downstream from the decoration control device 610C. Each decoration control device 610
The connection between them is the same.

The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, and a connection line SCL.
, Connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34
, Connection line SL1, connection line SL2, connection lines SE1 to 3, connection line Vms, and connection line Vse.

The connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse are as described in FIG.

Signals for controlling the first to fourth phases of the accessory driving first MOT 71 included in the first effect unit 63 are transmitted to the connection lines M11 to M14. Signals for controlling the first to fourth phases of the accessory driving second MOT 81 included in the second effect unit 64 are transmitted to the connection lines M21 to M24. The accessory driving first MOT 71 and the accessory driving second MOT 81 use a four-phase driving stepping motor.

The connection lines M31 to M34 are connection lines for controlling the motor. However, in the embodiment of the present invention, since the motor corresponding to the relay board 600 is not connected, the empty terminal monitor 603 for displaying the connection state is connected. Is done. The vacant terminal monitor 603 includes four LEDs corresponding to the connection lines M31 to M34, and can check whether or not each connection line is disconnected. Therefore, when some or all of the connection lines are disconnected, a part of the vacant terminal monitor 603 is not lit, so that it can be determined that the quality of the cable is bad.

In particular, as in the gaming machine 1 of the embodiment of the present invention, the first master IC 570a and the relay board 6
00 is connected to a connection line GND for supplying power and a connection line Vcc.
, Connection line Vled, connection line Vms, and connection line Vse (see FIG. 11 or FIG. 15). These wires for supplying electric power are originally used as cables having a large (thick) cross-sectional area that can secure a sufficient amount of current in order to realize a stable operation.

However, when a flat cable such as the cable 91 is used, the cross-sectional area of each cable needs to be the same (common) because of the connection of the connectors.
Therefore, it is conceivable to supply power using a plurality of connection lines instead of a cable having a large cross-sectional area. For example, six cables are used as the connection lines GND and three cables are used as the connection lines Vms. A configuration such as use can be realized.

At this time, even if a part of the connection line for supplying power is disconnected, if all the connection lines are not disconnected, it will operate without any problem, so that the LED is turned on,
Although it is possible to drive the motor, since a sufficient amount of current cannot be secured, abnormal heat generation may occur on the cable. In such a case, by connecting a power supply line to the vacant terminal monitor 603, a cable with inferior quality such that some of the connection lines are disconnected even though it seems to be operating normally at first glance is discovered. It is possible to perform replacement or perform necessary maintenance before a failure occurs.

Further, the relay board 600 includes an accessory driving motor (an accessory driving first MOT 71, an accessory driving second M
In order to drive OT81), the electric power supplied from the connection line Vms is supplied to each motor.
The electric power supplied to the accessory driving solenoid for moving the decoration piece 46 up and down is also supplied from the connection line Vms.

The relay board 600 is connected to a motor position detection sensor 560a for detecting the rotational position of the accessory driving motor. The connection lines SE1 to SE3 are connection lines for receiving the detection result by the motor position detection sensor 560, and the relay board 600 is connected to the motor position detection sensor 5.
The rotation position of the accessory driving motor detected by 60a is transmitted to the effect control device 550 via the connection lines SE1 to SE3.

The connection line SL1 and the connection line SL2 are connection lines for controlling the accessory driving solenoid. When the accessory driving solenoid is not used, the connection line SL1 and the connection line SL2 are also connected to the vacant terminal monitor 603 for displaying the connection state, similarly to the connection lines M31 to M34 described above.

The decoration control device 610 including the relay board 600 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND (hereinafter, a bundle of these five types of connection lines is referred to as one harness). Are connected to each other.

In addition, a decoration control device 610B and a decoration control device 610C are connected to the decoration control device 610A via a harness, and a decoration control device 610D (not shown) is connected to the decoration control device 610C via a harness.

Each decoration control device 610 includes a connector serving as an attachment port for connecting the harness to itself. Since this connector is common to each decoration control device 610, the connection order of each connection line is common, and erroneous wiring can be prevented.

FIG. 16 is a diagram for explaining a connection state between the effect control device 550 according to the embodiment of the present invention, the simple relay board 1600 and the decoration control device 610 included in the normal plate front frame 3.

In FIG. 16, the effect control device 550, the simple relay board 1600, the decoration control devices 610K, 6
Connection of 10L and 610P will be described. Further, for convenience of explanation, the decoration control device 610 is used.
As for each decoration control device connected downstream of the decoration control device 610L and the decoration control device 610P, the description is omitted.

The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, and a connection line SCL.
, Connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34
In addition to the connection line SL1, the connection line SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse, a connection line that receives a button signal from the effect button 17 and a connection line that transmits a sound signal to the speaker 30 It is connected to the simple relay board 1600.

As described with reference to FIG. 15, the effect control device 550 includes the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse.
As in the case of connecting the game board 10 and the game control board 10, the decoration control devices 610 arranged on the downstream side
Send and receive various signals.

Signals for controlling the illumination driving first MOT 13a of the first movable illumination 13 included in the illumination unit 11 are transmitted to the connection lines M11 to M14. Signals for controlling the illumination drive second MOT 14a of the second movable illumination 14 included in the illumination unit 11 are transmitted to the connection lines M21 to M24.

The connection lines M31 to M34 are connection lines for controlling the motor. However, in the embodiment of the present invention, the corresponding motor is not connected to the simple relay board 1600. An empty terminal monitor 603 to be displayed is connected.

Further, in order to drive the illumination drive motor (the illumination drive first MOT 13a and the illumination drive second MOT 14a), the electric power supplied from the connection line Vms is supplied to each motor.

The simple relay board 1600 is connected to a motor position detection sensor 560b for detecting the rotation position of the illumination drive motor. The simple relay board 1600 transmits the rotation position of the illumination drive motor detected by the motor position detection sensor 560b to the effect control device 550 via the connection lines SE1 to SE3.

Here, a method in which the I2CI / O expander 615 (described later in FIG. 18) provided in the decoration control device 610 controls the decoration device 620 will be described.

The effect control device 550 determines the output mode of the effect device (decoration device 620) based on the game data input from the game control device 500. And the production | presentation control apparatus 550 is the individual address (I2) of the decoration control apparatus 610 used as a control object so that it may become the determined output aspect.
Production control data (production control information) including the individual address of the CI / O expander 615 is output to the relay board 600. At this time, the production control data is transmitted from the relay board 600 to the connection line S.
It is output to all the decoration control devices 610 to be controlled via DA.

In the embodiment of the present invention, the rendering device controlled by the decoration control device 610 is mainly a light emitting device such as an LED, and the light emission mode of the LED corresponds to the output mode of the rendering device. In this case, lighting / flashing / extinguishing of the LED is instructed by the production control data,
LED blinking cycle and lighting brightness are also instructed.

Each decoration control device 610 is previously set with a unique individual address as described above. When the presentation control data is input, the address included in the input presentation control data and the set individual address It is determined whether or not. If it is determined that the address included in the input effect control data matches the set individual address, the I2CI / O expander 615 of the decoration control device 610 takes in the effect control data, The output mode of the corresponding decoration device 620 is controlled, and a response signal is sent to the master IC (the first master IC 570a and the second master IC 5 immediately after the 8th bit data is input).
70b).

As described above, the master IC is connected to all the decoration control devices 61 connected to the master IC.
The effect control data is transmitted to 0, and the decoration device 610 corresponding to the individual address included in the effect control data can control the effect device so that the requested output mode is obtained.

Each decoration control device 610 has I2 of the decoration control device 610 in addition to the individual address.
A reset address for initializing the CI / O expander 615 is set.
This reset address is an address provided in common to all the I2CI / O expanders 615, and cannot be used as an individual address. The reset address value cannot be changed (details will be described later).

The effect control device 550 is a decoration control device 610 (more precisely, the I2C of the decoration control device 610).
When the I / O expander 615) is initialized, initialization instruction data including the common address for reset is output to the relay board 600 or the simple relay board 1600. At this time, the initialization instruction data effect control data is connected to the decoration control device 610 connected to the effect control device 550 via the relay board 600 or the simple relay board 1600.
Is output from.

Since a common address for reset is set in advance in each decoration control device 610, it is determined whether or not the address included in the input data matches the common address for reset. When it is determined that they match, the I2CI / O expander 615 of the decoration control device 610 outputs a response signal to the master IC, takes in the input data as initialization instruction data, and loads the I2CI / O expander 615 itself. initialize.

When the I2CI / O expander 615 is initialized, the initialized I2CI
The rendering device controlled by the / O expander 615 is turned off.

As described above, the decoration control device 610 performs control based on a command from the effect control device 550, and therefore, the relationship between the effect control device 550 and the decoration control device 610 is the first master IC 570a of the effect control device 550 and the second master IC 570a. The master IC 570b is a master, and each decoration control device 61
The 0 I2CI / O expander 615 becomes the slave.

15 and 16, the control target of the decoration control device 610 other than the relay board 600 is LE.
Although the decoration device 620 is a light emitting device such as D, it is also possible to control a movable object such as a motor or a solenoid. In this case, since the effect device serves as a drive source such as a motor or a solenoid, the operation mode of these drive sources corresponds to the output mode of the effect device. The effect control data includes an operation / stop instruction for the drive source, and it is also possible to specify the operation speed.

Note that, even if the gaming machine 1 is provided with a low-priced front frame 3 ′ instead of the normal-price front frame 3, the connection state of various substrates included in the low-priced front frame 3 ′ is almost the same as FIG. It becomes the composition of.

However, since the low cost version front frame 3 ′ is not provided with the illumination drive motor (illumination drive first MOT 13a, illumination drive second MOT 14a), the low price simple relay board 1600 ′ includes
There is no connector to which the illumination drive motor is connected, and the connection lines M11 to M14 and the connection line M
21 to M24 are also not used. Therefore, in the inexpensive simple relay board 1600 ′, the empty terminal monitor 603 is also connected to the connection lines M11 to M14 and the connection lines M21 to M24.

Further, since the low-price front frame 3 'is not provided with the motor position detection sensor 560b, in the low-price simple relay board 1600', the connection lines SE1 to 3 are connected to the ground so that a signal of a certain level is obtained. However, it is configured such that it is always input to the production control device 550.

  FIG. 17 is a block diagram of the decoration control device 610 according to the embodiment of this invention.

As described above, the decoration control device 610 according to the embodiment of the present invention is classified into three types, that is, a branch type, a connection type, and a termination type, based on the connection form. FIG. 17 shows a branch type decoration control device 6.
An example in which a terminal-type decoration control device 610Y is connected to 10X is shown. Further, a decoration device substrate 625 is connected to the decoration control device 610Y.

The branch type decoration control device includes an I2CI / O expander 615, a connector (upstream connector) for receiving a signal received by the I2CI / O expander 615, and a plurality of decoration control signals received from the upstream connector. A connector (downstream connector) for transmitting to the device 610 is provided. For example, like the decoration control device 610X in the figure, the I2C is inside.
It includes an I / O expander 615 and LEDs (decoration device 620), and further includes one upstream connector 611 and two downstream connectors 612A and 612B.

The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is connected to the downstream connector 612B for output to the next decoration control device 610Y as it is.
The other is further branched, one connected to the I2CI / O expander 615 and the other connected to another downstream connector 612A.

Further, a decoration device 620 to be controlled is connected to the output side of the I2CI / O expander 615 of the decoration control device 610X. The output side of the I2CI / O expander 615 includes ports 0 to 15 described with reference to FIG. Further, all the ports of the decoration control device 610 are connected to internal LEDs via current limiting resistors R0 to R15 described later in FIG. Note that the current control resistors R0 to R15 are also provided in the decoration control device 610.

As described above, the I2CI / O expander 615 determines that the address included in the effect control data input from the effect control device 550 matches the individual address set in the I2CI / O expander 615. Only, the decoration device 620 connected to the I2CI / O expander 615 is controlled based on the decoration data included in the effect control data.

Since there is only one downstream connector, the signal received from the upstream connector is
The decoration control device that can be transmitted to only one decoration control device 610 is a connected decoration control device. For example, the decoration control device 610X described above includes only the downstream connector 612B and does not include the downstream connector 612A.

The terminal-type decoration control device includes an I2CI / O expander 615 and an I2CI / O.
Although the expander 615 has a connector (upstream connector) for receiving a signal received, the signal received from the upstream connector is not transmitted to the other decoration control device 610. For example, the decoration control device 610Y in the figure includes an I2CI / O expander 615 and an L
A connection line that includes an ED (decoration device 620) and that supplies current to the LEDs of the decoration device board 625 that is connected to the outside of the decoration control device 610Y; a connection line that supplies a power supply voltage to the LEDs of the decoration device board 625; And the decoration control apparatus 610 and the decoration apparatus board | substrate 625 are connected through the connection line which earth | grounds to a ground.

The decoration device substrate 625 does not include the I2CI / O expander 615 but is a substrate including only a light emitting device such as an LED. In this case, the current limiting resistor connected to the LED provided on the decoration device board 625 is provided on the decoration device board 625, but may be provided on the decoration control device 610 provided with the I2CI / O expander 615. .

It should be noted that the number of connection lines for passing current to these LEDs to be passed from the decoration control device 610 to the decoration device substrate 625 is determined in accordance with the number of LEDs provided on the decoration device substrate 625. . For example, when the decoration device substrate 625 includes two LEDs, the I2CI
Two control lines for connecting the port of the / O expander 615 and the corresponding LED;
At least one power supply line that supplies power supplied from Vled is required.

The I2CI / O expander 615 provided in the decoration control device 610Y also includes an address included in the effect control data input from the effect control device 550, and the I2CI / O.
Only when the address set in the expander 615 matches, the decoration device 620 connected to the I2CI / O expander 615 is controlled based on the decoration data included in the effect control data. In this case, the decoration device 6 provided in the central decoration control device 610.
20 and the decoration device 620 provided on the decoration device substrate 625 are controlled by the I2CI / O expander 615.

In this way, the decoration device substrate 625 is provided, and a part of the decoration device (
LED) is separated, even if it is an LED arranged at a distant place, a common I2C
It can be controlled by the I / O expander 615.

As described above, the decoration control device 610 can control a movable object such as a solenoid or a motor instead of a light emitting device such as an LED, and will be described in detail later with reference to FIG.

FIG. 18 is a block diagram illustrating a configuration of the I2CI / O expander 615 according to the embodiment of this invention.

The I2CI / O expander 615 includes a transistor 630 connected to the connection line SDA,
A filter 631 connected to the connection line SDA, a driver 632 connected to the connection line SDA,
Filter 633 connected to connection line SCL, bus controller 634, output setting register 635, output controller 636, driver 637 connected to ports 0-15 on the output side of I2CI / O expander 615, ports 0-15 Transistor 63 connected to
8A to 638P and a reset signal generation circuit 639. Further, in the embodiment of the present invention, a bus monitoring WDT (watchdog timer) 640 for determining whether or not the connection line SDA is occupied by another I2CI / O expander 615, and I2CI /
A self-occupied WDT 641 for determining whether or not the O expander 615 itself occupies the connection line SDA is provided.

The filter 631 is connected to the connection line SDA, removes noise of data input from the connection line SDA, and outputs the data from which noise has been removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

The transistor 630 uses a field effect transistor (FET) to suppress power consumption. The gate of the transistor 630 is connected to the driver 632, and the drain is connected to a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

If the voltage applied to the gate of the transistor 630 is smaller than a predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, transistor 6
If the voltage applied to the gate of 30 is not less than a predetermined value for operating the transistor 630,
When a current flows from the drain to which a predetermined voltage is applied to the grounded source, the voltage of the connection line SDA decreases. Note that the transistor 630 has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source.

When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage of a value that allows the transistor 630 to operate to the gate of the transistor 630 so that a current flows between the drain and the source. To do. The driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which noise has been removed to the bus controller 634.

In addition, a unique address is set in the I2CI / O expander 615 by address setting terminals A0 to A3 provided in the I2CI / O expander 615, and is input to the bus controller 634. Further, an address for resetting the I2CI / O expander 615 is also set in advance.

In the bus controller 634, the address of data input from the connection line SDA is I2CI.
It is determined whether or not the address matches the unique address set in the / O expander 615. If the address matches, the data is fetched as effect control data.

In addition, the bus controller 634 receives the address of data input from the connection line SDA as I
It is determined whether or not it matches the reset address set in the 2CI / O expander 615. If they match, the data is fetched as initialization instruction data, and the I2CI
The / O expander 615 is initialized.

In addition, the bus controller 634 changes the signal level of the connection line SCL from LOW to HIGH, and when the signal level of the connection line SCL changes from HIGH to LOW after fetching the eighth bit data. The response signal is sent from the connection line SDA to the first master IC 57.
Output to 0a. Furthermore, when it is confirmed that the signal level of the connection line SCL changes from LOW to HIGH, and the signal level of the connection line SCL changes from HIGH to LOW again, the connection line SDA is released. In other words, the response signal is output at the timing when the signal level of the connection line SCL changes from LOW to HIGH.

In the output setting register 635, the operation mode of the I2CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 fetches the initialization instruction data from the connection line SDA and the I2CI / O expander 615 is initialized, the output setting register 635 prevents the current from flowing to all the ports 0 to 15. To the initial state.

The output controller 636 is based on the data set in the output setting register 635.
The output state of the effect device is actually controlled by flowing current through the port driver 637 to the effect devices connected to the ports 0 to 15. This output state is updated to the contents specified in the effect control data when the bus controller 634 fetches the effect control data from the connection line SDA.

That is, based on the effect control data received from the first master IC 570a, it is set in the output setting register 635, and when the stop condition is received, each port 0-15 is received.
Is updated and reflected in the production device. Therefore, like a shift register, L
The effect control can be performed without the need to receive the AT signal, that is, without the need for wiring for receiving the LAT signal. In particular, the port output state can be set to a plurality of I2CI /
This is useful when there is a need to update the O expander 615 at the same time, and different I2CI /
Even the production device controlled by the O expander 615 can be controlled to execute the production operation at the same time, so that the production effect can be further enhanced.

When a current flows through a port, the driver 637 applies a voltage at which the transistors 638A to 638P connected to the port through which the current flows can operate.

The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to a port terminal connected to a connection line to which a voltage for operating the effect device is applied as shown in FIGS. 19 and 20, and the source is grounded Has been.

The voltage applied to the gates of the transistors 638A to 638P is the transistor 638A to
If it is smaller than a predetermined value for operating 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than a predetermined value for operating the transistor 638, the predetermined voltage applied to the gate from the power supply Vled shown in FIG. 19 or the power supply Vmot or the power supply Vsol shown in FIG. Current flows to the source grounded through the drain of the transistor 638, so that the output state of the effect device connected to the port terminal can be controlled.

In addition, the I2CI / O expander 615 of the decoration control device 610 includes all effect devices (decoration devices 620 such as LEDs) connected to the port terminals of the I2CI / O expander 615.
) Can be controlled simultaneously, so that one rendering device connected to the port terminal of the I2CI / O expander 615 can be controlled as one group.

Since the I2CI / O expanders 615 included in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I2CI / O expander 615 included in each decoration control device 610 is configured as a group unit control unit that can control the effect device in units of groups.

Therefore, the effect control device 550 that controls each decoration control device 610 functions as a group control unit that controls the group unit control unit.

The reset signal generation circuit 639 has a Vcc terminal connected to a connection line Vcc that supplies power to the I2CI / O expander 615, and a RES that receives an external reset signal.
The ET terminal is connected.

The reset signal generation circuit 639 is powered on to the I2CI / O expander 615,
When the voltage rises to a predetermined value, a reset signal is generated, and initialization is performed by inputting the generated reset signal to the bus controller 634, the output setting register 635, and the output controller 636.

When a reset signal of LOW level is input from the outside, the reset signal generation circuit 639 outputs a reset signal, so that the CPU 551 of the effect control device 550 outputs N
A reset signal may be input from the RESET terminal via the OR gate circuit 561. When the RESET terminal is not used, as shown in FIG. 19 and FIG.
The ET terminal may be pulled up to HIGH.

The bus monitoring WDT 640 is used to detect that another I2CI / O expander 615 occupies the connection line SDA. The bus monitoring WDT 640 is connected between the filter 631 and the bus controller 634, takes in the signal level of the connection line SDA, and measures the time during which the signal is continuously at the LOW level. Further, the bus monitoring WDT 640 is connected to the reset signal generation circuit 639. When a predetermined time has elapsed after the connection line SDA is occupied, the bus monitoring WDT 640 activates its own reset signal generation circuit 639 to perform the I2CI / O export. The panda 615 is initialized.

Since the connection line SDA is also connected to other I2CI / O expanders 615, the connection line SDA is connected to all the I2CI / O expanders 615 to which the connection line SDA is connected.
The occupation state of DA is detected. These I2CI / O expanders 6
15, the reset signal generation circuit 639 provided in the circuit 15 is activated to connect the connection line SD.
All I2CI / O expanders 615 to which A is connected are initialized.

The self-occupied WDT 641 is a connection line SD by itself (I2CI / O expander 615).
Used to detect A occupancy. The bus controller 634 operates the self-occupied WDT 641 while operating the driver 632 to drive the connection line SDA to the low level, and stops the self-occupied WDT 641 while not driving the connection line SDA to the low level. . When the self-occupied WDT 641 operates continuously for a predetermined time, the self-occupied WDT 6
41 initializes the I2CI / O expander 615 by causing the reset signal generation circuit 639 to generate a reset signal.

As a result, a period during which the bus controller 634 itself drives the connection line SDA to a low level (a period during which the I2CI / O expander 615 occupies the connection line SDA)
It becomes possible to monitor. The self-occupied WDT 641 starts measuring time at the timing when the connection line SDA is occupied to transmit a response signal (ACK, NACK) for the data received from the master IC, and when a predetermined time elapses, the reset signal generating circuit A reset signal is generated at 639. With this configuration, when the occupation of the connection line SDA is detected by the self-occupied WDT 641, only its own I2CI / O expander 615 is reset.

FIG. 19 illustrates I2 of the decoration control device 610 that controls the decoration device 620 according to the embodiment of this invention.
FIG. 6 is a circuit diagram around a CI / O expander 615.

The I2CI / O expander 615 has an NC terminal, a RESET terminal, and an SC as input terminals.
L terminal, SDA terminal, Vcc terminal, A0 to A3 terminal, and GND terminal are provided, and PORT0 to PORT15 are provided as output terminals.

A power source supplied to the I2CI / O expander 615 is connected to the RESET terminal via a pull-up resistor R. For this reason, the voltage applied to the reset terminal is always HIG
H is maintained.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

A power supply supplied to the I2CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

The A0 to A3 terminals are terminals for setting individual addresses in the I2CI / O expander 615. The individual address of the I2CI / O expander 615 is normally expressed by 4 bits. When the power of the I2CI / O expander 615 is applied to this terminal, “1” is set in the bus controller 634. When this terminal is connected to the ground, “0” is set in the bus controller 634.

Therefore, the individual address of the I2CI / O expander 615 shown in FIG.
0 ". The GND terminal is a terminal for grounding a voltage.

The PORT0 terminal to the PORT15 terminal are connected to the LED0 to LED0 through the current limiting resistors R0 to R15.
It is connected to a decoration device 620 composed of LEDs 15. As in PORT0, port 1
One LED may be connected to each, but a plurality of LEDs may be connected to one port like PORT1-15.

One I2CI / O expander 6 if each port has one LED
15 can control up to 16 LEDs. In addition, when the number of LEDs connected to each port is different, all LEDs connected in series to one port are set to 1
Speaking of types of LEDs, a maximum of 16 types of LEDs can be controlled by one I2CI / O expander 615.

When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 18) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. The current flows through the LED0 to LED15 connected to the PORT0 terminal to the PORT15 terminal,
Each LED0-LED15 lights up.

On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows through each LED0 to LED15, and each LED0 to LED15 is not lit.

Note that the PORT0 to PORT15 terminals of the I2CI / O expander 615 have L
Instead of the ED, it is possible to connect a motor or a solenoid and configure the effect device using the motor or the solenoid for games. Hereinafter, I2CI / O with reference to FIG.
A case where a motor and a solenoid are controlled using the expander 615 will be described.

FIG. 20 shows the I2CI / O expander 61 of the decoration control device 610 according to the embodiment of this invention.
FIG. 5 is a circuit diagram around 5 and shows a case where a motor and a solenoid are controlled.

The motor used here is constituted by a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of each phase that drive the stepping motor. In the embodiment of the present invention, the signal terminals of the respective phases of the motor are connected to the PORT0 terminal to the PORT3 terminal.

Transistor 6 connected to PORT0 to PORT3 terminals connected to motor
When a voltage is applied from the driver 637 to any one of the gates of 38A to 638D,
The current can flow from the drain to the source of the transistors 638A to 638D to which the voltage is applied, the current flows to the motor connected to the PORT0 terminal to the PORT3 terminal,
The accessory driving motor is driven.

The connection lines connecting the PORT0 to PORT3 terminals and the motor are branched, and one of the branched connection lines is connected to the power supplied to the motor by the diode D and the Zener diode ZD.
Connected through.

The PORT terminal 15 is connected to a solenoid to be used. When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT15 terminal connected to the solenoid, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied, A current flows through a solenoid connected to the PORT 15 terminal, and an effect device (not shown) driven by the solenoid is driven.

In FIG. 20, both the motor and the solenoid are connected to the I2CI / O expander 615, but at least one of the motor and the solenoid may be connected to one I2CI / O expander 615. .

For example, an I2CI / O expander 615 as a group that controls only the stepping motor may be provided exclusively, or an I2CI / O expander 615 as a group that controls only the solenoid may be provided exclusively. With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and therefore it becomes possible to group and control only the rendering devices that require high-speed processing.

FIG. 21 is a diagram for explaining circuit configurations of the decoration control device 610, the relay board 600, and the simple relay board 1600 according to the embodiment of the present invention. In particular, connection states related to input / output of signal lines and power supply lines are shown. It is a figure for demonstrating.

In this figure, among the decoration control device 610, the relay board 600, and the simple relay board 1600, the branch type decoration control device 610 (for example, the decoration control device 610A) will be described. Differences between the decoration control device 610, the terminal-type decoration control device 610, the relay board 600, and the simple relay board 1600 will be described.

In this figure, the components provided in the branch type decoration control device 610X described above,
The description will be given with the same numbering.

The branch type decoration control device 610 includes an upstream connector 611 and a downstream connector 612 (612A).
612B), and an I2CI / O expander 615.

The upstream connector 611 is a connector connected to the decoration control device 610 upstream from the decoration control device 610. The downstream connectors 612A and 612B are connected to the decoration control device 61.
It is connected to the decoration control device 610 on the downstream side of 0.

In order to connect the connection line SDA to the two downstream connectors 612A and 612B, the internal connection line SDA2111 extending from the upstream connector 611 is a branch 2101 at the first connection line SDA212.
1 and the second connection line SDA2131. The first connection line SDA2121 is connected to the downstream connector 612A, and the second connection line SDA2131 is connected to the downstream connector 612B.

Similarly, the internal connection line SCL2112 extending from the upstream connector 611 branches at a branch 2102 into a first connection line SCL2122 and a second connection line SCL2132. First connection line SCL2
122 is connected to the downstream connector 612A, and the second connection line SCL2132 is connected to the downstream connector 6
12B.

Further, in order to connect the connection line SDA to the I2CI / O expander 615, the second connection line SDA2131 branches at the branch 2103, and the branched second connection line SDA2131 is the I2C.
The SDA terminal shown in FIGS. 19 and 20 of the I / O expander 615 is connected. Further, in order to connect the connection line SCL to the I2CI / O expander 615, the second connection line SCL21 is used.
32 branches at the branch 2104, and the branched second connection line SCL2132 is connected to the SCL terminal shown in FIGS. 19 and 20 of the I2CI / O expander 615. Hereinafter, the I2CI / O expander 615, the connection line SDA connected from the branch 2103 to the I2CI / O expander 615, and the connection line S connected from the branch 2104 to the I2CI / O expander 615
A configuration including CL is referred to as an I2CI / O expander unit 2181.

The I2CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage for the I2CI / O expander 615. Also, although not shown in FIG. 21, I2C
From the I / O expander 615, an LED (decoration device 6) provided in the decoration control device 610 is provided.
20), the signal lines (see FIG. 19) of the respective ports 0 to 15 for driving are output.

Further, the signal output from the I2CI / O expander 615 of the decoration control device 610 to the upstream decoration control device 610 via the connection line SDA, and the upstream decoration control device 610,
A Zener diode ZD2141 is connected to the internal connection line SDA2111 in order to remove noise of a signal input to the I2CI / O expander 615 of the decoration control device 610 via the connection line SDA.

Specifically, the internal connection line SDA2111 branches at the branch 2105, the branched internal connection line SDA2111 is connected to the cathode side of the Zener diode ZD2141, and the anode side of the Zener diode ZD2141 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA2111 is released by the Zener diode ZD2141.

Further, in order to remove noise of a signal input from the upstream decoration control device 610 to the I2CI / O expander 615 of the decoration control device 610 via the connection line SCL, the internal connection line SCL2112 has a Zener diode ZD2142. Is connected.

Specifically, the internal connection line SCL2112 branches at a branch 2106, the branched internal connection line SCL2112 is connected to the cathode side of the Zener diode ZD2142, and the anode side of the Zener diode ZD2142 is grounded.

For this reason, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL2112 is released by the Zener diode ZD2142.

Further, the I2CI / O expander 615 of the decoration control device 610 is connected to the downstream connector 6.
The signal output to the decoration control device 610 connected to 12A via the connection line SDA, and the I2CI / I of the decoration control device 610 from the decoration control device 610 connected to the downstream connector 612A
A Zener diode ZD2143 is connected to the first connection line SDA2121 in order to remove noise of a signal input to the O expander 615 via the connection line SDA.

Specifically, the first connection line SDA2121 branches at a branch 2107, the branched first connection line SDA2121 is connected to the cathode side of the Zener diode ZD2143, and the anode side of the Zener diode ZD2143 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SDA2121 is released by the Zener diode ZD2143.

Similarly to the Zener diode ZD2143 connected to the first connection line SDA2121, the Zener diode ZD2145 is also connected to the second connection line SDA2131.

Further, the downstream connector 612 from the I2CI / O expander 615 of the decoration control device 610 is used.
A Zener diode ZD2144 is connected to the first connection line SCL2122 in order to remove noise of the signal input to the decoration control device 610 connected to A via the connection line SCL.

Specifically, the first connection line SCL2122 branches at a branch 2108, the branched first connection line SCL2122 is connected to the cathode side of the Zener diode ZD2144, and the anode side of the Zener diode ZD2144 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SCL2122 is released by the Zener diode ZD2144.

Similarly to the Zener diode ZD2144 connected to the first connection line SCL2122, the Zener diode ZD2146 is also connected to the second connection line SCL2132.

Further, the internal connection line V extending from the Vcc terminal of the upstream connector 601 connected to the connection line Vcc for supplying the power supply voltage to the I2CI / O expander 615 of the decoration control device 610.
The internal connection line GND2172, which extends from the GND terminal of the upstream connector 601 and is grounded, is connected via the smoothing capacitor C2161 and the bypass capacitor CP2162.

The smoothing capacitor C2161 is a capacitor for smoothing the voltage waveform of the power supply, and the bypass capacitor CP2162 is a capacitor for removing noise of the power supply voltage.

Therefore, the power supply voltage supplied to the I2CI / O expander 615 of the decoration control device 610 is smoothed by the smoothing capacitor C2161, and the bypass capacitor CP21.
The noise is removed by 62 and supplied to the I2CI / O expander 615.

Similarly, the internal connection line Vcc2 extending from the Vcc terminal of the downstream connectors 612A and 612B
173 and the internal connection line GND2174 extending from the GND terminal are the smoothing capacitor C21.
61 and a bypass capacitor CP2162. As a result, the connection line Vcc connected to the downstream decoration control device 610 is smoothed and the noise-removed voltage is connected.
To be applied.

The branch type decoration control device 610 has been described above. Next, the connection type decoration control device 610 will be described.

In addition to the downstream connector 612A, a Zener diode ZD connected to the connection line SDA
2143, Zener diode ZD2144 connected to connection line SCL, internal connection line V
A configuration including cc 2173, internal connection line GND 2174, smoothing capacitor C 2161 and bypass capacitor CP 2162 is referred to as a first downstream connector portion 2182.

In addition to the downstream connector 612B, a Zener diode ZD connected to the connection line SDA
2145, Zener diode ZD2146 connected to connection line SCL, internal connection line V
A configuration including cc 2173, internal connection line GND 2174, smoothing capacitor C 2161, and bypass capacitor CP 2162 is referred to as a second downstream connector portion 2183.

In the case where the decoration control device 610 is a connection type, since only one downstream connector is provided in the board, the downstream connector 612A exists but the downstream connector 612B does not exist.

Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are branched from the branch 2103.
2104, the second connection line SDA2131 and the second connection line SCL are not branched.
The point that 2132 does not exist is different from the branch type decoration control device 610.

The connection type decoration control device 610 is different from the branch type decoration control device 610 in that there is no electronic component constituting the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the terminal type decoration control device 610 will be described.

In the case where the decoration control device 610 is a terminal type, the downstream connector is not provided in the board, and therefore neither of the downstream connectors 612A and 612B exists.

Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are branched from the branch 2101.
2102, 2103, 2104 without branching, I2CI / O expander 615
The configuration is different from that of the branch-type decoration control device 610 in that it is connected to.

Further, the terminal-type decoration control device 610 also has a branch-type decoration control device 610 in that there are no electronic components constituting the first downstream connector portion 2182 and the second downstream connector portion 2183.
It becomes a different configuration. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the relay board 600 will be described.

Since the relay board 600 is configured to include only one downstream connector in the board, similarly to the connection type decoration control device 610, the downstream connector 612A exists but the downstream connector 612 exists.
B does not exist.

Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are branched from the branch 2103.
2104, the second connection line SDA2131 and the second connection line SCL are not branched.
Since 2132 does not exist, the configuration is the same as that of the connection type decoration control device 610.

However, the relay board 600 is different from the connection type decoration control device 610 in that it includes a pull-up resistor for pulling up the voltages of the connection line SDA and the connection line SCL.

Specifically, as shown in FIG. 21, in the relay board 600, the upstream connection line SDA connected to the first master IC 570 a and the downstream connection line S connected to the decoration control device 610.
A pull-up resistor R2151 for pulling up the voltage of DA is connected to the first connection line SDA21.
21. Similarly, the upstream connection line SCL connected to the first master IC 570a
The pull-up resistor R2152 for pulling up the voltage of the downstream connection line SCL connected to the decoration control device 610 is connected to the first connection line SCL2122.

More specifically, the first connection line SDA2121 branches at the branch 2109, and the branched first connection line SDA2121 is connected to the pull-up resistor R2151. Similarly, the first connection line SCL2122 branches at the branch 2110, and the branched first connection line SCL2122 is connected to the pull-up resistor R2152. Hereinafter, the pull-up resistor R2151 for pulling up the voltage of the connection line SDA and the pull-up resistor R2152 for pulling up the voltage of the connection line SCL are collectively referred to as a pull-up resistor unit 2180.

  Next, the simple relay board 1600 will be described.

The simple relay board 1600 includes a plurality of downstream connectors (downstream connectors 612A and 612B) in the board, similarly to the branch type decoration control device 610. However, simple relay board 1600
Is not provided with a circuit corresponding to the I2CI / O expander portion 2181, but instead is provided with a circuit corresponding to the pull-up resistor portion 2180 provided in the relay substrate 600. This is a configuration different from the decoration control device 610. Other configurations are the same as those of the branch type decoration control device 610.

In the present embodiment, the configuration of the pull-up resistor 2180 described above is provided only on the relay board 600 and the simple relay board 1600, and the decoration control device 610 and the effect control device 550 are provided.
However, as long as the levels of the connection line SDA and the connection line SCL can be correctly generated, the decoration control device 610 and the effect control device 550 may be provided. In short, the pull-up resistors R2151 and 2152 are connected to the connection line SDA and the connection line SC.
It suffices if the voltage Vcc can be supplied to the drain terminal of the transistor that drives L.

For example, if the pull-up resistors R2151 and 2152 are provided in the first master IC 570a, it is not necessary to provide the pull-up resistor unit 2180 in the relay board 600, the simple relay board 1600, or the decoration control device 610.

FIG. 22 is an explanatory diagram of the slave address 2200 included in the data output from the effect control device 550 to the decoration control device 610 according to the embodiment of this invention.

The slave address 2200 includes a fixed address part 2201 composed of upper 3 bits and a variable address part 2202 composed of lower 5 bits.

The fixed address unit 2201 is preset with a value of “110” and cannot be changed by the I2CI / O expander 615.

The variable address unit 2202 can be set by the I2CI / O expander 615. The variable address unit 2202 includes A0 to A0 of the I2CI / O expander 615 to be controlled.
A 4-bit I2CI / O expander address 2203 corresponding to the pattern set in the terminal of A3 and 1-bit R / W identification data 2204 indicating whether the data is a read request or a write request Composed.

Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 2204.

FIG. 23 shows the I2CI / O expander address table 2300 according to the embodiment of this invention.
It is explanatory drawing of.

The I2CI / O expander address table 2300 is a table managed by the first master IC 570a. The I2CI / O expander address table 2300 shows the correspondence between the slave address 2301 and the I2CI / O expander address 2302.

The slave address 2301 stores the slave address of the decoration control device 610 specified by the effect control device 550 as a transmission / reception target. As described above with reference to FIG. 20, the slave address includes a fixed address portion consisting of the upper 3 bits and a 4-bit I2CI /
It is configured by combining an O expander address and 1-bit R / W identification data.

In the I2CI / O expander address 2302, as described above with reference to FIGS.
A 4-bit I2CI / O expander address corresponding to each slave address is registered.

However, among the I2CI / O expander addresses, the address “1000” and the address “1011” (shaded entries in FIG. 23) are the I2CI / O expander 61.
5 cannot be used as a unique address for identifying each other.

The address “1000” is used as a default value at power-on of an address (all call address) specified when a common command is output to all the decoration control devices 610. The address “1011” is stored in the first master IC 570a by software.
This is a common address used when unconditionally resetting all the decoration control devices 610 connected to the.

As described above, since there are 14 addresses that can be set in the I2CI / O expander 615 of the decoration control device 610, the effect control device 550 can control the 14 I2CI / O expanders 615. Each decoration control device 610 includes PORT0 to POR.
Since T15 is provided, it is possible to control 16 (in other words, 16 types) LEDs. Therefore, the effect control device 550 can control 224 (in other words, 224 types) LEDs.

FIG. 24 is a diagram for describing work registers assigned to the output setting register 635 provided in the I2CI / O expander 615 according to the embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I2CI / O expander 615.

The work register is information for making a pre-defined setting for the I2CI / O expander 615, and the output of a rendering device (decoration device 620, for example, LED) connected to the I2CI / O expander 615. Information for specifying an aspect is stored.

In addition, the control register stores information defining a procedure for writing data to the work register. The work register is configured to store a plurality of pieces of information in different storage areas, and a different register number is assigned to each storage area.

The register number “00h” and the register number “01h” are the I2CI / O expander 6
This corresponds to a mode register for performing 15 initial settings. The register name “MODE1” is assigned to the storage area of the register number “00h”. The register name “MODE2” is assigned to the storage area of the register number “01h”. When a value is written in the storage areas of the register numbers “00h” and “01h”, the I2CI / O is based on the written value.
The expander 615 is initialized.

Note that bit 3 (OCH) of the “MODE2” register is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I2CI / O expander 615 is actually reflected in the effect device. In the embodiment of the present invention, as described in FIG. 18, “0” is set, and when the stop condition is received, the effect control data stored in the output setting register 635 is output, and the effect device Is set to actually control the output state.

Parameters to be controlled such as LEDs included in the decoration device 620 are set in the register numbers “02h” to “11h” (register names “PWM0” to “PWM15”). When a value is written to any of the storage areas of register numbers “02h” to “11h”, I2CI /
16 LEs constituting the light emitting device (decoration device 620) connected to the O expander 615
Among D, the luminance of the LED corresponding to the register number in which the value is written is adjusted based on the written value. For example, when a value is written in the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 19 is adjusted.

Note that the I2CI / O expander 615 can also control movable objects such as a motor and a solenoid as described above. When a solenoid is connected to the I2CI / O expander 615, whether the register number corresponding to the port to which the solenoid is connected is operated by energizing the solenoid or not operated without being energized. A value indicating is written. When a motor is connected to the I2CI / O expander 615, a value indicating the target rotational position of the motor is written in the register number corresponding to the port to which the motor is connected.

Register number “12h” (register name “GRPPWM”) and register number “13h”
(Register name “GRPFREQ”) is set with a parameter that specifies an operation pattern of the entire control target. When a value is written in the storage areas of the register numbers “12h” and “13h”, the blinking pattern of the entire LED (16 LEDs) is set based on the written value. Specifically, a duty cycle that is an on / off ratio of the entire LED is set in the register number “12h”, and a blinking cycle of the entire LED is set in the register number “13h”.

In register numbers “14h” (register name “LEDOUT0”) to “17h” (register name “LEDOUT3”), the output state of the LED controlled by each port is set. Each register can set four LED output states.

When a value is written in the storage area of the register number “14h”, the output states of the LEDs 0 to LED3 are set based on the written value. Similarly, the output state of LED4 to LED7 is stored in the storage area of the register number “15h”, and the storage area of the register number “16h” is the LED.
8 to LED11 output state, the storage area of register number "17h" LED12 to LED
15 output states are set.

Register numbers “18h” to “1Ah” (register names “SUBADR1” to “SUBAD”
R3 ") is set with a sub-address. When values are written in the storage areas of the register numbers “18h” to “1Ah”, the first subaddress to the third subaddress are set based on the written values.

In the register number “1Bh” (register name “ALLCALLADR”), an all call address for outputting a command to all the decoration control devices 610 is set. The all call address is used, for example, when the initialization processing is executed in all the decoration control devices 610 when the power is turned on.

FIG. 25 is an explanatory diagram of a start condition and a stop condition in which the master IC according to the embodiment of this invention outputs data via the connection line SDA and the connection line SCL.

The connection line SCL has a signal level of HIGH when data is not transmitted. Master I
C outputs the signal level of the connection line SCL LOW when outputting data to the decoration control device 610.
The decoration control device 610 acts as a strobe signal for taking in the data of the connection line SDA.

The connection line SDA has a signal level HIGH when data is not transmitted.
Data is output from the connection line SDA in accordance with the CL clock signal.

The master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal serving as a start condition indicating that data output starts. .

The I2CI / O expander 615 of the decoration control device 610 includes a connection line SDA and a connection line S.
When a signal serving as a start condition is input from CL, it is recognized that data output is started.

The master IC changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal that becomes a stop condition indicating that the output of data ends. .

The I2CI / O expander 615 of the decoration control device 610 recognizes that the output of data is finished when a signal serving as a stop condition is input. In the embodiment of the present invention, as described above, when the decoration control device 610 receives a signal that is a stop condition, control of the effect device (decoration device 620) controlled by the decoration control device 610 is started.

FIG. 26 is a timing chart at which the decoration control device 610 to which the data output from the master IC according to the embodiment of the present invention is input outputs a response signal.

The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

Then, the decoration control device 610 outputs a response signal to the master IC via the connection line SDA immediately before the start condition is satisfied and immediately before the number of changes in the signal level of the connection line SCL reaches nine. In other words, the decoration control device 610 outputs a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking the 8th bit data from the connection line SDA. To do.

As shown in FIG. 26, a response signal (ACK response signal) indicating that the data has been successfully received is indicated by a LOW level, and a response signal indicating that the data reception has failed (
The NACK response signal (corresponding to no ACK output in the figure) is indicated by a HIGH level.

Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC waits for a response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

FIG. 27 is a timing chart of signal levels of connection line SDA and connection line SCL when the master IC according to the embodiment of the present invention outputs effect control data.

First, when starting output of data, the master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, thereby indicating a start condition signal. And the decoration control device 610 is notified that data output is to be started.

Next, the master IC outputs the slave address of the decoration control device 610 to be controlled, which consists of a total of 7 bits. Further, the master IC outputs information indicating whether the request is a write request, which is a read request, at the eighth bit.

When the signal level of the connection line SCL becomes HIGH for the ninth time, the master IC
Since a response signal is input from the decoration control device 610, if it is an ACK response signal, the connection line S
If the signal level of DA changes to LOW and the response signal is NACK, the signal level of connection line SDA changes to HIGH.

Next, after outputting the address data, the master IC outputs the data with a bit number that is a multiple of eight. Further, after the eighth bit of data is output, the ninth bit of data is output after an ACK response signal is input. Thereafter, when data of a bit corresponding to a multiple of 8 is output, after confirming that an ACK response signal is input, a (multiple of 8 + 1) th bit is output and all data is output. Repeat until.

If the master IC outputs a bit that is a multiple of 8 after the data has been output and the ACK response signal is not input even after a predetermined time has elapsed, the master IC assumes that the data transmission has failed and starts again. Send the condition. Next, the address data is output again via the connection line SDA, and the data is output again from the first bit while confirming the ACK response signal.

The master IC outputs the signal indicating the stop condition after outputting the data of the last bit of the data and waiting for the ACK response signal to be input.

In FIG. 27, a total of 24 bits (slave address 8 bits, data 16 bits) from when the signal indicating the start condition is output until the signal indicating the stop condition is output.
However, depending on the size of the data to be transmitted, it may be 24 bits or more, or may be 24 bits or less.

FIG. 28 shows the case where the master IC according to the embodiment of the present invention designates the individual address of the slave and sets the effect control data in the decoration control device 610 and the I2CI / O.
It is a figure explaining the format of the data transmitted / received between the expanders 615. FIG.

The 8-bit data 2801 that is output first includes an address “A0 to A6” of the decoration control device 610 that is a target of data transmission, and a 1-bit that indicates whether the data is a read request or a write request. R / W identification data is included. Address “A0 to A6”
Among them, “A4 to A6” are fixed address portions having a value “110”, and “A0 to A3” correspond to individual addresses set at the terminals A0 to A3 of the I2CI / O expander 615 ( (See FIG. 19). The data 2801 is data corresponding to “ADDRESS” and “R / W” in FIG.

The 8-bit data 2802 to be output next includes setting data for the control register assigned to the output setting register 635 (see FIG. 18) of the I2CI / O expander 615. The data 2802 is “DATA” transmitted first in FIG.
Is the data corresponding to "."

Here, the control register will be described. The control register is composed of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters for designating the writing or reading method to the work register of the output setting register 635, and the lower 5 bits “D0”.
˜D4 ”is a register address that specifies an access start position (a start position at which writing is started or a start position at which reading is started) in the work register.

The auto-write parameter is accessed by the master IC including only the access start position area specified by the register address (auto-increment is prohibited) or including the area adjacent to the access start position area specified (auto-increment). Are parameters that specify whether or not “000”, “100”, “101”, “
Either “110” or “111” can be set.

When a value of “000” is set in the automatic writing parameter, auto-increment is prohibited, and only the area at the access start position specified by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is “10100”, only the storage area with the register number “14h” is accessed, and the other storage areas are not accessed. That is, it is used when only the value of the storage area of a specific register address is changed. When the values of the storage areas of a plurality of register addresses are changed continuously, the address designation can be omitted by permitting auto-increment as described below.

When the value of “100” is set in the auto-write parameter, auto-increment is permitted, and after accessing the area at the access start position specified by the register address, access is made sequentially while moving the area in the direction of increasing the register number. repeat. Then, after accessing the storage area where the register number is “1Bh” at the end, the storage area where the register number is “00h” is accessed and accessed again sequentially while moving the area in the direction in which the register number increases. repeat. For example, if the register address is “10100”, the register number becomes “15h” → “16” after accessing the storage area where the register number becomes “14h”.
"h"->-->"1Bh"->"00h"->"01h"->... (i.e., all areas) are repeatedly accessed.

When the value “101” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case of setting the value of, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area whose register number is “11h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the register number is “02h”.
The recording area (area relating to LED brightness adjustment) in the section of “11h” is repeatedly accessed. For example, if the register address is “10100”, the register number is “14h”.
After accessing the storage area, the register number is “15h” → “16h” →
The areas of “1Bh” → “00h” → “01h” →... Are accessed in order. And
After accessing the storage area where the register number is “11h”, the register number is “02h”
”→“ 03h ”→...“ 11h ”→“ 02h ”→“ 03h ”→...

When the value “110” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case of setting the value of, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “12h” is accessed, and thereafter, the register number is “12h”.
The recording area (area relating to the LED blinking cycle) in the section of “13h” is repeatedly accessed. For example, if the register address is “10100”, the register number is “14h”.
After accessing the storage area, the register number is “15h” → “16h” →
The areas of “1Bh” → “00h” → “01h” →... Are accessed in order. And
After accessing the storage area where the register number is “13h”, the register number is “12h”
”→“ 13h ”→“ 12h ”→“ 13h ”→..

When the value “111” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case of setting the value of, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the register number is “02h”.
The recording area (area relating to LED brightness and blinking cycle) in the section of “13h” is repeatedly accessed. For example, if the register address is “10100”, the register number is “15h” → “16h” after accessing the storage area where the register number is “14h”.
→ ・ → “1Bh” → “00h” → “01h” →...
After accessing the storage area where the register number is “13h”, the area where the register number is “02h” → “03h” → ··· “13h” → “02h” → “03h” → ··· , Repeatedly access.

Here, returning to the description of FIG. 28, the work register setting data 2803 is output following the control register setting data 2802. The setting data 2803 is data corresponding to “DATA” transmitted after the second in FIG.

When the automatic writing parameter is “000”, the setting data 2803 is 8-bit data for updating one storage area designated by the register address. When the automatic writing parameter is set to a value other than “000”, the setting data 2803 is a multiple of 8 necessary for repeatedly updating a plurality of areas starting from the storage area specified by the register address. It becomes bit data.

FIG. 29 shows the case where the master IC according to the embodiment of the present invention designates the slave individual address and sets the effect control data in the decoration control device 610, and the master IC and the I2CI / O.
It is the figure which applied the specific numerical value to the production control data transmitted / received between the expanders 615. FIG. 29 shows the effect control data for prohibiting auto-increment and updating only one specific storage area of the work register. Specifically, the PORT0 terminal to the PORT3 terminal of the I2CI / O expander 615 are shown. The case where the light emission state of the LED connected to is updated will be described.

First, the 8-bit data 2901 that is output first includes the destination decoration control device 610.
“1101100” indicating the slave address of the I2CI / O expander 615 is assigned.

The 8-bit data 2902 to be output next is set in the control register of the output setting register 635 of the I2CI / O expander 615 assigned to set the automatic writing parameter and LED output data. Contains the value.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I2CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

Note that “000” is designated in the auto-write parameter to prohibit auto-increment.

Next, the output 8-bit data 2903 includes data for setting the light emission mode of the decoration device 620 controlled by the destination decoration control device 610. Specifically, LE
Data to be set in the DOUT0 register is assigned. As a result, I2CI /
The light emission state (lighting, extinguishing, blinking, etc.) of the LED connected to the PORT0 terminal to the PORT3 terminal of the O expander 615 is designated, and the LED emits light in the designated state.

In this way, the light emission state of the LEDs of the PORT0 terminal to the PORT3 terminal of the I2CI / O expander 615 is controlled. Can be individually controlled by setting the output data 2903. Even if a motor or a solenoid is connected to the PORT terminal, the same control is performed.

FIG. 30 is a diagram illustrating the order in which the production control data of the master IC according to the embodiment of the present invention is transmitted. In FIG. 30, the order in which each data included in the effect control data is transmitted when auto-increment is permitted and all the storage areas of the work register are updated is defined.

First, the master IC transmits 8-bit data (data having the same format as the data 2801 in FIG. 28) that can specify the individual address of the decoration control device 610 to be controlled.

Next, the master IC transmits data (data having the same format as the data 2802 in FIG. 28) set in the control register of the output setting register 635 of the I2CI / O expander 615 to be controlled. In FIG. 30, in order to update all the storage areas of the work register by permitting auto-increment, “100” is designated as the automatic write parameter, and the register address designating the start position of writing or reading is “00h” which is the head area of the work register is designated.

Therefore, the decoration control device 6 to be controlled after receiving the control register set value
In the 10 I2CI / O expander 615, the storage area (MODE1 register) of the register number “00h” is updated first.

Next, after transmitting the control register set value, the master IC transmits a value (total of 8 bits) to be written to the MODE1 register. When the I2CI / O expander 615 receives the write value, the I2CI / O expander 615 updates the value of the MODE1 register, increments the register number, and prepares to update the next storage area (MODE2 register) of “01h”.

Furthermore, the master IC transmits the value (total 8 bits) to be written to the MODE2 register,
Thereafter, the setting values are sequentially transmitted to the registers in the remaining storage areas whose register numbers are “02h” to “1Bh”. Each time the I2CI / O expander 615 receives the write value, it updates the value of the corresponding register, increments the register number, and repeats the preparation for updating the next storage area, thereby assigning it to the work register. "00h" ~
All register values of “1Bh” are updated.

When the I2CI / O expander 615 updates the storage area of “1Bh” which is the last of the work registers, the I2CI / O expander 615 changes the register number to “00h” and waits for the update of the MODE1 register.

FIG. 31 is a diagram illustrating a format of initialization instruction data transmitted from the master IC to the I2CI / O expander 615 when the master IC according to the embodiment of the present invention initializes the I2CI / O expander 615. It is.

When the CPU 551 of the effect control device 550 instructs the master IC to perform initialization of the decoration control device 610, the master IC all the decoration control devices 6 connected under the master IC.
10 transmits initialization instruction data.

The first output 8-bit data 3101 includes a fixed address “110” shown in FIG.
And a reset address “1011” (see FIG. 23), which is a common address.
The data 3101 corresponds to “ADDRESS” in FIG. 27, and “0” indicating writing is set in the bit of “R / W”.

The first predetermined value “10100101” is set in the 8-bit data 3102 to be output next, and the second predetermined value “01011010” is set in the 8-bit data 3103 to be output next.
Is set. The data 3102 is “DAT” transmitted first in FIG.
The data 3103 corresponds to “DATA” transmitted second in FIG. 27.

When all the I2CI / O expanders 615 connected to the master IC receive initialization instruction data including a reset address, a first predetermined value, and a second predetermined value, the I2CI / O expander 615 initializes itself.

The reason why both the first predetermined value and the second predetermined value are output after the reset address is output is that the master IC does not transmit the reset address “1011”, but the influence of noise or the like. This is because the I2CI / O expander 615 erroneously fetches the reset address “1011” to prevent initialization from being executed at an incorrect timing.

Further, the reset address is an address common to all (in other words, a plurality of) I2CI / O expanders 615, unlike the individual address. For this reason, all (two or more) I2CI / O expanders 615 are selected and initialized only by transmitting the initialization instruction data including the reset address once. Therefore, the I2CI / O expanders 615 are individually set. Compared with the method of instructing initialization and selecting initialization, it is possible to instruct initialization at high speed.

In FIG. 31, the first predetermined value and the second predetermined value are different from each other, but may be the same value. Further, either the first predetermined value or the second predetermined value may be transmitted once.

FIG. 32 shows the abnormality determination table 3200 of the first master IC 570a according to the embodiment of the present invention.
FIG.

The abnormality determination table 3200 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3200 is provided to monitor the connection state between the first master IC 570a of the effect control device 550 and the I2CI / O expander 615 connected to the first master IC 570a. The abnormality determination table 3200 includes each I2CI /
Information corresponding to the O expander 615 is stored.

The abnormality determination table 3200 includes an I / O expander address 3201, a slave address 3202, an error counter 3203, a comparison value 3204, and an error flag 3205.

The I / O expander address 3201 includes I2 connected to the first master IC 570a.
This corresponds to the addresses (see FIG. 19) set in the terminals A0 to A3 of the CI / O expander 615.

In the slave address 3202, the slave address registered in the I2CI / O expander address table 2300 shown in FIG. 23 is registered.

The error counter 3203 is sent from the first master IC 570a to the I2CI / O expander 6
The effect control data is transmitted to 15 and incremented when the ACK cannot be received twice consecutively from the I2CI / O expander 615.

In the comparison value 3204, a value to be compared with the value of the error counter 3203 is registered in order to determine whether or not a failure has occurred in the I2CI / O expander 615. In addition,
The value of the comparison value 3204 may be set according to the type of the rendering device to be controlled.

Registered in the error flag 3205 is an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I2CI / O expander 615.

The method for determining whether or not a failure has occurred in the I2CI / O expander 615 will be described in detail. When the value of the error counter 3203 reaches a predetermined value set in the comparison value 3204, an error flag 3205 is determined. Is set to “ON”, and it is registered that a failure has occurred in the I2CI / O expander 615 corresponding to the entry.

In the embodiment of the present invention, as described later, production control data output processing (see FIG. 37).
Are executed in synchronism with the VDP interrupt (period of about 33.3 ms).

As described above, 2 from the first master IC 570a to the I2CI / O expander 615
If the ACK from the I2CI / O expander 615 cannot be received for the transmission of the production control data for the second time, the error counter 3003 is incremented.

Therefore, when an abnormality has occurred, the data output processing execution cycle is 33.3 ms.
Since the comparison value 3004 is “300”, the I2CI is 33.3 ms × 300≈10 s.
The occurrence of an abnormality relating to the / O expander 615 is detected.

FIG. 33 shows the abnormality determination table 3300 of the second master IC 570b according to the embodiment of this invention.
FIG.

Similar to the abnormality determination table 3200 of the first master IC 570a, the abnormality determination table 3300 of the second master IC 570b is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3300 includes the second master IC 570b of the effect control device 550 and the second master IC 570b.
It is provided to monitor the connection status with the I2CI / O expander 615 connected to the master IC 570b. The abnormality determination table 3300 includes each I2CI according to the connection state.
Information corresponding to the / O expander 615 is stored. Also, the abnormality determination table 3300
Is the same as the abnormality determination table 3200 of the first master IC 570a.

In the embodiment of the present invention, since there is no decoration control device 610 connected to both the first master IC 570a and the second master IC 570b, the I of each decoration control device 610 to be controlled.
An / O expander address is set for each master IC. Therefore, FIG. 32 and FIG.
3, an I / O expander address having the same value is set. Since only one address can be set as the I / O expander address, it is necessary to set a common address when a plurality of master ICs control one decoration control device 610.

The master IC according to the embodiment of the present invention includes a plurality of registers that are used to configure device operation and transmit / receive serial data. The command register (REG) 581 shown in FIGS. 11 and 12 is one of such registers, and instructs the connected decoration control device 610 to output a start condition or a stop condition.

The effect control device 550 transmits an effect instruction to the decoration control device (slave) 610 via the master IC, and executes various effect processes. FIG. 34 shows a procedure for initializing each slave.
Shows the outline of the procedure for transmitting the production control data to each slave.

FIG. 34 illustrates information transmitted and received between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when each decoration control device (slave) according to the embodiment of the present invention is initialized (reset). It is a figure to do.

When the slave initialization start process is started, the CPU 551 of the effect control device 550 starts the start condition (STA) and the stop condition (S) of the command REG581.
(1) is set to a bit instructing execution of (TO) (3401).

The master IC follows the information (STO, STA) set in the command REG581.
First, a stop condition is output to each decoration control device (slave) 610 to be controlled, and then a start condition is output (3411). Notify each slave that the data transmission is completed by outputting a stop condition, and then
By outputting the start condition, the preparation for receiving the command input is completed in each slave.

When the master IC outputs the start condition, the interrupt signal (IN
T) is input to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (1) of the transmission instruction data (3402). In the transmission resumption process (1) of the transmission instruction data, a reset address is set in the output buffer 572. The reset address is a fixed address determined in advance for resetting each slave. At this time, “0” is set in the STA and STO of the command REG581.

The master IC outputs predetermined data (reset command) to the reset address set in the output buffer 572 (3412). The reset command corresponds to the first predetermined value (data 3102) and the second predetermined value (data 3103) described in FIG.

When the master IC outputs the reset address, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (2) of the transmission instruction data (3403). In the transmission restart process (2) of the transmission instruction data, the first half value of the reset command is set in the output buffer 572. The first half value of the reset command corresponds to the first predetermined value (data 3102) described in FIG. At this time, the command REG 581
“0” is set in STA and STO. The master IC outputs the first half value of the reset command set in the output buffer 572 (3413).

Thereafter, when the master IC outputs the first half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (3) of the transmission instruction data (3404), and sets the latter half value of the reset command in the output buffer 572. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the latter half value of the reset command set in the output buffer 572 (3414). The latter half value of the reset command corresponds to the second predetermined value (data 3103) described with reference to FIG.

Further, when the master IC outputs the second half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission restart process (4) of the transmission instruction data (3405), sets “0” to the STA of the command REG581, and S
“1” is set in TO, and the master IC is instructed to output a stop condition.

The master IC outputs a stop condition to each slave according to the information set in the command REG 581 (3415).

Through the above processing, each slave is initialized. If initialization fails, (
3406), the process is restarted from step 3402.

FIG. 35 shows the CPU 551 and the master IC (the first master IC 570a or the second master IC 570) when transmitting the effect control data to each decoration control device (slave) according to the embodiment of the present invention.
It is a figure explaining the information transmitted / received between b).

When performing the effect control, the CPU 551 of the effect control device 550 first executes the command REG.
“1” is set to a bit instructing execution of a start condition (STA) 581 and a stop condition (STO) 581 (3501).

The master IC outputs a stop condition to each slave based on the values (“1”) set in the STA and STO of the command REG 581, and then outputs a start condition (3511).

When the master IC outputs a start condition to each slave, the master IC is ready to receive the presentation control data at each slave. Therefore, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets presentation control data indicating the address of the slave to be controlled and the control content in the output buffer 572 (3502). At this time, “0” is set in the STA and STO of the command REG581.

The master IC outputs the address and effect control data set in the output buffer 572 to each slave (3512). At this time, the slave corresponding to the output address is
An effect process is executed based on the received effect control data.

When the master IC outputs the address and effect control data to each slave,
An interrupt signal is input to U551 to generate an interrupt. The CPU 551 that generated the interrupt
“1” is set in the STA of the command REG581, and “0” is set in the STO (3503). Thereafter, the master IC outputs a so-called restart condition that outputs a start condition again (3513).

Subsequently, the CPU 551 and the master IC perform similar processing by designating different addresses (
3504, 3514, 3505, 3515). When the CPU 551 completes the output of the presentation control data for the last nth slave (3506), and the master IC outputs the presentation control data to the corresponding slave (3516), the output of all the data is completed, so Output the condition. Specifically, when the master IC has finished outputting the production control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt, and the CPU 551 that generated the interrupt generates “0” in the STA of the command REG581. ", STO is set to" 1 "(3507), and then the master IC outputs a stop condition (3517).

FIG. 36 shows a master IC (first master IC) from the production control device 550 according to the embodiment of the present invention.
570a or the second master IC 570b) is a diagram illustrating the stage of transmitting the presentation control data.

When the slave output data editing process described later is executed, the CPU 551 of the effect control device 550 secures an output data preparation area in the RAM 553 and stores the effect control data for each slave in the output data preparation area.

In addition, the output data preparation area is further divided for each slave, and stores the production control data corresponding to the address and production content corresponding to each slave. Specifically, the address corresponds to the data of the transmission order 1 shown in FIG. 30, and the effect control data corresponds to the data of the transmission orders 2 to 30 shown in FIG.

Further, the CPU 551 further secures an output data save area in the RAM 553 so that untransmitted effect control data is not overwritten, and saves the data stored in the output data preparation area by the slave output data save process to the output data save area. Let Thereafter, the saved data is set in the output buffer 572 of the master IC at a predetermined timing.

The output data preparation area and the output data saving area are secured in the RAM 553 for each master IC. In the embodiment of the present invention, the first master IC 570a and the second master IC 570 are used.
Each area corresponding to b is secured.

FIG. 37 is a flowchart showing a procedure of processing performed by the effect control device 550 according to the embodiment of this invention.

  The processing shown in FIG. 37 is executed by the CPU 551 of the effect control device 550.

When the production control device 550 is turned on, first, the production control device 550 is step 37.
The synchronization signal synchronized with the image update cycle from the VDP 556 in the processing of step 3707 (for example, the synchronization signal of 33.3 ms second cycle) is executed as the interrupt signal.
Wait until input to U551. Thereafter, every time a synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551 as an interrupt signal, steps 3705 to 3 are performed.
The process 721 is repeatedly executed.

First, the effect control device 550 executes initialization processing including initialization of the RAM 553 of the effect control device 550 (3701). At this time, an initialization stage number related to the first master IC 570a described later and an initialization stage number related to the second master IC 570b are both set to “0”.
Set to "".

Then, the effect control device 550 inputs the reset pulse to the first master IC 570a and the second master IC 570b via the output I / F 558a and the NOR gate circuit 561, and the first
The master IC 570a and the second master IC 570b are initialized in hardware (3702).

Subsequently, the effect control device 550 initializes the I2CI / O expander 615 of all the decoration control devices 610 connected to the first master IC 570a in order to initialize the first master IC5.
First slave IC 570a side slave initialization start processing for outputting initialization instruction data from 70a is executed (3703). Similarly, in order to initialize the I2CI / O expander 615 of all the decoration control devices 610 connected to the second master IC 570b, the second master IC
The second master IC 570b side slave initialization start process for outputting initialization instruction data from 570b is executed (3704). Details of the slave initialization start process will be described with reference to FIG.

Further, the effect control device 550 waits until both the initialization stage number relating to the first master IC 570 and the initialization stage number relating to the second master IC 570b become “0” (
3705). The initialization stage numbers are the first master IC 570a and the second master IC 570b.
Is the number indicating the progress of the initialization process, and immediately after the power is turned on, the production control device 550
Immediately after starting up, it is “0”, but when the initialization process is started, “
It is incremented by 1 from “1” to “4”. When the initialization process is completed, “0” is again displayed.
In the initialization instruction data transmission restart process described with reference to FIG. 42, processes corresponding to the set initialization stage number are sequentially executed.

When initialization of all the masters and slaves is completed, the production control device 550
56 accepts a synchronization signal (VDP interrupt) synchronized with the image update cycle and accepts a timer interrupt (3706).

As described with reference to FIG. 36, the effect control device 550 executes a slave output data saving process for saving the effect control data stored in the RAM 553 so as not to be overwritten (3).
707). As described above, the output data saved in the save area is set in the master IC at a predetermined timing.

Then, the effect control device 550 displays the image on the display device 53 in order to display the VDP 556.
Data serving as an instruction to display an image is output (3708). Furthermore, sound control data is output to the sound LSI 557 in order to output sound from the speaker 30 according to the gaming state.
The sound LSI 557 causes the speaker 30 to output sound based on the input sound control data (3709).

Next, the effect control device 550 executes slave output start processing for outputting effect control data from the first master IC 570a and the second master IC 570b to the decoration control device 610 (3).
710). The decoration control device 610 controlled here mainly controls a light emitter such as an LED, and is a light emission control device or a light emission control slave. Details of the slave output start processing will be described later with reference to FIG.

When the slave output start process is completed, the effect control device 550 edits the next data output to the VDP 556 (3711), and further edits the sound control data output to the sound LSI 557 (3712).

Further, the effect control device 550 executes a slave output data editing process for editing the effect control data to be transmitted to the decoration control device 610 that controls the light emitter (3713). In the slave output data editing process, as described with reference to FIG. 36, the production control data of each slave is generated and stored in the output data preparation area secured on the RAM 553.

Next, the effect control device 550 refers to the abnormality determination table 3200 shown in FIG. 32, and executes an error determination process related to the light emission control slave connected to the first master IC 570a (3714).

In the error determination process, the effect control device 550 determines whether or not the error flags 3205 of the entries corresponding to the light emission control slaves in the abnormality determination table 3200 are all “ON”, that is, an error occurs in all the light emission control slaves. It is determined whether or not. In other words, at least one light emission control slave whose error flag 3205 is “OFF” is at least one.
Determine whether there are more than two. If it is determined by this error determination process that an error has occurred in all the light emission control slaves, the conditions for resetting all the light emission control slaves connected to the first master IC 570a and the first master IC 570a are satisfied. It is assumed that.

The effect control device 550 determines whether or not the reset condition is satisfied based on the result of the error determination process in step 3714 (3715). As described above, when the error flags 3205 of all the light emission control slaves are “ON” at the time of the error determination process in step 3714, it is determined that the reset condition is satisfied.

When it is determined that the reset condition is satisfied (the result of 3715 is “Y”), the effect control device 550 initializes the first master IC 570a (3716) and the first master IC 570.
First slave IC 570a side slave initialization start processing for outputting initialization instruction data simultaneously to all I2CI / O expanders 615 (decoration control device 610) connected to a is executed (3717).

As described above, when it is determined that the reset condition is satisfied, in step 3717, all the I2CI / O expanders 615 connected to the first master IC 570a are instructed to initialize at the same time. That is, since all the I2CI / O expanders 615 are selected and initialized at the same time, the initialization can be performed at a higher speed than the method of individually selecting the I2CI / O expander 615 and instructing the initialization. I2 can be done
The CI / O expander 615 can be quickly returned to a normal state. At this time,
The CPU 551 writes the initialization instruction information to the reset REG 573 via the bus 563, thereby resetting the first master IC 570a in software.

If it is determined that the reset condition is satisfied in step 3715, the first master I
Since there is a possibility that an abnormality has occurred in C570a, the first master IC 570a is also initialized by the processing in step 3716.

The first master IC 570a is connected to the connection lines SDA and SCL by a command from the CPU 551.
1 is functioning as a signal level control means for controlling the signal level of the first master IC 570a itself when an abnormality relating to data transmission occurs in all the light emission control devices. Is also possible.

Therefore, if an abnormality related to data transmission occurs in all the decoration control devices 610, the first master IC 570a is initialized by the CPU 551 (arithmetic processing means) just in case. Thus, even if an abnormality has occurred in the first master IC 570a, the first master IC 570a can be reliably controlled.

Further, the effect control device 550 similarly executes error determination processing for the second master IC 570b (3718), and determines whether the reset condition is satisfied (3719).
). If the reset condition is satisfied, the second master IC 570b is reset (3720), and the slave initialization start processing on the second master IC 570b side for initializing the slave connected to the second master IC 570b is executed. (3721). Then VDP556
Until the synchronization signal is input to the CPU 551.

As described above, in the process shown in FIG. 37, the I2CI / O EX of the decoration control device 610 from the first master IC 570a and the second master IC 570b of the effect control device 550 is synchronized with the cycle of updating the image of the display device 53. The effect control data is transmitted to the panda 615. And
The I2CI / O expander 615 performs the decoration device 620 based on the received effect control data.
The display device 53 and the decoration device 620 are in harmony with each other.
Since it does not give the player a sense of incongruity, interest can be enhanced.

In addition, the first master IC 570a and the second master IC 570a are synchronized with the cycle of updating the image of the display device 53.
Each time the decoration control device 610 receives the effect control data transmitted from the master IC 570b, the value of the work register (see FIG. 24) is updated by the I2CI / O expander 615. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

Steps 3714 and 3718 are synchronized with the cycle of updating the image on the display device 53.
Since the error determination process is executed in step 1, the frequency for determining the error can be set appropriately. That is, if the error determination processing is executed too frequently, the CPU 55 of the effect control device 550
If the processing load of 1 increases and, conversely, if the execution frequency of the error determination process is too low, the occurrence of abnormality cannot be detected at an appropriate timing. By performing the error determination in synchronization with the cycle of updating the image of the display device 53, it becomes possible to detect the error at an appropriate timing, and to appropriately cope with the occurrence of a defect in each process.

FIG. 38 is a flowchart illustrating a procedure of slave initialization start processing on the first master IC 570a side and slave initialization start processing on the second master IC 570b side according to the embodiment of this invention.

The slave initialization start process on the first master IC 570a side is executed in steps 3703 and 3717 in FIG. 37, and the slave initialization start process on the second master IC 570b side is the same process executed in step 3704 or step 3721. .

In the initialization start process on the first master IC 570a side, first, the CPU of the effect control device 550
551 prohibits a master interrupt and a time interrupt (3801). Then, the first master IC 570a is selected as the master to be initialized (3802).

In the slave initialization start process on the second master IC 570b side, the first master IC 57
Similar to the 0a-side slave initialization start process, the CPU 551 inhibits the master interrupt and the time interrupt (3811). Then, the second master IC 570b is selected as the master to be initialized (3812).

In the subsequent processing, the first master IC 570a side slave initialization start processing and the second master I
For the C570b side slave initialization start process, a common process is executed for the selected master.

The CPU 551 sets “1” to the initialization stage number of the selected master (3803).
. Further, a monitoring timer for the selected master is set (3804), and timeout monitoring is started (3805).

In response to the selected master command REG581, the CPU 551 sets “1” to the STA.
“1” is set in STO, “0” is set in SI, and “0” is set in MODE (3806).

As described above, the STA is a bit for instructing the output of the start condition, and the STO is a bit for instructing the output of the stop condition. When “1” is set in each bit, a corresponding signal is output by the master IC. Step 3
In the processing of 806, signals of both a start condition and a stop condition are output.

SI is a bit for notifying the occurrence of the aforementioned master interrupt. When “1” is set, the master IC requests the CPU 551 to generate an interrupt, and this bit is set to “0”. The master IC that generated the interrupt is in a state of waiting for processing until changed to. When this bit is set to “0” by the CPU 551, the CPU
The interrupt generated in 551 is canceled, and the master IC that has been waiting for the process resumes the process to be performed next. In the process of step 3806, since “0” is set, the generation of the interrupt is canceled, and the master IC that has been waiting for the process resumes the operation.

MODE is a bit for designating a mode for transmitting data. When “1” is set, “buffer mode” is designated, and when “0” is set, “byte mode” is designated. Is done. In step 3806, since “0” is set, data is exchanged in the byte mode.

Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3807).
Return to the caller.

FIG. 39 is a flowchart illustrating a procedure of slave output start processing according to the embodiment of this invention.

The slave output start process is a process executed in step 3710 shown in FIG. 37, and is a process necessary for transmitting presentation control data from each master to the light emission control slave.

The CPU 551 first prohibits the master interrupt and the time interrupt (3901). Next, the start flag corresponding to the first master IC 570a is set to “ON” (3902).
. Furthermore, the monitoring timer of the first master IC 570a is set (3903), and timeout monitoring processing is started (3904). The start flag is a flag indicating whether or not the start condition is output and the transmission of the production control data is started, and is set for each master IC. The start flag is stored in the RAM 553 of the effect control device 550.

Further, the CPU 551 determines that the command REG 581 of the first master IC 570a is S
TA is set to “1”, STO is set to “1”, SI is set to “0”, and MODE is set to “1” (39
05). In the processing of step 3905, since “1” is set in MODE, data is transmitted and received in the buffer mode.

Similarly, for the second master IC 570b, the CPU 551 determines that the second master IC 5
The start flag 70b is set to ON (3906). In addition, set a monitoring timer (
3907), a timeout monitoring process is started (3908). Furthermore, the second master IC
In response to the command REG581 of 570b, “1” for STA, “1” for STO, “0” for SI
And “1” are set to MODE (3909).

The CPU 551 selects the first slave (decoration control device 610) of each master (39
10). In each master IC, the order of slaves for transmitting the effect control data is set in advance. The first slave in the order is set in the process of step 3910, and the effect control data is sequentially transmitted to each slave connected to the first master IC 570a in the effect control data transmission restart process described later.

Furthermore, the CPU 551 sets a retry counter to 0 (3911). The retry counter is a counter that is incremented when transmission fails when the production control data is transmitted to each master. When the retry counter becomes larger than a predetermined value, it can be determined that some trouble has occurred.

Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3912).
Return to the caller.

FIG. 40 shows the first master IC 570a side and the second master IC 570 according to the embodiment of the present invention.
It is a flowchart which shows the procedure of the process at the time of the transmission interruption interruption on the b side.

The transmission interruption interrupt is a so-called master interruption, and processing is executed according to the state at the time of interruption.

First, when a master interrupt from the first master IC 570a occurs, the CPU 551 ends the time-out monitoring for the first master IC 570a (4001). Further, the initialization stage number and start flag of the first master IC 570a are acquired (4002).
).

Similarly, when a master interrupt from the second master IC 570b occurs, the CPU 551 ends the time-out monitoring for the second master IC 570b (4011),
The initialization stage number and start flag of the master IC 570b are acquired (4012).

The CPU 551 determines whether or not the initialization stage number of the master IC to be initialized is “0” (4003). The case where the initialization stage number is “0” indicates that the initialization process is not being executed. That is, when the initialization stage number is other than “0”, it indicates that the initialization process is being executed.

If the initialization stage number of the master IC to be initialized is not “0”, the CPU 551 (
The result of 4003 is “N”). Since the initialization process is in progress as described above, the process of resuming the transmission of the initialization instruction data is executed (4004). Details of the transmission restart processing of the initialization instruction data will be described later with reference to FIG.

On the other hand, if the initialization stage number of the master IC to be initialized is not “0” (result of 4003 is “Y”), the CPU 551 has already completed the initialization process, and transmits the effect control data. Because it is in the middle of the transmission, a process for resuming the transmission of effect control data is executed (4005). Details of the transmission restart processing of the effect control data will be described later with reference to FIG.

FIG. 41 shows the first master IC 570a and the second master IC 570b according to the embodiment of the present invention.
5 is a flowchart showing a processing procedure when a time-out interrupt is generated.

This process is a process executed to initialize each master IC when a timer interrupt occurs when the first master IC 570a or the second master IC 570b does not return after a predetermined time has elapsed. .

When a timeout interrupt occurs in the first master IC 570a, the CPU 551 performs a soft reset on the first master IC 570a (4101). Further, a slave initialization start process (FIG. 38) on the first master IC 570a side for initializing the slave connected to the first master IC 570a is executed (4102).

When a timeout interrupt occurs in the second master IC 570b, the CPU 551 performs a soft reset on the second master IC 570b (4111). Furthermore, slave initialization start processing (FIG. 38) on the second master IC 570b side for initializing the slave connected to the second master IC 570b is executed (4112).

FIG. 42 is a flowchart illustrating a procedure of the transmission restart process of the initialization instruction data according to the embodiment of this invention.

The CPU 551 first determines whether or not to continue the transmission process of the initialization instruction data based on the status code (4201), and branches the process according to the determination result (4202). The status code is a value indicating the state of the master IC, and the status register (REG) 5
82. In the process of step 4201, a transmission process continuation determination table 440, which will be described later with reference to FIG. 44, from the combination of the set status code and the current initialization stage number.
With reference to 0, it is determined whether or not to continue the process of transmitting the initialization instruction data. The relationship between the initialization stage number and the status code will be described in detail with reference to FIG.

The initialization stage number is set according to the processing stage when the master IC is being initialized.
One of the values “1” to “4” is set, and when the initialization of the master IC is completed,
However, when initialization of the master IC is completed and the initialization stage number becomes “0”, the transmission restart process of the initialization instruction data is not called (see FIG. 40). Since there is a branch in step S4003 in the calling source process), the description will be made on the assumption that the initialization stage numbers are “1” to “4”.

If the determination result based on the combination of the initialization stage number and the status code is not “continuous” (the result of 4202 is “N”), the CPU 551 is not in a normal state (for example, the data transmission has failed). Therefore, the value “1” indicating the start of initialization is set as the initialization stage number (4203). Further, a monitoring timer is set, and timeout monitoring is started (42
04).

Finally, the CPU 551 outputs “1” to the STA of the command REG581 of the master IC to be processed, “1” to the STO, “0” to the SI, and “0” to the MODE so as to output the stop condition and the start condition. The setting is made (4205), and the process returns to the calling process.

On the other hand, when the determination result based on the combination of the initialization stage number and the status code is “continuation” (the result of 4202 is “Y”), the CPU 551 is executing the initialization process normally. Then, the process branches based on the initialization stage number (4206).

When the initialization stage number is “1”, the CPU 551 sets a reset address in the output buffer 572 of the processing target master IC (4207).

When “1” is set in the initialization stage number, it means that a start condition is output from the master IC. Referring to the transmission processing continuation determination table 4400 in FIG.
As the status code, “08h” or “10h” indicating that a start condition or a restart condition is transmitted is set. Therefore, “1” is set in the initialization stage number, and “08h” or “10h” is set in the status code.
Is set, the processing after step 4207 is executed.

The CPU 551 increments the initialization stage number (4208), sets a monitoring timer, and starts time-out monitoring (4209). Finally, in order to continue the processing, “0” is set in each of the STA, STO, SI, and MODE of the command REG 581 of the processing target master IC (4210), and the processing returns to the calling source processing.

When the initialization stage number is “2”, the CPU 551 sets the first half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4211).

When the initialization stage number is set to “2”, the output buffer 572 of the master IC
This means that the reset address is set in. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code includes an ACK indicating that the slave address (here, the reset address) has been transmitted and that the signal has been normally received from each slave. “18h” indicating that the response has been made is set. However, the status code is set to “20h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Accordingly, when “2” is set in the initialization stage number and “18h” is set in the status code, step 42 is performed.
11 and subsequent processes are executed.

When a value is set in the output buffer 572, the CPU 551 sets the initialization stage number to “1”.
As in the case of, the processing from step 4208 to 4210 is executed.

If the initialization stage number is “3”, the CPU 551 sets the latter half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4212).

If the initialization stage number is set to “3”, the output buffer 572 of the master IC
This means that the first half value of the reset command is set in. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code indicates that the data set in the output buffer 572 has been transmitted and that the signal has been normally received from each slave.
“28h” indicating that K is responded is set. However, the status code is set to “30h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Accordingly, when “3” is set as the initialization stage number and “28h” is set as the status code, the processing after step 4212 is executed.

When a value is set in the output buffer 572, the CPU 551 sets the initialization stage number to “1”.
As in the case of, the processing from step 4208 to 4210 is executed.

When the initialization stage number is set to “4”, the output buffer 572 of the master IC
Means that the second half value of the reset command is set. Referring to the transmission processing continuation determination table 4400 in FIG. 44, as in the case where the initialization stage number is “3”, “28h” or “30h” is set in the status code, and “28h” is set in the status code. In this case, the processing after step 4212 is executed.

When the initialization stage number is “4”, the processing necessary for the initialization process is completed, so the CPU
In step 551, the error flags of all the decoration control devices 610 connected to the master IC to be processed are set to OFF (4213), and the error counter is set to 0 and initialized (4).
214). Then, the initialization stage number is set to “0” indicating that the initialization process is not in progress.
Finally, in order to complete the initialization process and to output a stop condition from the master IC to be processed to all the decoration control devices 610 connected to the master IC, the STO of the command REG 581 of the master IC to be processed is output. “1”, STA, SI, and MODE are set to “0” (4216), and the process returns to the caller process.

FIG. 43 is a flowchart showing a procedure of resumption of transmission processing of effect control data according to the embodiment of the present invention.

The CPU 551 first determines processing to be executed based on the status code (4301).
), Branch depending on whether to continue processing, retransmit data, or stop data transmission (43
02). In the process of step 4301, based on the combination of the status code and the value set in the start flag, a process to be executed is determined with reference to a transmission process continuation determination table 4400 described later with reference to FIG.

The start flag is a flag for controlling the timing of transmitting the presentation control data for each of the first master IC 570a and the second master IC 570b. In particular,
When the slave output start process (FIG. 39) in step 3710 of FIG. 37 is executed, the start flag is set to “ON”. Further, as described later, when the production control data is set in the output buffer 572, the start flag is set to “off”. The status code is
As described above, this is a value indicating the state of the master IC, and the status register (REG) 582.
Is set to The relationship between the start flag and the status code will be described in detail with reference to FIG.

If the CPU 551 determines that the process is to be continued by the combination of the start flag and the status code (the result of 4302 is “continue”), the presentation control data is normally transmitted. At this time, when the start flag is “on”, as described above, after the start condition is output, the corresponding status code is
It becomes “08h” or “10h”. On the other hand, when the start flag is “off”, if the process is normally performed, the status code indicates that data transmission has been completed normally “2”.
8h "is set.

Therefore, the CPU 551 determines whether or not the start flag is “ON” (430).
3). If the start flag is “ON” (the result of 4303 is “Y”), the RAM 5
The data prepared on 53 is set in the output buffer 572 (4304). Then, the start flag is set to “off” (4305), a monitoring timer is set, and timeout monitoring is started (4306). Finally, the command REG 581 of the master IC to be processed
STA, STO, and SI are set to “0”, and MODE is set to “1” in order to transmit the data set in the output buffer 572 in the buffer mode (4307),
Return to the calling process.

On the other hand, when the start flag is “OFF” (the result of 4303 is “N”), the CPU 551 sets the error flag corresponding to the selected slave (decoration control device 610) to “OFF” (4308). Further, an error counter is initialized (4309).

Thereafter, the CPU 551 determines whether or not the transmission resumption process has been completed for all the slaves (4310). If the processing is completed for all slaves (4
310 is “Y”), a stop condition is output, and “1” is set in the STO and MODE of the command REG 581 so that the mode for transmitting data is designated as “buffer mode”.
", STA and SI are set to" 0 "(4311), and the process returns to the caller process.

When the processing has not been completed for all slaves, the CPU 551 (4310).
Is "N"), the retry counter is set to 0 (4312), and the next slave to be processed is selected (4313). Then, output data to the selected slave is prepared (43
14) The start flag is set to “ON” (4315), the monitoring timer is set, and the time-out monitoring is started (4316).

Finally, the CPU 551 outputs a start condition and sets “STA mode” and “MODE” of the command REG 581 so as to designate the mode for transmitting data as “buffer mode”.
“1”, STO and SI are set to “0” (4317), and the process returns to the caller process.

If it is determined that the effect control data is retransmitted by the combination of the start flag and the status code (the result of 4302 is “retransmit”), the CPU 551 increments the value of the retry counter (4318). Then, it is determined whether or not the value of the retry counter has reached the designated value (4319). The designated value at this time is set in the abnormality determination table 3200 or the abnormality determination table 3300 shown in FIG. 32 or 33, and corresponds to the comparison value 3204 corresponding to the currently selected slave.

When the value of the retry counter has not reached the specified value, the CPU 551 (4322).
The result is “N”), the slave is selected again during the current selection (4320), data to be output to the selected slave is prepared (4314), and the processing after step 4315 is executed.

On the other hand, when the value of the retry counter reaches the specified value, the CPU 551 (4322).
Is “Y”), the error flag 3205 of the selected slave is set to “ON”, and the processing after step 4310 is executed.

Finally, if it is determined by the combination of the start flag and the status code that the transmission restart process of the effect control data is to be stopped (the result of 4302 is “stop”), the CPU 551 returns to the calling process. When the transmission restart process of the effect control data is stopped, the connection line SDA or the connection line SCL is occupied for some reason, and furthermore, since this occupied state cannot be released, data transmission / reception cannot be performed. Is the case.

FIG. 44 is a diagram showing an example of a transmission processing continuation determination table 4400 for determining continuation of data transmission resumption processing according to the embodiment of this invention.

The transmission process continuation determination table 4400 stores information for determining whether to continue the data transmission restart process as described above. The data transmission restart process includes an initialization instruction data transmission restart process (FIG. 42) and an effect control data transmission restart process (FIG. 43). The transmission process continuation determination table 4400 includes a process for each case. Continuation judgment is registered.

The transmission process continuation determination table 4400 includes a status code 4401, initialization instruction data transmission resumption process continuation determination 4402, effect control data transmission resumption process continuation determination 4403, and state 4404.

As described above, the status code 4401 is the master IC regardless of the processing to be executed.
It is a value indicating the state of.

A state 4404 is a state of the master IC corresponding to the status code 4401. For example, when the status code is “08H”, it indicates a state where the transmission of the start condition is completed. Further, when the status code is “10H”, it indicates that the transmission of the start condition, that is, the transmission of the restart condition is completed.

In the embodiment of the present invention, the connection line SDA or the connection line SCL is occupied for some reason, and if it cannot be released, “70H” or “78H” is set in the status code 4401.

Subsequently, continuation determination 440 of the initialization instruction data transmission restart process corresponding to the status code is performed.
2 and the continuation determination 4403 of the effect control data transmission restart process will be described.

In the initialization instruction data transmission restart process, the process is executed for each stage corresponding to the initialization stage number, and the continuation determination 4402 of the initialization instruction data transmission restart process is defined for each initialization stage number. Specifically, as shown in the figure, “continuation” or “resumption” is defined corresponding to the combination of the value of the initialization stage number and the value of the status code.

When the value of the continuation determination 4402 is “continuation”, it indicates that the initialization instruction data transmission restart process is being processed normally. Specifically, when the output of the start condition is successful when the initialization stage number is 1, or when the address transmission is successful when the initialization stage number is 2, the value of the continuation determination 4402 is “continue”. become. That is, when the process executed in the initialization instruction data transmission restart process and the status code set in the status register (REG) 582 match, the value of the continuation determination 4402 becomes “continue”.

On the other hand, when the value of the continuation determination 4402 is “restart”, it is set when the initialization instruction data transmission restart process is restarted, such as when the initialization instruction data transmission restart process is not normally processed. That is, the process executed in the initialization instruction data transmission restart process is not consistent with the status code set in the status register (REG) 582, for example, when data transmission has failed.

In the effect control data transmission restart process, the process is executed based on the set value of the start flag, and the continuation determination 4403 of the effect control data transmission restart process is defined for each set value of the start flag. Specifically, as shown in the figure, “continuation”, “retransmission” or “cancel” is defined corresponding to the combination of the value of the start flag and the value of the status code.

The start flag is set to ON when data is first transmitted after the start condition is output, and is set to OFF when the process is continued. That is, when the initial setting is completed, the start flag is set to OFF, and then data is continuously transmitted. When the value of the continuation determination 4403 is “continuation”, after the start condition transmission (start flag is ON) and the status code is set to “08H” or “10H”, after data transmission (start flag is OFF) Is set with a status code “28H” indicating successful data transmission.

On the other hand, if the connection line SDA or the connection line SCL is in an occupied state for some reason and cannot be released, the data transmission / reception is stopped because the data cannot be transmitted / received.
Specifically, the status code 4401 is “70H” or “78H”.

In other cases, that is, when the status code and the start flag are not matched in a state where data can be transmitted and received, “retransmission” is set, and processing for retransmitting the presentation control data is executed.

FIG. 45 is a flowchart illustrating a procedure of data transmission processing by the master IC according to the embodiment of this invention. This process is a process common to the first master IC 570a and the second master IC 570b. The CPU 551 causes the command register 581 (see FIGS. 11 and 12).
When the SI bit of “0” is set, the master IC that has been waiting due to the occurrence of the interrupt process starts the process.

First, the controller 574 of the master IC determines whether or not output of a stop condition is requested, that is, whether or not “1” is set in the STO of the command REG 581 (4501).

When the controller 574 is requested to output a stop condition (4)
When the result of 501 is “Y”), stop condition output processing is executed (4502). The stop condition output process executes a process necessary for executing the stop condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the stop condition output processing will be described later with reference to FIG.

The controller 574 further determines whether or not the output of the start condition is requested, that is, whether or not “1” is set in the STA of the command REG581 (4503). When the output of the start condition is requested (the result of 4503 is “Y”), the start condition output process is executed (4506). The start condition output process executes a process necessary for executing the start condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the start condition output processing will be described later with reference to FIG.

When the output of the start condition is requested, the controller 574 (4
The result of 503 is “N”), and the value of STCD is set in the status code (4506). S
TCD is a variable for substituting a set status code. When a value is set for the status code, this process ends.

When the controller 574 does not request the output of the stop condition (
The result of 4501 is “N”), and it is determined whether or not the output of the start condition is requested, that is, whether or not “1” is set in the STA of the command REG581 (4).
505). When the output of the start condition is requested (the result of 4505 is “Y”), the start condition output process is executed (4506). Then, the STCD value set in the start condition output process is set in the status code (45
07). Thereafter, a transmission interruption interrupt is generated by setting “1” to the SI of the command REG581.

When the output of the start condition is not requested, the controller 574 (
The result of 4505 is “N”), and data transmission processing to the slave is executed (4508). Then, the STCD value set in the data transmission process to the slave is set in the status code (4507). Thereafter, a transmission interruption interrupt is generated by setting “1” to the SI of the command REG581.

FIG. 46 is a flowchart showing a procedure of stop condition output processing according to the embodiment of the present invention.

The stop condition is output by changing the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH. In the stop condition output process, the process is executed according to the signal level of each connection line at the start of the process.

When the controller 574 starts the stop condition output process, the connection line SCL
Then, the processing is branched according to the signal level of the connection line SDA (4601).

When both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH, the controller 574 turns on the transistor 578b (FIG. 11 or FIG. 12) and sets the signal level of the connection line SCL to LOW. (4602). After the processing of step 4602 is completed, or when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, the transistor 578a (FIG. 11 or FIG. 12) is turned on to establish a connection. The signal level of the line SDA is set to LOW (4603).

The controller 574 executes an SCL release monitoring process for releasing the connection line SCL after the process of step 4603 is completed or when both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW. (4604).

In the SCL release monitoring process, the signal level of the connection line SCL that is at the LOW level is set to HIG.
This is a process of setting the state to H so that data can be transmitted and received. Details of the SCL release monitoring process will be described later with reference to FIG. When the SCL release monitoring process ends normally, the signal level of the connection line SCL is set to HIGH. Connection line SCL
If the signal level cannot be set to HIGH and the connection line SCL cannot be released, a transmission interruption interrupt is generated.

The controller 574 connects the connection line S after the processing of step 4604 is completed or when the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW.
The SDA release monitoring process for releasing the DA is executed (4605).

The SDA release monitoring process is a process of changing the signal level of the connection line SDA from LOW to HIGH. If the connection line SDA is occupied for some reason and the signal level remains LOW, it is occupied. A process of releasing the connection line SDA is included. Details of the SDA release monitoring process will be described later with reference to FIG. Note that when the SCL release monitoring process ends normally, the signal level of the connection line SDA is changed from LOW to HIGH, and at this time, the signal level of the connection line SCL is maintained at HIGH, so that the stop condition is established. To do. If the connection line SDA cannot be released, a transmission interruption interrupt is generated.

FIG. 47 is a flowchart illustrating a procedure of SCL release monitoring processing according to the embodiment of this invention.

When the SCL release monitoring process is started, the controller 574 causes the transistor 578b (
Turning off FIG. 11 or FIG. 12) releases the connection line SCL (4701). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SCL release the connection line SCL, the signal level of the connection line SCL is changed to HIGH. Subsequently, it is determined whether the signal level of the connection line SCL is changed to HIGH and the connection line SCL is released (4702).

When the signal level of the connection line SCL is HIGH, the controller 574 (
Since the result of 4702 is “Y”), the process is successful, and the process returns to the calling process. on the other hand,
When the signal level of the connection line SCL is not HIGH (the result of 4702 is “N”)
), It is determined whether or not the signal level of the connection line SCL becomes HIGH until a predetermined time elapses (4702).

The controller 574 indicates that the signal level of the connection line SCL remains HIGH even after a predetermined time has elapsed.
If it does not become (the result of 4703 is “Y”), “78H” indicating that the connection line SCL cannot be released is set in the status code (4704), and a transmission interruption interrupt is generated.

FIG. 48 is a flowchart illustrating a procedure of SDA release monitoring processing according to the embodiment of this invention.

When the signal level of the connection line SDA cannot be HIGH, that is, the connection line S
When DA is occupied, data cannot be output via the connection line SDA. Therefore, without applying an operable voltage to the transistor 578a by the driver 576a, the transistor 578a is not turned on (with the connection line SDA released).
Change the signal level of the connection SCL at least nine times.

By performing such processing, the I2CI is in the read mode (details will be described later).
The / O expander 615 outputs data to the connection line SDA in accordance with the change in the signal level of the connection SCL, but in the middle of the change in the signal level of the connection SCL at least nine times, the acknowledge signal from the master IC is output. Timing to check occurs. At this time, since the connection line SDA is released, it becomes HIGH level, and the I2C enters the read mode.
Since the I / O expander 615 determines that the acknowledge signal has not been received, the data transmission is stopped and the connection line SDA is released. RCVF is the 9 connection SCL
It is a flag indicating whether or not the signal level change has been executed.

In this way, the connection line SDA is forcibly released from the I2CI / O expander 615 that has entered the read mode, so that the signal level of the connection line SDA is maintained at HIGH. Hereinafter, the procedure of the SDA release monitoring process will be described.

First, the controller 574 sets RCVF to OFF (4801). Thereafter, the transistor 578a (FIG. 11 or FIG. 12) is turned off to release the connection line SDA (4
802). At this time, another IC (I / O expander 61) connected to the connection line SDA
5) etc. release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

The controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4803). If the signal level of the connection line SDA is HIGH (the result of 4803 is “Y”
) Since the connection line SDA can be released, the process returns to the calling process.

On the other hand, when the signal level of the connection line SDA is not HIGH, the controller 574 (
4803 is “N”), the signal level of the connection line SDA remains H until a predetermined time elapses.
It is determined whether or not the IGH is reached (4804). When a predetermined time elapses (the result of 4804 is “Y”), it is determined that the connection line SDA is in an occupied state, and processing for releasing the connection line SDA after step 4805 is executed.

First, the controller 574 sets 0 to the value of the variable LP indicating the number of times that a signal has been input to the connection line SCL (4805). Subsequently, the SCL release monitoring process described in FIG. 47 is executed (4806). Further, the connection line SC changed to HIGH by the SCL release monitoring process
The signal level of L is set to LOW by turning on the transistor 578a (480).
7). By the processing in steps 4806 and 4807, the signal level of the connection line SCL becomes LO.
It changes from W to HIGH, and further from HIGH to LOW. Further, by adding 1 to LP (4808), the number of signal level changes of the connection line SCL is counted.

The controller 574 determines whether or not the value of LP has reached 9, that is, whether or not the number of signal level changes of the connection line SCL has reached 9 (4809). If the LP value has not reached 9 (the result of 4809 is “N”), the processing from steps 4806 to 4808 is executed again.

When the value of LP reaches 9 (the result of 4809 is “Y”), the controller 574
Then, it is determined whether or not the signal level of the connection line SDA is HIGH (4810). Connection line S
If the DA signal level is not HIGH (the result of 4810 is “N”), it is determined whether or not the signal level of the connection line SDA has become HIGH until a predetermined time has elapsed (4811). . If the signal level of the connection line SDA is not set to HIGH even after the predetermined time has elapsed (the result of 4811 is “Y”), “7” indicating that the connection line SDA cannot be released.
0H "is set as the status code (4812), and a transmission interruption interrupt is generated.

On the other hand, when the signal level of the connection line SDA is set to HIGH (the result of 4810 is “Y”), the controller 574 turns on the transistor 578a to connect the connection line SDA.
Is set to LOW (4813), and SCL release monitoring processing is executed (4814).
). Further, the transistor 578a is turned off to release the connection line SDA (4815), and R
CVF is set to ON (4816).

Note that a mechanism for releasing the connection line SDA by changing the signal level of the connection line SCL nine times will be described in detail with reference to FIG.

FIG. 49 is a flowchart showing a procedure of start condition output processing according to the embodiment of the present invention.

The start condition is output by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. In the start condition output process, the process is executed according to the signal level of each connection line at the start of the process.

When the controller 574 starts the start condition output process, the connection line SCL
Then, the processing branches depending on the signal level of the connection line SDA (4901).

When the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the controller 574 turns on the transistor 578b (FIG. 11 or 12) and sets the signal level of the connection line SCL to LOW. (4902).

The controller 574 executes the SDA release monitoring process after the process of step 4902 is completed or when both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW (4903). Subsequently, it is determined whether or not the value of RCVF is ON (49
04). When the execution of the SDA release monitoring process is normally completed, the signal level of the connection line SDA becomes H
It is set to IGH.

If the RCVF value is not on (the result of 4904 is “N”), the controller 574
Alternatively, the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH.
In this case, the SCL release monitoring process is executed (4905). When the value of RCVF is on, the SCL release monitoring process has been executed (step 4814 in FIG. 48), and the connection line SCL
This is because the signal level is high.

When the RCVF value is ON (the result of 4904 is “Y”), or after the execution of the SCL release monitoring process in step 4905, the controller 574 outputs the start condition again (
“10H” indicating that the restart condition is completed is set in STCD (4
907).

When the signal level of the connection line SCL and the signal level of the connection line SDA are both HIGH, the controller 574 indicates “08H indicating that the start condition has been output.
"Is set to STCD (4906).

At the time when the processing of step 4906 or step 4907 is completed, the signal level of the connection line SCL and the signal level of the connection line SDA are both set to HIGH. Therefore, the controller 574 turns on the transistor 578a (FIG. 11 or FIG. 12) and sets the signal level of the connection line SDA to LOW (4908). By performing the processing in this way, the start condition is established because the signal level of the connection line SDA is changed from HIGH to LOW while the signal level of the connection line SCL is maintained at HIGH.

Subsequently, the controller 574 turns on the transistor 578b and sets the signal level of the connection line SCL to LOW (4909). Further, the FBF value is set to ON (4
910). The FBF is a flag indicating that the start condition has been established. For example, when data is transmitted after the start condition is established, if the FBF is ON, the slave address since it is the first transmitted data. Judge. And
By setting the FBF to OFF after receiving the address, each slave can recognize that the received data is effect control data.

FIG. 50 is a flowchart illustrating a procedure of data transmission processing to the slave-side I2CI / O expander 615 according to the embodiment of this invention.

First, the controller 574 initializes a variable CTR for storing the number of data transmissions to 0 (5001). Subsequently, the transistor 578b (FIG. 11 or FIG. 12) is turned on, the signal level of the connection line SCL is set to LOW (5002), and the transistor 578a (FIG. 11) is set.
Alternatively, FIG. 12) is turned off to release the connection line SDA (5003). At this time, the connection line S
If all other ICs (I / O expander 615, etc.) connected to DA release connection line SDA, the signal level of connection line SDA is changed to HIGH.

The controller 574 determines whether or not the signal level of the connection line SDA is HIGH (second level), that is, whether or not the connection line SDA is released (5004). When the signal level of the connection line SDA is not HIGH (the result of 5004 is “N”), the connection line S
Wait until the signal level of DA becomes HIGH. That is, the connection line SDA is at the LOW level (
1st level), it is determined that the state is occupied, and data transmission to the I / O expander 615 is restricted.

On the other hand, when the signal level of the connection line SDA is HIGH, the controller 574 (50
04 is “Y”), it is determined whether or not the value of the variable CTR is 8, that is, whether or not the number of data transmissions has reached 8 (5005).

If the number of data transmissions has not reached eight, the controller 574 (5005).
Is "N"), data is output to the slave via the connection line SDA, and 1 is added to CTR (5006). Subsequently, an SCL release monitoring process is executed (5007), and step 500 is executed.
Data is further output by executing the processing from step 2 onward.

On the other hand, when the number of data transmissions reaches eight (the result of 5005 is “Y”), the controller 574 outputs a response signal from the I2CI / O expander 615 on the slave side via the connection line SDA (5008). ).

The controller 574 fetches the output response signal from the connection line SDA (5009).
The SCL release monitoring process is executed (5010). Further, it is determined whether or not the content of the response signal fetched in step 5009 is “ACK” (5011).

When the content of the response signal from the slave is “ACK”, the controller 574 (50
11 is “Y”), the transistor 578b is turned on, the signal level of the connection line SCL is set to LOW (5012), and the connection line SDA is released by the slave (5013).
). Further, it is determined whether or not the current data transmission mode is the buffer mode (501).
4).

When the current data transmission mode is the buffer mode, the controller 574 (501)
If the result of 4 is “Y”), it is determined whether or not the transmission of the last byte is completed (5015). When transmission of the last byte is not completed and data is transmitted (the result of 5015 is “
N "), the value of FBF is set to OFF, and a variable CTR indicating the number of data transmissions is set to 0 (5016). As described above, the FBF is a flag indicating that the start condition has been established, and is set to OFF after the initial data transmission, thereby indicating that the transmission of the slave address has been completed. Can be handled. Thereafter, it waits until the signal level of the connection line SDA becomes HIGH (5004), and the next data is transmitted.

When the current data transmission mode is not the buffer mode, that is, in the byte mode (result of 5014 is “N”), or when the last byte transmission is completed (the result of 5015 is “Y ]), It is determined whether or not the FBF is set to ON (5017). When FBF is set to ON (the result of 5017 is “Y”
), The status code “1” indicating that the FBF is set to OFF and the address transmission is successful.
8H "is set in STCD (5018). On the other hand, when the FBF is not set to ON (result of 5017 is “N”), the status code “28H” indicating that the data transmission is successful is set in the STCD (5019).

In addition, the controller 574 determines that the response signal from the slave is “A”.
If it is not CK ”, that is, if it is“ NACK ”indicating that data could not be received (the result of 5011 is“ N ”), the transistor 578b is turned on and the connection line S
The CL signal level is set to LOW (5012).

Further, the controller 574 determines whether or not the FBF is set to ON (5
021). When the FBF is set to ON (the result of 5021 is “Y”), the status code 20H indicating that the address transmission has failed is set in the STCD (5022).
). On the other hand, if the FBF is not set to ON (the result of 5021 is “N”), the status code 30H indicating that the data transmission has failed is set in the STCD (5023).
). When the above process ends, the process returns to the caller process.

FIGS. 51 to 53 show the I2CI / O expander 6 on the slave side according to the embodiment of the present invention.
15 is a flowchart showing a processing procedure in FIG.

FIG. 51 is a flowchart illustrating a processing procedure in the slave-side I2CI / O expander 615 according to the embodiment of this invention.

The slave-side I2CI / O expander 615 executes various controls by the bus controller 634 as described with reference to FIG.

First, when a reset signal is generated by the reset signal generation circuit 639 (see FIG. 18, the same applies hereinafter), the bus controller 634 executes initialization processing of itself (I2CI / O expander 615) (5101). At this time, the transistor 63 is driven by the driver 632.
0 turns off and the connection line SDA is released. In addition, the driver 637 allows ports 0 to 1
All of the transistors 638A to 638P connected to 5 are turned off. Further, the output setting register 635 is set to a predetermined initial state. Next, the signal levels of the connection line SCL and the connection line SDA are captured. And it waits until it becomes the state 5103 in which the signal level of both the connection line SCL and the connection line SDA is HIGH (5102).

When the connection line SCL and the connection line SDA are in the state 5103, the bus controller 634 (
The result of 5102 is “Y”), and the process waits until the signal level of either the connection line SCL or the connection line SDA changes (5104).

When the signal level of the connection line SDA changes to LOW from the state 5103 (result of 5104 is “SDAＤＡ”), the bus controller 634 sets the variable CN to 0, sets the state number to 1, and sets the data Is cleared (5105). The variable CN is a counter indicating the number of times data has been received. Further, the state number is set according to a signal transmitted from the master, and corresponds to, for example, a process requested by the slave (write process, read process, etc.). Note that when the signal level of the connection line SDA changes from LOW in the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are both HIGH, this corresponds to the start condition being output from the master IC. 1 indicates that a start condition has been output.

At this time, the signal level of the connection line SCL is HIGH, and the signal level of the connection line SDA is LOW.
The state 5106 is as follows. The bus controller 634 waits until the signal level of the connection line SCL or the connection line SDA changes (5107).

When the signal level of the connection line SCL changes to LOW from the state 5106 (the result of 5107 is “SCL ▽”), the bus controller 634 receives the data eight times, that is, whether or not the variable CN has become 8. It is determined whether or not (5108). If the value of the variable CN is not 8 (the result of 5108 is “N”), at this stage, the connection line SCL and the connection line SDA
The state 5109 in which both signal levels are LOW. Thereafter, the process waits until the signal level of the connection line SCL or the connection line SDA changes (5110).

When the signal level of the connection line SDA changes to HIGH (result of 5110 is “SDAΔ”), the bus controller 634 determines that the signal level of the connection line SCL is LOW and the connection line SDA.
The state shifts to the state 5111 in which the signal level is HIGH, and waits until the signal level of the connection line SCL or the connection line SDA changes (5112).

When the signal level of the connection line SDA changes to LOW, the bus controller 634 (
When the result of 5112 is “SDA ▽”), the state 5109 is entered, and the connection line SCL or the connection line SD
Wait until the signal level of A changes (5110).

On the other hand, when the signal level of the connection line SCL changes to HIGH (the result of 5112 is “SCLΔ”), the bus controller 634 determines whether the state number is 1 or 2, that is, after the start condition is output. Or whether the requested process is a write request (5115).

When the state number is 1 or 2, the bus controller 634 (the result of 5115 is “
Y "), 1 is added to the value of the variable CN, and the data stored in the reception buffer is captured (511).
6). If the state number is not 1 or 2 (the result of 5115 is “N”), or step 511
When the processing of 6 is completed, the signal level of the connection line SCL and the connection line SDA is both HIGH 5103, and the process waits until the signal level of the connection line SCL or the connection line SDA changes (5104).

In the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are HIGH, the bus controller 634 changes the signal level of the connection line SCL to LOW (5104).
Is "SCL ▽"), it is determined whether or not the variable CN has become 8, that is, whether or not data has been received eight times (5117). When the value of the variable CN is not 8, (5117
Is "N"), the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH at this stage, and the processing after step 5112 is executed. On the other hand, when the value of the variable CN becomes 8 (the result of 5117 is “Y”), the processing after step 5201 shown in FIG. 52 is executed.

Further, the bus controller 634 has a signal level of the connection line SCL of HIGH and the connection line SD.
In the state 5106 where the signal level of A is LOW, the signal level of the connection line SDA is HI.
When the state changes to GH (result of 5107 is “SDAΔ”), it is determined whether or not the state number is 2, that is, the requested process is a read request (5118). Note that the change of the signal level of the connection line SDA from HIGH in the state 5106 in which the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW corresponds to the output of the stop condition.

If the state number is 2 (the result of 5118 is “Y”), the bus controller 634 is informed. The data stored in the preparation area is stored in the setting register (5119). When the state number is not 2 (the result of 5118 is “N”) or when the processing of step 5119 is completed, 0 is set to the state number (5120). At this time, since the signal levels of the connection line SCL and the connection line SDA are both HIGH 5103, the connection line SCL or the connection line SDA
Until the signal level changes (5104), and the processing is continued.

FIG. 52 is a flowchart illustrating a procedure such as address recognition processing in the slave-side I2CI / O expander 615 according to the embodiment of this invention.

Note that the I2CI / O expander 615 used in the present embodiment can be used regardless of whether the read mode can be generated or not. Therefore, any type of I2CI
The flowchart will be described assuming that the / O expander 615 is provided.

  Here, the reading mode will be described.

In this embodiment, each time a predetermined unit byte of data is transmitted from the master IC to the I2CI / O expander 615, a 1-bit response signal is received from the I2CI / O expander 615 to the master IC. Production control data is transmitted to the I2CI / O expander 615.

By the way, it may be convenient for some gaming machines to be configured to transmit data of a predetermined unit byte from the I2CI / O expander 615 to the master IC.
For example, the I2CI / O expander 615 may detect a detection state of various sensors related to a game and develop a gaming machine having specifications that can be transmitted to a master IC.

The I2CI / O expander 615 used in such a game machine generates a “read mode” inside the I2CI / O expander 615 in response to a request from the master IC.
A 1-bit response signal from the master IC to the I2CI / O expander 615 every time a predetermined unit byte of data is transmitted from the I2CI / O expander 615 to the master IC in response to the change in the SCL signal from the master IC. Is preferably configured to transmit.

Specifically, when the bit of the R / W identification data 2204 is “1” in the address data transmitted from the master IC to the I2CI / O expander 615 on the slave side, the read mode is generated. A request (hereinafter referred to as “read request”) is defined in advance.

When the signal level of the connection line SCL changes to LOW with the signal levels of the connection line SCL and the connection line SDA being HIGH (the result of 5104 in FIG. 51 is “SCL ▽”), the bus controller 634 When reception is completed 8 times, that is, when reception of data is completed (511
7 is “Y”), the connection line SDA is released on the master IC side (5201).

Subsequently, the bus controller 634 determines whether or not the state number is 1, that is, whether or not it is immediately after the start condition is output (5202). If the status number is 1 (the result of 5202 is “Y”), it is confirmed whether the received address matches the address assigned to itself (I2CI / O expander 615) (5203, 5
204).

If the received address does not match its own address (the result of 5204 is “N”
), The state number is set to 0 (5217), and the processing after step 5213 is executed. Here, the received address corresponds to the above-mentioned “read request”, and I2 for performing the processing.
Even when the CI / O expander 615 cannot generate the above-described read mode, the determination result in step 5204 is set to “N”.

On the other hand, if the received address matches its own address (the result of 5204 is “Y”), it is determined whether or not the requested process is a read request (5205). If the requested process is a read request (the result of 5205 is “Y”), the processes after step 5301 in FIG. 53 are executed.

On the other hand, if the requested process is not a read request, that is, if it is a write request (result of 5205 is “N”), the bus controller 634 sets 2 as the corresponding state number (5206).

Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting the occupation of the signal line. Further, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641 (5207). The self-occupied WDT 641 starts a timer when the bus controller 634 starts occupying the bus, and when a predetermined time elapses, the self-occupied WDT 641 itself (I2
CI / O expander 615) is reset. By processing in this way, even when the connection line SDA is continuously occupied, the occupation can be released by reset when the time set in the self-occupied WDT 641 has elapsed. At this time, the influence on others can be minimized by resetting only itself.

At this time, the signal levels of the connection line SCL and the connection line SDA are both LOW 52
Next, the bus controller 634 indicates that the signal level of the connection line SCL is H.
Wait until it changes to IGH (5209).

When the signal level of the connection line SCL changes to HIGH, the bus controller 634 (52
09 is “SCLΔ”), the signal level of the connection line SCL is HIGH, the signal level of the connection line SDA is LOW 5210, and the signal level of the connection line SCL is LOW.
Wait until it changes to W (5211).

When the signal level of the connection line SCL changes to LOW, the bus controller 634 (520
9 results in “SCL ▽”), the driver 632 is driven to turn off the transistor 630, thereby releasing the connection line SDA, stopping the self-occupied WDT 641, and the self-occupied WDT.
The bus monitoring by 641 is terminated (5212). And the value of variable CN is set to 0,
The reception buffer is cleared (5213). At this time, the signal level of the connection line SCL is LOW.
Since the signal level of the connection line SDA becomes HIGH and the state 5111 in FIG. 51 is obtained, FIG.
Step 1112 and the subsequent steps are executed.

If the status number is not 1 in the processing of step 5202 (result of 5202 is “N”), the bus controller 634 determines whether the reception is successful (5214, 5215).
. If the reception is successful (the result of 5215 is “Y”), the data in the reception buffer is stored in the preparation area (5216), and the processing after step 5207 is executed.

On the other hand, when the data reception has failed (the result of 5215 is “N”), the bus controller 634 sets the state number to 0 (5217), and executes the processing after step 5213.

FIG. 53 is a flowchart illustrating a procedure of data read processing in the slave-side I2CI / O expander 615 according to the embodiment of this invention.

If the processing requested from the master IC is a read request (the result of 5205 in FIG. 52 is “N”), the bus controller 634 sets the state number to 3 corresponding to the read processing (5301).

Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting the occupation of the signal line. Further, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641 (5302). At this time, the signal levels of the connection line SCL and the connection line SDA are both LOW, and the bus controller 634 receives the connection line S.
Wait until the CL signal level changes to HIGH (5304).

When the signal level of the connection line SCL changes to HIGH, the bus controller 634 (53
The result of 04 is “SCLΔ”), the state 5305 is entered, and further, the process waits until the signal level of the connection line SCL changes to LOW (5306).

When the signal level of the connection line SCL changes to LOW, the bus controller 634 (530)
6 results in “SCL ▽”), the driver 632 is driven to turn off the transistor 630, thereby releasing the connection line SDA and stopping the self-occupied WDT 641.
The bus monitoring by 641 is terminated (5307).

Further, the bus controller 634 sets the value of the variable CN to 0 (5308), and outputs data to the connection line SDA (5309). At this time, when a LOW level signal is output to the connection line SDA, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641. When a HIGH level signal is output to the connection line SDA, the self-occupied WDT 641 is not operated (5310). This is because the bus is not occupied if the signal level of the connection line SDA is HIGH.

At this time, the bus controller 634 waits until the signal level of the connection line SCL is LOW (5311) and the signal level of the connection line SCL changes to HIGH (5312).
). When the signal level of the connection line SCL changes to HIGH (the result of 5312 is “Y”), 1 is added to the value of the variable CN (5313). Then, the state 5314 in which the signal level of the connection line SCL is HIGH is entered, and the process waits until the signal level of the connection line SCL changes to LOW (5315). When the signal level of the connection line SCL changes to LOW (the result of 5315 is “SCL ▽”), when the bus is monitored by the self-occupied WDT 641, the self-occupied WDT 641 is stopped and the bus is monitored by the self-occupied WDT 641. Finish (531
6).

The bus controller 634 determines whether or not the value of the variable CN has reached 8, that is, the connection line S
It is determined whether or not all eight data have been output to DA (5317). If the output of all the data has not been completed (the result of 5317 is “N”), the next data is output to the connection line SDA (5318), and the processing after step 5310 is executed.

On the other hand, the bus controller 634 reaches the value of the variable CN, completes transmission of all data (the result of 5317 is “Y”), drives the driver 632, and turns off the transistor 630, thereby connecting the connection line. The SDA is released (5319). However, this step 531
The process 9 is necessary only when the bus controller 634 has set the connection line SDA to the LOW level. Therefore, when the bus controller 634 has set the connection line SDA to the HIGH level, it is necessary to execute it. There is no.

At this time, the signal level of the connection line SCL is LOW, and the signal level of the connection line SDA is HIGH.
Therefore, the process waits until the signal level of the connection line SCL becomes HIGH (5321).

At this time, 8-bit data has already been transmitted from the I2CI / O expander 615 to the master IC 570a (see FIG. 11 and the master IC 570b in FIG. 12). ACK from the master IC 570a (570b) to the I2CI / O expander 615
Response signal is transmitted.

When the signal level of the connection line SCL becomes HIGH, the bus controller 634 (
The result of 5321 is “SCLΔ”), and the signal level (response signal) of the connection line SDA is taken in (
5322). Then, it is determined whether or not the captured response signal is ACK (LOW level), that is, whether or not the master IC is ready to receive the next data (532).
3).

At this time, when the received response signal is ACK, the result of 5323 is “Y”.
The signal level of the connection line SCL is HIGH, the signal level of the connection line SDA is LOW (5324), and the bus controller 634 waits until the signal level of the connection line SCL changes to LOW (5325). When the signal level of the connection line SCL changes to LOW (53
The result of 25 is “SCL ▽”), the value of the variable CN is set to 0 (5326), and the processing after step 5318 is executed to output the next data.

On the other hand, when the captured response signal is NACK (the result of 5323 is “N”),
The bus controller 634 sets the variable CN to 0 and the state number to 0, and clears the reception buffer (5327). At this time, the signal levels of the connection line SCL and the connection line SDA are both HIGH, corresponding to the state 5103 in FIG. 51 and step 510 in FIG.
Step 4 is executed.

Next, the timing at which data is exchanged between the CPU 551 of the effect control device 550 and the first master IC 570a and the second master IC 570b in the embodiment of the present invention will be described.

FIG. 54 shows the CPU 551 of the effect control device 550 at the time of VDP interruption according to the embodiment of this invention.
5 is a timing chart showing a state in which processing by the first master IC 570a and the second master IC 570b is executed in parallel according to an instruction from.

In the embodiment of the present invention, when a VDP interrupt occurs at the timing of updating the image displayed on the display device 53, the CPU 551 of the effect control device 550 starts outputting effect control data to each master IC. When each master IC receives the effect control data from the CPU 551, the master IC performs processing such as transmitting the received effect control data to each slave independently of the other master ICs. When the output of the effect control data is completed for all the slaves, each master IC outputs a stop condition and updates the effect mode of the effect device (decoration device 620) controlled by each slave.

In this way, the processing by the first master IC 570a and the second master IC 570b is executed in parallel, and further, the effect that is harmonized with the image display is achieved by synchronizing the update timing of the effect mode of each effect device with VDP interrupt Can be performed.

More specifically, when a VDP interrupt occurs, the CPU 551 of the effect control device 550 executes a slave output start process (steps 3710 and 39 in FIG. 37) and outputs a start condition to each master IC. .

Then, CPU 551 edits output data to each device controlled by effect control device 550. Specifically, VDP output data editing for producing effects on the display device 53 (FIG. 3).
7, step 3711), speaker-related data editing for outputting sound from the speaker 30 (step 3712 in FIG. 37), and a decoration control device 61 that controls the LED as a rendering device.
Editing of the effect control data to be output to 0 (step 3713 in FIG. 37) and data editing for controlling a driving body such as a motor are performed. When a master interrupt to the CPU 551 is generated by each master IC during the execution of these editing processes, the edited effect control data is output to the output buffer 572 of each master IC by the effect control data transmission restart process (FIG. 43).
Is written to. Then, the effect control data is output to each slave by the data transmission process by the master shown in FIG.

Finally, when the production control data is transmitted to all the slaves to be transmitted, a stop condition is output from the master IC to the slave by the transmission restart process of the production control data (step S4311 in FIG. 43). The effect control data received by each slave is reflected in the effect mode of each effect device.

Thereafter, the CPU 551 waits until the next VDP interrupt occurs. And the next V
When a DP interrupt occurs, the above-described slave output start processing (steps 3710 and 39 in FIG. 37) is executed to output a start condition to each master IC, and thereafter the same processing is repeated.

  Next, a configuration example of the grouped effect device (decoration device 620) will be described.

FIG. 55 is a diagram showing an example of connection between the I2CI / O expander 615 of the decoration control device 610 and the decoration device 620 according to the embodiment of the present invention.
It is a figure which shows the structure controlled by 2CI / O expander 615. FIG.

As an example, the decoration device 620 includes LEDs (red (R), green (G)).
By controlling three blue (B) LEDs as one set, it is possible to emit light in various colors. For example, when all red, green, and blue LEDs are colored, white light can be emitted.

In the embodiment of the present invention, one I2CI / O expander 615 can control LEDs corresponding to 16 ports (PORT 0 to 15). It is possible to connect up to 5 sets.

However, in order to produce an effect that further enhances interest, there may be a case where an LED (production device) is connected to more than 16 ports. In FIG. 55, 5 sets or more (8 sets) of LEDs are
A configuration in which connection is controlled across two I2CI / O expanders 615 will be described.

As described above, the I2CI / O expander 615 has 16 ports (PORT 0 to 15).
) Is provided, it is possible to connect up to five sets of three-color LEDs. However, when the production is performed with 8 sets of LEDs as one group,
At least two I2CI / O expanders 615 are required.

Therefore, in the configuration shown in FIG. 55, one I2CI / O expander 615 controls the red and green LEDs of each set, and the other I2CI / O expander 615 (615b)
Each set of blue LEDs is configured to be controlled. And these two I2CI
/ O expander 615 is controlled as the same group, and, as will be described later with reference to FIG. 56, by receiving the stop condition output from the effect control device 550 and simultaneously executing the effect control, a plurality of I2CI / O expands. L controlled by panda 615
This makes it possible to produce an ED without any discomfort.

FIG. 56 is a diagram illustrating the timing at which the decoration control device 610 receives data and controls the effect device according to the embodiment of the present invention, and the case where the received data is reflected when the stop condition is output will be described. FIG.

In this figure, first, a start condition is output from the effect control device 550, then effect control data is sequentially output from the effect control device 550 to a plurality of I2CI / O expanders 615, and finally, the effect control device. A state in which a stop condition is output from 550 is shown. For convenience of explanation, the I2CI / O expander 615 of the decoration control device 610 is used.
Are provided, and each of the first I2CI / O expander to the fifth I2C
I / O expander.

Here, “data1” in the figure is the first I2 from the production control device 550.
The effect control data transmitted to the CI / O expander is shown, and hereinafter, “data2” to “d”
“ata5” is sent from the production control device 550 to the second I2CI / O expander to the fifth I2CI.
The presentation control data transmitted to each of the / O expanders.

Also, in the figure, “effect device (1)” indicates an LED or the like connected to the I / O port of the first I2CI / O expander. “Director (5)” is an I / O of the second I2CI / O expander to the fifth I2CI / O expander.
Each corresponds to an LED or the like connected to the port.

When the effect control data is transmitted from the effect control device 550 to each of the first I2CI / O expander to the fifth I2CI / O expander, the effect control device 550 is switched at the timing of switching the selection of the I2CI / O expander. Is outputting a start condition (functioning as a restart condition) to the I2CI / O expander. However, after the production control device 550 first outputs the start condition, the first I2CI /
Until the production control data is transmitted to all of the O expander to the fifth I2CI / O expander (the period indicated by T in the figure), the stop condition is not output, and the stop condition is output after the elapse of this period T. doing.

In the embodiment of the present invention, the production control data is serially transmitted from the connection line SDA, so that there is a time difference in the timing at which the production control data arrives for each I2CI / O expander. Each I2CI / O expander temporarily secures the received effect control data in a buffer (not shown) built in the bus controller 634 (FIG. 18) when receiving the effect control data from the effect control device 550. Only.

Here, each I2CI / O expander independently receives the effect control data and the LED
A case is assumed where processing that changes the light emission mode is performed. Since a time difference is caused in the change in the light emission mode of the LED, there is a possibility that an uncomfortable effect may be performed.

For example, red (R), green (G), and blue (B) LEDs have a plurality of I's as shown in FIG.
In the case of being connected across 2CI / O expanders, there is a possibility that the LED emits light in a color that misleads the player.

Specifically, the reliability notification device 15 (FIG. 2) described above is set so that the degree of expectation that is a big hit differs depending on the color of light emission, and if the reliability notification device 15 glows red, the big hit is determined. It is assumed that it is in the specification. And the case where the alerting | reporting operation | movement which makes the reliability alerting | reporting apparatus 15 light-emit in purple which does not become a big hit decision is assumed.

When performing such a notification operation, the red LE in the luminous body provided in the reliability notification device 15 is used.
Control is performed so that the D and the blue LED are turned on simultaneously and the luminous body emits purple light. However, as shown in FIG. 55, the L connected across a plurality of I2CI / O expanders is used.
Due to the time difference when the ED emits light, if there is a moment when only the red LED is lit, it may be misunderstood that the player is a big hit and there is a risk of trouble between the game store and the player.

Therefore, in the embodiment of the present invention, when the stop condition is received from the effect control device 550, the effect control data in the buffer is overwritten in the output setting register 635, and the storage contents of the output setting register 635 are stored in the output controller 636. By driver 637
The process of changing the light emission mode of the LED connected to the I2CI / O expander is performed.

Therefore, as shown in FIG. 56, at the time of stop condition output, the effect control data received by each I2CI / O expander can be simultaneously reflected in the output mode of each effect device, and an effect without a sense of incongruity can be performed. It becomes possible.

In the embodiment of the present invention, the timing at which the effect control data received by the I2CI / O expander is reflected in the output mode of each effect device is the time when the stop condition exemplified as the update command signal is received. The update command signal may be used. An update command signal that can be expressed by a signal change of the connection lines SDA and SCL even if it is transmitted in the middle of the transmission of the production control data, not limited to the one transmitted at the end of the production control data as in the stop condition If so, it is applicable.

FIG. 57 is a diagram illustrating a procedure for releasing a bus when the I2CI / O expander 615 occupies the bus in the embodiment of the present invention.

When a start condition is output from the master IC, the master IC
Data output to the 2CI / O expander 615 is started, and the STA (start flag) of the master IC is set to ON. Thereafter, the master IC sequentially transmits 8-bit data from B7 to B0 to the I2CI / O expander 615 while sequentially changing the signal level of the connection line SCL. At this time, the I2CI / O expander 615 on the slave side sequentially captures data corresponding to the change in the signal level of the connection line SCL.

When 8 bits (1 byte) of data, that is, 1 time of data is transmitted, the connection line SDA is released on the master IC side (step 5201 in FIG. 52). Connection line SD
When A is released, the signal level is set to HIGH. And it waits until a reply signal (ACK, NACK) is transmitted from the slave side.

The slave-side I2CI / O expander 615 sets the signal level of the connection line SDA to LOW.
The response signal (ACK) is output. After that, the master IC changes the signal level of the connection line SCL from LOW to HIGH and then changes from HIGH to LOW, and the slave-side I2CI / O expander 615 occupies the connection line SDA. (Corresponding to steps 5207 to 5212 in FIG. 52).

Referring to FIG. 57, when the seventh bit data is transmitted on the master IC side, it is recognized on the slave side that the signal level of the connection line SCL has changed due to noise or the like.
The 2CI / O expander 615 recognizes that the 8th bit of data has been transmitted. Therefore, the slave sets the signal level to LOW in order to output the response signal (ACK) and occupies the connection line SDA. In the embodiment of the present invention, the self-occupied WDT 6 is simultaneously used.
41 starts monitoring the occupation of the connection line SDA by the slave.

At this time, since the connection line SDA is occupied by the slave I2CI / O expander 615 and the signal level is LOW, the master IC cannot transmit data (B0) until it is changed to HIGH. ing. Further, since the slave I2CI / O expander 615 is on standby until the signal level of the connection line SCL changes, the slave I2CI / O expander 615 is on standby until the signal level of each other changes. End up. Therefore, in the embodiment of the present invention, as described above, the I2CI / O expander 6 on the slave side is used.
15 occupies the connection line SDA is monitored by the self-occupied WDT 641, so when a predetermined time has elapsed since the occupancy started, by resetting the slave I2CI / O expander 615 itself The connection line SDA is forcibly released.

When the connection line SDA is released, the master IC transmits the last data. At this time, the slave-side I2CI / O expander 615 transmits a response signal (NACK) indicating that data could not be received normally. As a result, the CPU 551 sends a retransmission request to the master IC.
Can re-send data and resume processing.

58, in the embodiment of the present invention, a state in which the connection line SDA is occupied for some reason occurs, and the I2CI / O expander 615 that detects the occupation of the connection line SDA resets itself to It is a figure explaining the procedure which tries to release | release.

FIG. 57 illustrates the case where the I2CI / O expander 615 occupying the connection line SDA releases the connection line SDA by resetting itself.
Monitors the entire bus and forcibly releases the bus when other slaves (such as other I2CI / O expanders 615 connected to the connection line SDA) do not release the bus because the connection line SDA is occupied The procedure to make is explained.

The monitoring by the bus monitoring WDT 640 starts when the signal level of the connection line SDA becomes LOW level and ends when the signal level of the connection line SDA becomes HIGH level. That is, when the signal level of the connection line SDA is continuously LOW, a command for outputting a reset signal is output from the bus monitoring WDT 640 to the reset signal generation circuit 639.

As described in FIG. 57, when the bus is occupied by the slave-side I2CI / O expander 615, input / output of signals between the master IC and the slave-side I2CI / O expander 615 is stopped and connected. The signal level of the line SDA does not change (becomes waiting until the signal level changes). Therefore, when the signal level of the connection line SDA does not change for a predetermined time, all the I2CI / O expanders 615 connected to the connection line SDA reset themselves by each determination, Release the bus.

Referring to FIG. 58, after data B1 is output from the master IC, the bus is occupied by another slave. In the case of FIG. 58, since the bus is not occupied by the own slave, the slave that is actually occupied cannot be specified. Therefore, each of the slaves (I2CI / O expander 615) connected to the connection line SDA releases the bus by resetting itself. (To be precise, I2C connected to the connection line SDA
Only the I / O expander 615 that has a function of resetting itself performs the reset process. As a result, the remaining data is transmitted from the master IC, a response signal (NACK) indicating that the reception has failed is output from the slave, and the data is retransmitted by responding, and the processing is continued.

FIG. 59 shows an I2CI / O expander 615 on the slave side in the embodiment of the present invention.
When the bus is occupied by I2CI on the slave side by a command from the master IC
It is a figure explaining the procedure in which / O expander 615 releases a bus | bath.

If the number of changes in the signal level of the connection line SCL differs between the master side and the slave side due to noise or the like, as described above, the connection line SDA becomes the slave side I2CI / O expander 615.
And the bus is not released.

Therefore, when a predetermined time or more elapses while the bus is occupied, the monitoring timer circuit 5
62 causes a timeout interrupt to occur in the CPU 551 (see FIGS. 10 and 41).
. At this time, the CPU 551 initializes the master IC by executing a soft reset. Each slave (I2CI / O expander 615 connected to the master IC)
) To output a stop condition and a start condition.

At this time, in the slave-side I2CI / O expander 615, first, stop condition output processing shown in FIG. 46 is executed. At this time, the connection line SCL and the connection line SD
Since both signal levels of A are LOW, SCL release processing is executed (46 in FIG. 46).
04, FIG. 47). Since the connection line SDA is occupied, the SCL release processing is executed normally, and the signal level of the connection line SCL is set to HIGH.

Subsequently, the process of step 4605 of FIG. 46 is executed, and the SDA release monitoring process (FIG. 48).
Is executed. In the SDA release monitoring process, the signal level of the connection line SDA is changed to HIGH in the process of step 4803. However, since it is occupied by the slave I2CI / O expander 615, it cannot be set to HIGH. Therefore, step 48
Processes after 05 are executed.

At this time, the master IC changes the signal level of the connection SCL at least nine times. By doing so, the I2CI / O expander 615 on the slave side changes the signal level of the connection SCL to HIG while the signal level of the connection SCL is changed at least nine times.
A change from H to LOW is detected, and the connection line SDA is released (corresponding to exiting the loop of steps 5208 to 5211 in FIG. 52).

Next, after confirming that the connection line SDA has been released, the master IC outputs a stop condition to the I2CI / O expander 615 on the slave side, then outputs a start condition, and performs data transmission again. .

FIG. 60 shows a command from the master IC when the read mode occurs in the slave I2CI / O expander 615 and the bus is occupied by an erroneous command from the master IC in the embodiment of the present invention. FIG. 6 is a diagram illustrating a procedure by which the slave-side I2CI / O expander 615 releases the bus.

In the present embodiment, the slave IC side I2CI / O expander 615 from the master IC is used.
On the other hand, it is not intended to transmit a command for generating the read mode, but it is assumed that the I2CI / O expander 615 makes a decision on its own and shifts to the read mode due to the influence of noise or the like. Give an explanation.

Even when the I2CI / O expander 615 is in the read mode, if a predetermined time or more elapses while the bus is occupied, a timeout interrupt is sent to the CPU 551 by the monitoring timer circuit 562 as in the case of the write request. (See FIGS. 10 and 41). At this time, as described in FIG. 58, the CPU 551 first initializes the master IC by executing a soft reset. And it tries to output a stop condition and a start condition to each slave (I2CI / O expander 615 connected to the master IC). At this time, as described above, the SDA release monitoring process (FIG. 48).
) Is executed.

When the SDA release monitoring process is executed and the signal level of the connection SCL is changed at least nine times, the I2CI / O expander 615 outputs data to the connection line SDA in accordance with the change of the signal level of the connection SCL. While the SCL signal level changes nine times, the timing for confirming the response signal (ACK) from the master IC occurs. At this time, since the connection SDA is left open on the master IC side, the slave side I2CI /
When the O expander 615 captures the signal level of the connection SDA, the O expander 615 recognizes that it has received a response signal of NACK that becomes HIGH level, determines that the subsequent data transmission should be stopped, and releases the connection line SDA. To do.

According to the embodiment of the present invention, each master IC (signal level control means) included in the effect control device 550 (group overall control means) is a decoration control device 610 (group unit control means).
Since the response signal is transmitted from the decoration control device 610 to the effect control device 550, it is possible to confirm whether or not the data transmission has been performed, thereby preventing malfunction.

Further, according to the embodiment of the present invention, the effect control device 550 transmits data to the decoration control device 610 via one data line (connection line SDA), and the decoration control device 610 transmits to the effect control device 550. Since the response signal is transmitted through the same data line, the wiring between the substrates can be reduced.

Furthermore, according to the embodiment of the present invention, a single data line is common to data transmission from the group overall control means to the group unit control means and response signal transmission from the group unit control means to the group overall control means. Since the data line is occupied by the group unit control unit and cannot be used because it is used, the initialization unit initializes the group unit control unit, thereby occupying the data line. Since the state can be canceled, communication can be prevented from being stopped.

Further, according to the embodiment of the present invention, the group unit control means that occupies the data line itself determines the occurrence of the communication stop state and initializes itself, thereby other group unit control means. The data line can be released without affecting the process.

Further, according to the embodiment of the present invention, when the occupation state of the data line is detected, all of the group unit control means connected to the data line initializes itself, thereby reliably connecting the data line. Can be released.

According to the embodiment of the present invention, a command for releasing a data line can be transmitted from the group overall control means. In addition, since the start timing and output end timing of the response signal are commanded from the group overall control means, the processing of the group unit control means is simplified. Then, after a response signal starts to be output, if a problem occurs such that an output end command does not arrive, the occupancy cancel command means cancels the problem and the communication can be restored to a normal state.

Furthermore, according to the embodiment of the present invention, the decoration control device 6 that can be connected to one master IC.
Even if there is an upper limit to the number of 10, by providing a plurality of master ICs in the effect control device 550, more decoration control devices 610 can be used.

In the embodiment of the present invention, the first master IC 570a (first signal level control means) controls the effect device provided in the game board 10, and the second master IC 570b (second signal level control means). Is configured to control the effect device provided in the front frame 3. Thus, when developing the front frame 3 and the game board 10 by making the effect device provided in the game board 10 and the effect device provided in the front frame 3 into different groups, the decoration control device. 610
Therefore, it is only necessary to consider the upper limit number for each group to be developed. Therefore, development efficiency can be improved by developing devices in parallel for each configuration.

Furthermore, according to the embodiment of the present invention, the master IC is selected by the CPU 551,
Since a plurality of decoration control devices 610 (I2CI / O expander 615) connected to the selected master IC are initialized together, the decoration control devices 610 are selected one by one and initialized. Compared with the method, high-speed initialization processing can be performed.

At this time, only the decoration control device 610 connected to the selected master IC is initialized,
Control that does not initialize the decoration control device 610 connected to another master IC that is not selected becomes possible.

Therefore, since only the decoration control device 610 belonging to the minimum necessary range can be initialized among all the decoration control devices 610 provided in the gaming machine, the decoration control device 610 is initialized and the effect device. The frequency at which the operation is interrupted can be reduced.

Further, according to the embodiment of the present invention, when all the master ICs are to be reset, a hard reset is performed. Therefore, compared with a case where each master IC is soft reset one by one. Initialization can be performed at high speed.

On the other hand, when a part of the master ICs is to be reset, the initialization is executed by a soft reset via the data bus. Therefore, it is complicated to input signals individually to the initialization signal input terminals of all the master ICs. It is sufficient to provide one port without requiring a simple circuit. In other words, all master ICs that are always executed at the time of startup can be reset at high speed, and only a part of master ICs that are executed only in an emergency can be reset with a simplified circuit. Therefore, this is particularly effective in a configuration with a large number of master ICs.

In addition, according to the embodiment of the present invention, since the processing by the master IC operates in parallel, high-speed processing is possible. Further, since the effect mode of the effect device is controlled to be synchronized with the screen update timing, the effect of light emission in harmony with the screen display becomes possible.

Furthermore, according to the embodiment of the present invention, the timing at which the captured data is reflected as the output mode of the effect device is determined by the signal level change (reception of the stop condition) of the timing signal line and the data line. A signal such as a conventional LAT signal becomes unnecessary. This eliminates the need for wiring for transmitting the LAT signal, and makes it possible to simplify the wiring.

Further, according to the embodiment of the present invention, it is possible to transmit individual effect control data to the plurality of decoration control devices 610 using the same signal line, and each effect device to be controlled. It is possible to simultaneously update the production mode.

Here, the master IC 570 used in the embodiment of the present invention can control a maximum of 14 I2CI / O expanders 615 per one. Therefore, 15 or more I
In order to control the 2CI / O expander 615, it is necessary to provide a plurality of master ICs. In the configuration described above (FIG. 10), two master ICs (a first master IC 570a and a second master IC 570b) are provided. .

In the modification shown below, when 15 or more I2CI / O expanders 615 are controlled, a connection line (for example, connection line SCL) connecting the master IC 570 and the I2CI / O expander 615 is branched. I2C with the same address as the number of branches
A configuration in which the I / O expander 615 can be arranged will be described. In such a configuration, 1
One master IC 570 can control 15 or more I2CI / O expanders 615.

FIG. 61 is a block diagram showing a configuration of an effect control device 550 according to the first modification of the embodiment of the present invention.

Compared to the block diagram shown in FIG. 10, the production control device 550 of the first modified example is the second
The master IC 570b is not provided, and the switch unit 567 for branching the connection line SCL and the connection line SDA is provided. The switch unit 567 includes a bus switch 567a and a bus switch 567b.

The bus switch 567a branches the connection line SCL and connects the connection terminal 90 for connection to the game board 10 or the connection terminal 92 for connection to the front frame 3 and the first master IC 570a. In addition, the bus switch 567b branches the connection line SDA and connects the connection terminal 90 for connection to the game board 10 or the connection terminal 92 for connection to the front frame 3, and the first master IC.
570a is connected.

The bus switch 567a and the bus switch 567b are configured by circuits using relay contacts, and are controlled by the CPU 551 so that the connection destination of the first master IC 570a is the same.

In the first modified example shown in FIG. 61, two transmission target groups, that is, a group on the game board side and a group on the front frame side, are branch destinations of the connection lines. The tip may be three or more. In this case, I2 arranged at the branch destination corresponding to the branch destination
CI / O expanders 615 are grouped. At this time, an importance level may be set for each transmission target group according to the type of production (for example, notification content), and the frequency at which a signal is transmitted may be changed according to the importance level. Detailed control can be performed by increasing the connection frequency for the transmission target group including the effect device that performs the effect with high importance.

FIG. 62 is a flowchart showing a processing procedure performed by the effect control device 550 according to the first modification of the embodiment of the present invention.

In the flowchart shown in FIG. 62, similar to the flowchart shown in FIG. 37, the process executed by the CPU 551 of the effect control device 550 and the process performed when the effect control device 550 is turned on and the process performed when a VDP interrupt occurs Is executed.

When the effect control device 550 is powered on, first, the effect control device 550 is step 62.
A synchronization signal (for example, a synchronization signal having a period of 33.3 ms seconds) synchronized with the image update period from the VDP 556 in the process of step 6209 is executed as the interrupt signal.
Wait until input to U551. Thereafter, every time a synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551 as an interrupt signal, the steps 6210 to 6 are performed.
The process 224 is repeatedly executed.

First, the effect control device 550 executes initialization processing including initialization of the RAM 553 of the effect control device 550 (6201). At this time, an initialization stage number relating to a first master IC 570a described later is set to “0”.

Then, the effect control device 550 inputs a reset pulse to the first master IC 570a via the output I / F 558a and the NOR gate circuit 561, and initializes the first master IC 570a in hardware (6202).

Subsequently, the effect control device 550 sets the bus switch 567a and the bus switch 567b so that the connection line SCL and the connection line SDA are connected to the front frame 3 (6203). And I2CI / O expander 6 of all the decoration control apparatuses 610 with which front frame 3 was equipped
1 to output initialization instruction data from the first master IC 570a.
Master IC 570a side slave initialization start processing is executed (6204). The details of the slave initialization start process are the same as those described with reference to FIG. Further, the effect control device 550 waits until the initialization stage number becomes “0” (6205).

Further, the effect control device 550 sets the bus switch 567a and the bus switch 567b so that the connection line SCL and the connection line SDA are connected to the game board 10 (6206).
Similarly to the processing in step 6204, the first master IC 570 is initialized in order to initialize the I2CI / O expander 615 of all the decoration control devices 610 provided in the game board 10.
First slave IC 570a side slave initialization start processing for outputting initialization instruction data from a is executed (6207). Further, it waits until the initialization stage number becomes “0” (6208).
).

When the initialization of all the slaves (I2CI / O expander 615) is completed, the production control device 550 permits the reception of the synchronization signal (VDP interrupt) synchronized with the image update cycle and the reception of the timer interrupt from the VDP 556. (6209).

When the VDP interrupt occurs or the initialization process ends, the effect control device 550 inverts the bus SW flag (6210). For example, the bus SW flag is set to ON when the first master IC 570a is connected to the game board side, and is set to OFF when the first master IC 570a is connected to the front frame side. In step 6210, the bus SW flag is switched from on to off or from off to on.

Furthermore, the effect control device 550 causes the bus switch 567 to correspond to the bus SW flag.
a and the bus switch 567b are switched (6211). Thus, by switching the bus switch 567a and the bus switch 567b each time a VDP interrupt occurs,
The effect device provided in the game board 10 and the effect device provided in the front frame 3 can be controlled alternately.

Subsequently, as described in FIG. 36, the effect control device 550 executes slave output data saving processing for saving the effect control data stored on the RAM 553 so as not to be overwritten (6212). As described above, the output data saved in the save area is set in the first master IC 570a at a predetermined timing.

Then, the effect control device 550 displays the image on the display device 53 in order to display the VDP 556.
Data serving as an instruction to display an image is output (6213). Furthermore, sound control data is output to the sound LSI 557 in order to output sound from the speaker 30 according to the gaming state.
The sound LSI 557 causes the speaker 30 to output sound based on the input sound control data (6214).

Next, the effect control device 550 executes a slave output start process for outputting effect control data from the first master IC 570a to the decoration control device 610 (6215). The decoration control device 610 controlled here is a light emission control slave that mainly controls light emitters such as LEDs. Details of the slave output start processing are as described in FIG.

When the slave output start process is completed, the effect control device 550 edits the next data output to the VDP 556 (6216), and further edits the sound control data output to the sound LSI 557 (6217).

Further, the effect control device 550 executes slave output data editing processing for editing the effect control data to be transmitted to the decoration control device 610 that controls the light emitter (6218). In the slave output data editing process, as described with reference to FIG. 36, the production control data of each slave is generated and stored in the output data preparation area secured on the RAM 553.

Next, the effect control device 550 refers to the abnormality determination table 3200 shown in FIG. 32 and executes an error determination process regarding the light emission control slave corresponding to the bus SW flag (6219).
). That is, the value of the error flag 3205 of the entry corresponding to the bus SW flag and corresponding to the light emission control slave connected to the game board 10 or the front frame 3 is referred to and it is determined whether or not the reset condition is satisfied. The details of the error determination process are as described in FIG.

The effect control device 550 determines whether or not the reset condition is satisfied based on the result of the error determination process in Step 6219 (6220). If it is determined that the reset condition is satisfied (the result of 6220 is “Y”), the first master IC 570a is initialized (
6221), the first master IC 570a side slave initialization start processing for simultaneously outputting the initialization instruction data to all the I2CI / O expanders 615 (decoration control device 610) corresponding to the bus SW flag is executed (6222). .

Thereafter, the effect control device 550 waits until data is transmitted to all the I2CI / O expanders 615 (decoration control device 610) corresponding to the bus SW flag (62).
23).

The effect control device 550 transmits data to all the I2CI / O expanders 615 (decoration control device 610) corresponding to the bus SW flag (the result of 6223 is “Y”).
), The bus switch 567 so that the connection line SCL and the connection line SDA are connected to the front frame side.
a and the bus switch 567b are set (6224).

Note that the reliability notification device 15 (see FIG. 2) provided in the game board 10 performs an effect corresponding to the result of the variable display game, and therefore is more than a group on the front frame side that does not include the reliability notification device 15. The group on the game board side including the reliability notification device 15 is considered to be more important.

As the reason, firstly, the reliability notification device 15 that notifies the possibility that a big hit will occur due to the variable display game is intended to cut off the player's interests when performing incorrect notification.
There is a premise that it can be regarded as a production device having an important function. for that reason,
A group on the gaming board side (notification target group) that includes the I2CI / O expander 615 that controls the reliability notification device 15 is a front surface that does not include the I2CI / O expander 615 that controls the reliability notification device 15. It becomes a group with higher importance than the group on the frame side (notification exclusion group).

After the series of effects processing is completed as in the process of step 6224, by setting the bus switch so that the connection line SCL and the connection line SDA are connected to the group side of the less important front frame, the noise is reduced. It is possible to prevent the production device having high importance from malfunctioning due to the occurrence. If there are three or more groups, it may be configured to branch to the group with the lowest importance in the processing of step 6224, or the group with the highest importance or higher than the predetermined threshold value. In such a case, it may be configured to branch to the least important group.

Here, the bus switch described in the first modification of the embodiment of the present invention is the connection line SCL.
The connection line SDA is branched, but only the connection line SCL may be branched. 63 and 64 show an example of a configuration for branching only the connection line SCL. 63 and 64 are diagrams showing the configuration in the vicinity of the bus switch, and other configurations not shown are the same as those in FIG.

FIG. 63 is a diagram illustrating the configuration of the switch unit of the effect control device 550 according to the second modification of the embodiment of the present invention.

The bus switch 568 is configured to branch only the connection line SCL. Therefore, the first master IC 570a transmits a timing signal to the game board 10 or the front frame 3 connected by the bus switch 568 via the connection line SCL.

On the other hand, the connection line SDA is connected to both the game board 10 and the front frame 3 without branching.
Therefore, the data transmitted from the first master IC 570a is the game board 10 and the front frame 3
Sent to both.

However, since the timing signal is transmitted only to one of the game board 10 or the front frame 3, the I2CI / O expander 615 (not shown) of the game board 10 or the front frame 3 that does not receive the timing signal.
The decoration control device 610) keeps the timing signal (SCL) at a high level,
A state in which the data signal (SDA) is alternately changing between the high level and the low level is detected.

Since this state indicates the start condition and the stop condition as described above, the I2CI / O expander 615 that does not receive the timing signal captures the transmitted data signal and changes the operation mode of the rendering device. There is no control. Therefore, even if the same address is assigned to the I2CI / O expander 615 on the game board side and the I2CI / O expander 615 on the front frame side, an unintended effect is not performed.

Thus, according to the second modification of the embodiment of the present invention, the circuit can be simplified by reducing the number of bus switches to one, and the cost can be reduced.

FIG. 64 is a diagram illustrating the configuration of the switch unit of the effect control device 550 according to the third modification of the embodiment of the present invention.

In the third modification of the embodiment of the present invention shown in FIG. 64, the switch unit 569 includes two transistors 569a and 569b. Transistor 569a and transistor 569b
A connection line SCL is connected to the drain of the. The game board side I2CI / O expander 615 is connected to the source of the transistor 569a, and the front frame side I2CI / O expander 615 is connected to the source of the transistor 569b.

In this configuration, when a predetermined voltage is applied to the gate of the transistor 569a or 569b, a timing signal output via the connection line SCL is transmitted to the I2CI / O expander 615 provided in the game board 10 or the front frame 3. Can be sent to.

Further, in such a configuration, a signal cannot be transmitted from the I2CI / O expander 615 on the game board side or the front frame side to the first master IC 570a, but the connection line SCL is unidirectional from the master side to the slave side. Since it is sufficient to transmit the timing signal, no adverse effects occur.

According to the third modification of the embodiment of the present invention, since the transistor is used as a switch for switching the connection destination of the connection line SCL, the control target can be switched at high speed.

Note that the switch for switching the connection destination of the connection line SCL may be a relay type shown in FIG. 61 or a transistor circuit other than the transistor circuit shown in FIG. Any device can be used as long as it can transmit a signal by selecting a transmission target group. For example, a general-purpose bus switch circuit that switches the branch destination of the bus used in the USB interface may be used.

The embodiment disclosed this time is illustrative in all points and is not restrictive.
The scope of the present invention is shown not by the above description of the invention but by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

Moreover, the following is mentioned as a typical thing of the viewpoint of this invention other than what was described in the claim.

(1) When the game ball passes through a predetermined start winning area provided in the game area, a variable display game that displays a plurality of identification information in a variable manner is executed, and a bonus is given to the player according to the result of the variable display game. In a gaming machine capable of generating a special game state to be granted, it corresponds to a game control means for comprehensively controlling a game in the game area, a plurality of effect devices for effecting a game, and a command from the game control means. And an effect control means for controlling the plurality of effect devices, each of the effect device systems being divided into a plurality of groups, and a group unit control means for controlling the effect devices belonging to the divided groups For each group, and the production control means is configured as a group overall control means for overall control of each of the group unit control means, and the group overall control. A timing signal line for transmitting a timing signal from the stage to the group unit control means, and a data line for transmitting a data signal from the group control unit to the group unit control means, thereby providing the group control unit and the group control unit. Data transmission is possible between each group unit control means, the group overall control means,
Address setting means for selecting a destination group unit control means from among the group unit control means to set an address, and the timing signal while setting the signal level of the data line to a signal level corresponding to transmission data By repeatedly changing the signal level of the line,
Transmitting means for transmitting data including the address to the group unit control means of the transmission destination;
The group unit control means is connected to the group overall control means in a form belonging to any of a plurality of transmission target groups, and the data transmitted from the transmission means indicates an address addressed to the group control means. Signal branching means for taking in the transmitted data and transmitting at least a signal of the timing signal line only to a part of transmission target groups between the group overall control means and the group unit control means is provided. A featured gaming machine.

According to the invention of (1), the same address can be set in different group unit control means by the signal branching means. Therefore, even if there is an upper limit on the number of addresses to be allocated, a larger number of group unit control means can be controlled.

(2) The gaming machine according to (1), wherein the data line is connected to all the group unit control means without being branched by the signal branching means.

According to the invention of (2), even when the same data signal is transmitted to the group unit control units having the same address via the data line, only the one group unit control unit has the timing signal line. Since the timing signal is transmitted via the signal, even if the signal branching means is simplified, it can be operated without any problem.

(3) The group unit control means includes a response signal output means for outputting the response signal to the group overall control means via the data line through which the transmission means has transmitted data, and the group overall control means. Comprises a response signal fetching means for fetching a response signal from the group unit control means, and a judgment means for judging success or failure of data transmission based on the fetched response signal, the signal branching means on the timing signal line The gaming machine according to (2), wherein the gaming machine is a unidirectional signal transmission means capable of communicating only in a direction in which data is transmitted from the group overall control means to the group unit control means.

According to the invention of (3), when each signal level control means included in the group overall control means transmits data to the group unit control means, a response signal is transmitted from the group unit control means to the group overall control means. It is possible to confirm whether or not data transmission has been performed, thereby preventing malfunction. In addition, the group overall control means transmits data to the group unit control means via a single data line, and a response signal is also sent from the group unit control means to the group overall control means via the same data line. Wiring between the substrates can be reduced. At this time, since the transmission direction of the timing signal line is unidirectional, the circuit can be realized with a simplified configuration, and the cost can be reduced. In addition, since the data line is bidirectional, a response signal sent from the group unit control means to the group overall control means is transmitted,
Confirmation of signal transmission is not hindered.

(4) a game board in which a game area in which a game is played by launching a game ball is formed, and a front frame to which the game board is detachably attached, and the plurality of transmission target groups include the game A first unit configured by the group unit control means for controlling the effect device provided on the board;
A group and a second group configured by the group unit control means for controlling the effect device provided in the front frame, and the signal branching means is either the first group or the second group. The gaming machine according to any one of (1) to (3), wherein a signal of the timing signal line is transmitted to either of them.

According to the invention of (4), the game board and the game frame (front frame) can be developed separately, and the development efficiency can be improved.

(5) The effect device includes a notification device indicating a possibility that a special game state may occur due to the variation display game, and each transmission target group includes a group unit control means for controlling the notification device. Including a notification target group and a notification exclusion group to which the group unit control means for controlling the notification device does not belong, and any one of the plurality of transmission target groups includes a signal of the timing signal line When the data transmission is not performed from the group overall control unit to the group unit control unit, the timing signal line is connected to the notification exclusion group among the plurality of transmission target groups. The gaming machine according to any one of (1) to (4), which is characterized.

According to the invention of (5), it is possible to prevent an important notification device from malfunctioning due to generation of noise or the like.

As described above, the present invention can be applied to a gaming machine in which an effect control device controls an effect device via a plurality of decoration control devices.

1 gaming machine 2 body frame (outer frame)
3 Front frame (game frame)
9a, 9b Decoration member 10 Game board 12 Auxiliary game device unit 13 First movable illumination 13a Illumination drive first motor (MOT)
14 2nd movable illumination 14a Illumination drive 2nd motor (MOT)
15 Reliability notification device 29 Abnormality notification LED
30 Speaker 45 Side lamp 51 Center case 53 Display device 58 Movable effect device 63 First effect unit 64 Second effect unit 70 First effect member 71 The accessory drive first motor (MOT)
80 2nd production member 81 Second article drive second motor (MOT)
500 Game control device 550 Production control device 570a First master IC
570b Second master IC
567, 569 Switch section 567a, 567b, 568 Bus switch 569a, 569b Transistor 581 Command register (REG)
582 Status register (REG)
583 Self-address setting register (REG)
600 Relay board 603 Empty terminal monitor 610 Decoration control device 615 I2CI / O expander 620 Decoration device 625 Decoration device board 640 Bus monitoring watchdog timer (WDT)
641 Self-occupied watchdog timer (WDT)
1600 Simple relay board 3200, 3300 Abnormality determination table

Claims (1)

Dividing a plurality of effect devices into a plurality of groups, each unit having a unit control means for controlling the effect device, and an overall control means for comprehensively controlling each of the unit control means,
Between the overall control means and the unit control means, a data line and a timing signal line are connected to enable data transmission from the overall control means to the unit control means,
The overall control means includes
Arithmetic processing means for performing arithmetic processing related to the control of the rendering device;
A signal level control unit connected to the unit control unit and controlling each signal level of the data line and the timing signal line with the unit control unit based on a command from the arithmetic processing unit; Comprising and including
The arithmetic processing by the arithmetic processing means and the control of each signal level by the signal level control means can be executed in parallel,
The data transmitted by the overall control unit includes presentation mode information that defines the output mode of the rendering device, and update regulation information that defines the timing at which the unit control unit updates the output mode of the rendering device,
The unit control means includes
As the starting address the predetermined address of the storage destination, stores the sent from the overall control unit data, has a function of sequentially updates the stored destination address each time it stores the data,
Update the output mode of the rendering device to the output mode defined by the rendering mode information at the timing defined in the update regulation information transmitted from the overall control means,
The signal level control means and the unit control means are:
A gaming machine comprising an initialization means for initializing itself when power supply is started.

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