JP5878950B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine comprising a plurality of group unit control means for controlling a production device divided into groups and a group overall control means for controlling a plurality of group unit control means. Regarding technology.

  As a gaming machine that can simplify the wiring between the sub-relay board and the illumination board, the top LED central board arranged in the center of the top illumination area is serially connected to the sub-relay board, and the top illumination A gaming machine having a configuration in which a top LED right substrate disposed on the right side of the region and a top LED left substrate disposed on the left side of the top illumination region are separated from the top LED central substrate and connected by wiring. . Thereby, the number of wirings from the sub relay board to the top illumination area can be reduced to simplify the wiring (for example, see Patent Document 1).

JP 2008-212271 A

  The gaming machine described in Patent Document 1 has a problem that the processing load of the CPU is heavy and high-speed control cannot be performed.

  An object of this invention is to provide the gaming machine which speeds up production control.

The present invention relates to a game control means for comprehensively controlling a game, a plurality of effect devices for effecting a game, and an effect control means for controlling the plurality of effect devices in response to a command from the game control means. Each group of the production device is divided into a plurality of groups, group unit control means for controlling the production devices belonging to the divided group is provided in each group, and the production control means is provided in the group. together they constitute a group supervisory controlling means for centrally controlling the respective unit control means, between the group supervisory controlling means and wherein each said group-unit control unit, and the timing signal line for transmitting a timing signal, data wherein said group supervisory controlling means by providing a data line for transmitting signals, a to enable data transmission between each group unit control means, the grayed The group control unit sequentially transmits the data to the group unit control unit by repeatedly changing the signal level of the timing signal line while setting the signal level of the data line to the signal level corresponding to the data to be transmitted. The transmission means is connected to the arithmetic processing means for performing arithmetic processing related to the control of the rendering device and the group unit control means, and based on a command from the arithmetic processing means, Signal level control means for controlling each signal level of the data lines and timing signal lines between the group unit control means, and the group overall control means transmits data to the group unit control means. Is control information related to the rendering mode of the rendering device, and the group unit control means determines the rendering mode of the rendering device. Reflection regulation information that defines the timing to be displayed is included, and the group unit control means is configured to input the initialization signal to an initialization signal input terminal provided separately from the data line, thereby causing the group unit control means to First initialization means for initializing, and second initialization means for initializing the group unit control means in response to receiving predetermined initialization instruction data from the group overall control means via the data line And at the timing specified in the reflection definition information transmitted from the group overall control means, the effect aspect of the effect device is reflected in the effect aspect corresponding to the control information, and the arithmetic processing by the arithmetic processing means And control of each signal level by the signal level control means can be executed in parallel.

  According to the present invention, since the arithmetic processing means and the signal level control means operate in parallel, high-speed processing is possible.

It is explanatory drawing of the game machine of embodiment of this invention. It is a front view of the game board of the embodiment of the present invention. It is a disassembled perspective view of the center case of embodiment of this invention. It is a figure which shows the state before the movable production apparatus of embodiment of this invention operate | moves. It is a figure which shows the state contact | abutted in the contact part as a result of the movable production | presentation apparatus of embodiment of this invention operating, and operating the 1st production unit and the 2nd production unit. It is a disassembled perspective view of the 1st effect member of embodiment of this invention. It is a disassembled perspective view of the 2nd production member of an embodiment of the invention. It is a figure explaining wiring of the game machine of an embodiment of the invention. It is a block diagram which shows the structure of the game machine of embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of embodiment of this invention. It is a block diagram showing a configuration of the first master IC provided in the effect control device of the embodiment of the present invention and the effect device provided in the game board. It is a block diagram which shows the structure of the production | presentation apparatus with which the 2nd master IC with which the presentation control apparatus of embodiment of this invention was equipped and the front frame was equipped. It is a figure which shows the structure of the game board of embodiment of this invention. It is a figure which shows the structure of the front frame of embodiment of this invention. It is a figure explaining the connection state of the relay control board and decoration control apparatus which are included in the production | presentation control apparatus of embodiment of this invention, and a game board. It is a figure explaining the connection state of the presentation control apparatus of embodiment of this invention, the simple relay board | substrate contained in a front frame, and a decoration control apparatus. It is a block diagram of the decoration control apparatus of embodiment of this invention. It is a block diagram showing the configuration of I ² CI / O expander of the embodiment of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the decoration device of the embodiment of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device of the embodiment of the present invention, and shows a case where a motor and a solenoid are controlled. It is a circuit diagram of the connection line regarding the input / output of the decoration control device (including the relay board and the simple relay board) of the embodiment of the present invention. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of embodiment of this invention. It is an explanatory view of I ² CI / O expander address table according to the embodiment of the present invention. It is a diagram for explaining an embodiment of a I ² CI / O Aix work register assigned to the output setting register provided in expander of the present invention. It is explanatory drawing of the start condition and stop condition which the master IC of embodiment of this invention outputs data via the connection line SDA and the connection line SCL. It is a timing chart which the decoration control apparatus into which the data output from the master IC of embodiment of this invention was input outputs a response signal. It is a timing chart of the signal level of the connection line SDA and the connection line SCL when the master IC of the embodiment of the present invention outputs effect control data. Data transmitted / received between the master IC and the I ² CI / O expander when the master IC according to the embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device. It is a figure explaining the format of. When the master IC according to the embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device, the effect transmitted / received between the master IC and the I ² CI / O expander It is the figure which applied the specific numerical value to control data. It is a figure explaining the order which transmits presentation control data of master IC of an embodiment of the invention. If the master IC of the embodiment of the present invention initializes the I ² CI / O expander, is a diagram illustrating the format of the initialization instruction data to be transmitted to the I ² CI / O expander from the master IC . It is a figure explaining the abnormality determination table of the 1st master IC of an embodiment of the invention. It is a figure explaining the abnormality determination table of the 2nd master IC of an embodiment of the invention. It is a figure explaining the information transmitted / received between CPU and master IC (1st master IC or 2nd master IC) at the time of initialization (reset) of each decoration control apparatus (slave) of embodiment of this invention. . The figure explaining the information transmitted / received between CPU and master IC (1st master IC or 2nd master IC), when transmitting presentation control data to each decoration control apparatus (slave) of embodiment of this invention. It is. It is a figure explaining the step which transmits production | presentation control data from the production | presentation control apparatus of embodiment of this invention to master IC (1st master IC or 2nd master IC). It is a flowchart which shows the procedure of the process by the presentation control apparatus of embodiment of this invention. It is a flowchart which shows the procedure of the 1st master IC side slave initialization start process and 2nd master IC side slave initialization start process of embodiment of this invention. It is a flowchart which shows the procedure of the slave output start process of embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of transmission interruption interrupt generation by the 1st master IC and 2nd master IC of embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the time-out interruption generation | occurrence | production by the 1st master IC and 2nd master IC of embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the initialization instruction | indication data of embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of presentation control data of embodiment of this invention. It is a figure which shows an example of the transmission process continuation determination table for determining continuation of the transmission restart process of the data of embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process by the master IC of embodiment of this invention. It is a flowchart which shows the procedure of the stop condition output process of embodiment of this invention. It is a flowchart which shows the procedure of the SCL release monitoring process of embodiment of this invention. It is a flowchart which shows the procedure of the SDA release monitoring process of embodiment of this invention. It is a flowchart which shows the procedure of the start condition output process of embodiment of this invention. It is a flowchart illustrating a procedure of data transmission processing to the I ² CI / O expander slave embodiment of the present invention. 6 is a flowchart showing a processing procedure when a reset signal is generated in the slave I ² CI / O expander according to the embodiment of the present invention. In I ² CI / O expander slave embodiment of the present invention is a flow chart showing a procedure such as address recognition. It is a flowchart illustrating the I ² CI / O Aix procedure of read processing of data in the expander of the slave side of the embodiment of the present invention. It is a timing chart which shows the state in which the process by 1st master IC and 2nd master IC is performed in parallel by the instruction | indication from an effect control apparatus at the time of VDP interruption of embodiment of this invention. It is a figure which shows the example of a connection of the decoration control apparatus and decoration apparatus in embodiment of this invention, and is a figure which shows the structure which controls LED for 8 sets by two decoration control apparatuses. It is a figure which shows the timing which the decoration control apparatus in embodiment of this invention receives data, and controls an effect | presentation apparatus, and is a figure explaining the case where the data received at the time of outputting a stop condition are reflected. It is a figure explaining the procedure which releases a bus | bath when the self slave occupies the bus | bath in embodiment of this invention. In the embodiment of the present invention, a state where the connection line SDA is occupied for some reason occurs, and the I ² CI / O expander that detects the occupation of the connection line SDA resets itself and releases the bus. It is a figure explaining the procedure which tries to do. When the bus by I ² CI / O expander slave in the embodiment of the present invention have been occupied, it provides instructions I ² CI / O expander slave releases the bus in response to a command from the master IC It is a figure to do. In the embodiment of the present invention, when a read mode occurs in the slave I ² CI / O expander due to an erroneous command from the master IC and the bus is occupied, It is a figure explaining the procedure which releases a bus | bath. It is a figure which shows an example of the lighting pattern table for storing the lighting pattern data of the decoration apparatus of the modification of embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of the modification of embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of time-out interruption generation | occurrence | production by the general purpose timer circuit of the modification of embodiment of this invention. It is a flowchart which shows the procedure of the slave output data edit process of the modification of embodiment of this invention. It is a figure explaining the execution timing of the master output process and slave output data edit process of embodiment and modification of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is an explanatory diagram of a gaming machine 1 according to an embodiment of the present invention.

  A front frame (game frame) 3 of the gaming machine 1 is assembled to the main body frame (outer frame) 2 via a hinge 4 so as to be openable and closable on the front surface of the gaming machine 1. A game board 10 (see FIG. 2) is accommodated on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 10 is attached to the front frame 3.

  Around the cover glass of the glass frame 18, decoration members 9 a and 9 b that emit decoration light are provided. The decoration members 9a and 9b are provided with a decoration device composed of a lamp, an LED, or the like. By causing the decoration device to emit light in a predetermined light emission mode, the decoration members 9a and 9b emit light in a predetermined light emission mode.

  Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 11 is provided above the glass frame 18.

  In the illumination unit 11, a first movable illumination 13 and a second movable illumination 14 are arranged on the left and right. The first movable illumination 13 and the second movable illumination 14 include an illumination drive first motor (MOT) 13a and an illumination drive second motor (MOT) 14a in addition to an illumination member such as an LED. It is controlled so as to operate according to the contents of the production.

  An abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided at the lower right of the lighting unit 11.

  The open / close panel 20 below the front frame 3 is provided with an upper plate for supplying a game ball to a ball hitting device (not shown), and the fixed panel 22 is provided with a lower plate 23 and an operation unit 24 of the ball hitting device. The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

  In addition, the upper edge portion of the upper plate 21 is provided with an effect button 17 for receiving an operation input from the player. When the player operates the effect button 17, the effect content of the special figure variation display game on the display device 53 (see FIG. 2) provided on the game board 10 is selected, and the special figure variation display game on the display device 53 is selected. In addition, it is possible to perform an effect in which the player's operation is intervened.

  The special figure variation display game is started when the launched game ball wins a start opening 36 (see FIG. 2) provided in the game board 10. In the special figure fluctuation display game, a plurality of pieces of identification information are variably displayed on the display device 53. Then, when the identification information that has been variably displayed is stopped and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (a state where a privilege is granted) Transition to a special gaming state.

  In the upper right portion of the upper plate 21, a ball lending button 26 that is operated when a player borrows a game ball and a discharge button 27 that is operated to discharge a prepaid card from a card unit (not shown) are provided. . Further, a balance display unit 28 for displaying the balance of the prepaid card is provided between the ball lending button 26 and the discharge button 27.

  FIG. 2 is a front view of the game board 10 according to the embodiment of the present invention.

  The gaming machine 1 shown in FIG. 1 fires a game ball in an internal game area 10a (bounces it) to play a game, and a game area 10a is provided on the back side of the cover glass of the glass frame 18. The game board 10 which comprises is installed.

  The game board 10 includes a flat game board main body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and has a game area 10a surrounded by a guide rail 32 on the front surface of the game board main body 10b. ing. A front component 33 is attached to the front surface of the game board main body 10 b and outside the guide rail 32. Then, a game ball (hit ball; game medium) is launched from the launching device into the game area 10a surrounded by the guide rail 32 to play a game.

A center case 51 that forms a window 52 serving as a display area for a special figure variation display game is attached to the approximate center of the game area 10a. Behind the window 52 formed in the center case 51, a display device 53 is arranged as an effect display device capable of executing an effect of a special figure variable display game that displays a plurality of identification information in a variable manner. The display device 53 includes, for example, a liquid crystal display, and is arranged so that a display portion 53 a whose display contents can be changed is visible from the front side of the game board 10 through the window portion 52 of the center case 51. Note that the display device 53 is not limited to a device including a liquid crystal display, and may include a display such as an EL or a CRT.

  In addition, a reliability notification device 15 that notifies the possibility of jackpot (reliability) is provided on the upper portion of the center case 51. The reliability notification device 15 includes LEDs of a plurality of colors (for example, LEDs of three colors of red, blue, and green) and is controlled to emit light in a color and manner according to the reliability.

  Further, a ball introduction path (warp flow path) 50 through which a game ball can flow down is provided on the left portion of the center case 51, and is opened with the entrance 50a open toward the game area 10a. The ball introduction path 50 communicates with the inside of the center case 51, and the game ball that has flowed from the inlet 50a passes through the back side of the center case 51 and is discharged onto the unit-side stage portion 49b. Further, the game ball that rolls on the unit-side stage portion 49b can flow down onto the base-side stage portion 49a disposed below the unit-side stage portion 49b.

  A plurality of ornaments 47 are arranged on the peripheral edge of the center case 51. A decorative lamp 48 is disposed at the lower left portion of the center case 51, and a plurality of decorative pieces 46 are disposed in an upper and lower movable state at the upper portion of the center case 51. The decoration tool 47, the decoration lamp 48, and the decoration piece 46 perform an effect operation according to a command from an effect control device 550 described later. The configuration of the center case 51 will be described in more detail with reference to FIG.

  Further, in the game area 10a, below the center case 51, a start opening 36 for starting a special figure changing display game that can receive (win) a game ball is arranged. Further, on the side of the center case 51 (on the left side), a general map start gate 34 for starting the general map change display game is arranged.

  Further, in the game area 10a, side lamps 45 that perform various decorative displays by light emission are arranged on the lower left and lower right of the center case 51. The side lamp 45 is provided with a general winning opening 44.

  Further, a big winning opening 42 is arranged below the start opening 36, and an out opening for collecting the game balls that have flowed down without winning at the lower edge of the gaming area 10a below the big winning opening 42. 43 is established. The special winning opening 42 includes an attacker-type opening / closing door 42a that can be opened by rotating in a direction in which the upper end side is tilted to the near side. The state of the open / close door 42a is changed from a closed state (a disadvantageous state for the player) to an open state (a state advantageous for the player) according to the result of the special figure variation display game.

  In addition, in the game area 10a excluding attachment portions such as the center case 51, the start port 36, the side lamp 45, etc., there are a windmill (not shown) as a hitting direction changing member, and many No. nails (not shown) are provided. A vertically arcuate game ball passage 57 is formed between the center case 51 and the front structural member 33 located on the opposite side of the normal start gate 34 with the center case 51 interposed therebetween.

  Further, the game board 10 is provided with a special figure / special figure display 35 for executing a special figure change display game and a normal figure change display game. The general-purpose / special-figure display 35 displays the number of unprocessed times (special figure start memory number) of the special-figure display game and the unprocessed number of general-purpose variable display games (number of general figure start memory). The general-purpose / special-purpose display 35 is provided as a segment LED together with a game state display LED (not shown) representing a game state.

  A gate SW 34a (see FIG. 9) for detecting a game ball that has passed through the general chart start gate 34 is provided in the general chart start gate 34. Then, when the game ball that has been driven into the game area 10a passes through the normal figure start gate 34, the normal figure change display game is started.

  In addition, when the game ball passes through the general chart start gate 34 in a state where the normal map variable display game cannot be started, if the general chart start memory number is less than the upper limit number, the general chart start memory number is incremented by one, One random number indicating whether or not the normal figure change display game is won is stored as a normal figure start memory.

  The state in which the general map change display game cannot be started is, for example, a state in which the general map change display game has already been performed and the normal map change display game has not been completed, Is the state that has been converted to the open state.

  It should be noted that the universal map change display game may display the universal map change display game in a part of the display area of the display device 53. In this case, for example, numbers, symbols, character designs, etc. are used as identification symbols. This identification symbol is displayed by variably displaying for a predetermined time and then stopped and displayed.

  When the stop display of the normal map change display game becomes a special result mode, the opening / closing member 36a of the start port 36 is opened for a predetermined time (for example, 0.5 seconds) as a win for the normal map change display game. Is done. Thereby, it becomes easy to win a game ball in the start opening 36, and the special figure variation display game can be started easily. The opening / closing member 36a of the start port 36 normally maintains a closed state (a disadvantageous state for the player) with an interval of about the diameter of the game ball. When the stop display mode is entered (when the normal-game fluctuation display game is won), the game ball is opened in the reverse “C” shape by the solenoid (Fuden SOL 36b, see FIG. 9), and the game ball is placed at the start port 36. It is changed to a state that is easy to flow in (a state that is advantageous to the player).

  In addition, the gaming machine 1 according to the embodiment of the present invention, based on the result form of the special figure fluctuation display game, as a gaming state, the time-short operation state (in which the fluctuation display time of the special figure fluctuation display game on the display device 53 is shortened ( 2nd operation state) can be generated. The short-time operation state (second operation state) is a state in which the opening / closing member 36a of the start port 36 is likely to be open compared to the normal operation state (first operation state).

  In the short-time operation state, the execution time of the normal variation display game is controlled to be shorter than the execution time in the normal operation state (for example, 10 seconds is 1 second), and the number of opening of the start port 36 per unit time is It is controlled to increase substantially. Further, in the short-time operation state, when the start port 36 is opened due to the winning of the normal fluctuation display game, the opening time is controlled to be longer than the opening time of the normal operation state (for example, 0 3 seconds is 1.8 seconds). Further, in the short-time operation state, the start port 36 is opened a plurality of times (for example, two times) instead of once for the one-time winning result of the normal map display game. Further, in the short-time operation state, control is performed so that the probability of winning the normal-variation display game is higher than that in the normal operation state. That is, the number of times of opening of the start port 36 is increased as compared with the normal operation state, and it becomes easy to win a game ball in the start port 36, and the special figure variation display game can be started easily.

  In addition, a start port SW 36 d (see FIG. 9) for detecting a game ball that has passed through the start port 36 is provided inside the start port 36. When a game ball is detected by the start port SW36d, a start right for starting a special figure variation display game as an auxiliary game is generated. At this time, the right to start the special figure variation display game is stored as a special figure start memory within a predetermined upper limit number (for example, 4).

  When the special figure fluctuation display game cannot be started immediately, for example, when the special figure fluctuation display game has already been performed and the special figure fluctuation display game has not been completed, or when the special game state has been entered, the start port 36 When the game ball wins, if the special figure start memory number is less than the upper limit number (for example, less than 4), the special figure start memory number is incremented by 1 and extracted at the timing when the game ball wins the start opening 36. One random number is stored as a special figure start memory. When the special figure fluctuation display game is ready to start, the special figure fluctuation display game is started based on the special figure start memory.

  The special figure variation display game as an auxiliary game is executed by the general figure / special figure display device 35 provided on the game board 10, and after a plurality of identification information is variably displayed, a predetermined result mode is stopped and displayed. Done. Further, a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) are displayed in a variable manner on the display device 53 in correspondence with the special figure fluctuation display game. And as a result of the special figure variation display game, when the display mode of the general figure / special map display 35 becomes a special result mode, it becomes a big win and becomes a special game state (so-called big hit state). Correspondingly, the display mode of the display device 53 is also a special result mode (for example, any one of the numbers in the flat order such as “7, 7, 7”). In addition, you may comprise so that a special figure fluctuation display game may be performed only with the display apparatus 53 instead of the general figure and special figure display 35. FIG.

  Further, the gaming machine 1 according to the embodiment of the present invention can generate a probability variation state (second probability state) as a gaming state based on the result mode of the special figure variation display game. This probability variation state (second probability state) is a state in which the probability of a hit result in the special figure variation display game is higher than the normal probability state (first probability state). Note that the probability variation state and the above-described short-time operation state can be generated independently, and both can be generated at the same time, or only one of them can be generated.

  FIG. 3 is an exploded perspective view of the center case 51 according to the embodiment of the present invention.

  The center case 51 includes a frame decoration portion 65 disposed as a front surface configuration portion on the front surface side of the game board main body 10b (game board 10), and a frame base portion 60 disposed as a back surface configuration portion on the back surface side of the game board main body 10b. And are polymerized before and after. The frame decoration portion 65 includes an annular decoration base 66 that is fixed to the surface of the game board main body 10b. On the back side of the decoration base 66, there is provided a decoration panel unit 67 that is substantially the same size as the decoration base 66 and formed in a circular shape, and the frame decoration portion 65 superimposes the decoration base 66 and the decoration panel unit 67 back and forth. Configured.

  Under the decoration base 66, a base side stage portion 49a capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface, and a decoration lamp is provided between the base side stage portion 49a and the game ball passage 57. 48 is arranged (see FIG. 2). A ball introduction path (warp flow path) 50 through which a game ball can flow down is provided on the opposite side of the decoration lamp 48 across the base side stage portion 49a, and the entrance 50a of the ball introduction path 50 is connected to the decoration base 66. The outlet 50b of the ball introduction path 50 is communicated with the back side of the decorative panel unit 67 described later.

  The decorative panel unit 67 includes a cover panel portion 69 formed of a substantially circular transparent resin plate, and a plurality of decorative tools 47 are arranged on the peripheral edge of the front side of the cover panel portion 69. When the decorative panel unit 67 and the frame decorative portion 65 are overlapped, the decorative tool 47 is set so as to be arranged along the inner peripheral edge of the decorative base 66 (see FIG. 2). In addition, a reliability notification device 15 is disposed on the upper portion of the cover panel unit 69.

In addition, a unit-side stage portion 49b capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface at the lower portion on the back side of the cover panel portion 69. The unit side stage portion 49b is disposed above the base side stage portion 49a of the decorative base 66.

  Further, a sphere inlet 68 is opened at a location where the cover panel 69 overlaps with the outlet 50 b of the sphere introduction path 50, and the sphere introduction path 50 and the unit side stage portion 49 b communicate with each other via the sphere inlet 68. doing. Therefore, when a game ball flowing down the game area 10a flows into the ball introduction path 50, the ball introduction path 50 is configured so that the game ball can be introduced onto the unit side stage portion 49b.

  The frame base 60 includes a frame-like base case 61 that is fixed to the back side of the game board 10 in a state where the front side is open, and is opened inside the base case 61 (in other words, inside the center case 51). The part 62a forms a concave chamber 62 provided on the front side.

  In addition, a rectangular window 52 is opened in the front-rear direction behind the concave chamber 62 in the base case 61, and a display device 53 is attached from the rear of the base case 61 to display the display portion of the display device 53. 53 a faces the front of the center case 51 through the window 52 and the recessed chamber 62.

  Further, a plurality of decorative pieces 46 that can be moved up and down by an accessory driving solenoid (not shown) are disposed on the front side of the upper edge of the window 52, and display portions are provided on the left and right edges of the window 52. A movable effect device 58 that moves forward 53a and performs an effect operation is provided.

  Then, when the frame decoration portion 65 is overlapped in front of the frame base portion 60, the opening 62a and the window portion 52 of the concave chamber 62 are covered with the cover panel portion 69 from the front, and the display portion 53a of the display device 53 is covered with the frame decoration portion. It is configured to face the front of the center case 51 from the inside of 65 (where the cover panel portion 69 is exposed).

  4 and 5 are diagrams illustrating the configuration of the movable effect device 58 according to the embodiment of the present invention.

  The movable effect device 58 is configured by providing the first effect unit 63 and the second effect unit 64 at positions separated from each other, and the first effect unit 63 and the second effect unit 64 are operated in conjunction with each other. .

  FIG. 4 is a diagram illustrating a state before the movable effect device 58 is operated, and FIG. 5 is a result of the movable effect device 58 being operated and the first effect unit 63 and the second effect unit 64 being operated. It is a figure which shows the state contact | abutted in a part (1st contact part 121 and 2nd contact part 122).

  The first effect unit 63 is disposed on the left side of the center case 51, that is, on the left side of the peripheral edge of the window portion 52 of the base case 61. Further, the second effect unit 64 is disposed on the right side of the center case 51. When viewed from the front of the center case 51, the concave chamber 62 and the window 52 are arranged so as to face between the first effect unit 63 and the second effect unit 64.

  The first effect unit 63 includes a first effect member 70 that can move forward of the display unit 53a, and an accessory driving first motor (MOT) that serves as a first effect drive source that generates the driving force of the first effect member 70. ) 71 and a first effect transmission mechanism (a first main arm member 73 and a first sub arm member 74) that transmits the driving force (rotational power) generated from the accessory driving first MOT 71 to the first effect member 70. .

  Further, an output shaft (first output shaft) 71a of the accessory driving first MOT 71 extends in the front-rear direction of the center case 51, and a first drive gear 76 is rotatably mounted on the first output shaft 71a. Yes.

The first main arm member 73 is formed with a first main arm gear 77 that meshes with the first drive gear 76, and is pivotally mounted above the first drive gear 76. The first sub arm member 74 is formed with a first sub arm gear 78 that meshes with the first drive gear 76, and is pivotally attached to the lower side of the first drive gear 76. The first main arm member 73 and the first sub arm member 74 are axially attached to the first effect member 70 at positions where the end portions opposite to the end portions axially attached to the base case 61 are different from each other. 70 is supported.

  When the first effect unit 63 drives the accessory driving first MOT 71 and rotates the first driving gear 76 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving first MOT 71 is generated. The first main arm member 73 is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 is rotated counterclockwise when viewed from the front of the center case 51 by this driving force. To do. The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same counterclockwise direction as the arm member 73. As a result, the first effect member 70 rises while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended upward by the driving force of the accessory driving first MOT 71 and set in the vertical posture, as shown in FIG. The first effect stop state is set to be deviated from the front of the display portion 53a, and the first effect member 70 is located on the side of the window portion 52 and is hidden behind the frame decoration portion 65 and behind the game board main body 10b. (See FIG. 2).

  On the other hand, when the first driving gear MOT 71 is driven from the first effect stop state and the first driving gear 76 is rotated counterclockwise when viewed from the front of the center case 51, the driving force (rotational power) of the first driving gear MOT 71 is rotated. ) Is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 rotates clockwise as viewed from the front of the center case 51 by this drive force. Move.

  The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same clockwise direction as the arm member 73. As a result, the first effect member 70 is lowered while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended to the front of the display unit 53a and set in the horizontal posture by the driving force of the accessory driving first MOT 71, as shown in FIG. The first effect execution state is reached in which the member 70 is positioned in front of the display unit 53a, and the first effect member 70 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  The second effect unit 64 includes a second effect member 80 that can move to the front of the display unit 53a, and an accessory driving second motor (MOT) as a second effect drive source that generates the drive force of the second effect member 80. ) 81 and a second effect transmission mechanism (second main arm member 83 and second sub arm member 84) that transmits the driving force (rotation power) generated from the accessory driving second MOT 81 to the second effect member 80. .

  Further, the accessory driving second MOT 81 has an output shaft (second output shaft) 81a extending in the front-rear direction of the center case 51, and a second drive gear 86 is pivotally attached to the second output shaft 81a so as to be able to rotate together. Yes.

The second main arm member 83 is formed with a second main arm gear 87 that meshes with the second drive gear 86, and is pivotally attached to a position closer to the first effect unit 63 than the second drive gear 86. The second sub arm member 84 is formed with a second sub arm gear 88 that meshes with the second drive gear 86, and is pivotally attached to the lower side of the second drive gear 86. The second main arm member 83 and the second sub arm member 84 are pivotally attached to the second effect member 80 at positions where the end portions opposite to the end portions that are axially attached to the base case 61 are different from each other. 80 is supported.

  When the second effect unit 64 drives the accessory driving second MOT 81 and rotates the second driving gear 86 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving second MOT 81 is generated. This is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates counterclockwise when viewed from the front of the center case 51 by this driving force. To do. Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same counterclockwise direction as the arm member 83. As a result, the second effect member 80 is lowered while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, the second main arm member 83 and the second sub arm member 84 are rotated by the driving force of the accessory driving second MOT 81 to cause the second effect member 80 to reach the bottom dead center, and then the second main arm member 83 and When the second sub-arm member 84 is rotated to extend obliquely downward and set in a vertical posture and the second effect member 80 is slightly raised from the bottom dead center, as shown in FIG. The second effect stop state is reached in which the member 80 is positioned away from the front of the display unit 53a, and the second effect member 80 is hidden behind the frame decoration part 65 and behind the game board main body 10b (see FIG. 2).

  On the other hand, when the accessory driving second MOT 81 is driven from the second effect stop state and the second driving gear 86 is rotated counterclockwise as viewed from the front of the center case 51, the driving force (rotational power) of the accessory driving second MOT 81 is rotated. ) Is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates clockwise as viewed from the front of the center case 51 by this driving force. Move.

  Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same clockwise direction as the arm member 83. As a result, the second effect member 80 rises while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, when the second main arm member 83 and the second sub arm member 84 are extended to the front of the display unit 53a and set in the horizontal posture by the driving force of the accessory driving second MOT 81, as shown in FIG. The second effect execution state in which the member 80 is positioned in front of the display unit 53a is entered, and the second effect member 80 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  FIG. 6 is an exploded perspective view of the first effect member 70 according to the embodiment of the present invention.

  The first effect member 70 is a substantially semicircular member when viewed from the front of the center case 51, and is set in a posture in which an arc surface is disposed on the first effect unit 63 side.

  The first effect member 70 is provided with a first effect base 100 serving as a base. The first effect base 100 is formed of a transparent resin. Formed on the upper part of the first effect base 100 is a first main arm shaft attachment portion 101 for axially attaching the first main arm member 73 from the front of the first effect base 100, and on the lower part of the first effect base 100, A first sub-arm shaft attachment portion 102 for attaching the first sub-arm member 74 from the rear of the first effect base 100 is formed.

A first light diffusion sheet 103 that can transmit light while diffusing light is superposed on the front surface of the first effect base 100. Furthermore, the transparent first protective panel 104 is polymerized on the front surface of the first light diffusing sheet 103 to prevent the first light diffusing sheet 103 from falling off the first effect member 70.

  Further, the rear portion of the first production base 100 is recessed forward to form a first substrate storage space portion 105, and a light emitting device such as an LED (decoration device 620, see FIG. 17) is formed in the first substrate storage space portion 105. The mounted first light emitting substrate 106 is accommodated. Further, in this state, the first substrate housing space portion 105 is closed with the first base lid portion 107 to prevent the first light emitting substrate 106 from falling off the first effect member 70.

  Then, when light is generated from the light emitting device of the first light emitting substrate 106, the light passes through the first effect base 100, the first light diffusion sheet 103, and the first protective panel 104 and is irradiated to the front of the center case 51. It is configured as follows.

  Further, a first effect magnet holder 124 whose rear part is opened is formed on the first substrate housing space 105 side of the first contact part 121 so as to be recessed. The first effect magnet holder 124 has a first magnet 125 made of a button-shaped permanent magnet in a posture in which the magnetic pole faces the second effect member 80 side, and the first magnet 125 is connected to the first contact portion 121 (first effect). The magnet holder 124) is stored so as not to fall off.

The first light emitting substrate 106 is equipped with an I ² CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and a control signal (electric signal) output from the effect control device 550, etc. A data line and a clock line (signal line) for transmission are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 108.

  FIG. 7 is an exploded perspective view of the second effect member 80 according to the embodiment of the present invention.

  The second effect member 80 has a substantially parallelogram shape with a cutout portion at the top when viewed from the front of the center case 51. In the second effect stop state, the upper and lower side surfaces of the second effect member 80 are inclined downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 4), and in the second effect execution state, The left and right side surfaces of the second effect member 80 are set in a posture to incline downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 5).

  The second effect member 80 includes a second effect base 110 that serves as a base. The second effect base 110 is formed of a transparent resin. In the upper part of the second effect base 110, a second main arm axis attaching part 111 for axially attaching the second main arm member 83 from the front of the second effect base 110 is formed, and in the lower part of the second effect base 110, A second sub-arm shaft attachment portion 112 is formed to attach the second sub-arm member 84 from the rear of the second effect base 110.

  Further, a second light diffusing sheet 113 that can transmit light while diffusing light is superposed on the front surface of the second effect base 110. By superposing the transparent second protective panel 114 on the front surface of the second light diffusing sheet 113, the second light diffusing sheet 113 is prevented from falling off the second effect member 80.

  In addition, the rear portion of the second effect base 110 is recessed forward to form a second substrate storage space 115, and a light emitting device (decoration device 620) such as an LED is mounted in the second substrate storage space 115. The second light emitting substrate 116 is accommodated, and in this state, the second substrate accommodating space 115 is closed by the second base lid portion 117 to prevent the second light emitting substrate 116 from dropping from the second effect member 80. .

  Then, when light is generated from the light emitting device of the second light emitting substrate 116, the light passes through the second effect base 110, the second light diffusion sheet 113, and the second protection panel 114 and is irradiated to the front of the center case 51. It is configured as follows.

  Further, a second effect magnet holder 128 having an open rear portion is formed on the second substrate housing space 115 side of the second contact portion 122 so as to be recessed. In the second effect magnet holder 128, a second magnet 129 made of a button-shaped permanent magnet is stored at a position symmetrical to the first magnet 125 across the first contact portion 121 and the second contact portion 122. Has been.

Similarly to the first light-emitting substrate 106, the second light-emitting substrate 116 is equipped with an I ² CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620.
A data line and a clock line (signal line) for transmitting a control signal output from 50 are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 118.

  The movable effect device 58 includes the first contact member 121 on the first effect member 70 and the second contact member 122 on the second effect member 80. When the first effect unit 63 is converted to the first effect execution state and the second effect unit 64 is converted to the second effect execution state, the first contact portion 121 and the second contact portion 122 contact each other. The first effect member 70 and the second effect member 80 form one decorative body. At this time, the first magnet 125 and the second magnet 129 are arranged so as to generate an attractive force between the first magnet 125 and the second magnet 129. Further, the decorative body thus formed is configured to be positioned in front of the central portion of the display portion 53a.

  FIG. 8 is a diagram illustrating wiring of the gaming machine 1 according to the embodiment of the present invention.

  FIG. 8 shows a state before the center case 51 is attached to the game board main body 10 b and the display device 53 is attached to the center case 51. An effect control device 550 is attached to the back surface of the display device 53. The effect control device 550 is provided with a connection terminal 90, and transmits a control signal and supplies power to the effect device to be controlled via the connection terminal 90. Specifically, it is connected via a cable 91 to a relay board 600 described later.

  In addition, a game control device 500 and a control unit 700 including various control boards are arranged at the lower back of the game board main body 10b. The control board mounted on the control unit 700 includes a relay board 600 that relays the control signal transmitted from the effect control apparatus 550 to the decoration control apparatus 610 (see FIG. 11). Although the details will be described later, the decoration control device 610 controls an effect device such as a light emitting device (for example, LED) or a movable object (for example, a motor) for effecting a game. The relay board 600 can be connected to a light emitting device or a movable object, similarly to the decoration control device 610.

  The relay board 600 is provided with an upstream connector 601 connected to the effect control device 550 via the cable 91. One connector 91a of the cable 91 is connected to the connection terminal 90 of the effect control device 550 as described above. The other connector 91 b of the cable 91 is connected to the upstream connector 601 of the relay board 600. Furthermore, connectors 602a to 602e for connecting to a decoration control device 610 that controls each effect device provided in the gaming machine 1 are provided.

  Further, the relay board 600 is provided with a vacant terminal monitor 603 indicating the connection state of the connected cables. Details of the empty terminal monitor 603 will be described with reference to FIG.

  Although illustration is omitted, units constituting the game control device 500 are provided so as to cover the connector mounting surface of the relay board 600. Therefore, the game control apparatus 500 has an arrangement configuration that is attached after attaching necessary cables to the connectors of the relay board 600.

  Connected to the front frame 3 is a cable 3b for transmitting signals for controlling the speaker 30 and the decorative members 9a, 9b and the like disposed on the front frame 3. The connector of the cable 3b is connected to the connection terminal 92 of the effect control device 550.

  An opening 45b for attaching the side lamp 45 is formed in the game board main body 10b. A cable 45a for transmitting power and signals is connected to the side lamp 45, and is introduced from the opening 45b to the back side of the game board 10. The cable 45a introduced to the back side of the game board 10 is connected to the relay board 600, for example, connected to the connector 602d.

  Further, as shown in FIG. 2, a starting port 36 and a special winning port 42 are arranged at the lower part of the game board 10. On the back side of the game board 10 on which the start port 36 is arranged, there is arranged a general electric solenoid (SOL) 36b for opening and closing an open / close member 36a that is opened when a win-win game is won. In addition, a special winning opening SOL 42 b for opening and closing the special winning opening 42 when the special figure variation display game is won is also arranged on the back side of the game board 10. A cable (not shown) for receiving an input of a control signal is connected to the general electric power SOL 36 b and the special winning opening SOL 42 b, and these cables are connected to the game control device 500. The cable 42C is connected to the relay board 600 as a cable for transmitting power and a signal for lighting the effect LED provided in the special winning opening 42, and is connected to the connector 602f, for example.

  As described above, the center case 51 is attached to the center of the game board 10. Inside the center case 51, a movable effect device 58 constituted by the first effect member 70 and the second effect member 80 is provided. In FIG. 8, the first effect member 70 and the second effect member 80 are in contact with each other at the contact surfaces (121, 122).

  Further, as described above, the first effect unit 63 and the second effect unit 64 of the movable effect device 58 include the motor (the accessory driving first motor) for operating the first effect member 70 and the second effect member 80. 71, an accessory driving second motor 81) is provided. A cable 652 for supplying signals for controlling these motors and power for driving the motors is connected to the movable effect device 58. In addition, the movable rendering device 58 is provided with a motor position detection sensor (not shown) for detecting the operation state of these motors, and a cable 651 for receiving a sensing result is connected. The cable 652 and the cable 651 extend from the opening 51 b of the center case 51 to the back side of the game board 10 and are connected to the relay board 600. For example, the cable 652 is connected to the connector 602C, and the cable 651 is connected to the connector 602e.

  Furthermore, a cable 653 is connected to transmit the control signal output from the effect control device 550 to a decoration control device 610 (see FIG. 11) for controlling the effect device such as an LED disposed inside the center case 51. The The cable 653 is connected to the relay board 600 on the back side of the game board 10 through an opening 51a provided in the center case 51, and is connected to, for example, a connector 602a.

  FIG. 9 is a block diagram showing a configuration of the gaming machine 1 according to the embodiment of the present invention.

  The gaming machine 1 includes a game control device 500 that controls the game in an integrated manner, an effect control device 550 that controls the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) for paying out game balls. A payout control device 580 for controlling is provided.

  First, the configuration of the game control device 500 will be described. The production control device 550 will be described with reference to FIG.

  The game control device 500 includes a game microcomputer 501, an input I / F (Interface) 505, an output I / F (Interface) 506, and an external communication terminal 507.

  The gaming microcomputer 501 includes a CPU 502, a ROM (Read Only Memory) 503, and a RAM (Random Access Memory) 504.

  The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 503 stores invariant information (programs, data, etc.) for game control. The RAM 504 is used as a work area during game control.

  The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects the setting information of the game control device 500.

  The CPU 502 receives various input devices (start opening SW36d, general winning opening SW44a to 44n, gate SW34a, count SW42d, glass frame opening SW18a, front frame opening SW3a, ball break SW54, vibration sensor 55, and the like via In response to the detection signal from the magnetic sensor 56), various processes such as a big hit lottery are performed.

  The start port SW36d is a switch that detects that a game ball has won the start port 36. The general winning ports SW 44 a to 44 n are switches that detect that a game ball has won the general winning port 44.

  The gate SW 34a is a switch that detects that a game ball has passed through the usual start gate 34. The count SW 42d is a switch that detects that a game ball has won a prize winning opening 42.

  The glass frame opening SW 18a is a switch that detects that the glass frame 18 has been opened. The front frame opening SW 3a is a switch for detecting that the front frame 3 is opened.

  The ball cut SW 54 is a switch that detects that the number of game balls stored in the gaming machine 1 and used for payout has become a predetermined number or less.

  The vibration sensor 55 is a sensor that detects vibration applied to the gaming machine 1 and detects an illegal act such as vibrating the gaming machine 1. The magnetic sensor 56 is provided in the vicinity of the second start winning opening, the general winning opening 44, the large winning opening 42, and the normal start gate 34 of the start opening 36, and is a sensor for detecting magnetic force. The magnetic sensor 56 detects a fraud that brings a magnet close to each winning hole and guides the game ball launched to the gaming area 10a to each winning hole.

  In addition, the CPU 502 transmits a command signal to the ordinary / special-purpose display 35, the ordinary electric power SOL 36b, the special winning opening SOL 42b, the payout control device 580, and the effect control device 550 via the output I / F 506, thereby playing Overall control.

As described above, the special figure change display game and the universal figure change display game are executed on the special figure / special figure display unit 35. Furthermore, the number of unprocessed times (special figure start memory number) of the special figure change display game and the number of unprocessed times (standard figure start memory number) of the normal figure change display game are displayed. A general chart start memory including a random number indicating whether or not the special figure fluctuation display game is won and a special figure start memory including a random number indicating whether or not the special figure fluctuation display game is a win are stored.

  The general electric power SOL 36b opens the opening / closing member 36a when the stop display of the general-purpose variable display game becomes a special result mode, thereby making it easy for the game ball to win the start opening 36.

  The special winning opening SOL42b opens the open / close door 42a of the special winning opening 42 when the result of the special figure change display game becomes a special result mode and becomes a special gaming state (a big hit state), and a game ball Is converted to a state where it is easy to win.

  The game control device 500 outputs game machine data from the external information terminal 508 to a game hall management device (not shown) via an information collection terminal device (not shown). The gaming hall management device is a computer that collects and manages gaming data of the gaming machines 1 installed in the gaming hall.

  The payout control device 580 receives, from the game control device 500, a payout command for the number of game balls corresponding to the winning port when the game ball wins the general winning port 44 or the big winning port 42. Further, even when the ball lending button 26 is operated, a payout command for paying out a predetermined number of game balls is received from the game control device 500. The payout control device 580 controls a payout motor (not shown) based on the received payout command, and pays out the number of game balls specified in the payout command.

  The game control device 500 uses a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like as game data indicating the game situation via the output I / F 506, and the effect control device 550. Send to.

  FIG. 10 is a block diagram showing a configuration of the effect control device 550 according to the embodiment of the present invention.

  The effect control device 550 determines the contents of the effect based on the game data input from the game control device 500, controls the display device 53, and controls various effect devices provided in the game board 10 and the front frame 3. To do. The rendering device includes a light emitting device such as an LED and a movable object such as a motor or a solenoid.

  The production control device 550 includes a CPU 551, a control ROM 552, a RAM 553, an image ROM 554, a sound ROM 555, a VDP 556, a sound LSI 557, an input I / F 558b, an output I / F 558a, a power-on detection circuit 559, a first master IC 570a, a second master IC 570b, A NOR gate circuit 561 and a monitoring timer circuit 562 are provided. Further, the effect control device 550 includes a connection terminal 90 connected to the game board 10 and a connection terminal 92 connected to the front frame 3. The functions common to the first master IC 570a and the second master IC 570b will be described simply as “master IC”.

  The CPU 551 receives the command signal transmitted from the game control device 500 as an interrupt signal (INT) as a communication interrupt, and controls various effects based on the input command signal. The CPU 551 receives an interrupt signal (INT) as a master interrupt from the first master IC 570a and the second master IC 570b, and also receives an interrupt signal (INT) as an image update interrupt from the VDP 556. Is done.

Further, the CPU 551 receives an interrupt signal (INT) as a timeout interrupt also from the monitoring timer circuit 562. The monitoring timer circuit 562 includes a plurality of types of monitoring timers, and outputs an interrupt signal to the CPU 551 when the monitoring timer value set by the CPU 551 is up. When the CPU 551 receives an input of an interrupt signal, the CPU 551 interrupts the process being executed and executes a process corresponding to the input interrupt signal.

  The control ROM 552 stores invariant information (program, data, etc.) for effect control. The RAM 553 is used as a work area during production control.

  The image ROM 554 is connected to the VDP 556 and stores image data displayed on the display device 53. The VDP 556 is a processor that controls image output to the display device 53.

  In addition, the VDP 556 includes a synchronization signal generating unit that generates a synchronization signal that is synchronized with a cycle (33 ms cycle) for updating an image displayed on the display device 53. Every time the synchronization signal is generated, the synchronization signal generation means inputs the generated synchronization signal to the CPU 551 as an interrupt signal.

  The sound ROM 555 is connected to the sound LSI 557 and stores sound data output from the speaker 30 provided in the front frame 3. The sound LSI 557 is a circuit that controls the sound output from the speaker 30.

  The input I / F 558b is an interface that receives information input from the outside via the filters 565a and 565b. Specifically, input of a signal indicating that the effect button 17 provided on the front frame 3 has been operated is received, position information of each motor detected by a motor position detection sensor provided on the game board 10, etc. Or accept input.

  The power-on detection circuit 559 generates a reset signal that initializes the registers of the first master IC 570a and the second master IC 570b to a default state (all 0) when the effect control device 550 is powered on, and generates a NOR gate. Output to the circuit 561.

  Further, the CPU 551 outputs a reset signal to the output I / F 558a via the bus 563 when a predetermined condition is satisfied. The output I / F 558a outputs the input reset signal to the NOR gate circuit 561, and further outputs the reset signal from the NOR gate circuit 561 to the first master IC 570a and the second master IC 570b. The predetermined condition is, for example, a case where an error flag is “ON” in all the decoration control devices 610 (see FIGS. 32 and 33).

  Further, the output I / F 558a outputs a control signal to an effect device (an effect device driven by a movable object such as a motor or a solenoid) provided in the game board 10 or the front frame 3 via the driver 564a and the driver 564b. .

  Note that the reset signal input from the power-on detection circuit 559 to the NOR gate circuit 561 and the reset signal input from the CPU 551 to the NOR gate circuit 561 via the output I / F 558a are in a LOW level state in any case. It functions as a signal for commanding reset at the time. Therefore, if a reset signal is output to the NOR gate circuit 561 from at least one of the power-on detection circuit 559 and the CPU 551, the reset signal is input to the first master IC 570a and the second master IC 570b via the NOR gate circuit 561. .

  FIG. 11 is a block diagram showing the configuration of the first master IC 570a provided in the effect control device 550 and the effect device provided in the game board 10 according to the embodiment of the present invention.

  The game board 10 includes a relay board 600 connected to the first master IC 570a, a decoration device board 625 connected to the relay board 600, and an auxiliary game device unit 12.

  The relay board 600 transmits (relays) the electrical signal transmitted from the first master IC 570 a to the decoration control device 610 provided in the game board 10. In addition, the relay board 600 has a function of controlling the effect device, similarly to the decoration control device 610, and controls the decoration device board 625 directly connected to the relay board 600.

The decoration device 620 includes an I ² CI / O expander 615 provided in the decoration control device 610.
(Refer to FIG. 17) is a light-emitting device that produces an effect by flashing light by passing an electric current, such as an LED. The decoration device substrate 625 is a substrate provided on the side lamp 45 (see FIG. 8), and a light emitting device (LED) of the side lamp 45 is mounted thereon. The light emitting device of the side lamp 45 is directly controlled by an I ² CI / O expander 615 provided on the relay board 600.

  The auxiliary gaming device unit 12 includes a decoration device 620 that is a light emitting device such as an LED, a first accessory driving first motor (MOT) 71 that is a movable object, and a second accessory driving second MOT 81. The decoration device 620 in the auxiliary gaming device unit 12 is controlled by the decoration control device 610 included in the auxiliary gaming device unit 12. In the embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are configured to be controlled by the relay board 600, but are included in the auxiliary gaming device unit 12 like the decoration device 620. The decoration control device 610 may be configured to be controlled.

The first accessory driving MOT 71 and the second accessory driving MOT 81 are driving devices that perform an effect operation by rotating when current flows. Since the accessory driving first MOT 71 and the accessory driving second MOT 81 are directly controlled by the driver 564 of the effect control device 550 via the relay board 600, the process of interposing the I ² CI / O expander 615 is not performed. .

  In the embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are included in the movable effect device 58. Specifically, the accessory driving first MOT 71 includes the first effect unit 63, the accessory driving first. 2MOT 81 is included in the second effect unit 64.

  The effect control device 550 controls the first and second effect units driving MOT 71 and second MOT 81 to cause the first effect unit 63 and the second effect unit 64 to perform an effect operation.

The first master IC 570a designates an address individually assigned to the decoration control device 610 that controls the decoration device 620 to be controlled, and outputs the control contents of the decoration device 620 to the decoration control device 610 of the designated individual address. To do. It should be noted that the individual address of the decoration control device 610 is precisely the I ² CI / O expander 615 (FIG. 1) included in the decoration control device 610.
7).

  The first master IC 570a is connected to a relay board (decoration control device) via seven types of connection lines: a connection line SDA, a connection line SCL, a connection line GND, a connection line Vcc, a connection line Vled, a connection line Vms, and a connection line Vse. ) 600. These connection lines are configured by a cable 91 (see FIG. 8) that connects the first master IC 570a and the relay substrate 600.

Connection line SDA is a connection line for communicating data signals between effect control device 550 and decoration control device 610, and functions as a data line in the embodiment of the present invention. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication on the connection line SDA, and functions as a timing signal line in the embodiment of the present invention. The connection line GND is a ground of the power supplied by the connection line Vcc, the connection line Vled, the connection line Vms, and the connection line Vse.

  The connection line Vcc is a connection line for supplying logic power to the relay board 600 and the decoration control device 610. The connection line Vled is a connection line for supplying power for causing the LED (decoration device 620) to emit light. The connection line Vms is a connection line for supplying power to the motors and solenoids (specifically, the accessory driving first MOT 71 and the accessory driving second MOT 81) included in the auxiliary gaming device unit 12. The connection line Vse is a connection line for supplying power to various sensors (a state detection sensor that detects the state of the motor included in the rendering device, and specifically corresponds to the motor position detection sensor 560a). is there.

  Between the relay board 600 and the auxiliary gaming device unit 12, seven types of connection lines that connect the effect control device 550 and the relay board 600 are connected. In the embodiment of the present invention, the motor position detection sensor 560a, the accessory driving first MOT 71, and the accessory driving second MOT 81 are directly controlled by the relay board 600, and therefore, the connection line Vms among the seven types of connection lines described above. The five types of connection lines other than the connection line Vse are connected to the decoration control device 610 disposed at the uppermost stream of the auxiliary gaming device unit 12. Specifically, a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND are connected between the relay board 600 and the decoration control device 610.

  When the wiring (cable) shown in FIG. 8 is associated with each connection line, various connection lines (connection line Vcc, connection line Vled, connection line SDA, connection line SCL) delivered from the effect control device 550 to the relay board 600 are provided. , Connection line Vms, connection line Vse, and connection line GND) are included in the cable 91.

  These various connection lines are further branched from the relay board 600 and delivered to another board. The connection line Vcc, the connection line Vled, the connection line SDA, and the connection line SCL branched from the relay board 600 are connected to the cable 653. The connection line Vms is included in the cable 652, and the connection line Vse is included in the cable 651. Further, the connection line GND branched from the relay board 600 is included in all the cables 651 to 653.

  The first master IC 570a and the decoration control device 610 perform two-line bidirectional communication using the connection line SDA and the connection SCL. The first master IC 570a functions as a (first) signal level control means for controlling each signal level of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551. To do.

  When transmitting data to the relay board 600 and the decoration control device 610, the first master IC 570a first changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. As a result, a start condition for starting data output to the decoration control device 610 is satisfied (a start condition is issued (output) to the decoration control device 610).

  Thereafter, the first master IC 570a changes the signal level of the connection line SCL to LOW, and sets the signal level of the connection line SDA to the level of the first bit of the transmission data while the signal level of the connection line SCL is LOW. Then, after a predetermined time, the signal level of the connection line SCL is changed from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 acquires the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Next, the first master IC 570a returns the signal level of the connection line SCL from HIGH to LOW.

  When this procedure is executed once, 1-bit data is transmitted from the first master IC 570a to the decoration control device 610. Finally, this procedure is repeated 8 times, so that all 8 bits of the transmission data are transferred to the first master. The data is transmitted from the IC 570a to the decoration control device 610 (1 byte of data is transmitted).

  Then, when the data transmission of the last 8 bits is completed, the first master IC 570a releases the connection line SDA and returns a response from the decoration control device 610 when the signal level of the connection line SCL is returned from HIGH to LOW. A reception standby state in which a signal is received is set.

  In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the first master IC 570a via the connection line SDA. Next, when the first master IC 570a changes the signal level of the connection line SCL from LOW to HIGH to capture the level of the response signal, and changes the signal level of the connection line SCL from HIGH to LOW after a predetermined time, the decoration control device 610 releases the connection line SDA.

  The first master IC 570a alternately repeats such data transmission for 1 byte (transmission of downlink data) and reception of a response signal for 1 bit (reception of uplink data), and outputs the result to the decoration control device 610. Continue until all the data to be output is output. When the output of data to be output is completed, the first master IC 570a changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, thereby controlling the decoration. A stop condition for ending data output to the device 610 is established (a stop condition is issued to the decoration control device 610).

  The input buffer 571 is a storage device that temporarily stores data input from the decoration control device 610 via the connection line SDA.

  Specifically, when the first master IC 570a is set to the input mode, the data transmitted from the decoration control device 610 to the first master IC 570a is temporarily removed to the input buffer 571 after the noise is removed by the filter 575a. Is remembered.

  The output buffer 572 temporarily stores data output to the decoration control device 610 via the connection line SDA.

  The reset register (REG) 573 is connected to the bus 563, receives a command from the CPU 551 of the effect control device 550, and outputs a reset signal to the controller 574. The controller 574 comprehensively controls the first master IC 570a and executes various processes.

  The filter 575a removes noise from data input from the connection line SDA. When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage at which the transistor 578a can operate to the transistor 578a.

  A predetermined voltage is applied to the connection line SDA by a pull-up resistor R (see FIG. 21), and the connection line SDA is connected to the filter 575a and the transistor 578a.

  As the transistor 578a, a field effect transistor (FET) is used in order to suppress power consumption. The gate of the transistor 578a is connected to the driver 576a, the drain is connected to the connection line SDA to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578a is smaller than a predetermined value for operating the transistor 578a, no current flows between the drain and the source, so that the voltage applied to the connection line SDA does not drop, and as a result The connection line SDA becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578a is equal to or higher than a predetermined value for operating the transistor 578a, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. As a result, the connection line SDA becomes LOW level.

Note that the transistor 578a has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, the connection line SDA has a normal I ²
It is possible to pass a current of about 10 milliamperes that is much larger than the current value used when using the C bus, and the data transmission between the production control device 550 and the decoration control device 610 can withstand a failure due to noise. It has become.

  When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage having a value at which the transistor 578a can operate to the gate of the transistor 578a so that a current flows between the drain and the source of the transistor 578a. Then, the driver 576a outputs data from the connection line SDA by setting the voltage of the connection line SDA to the HIGH level or the LOW level.

  Further, the filter 575b removes noise from data input from the connection line SCL. When the driver 576b outputs data from the connection line SCL, the driver 576b applies a voltage at which the transistor 578b can operate to the transistor 578b.

  A predetermined voltage is applied to the connection line SCL by the pull-up resistor R (see FIG. 21), and the connection line SCL is connected to the filter 575b and the transistor 578b.

  A field effect transistor (FET) is used as the transistor 578b in order to reduce power consumption. The gate of the transistor 578b is connected to the driver 576b, the drain is connected to the connection line SCL to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578b is smaller than a predetermined value for operating the transistor 578b, no current flows between the drain and the source, so that the voltage applied to the connection line SCL does not drop, and as a result The connection line SCL becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578b is equal to or higher than a predetermined value for operating the transistor 578b, a current flows from the drain to which the predetermined voltage is applied to the grounded source, whereby the connection line SCL As a result, the connection line SCL becomes the LOW level.

Note that the transistor 578b has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, the connection line SCL has a normal I ^2.
It is possible to pass a current of about 10 milliamperes that is much larger than the current value used when using the C bus, and the data transmission between the production control device 550 and the decoration control device 610 can withstand a failure due to noise. It has become.

When the driver 576b outputs a clock signal from the connection line SCL, the driver 576b applies a voltage having a value at which the transistor 578b can operate to the gate of the transistor 578b so that a current flows between the drain and the source of the transistor 578b. Then, the driver 576b outputs a clock signal from the connection line SCL by repeatedly changing the voltage of the connection line SCL between a HIGH level and a LOW level.

  The power-on reset circuit 577 defaults storage areas such as the input buffer 571 and the output buffer 572 when the first master IC 570a is powered on and the voltage in the power-on reset circuit 577 reaches a predetermined value. A reset signal for setting the state is output to the controller 574. The power-on reset circuit 577 may be provided outside the first master IC 570a and shared with the second master IC 570b described later.

  The command register (REG) 581 is a register for receiving a command from the CPU 551 of the effect control device 550. In the embodiment of the present invention, each bit of STA, STO, SI, and MODE is pre-assigned to the command register 581, and “0” or “1” can be individually set for each bit by the CPU 551. It has become.

  The STA is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a start condition (start condition). When “1” is set in the STA, the first master IC 570a issues (outputs) a start condition to the decoration control device 610 to be controlled to establish the start condition.

  The STO is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a stop condition (stop condition). When “1” is set in the STO, the first master IC 570a issues (outputs) a stop condition to the decoration control device 610 to be controlled to establish the stop condition.

  SI is a bit that is set when an interrupt is generated in the effect control device 550 from the first master IC 570a. When an interrupt is generated from the first master IC 570 a to the CPU 551, “1” is set to SI by the controller 574 and an interrupt signal (INT) is input to the CPU 551. Thereafter, while the SI is set to “1”, the first master IC 570a suspends processing. However, when the CPU 551 sets SI to “0”, the first master IC 570a interrupts. Suspend and resume processing.

  MODE is a bit for designating a mode for transmitting data, and “buffer mode” is designated when “1” is set, and “byte mode” is designated when “0” is set. . The buffer mode is a mode for transmitting a plurality of continuous bytes of data at a time and transmitting a maximum of 68 bytes of data. The byte mode is a mode in which only one byte of data can be transmitted in one transmission, and is used for data transmission / reception in units of bytes.

  The status register (REG) 582 stores information indicating the status of the first master IC 570a. “0” is always set in the lower 2 bits, and the status code is set in the upper 5 bits.

  The own address setting register (REG) 583 is a register that is set when the first master IC 570a functions as a slave (decoration control device). A commercially available master IC usually has a function as a master and a function as a slave, and is used according to the application. In the own address setting REG 583, an address for specifying itself when the first master IC 570a functions as a slave is set.

  FIG. 12 is a block diagram showing the configuration of the second master IC 570b provided in the effect control device 550 and the effect device provided in the front frame 3 according to the embodiment of the present invention.

  The front frame 3 includes a simple relay board 1600 connected to the second master IC 570b, a decoration control device 610 connected to the simple relay board 1600, a speaker 30, a motor position detection sensor 560b, an illumination drive first MOT 13a, and an illumination drive first. 2MOT 14a and the like are included.

The simple relay board 1600 transmits (relays) the electrical signal transmitted from the second master IC 570 b to the decoration control device 610 provided in the front frame 3. Unlike the relay board 600, the simple relay board 1600 does not include the I ² CI / O expander 615. Therefore, the electronic component provided in the simple relay board 1600 includes arithmetic processing for controlling the effect device. Does not have a function to execute. Therefore, since the illumination driving first MOT 13a and the illumination driving second MOT 14a that are directly connected to the simple relay board 1600 cannot be controlled by their own judgment, the simple relay board 1600 receives the electric signal received from the second master IC 570b. Thus, it plays a role of relaying to the illumination driving first MOT 13a and the illumination driving second MOT 14a.

  The illumination drive first MOT 13a and the illumination drive second MOT 14a drive the light emitting member provided inside based on the signal transmitted from the effect control device 550, and execute various effects.

  In addition, the effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17 via the simple relay board 1600. Further, the position information of the illumination drive first MOT 13 a and the illumination drive second MOT 14 a detected by the motor position detection sensor 560 b is input via the simple relay board 1600.

  Further, the simple relay board 1600 receives a signal from the sound LSI 557 of the effect control device 550 and outputs it from the speaker 30.

  Since the configuration of the second master IC 570b is the same as that of the first master IC 570a, the same reference numeral is assigned to each configuration of the second master IC 570b, and description thereof is omitted. Similarly to the first master IC 570a, the second master IC 570b controls the signal levels of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551 ( It functions as a second) signal level control means.

  The connection method between the effect control device 550 and the relay board 600 and the connection method between the relay board 600 and the decoration control device 610 other than the relay board 600 will be described in detail later with reference to FIGS. The configuration of the relay board 600 and the decoration control device 610 will be described in detail later with reference to FIGS.

  The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The decoration device (LED) 620 controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration members 9a and 9b, the illumination unit 11, and the abnormality notification LED 29. On the other hand, the decoration control device 610 attached to the game board 10 is included in the auxiliary game device unit 12 configured by integrating the center case 51, the display device 53, and the effect control device 550.

  In FIG. 13, a configuration and connection form of the decoration control device 610 included in the relay board 600 and the auxiliary game device unit 12 provided in the game board 10 will be described. In FIG. 14, configurations and connection forms of the simple relay board 1600 and the decoration control device 610 provided in the front frame 3 will be described.

  FIG. 13 is a diagram showing a configuration of the game board 10 according to the embodiment of the present invention.

  As described above, the center case 51 constituting the auxiliary gaming device unit 12 is configured by combining the frame decoration portion 65 and the frame base portion 60.

  The frame decoration unit 65 is provided with a plurality of effect devices for performing auxiliary games such as a variable display game, and a decoration control device 610 for controlling the effect devices. These decoration control devices 610 are connected to each other by a predetermined signal cable, and the effect device controlled by the decoration control device 610 is also connected by a cable, whereby the frame decoration portion 65 is integrally configured.

  The frame base 60 is also provided with a plurality of effect devices for performing an auxiliary game such as a variable display game, and a plurality of decoration control devices 610 for controlling the effect devices. By connecting these decoration control devices 610 to each other by a predetermined signal cable, and also connecting the effect device controlled by the decoration control device 610 with a cable, the frame base 60 is integrally configured.

  Therefore, the frame decoration part 65 and the frame base 60 constitute an integrated production unit in the present embodiment. On the other hand, since the side lamps 45 and the like are single production devices that are not included in the integrated production unit, they constitute a separate production device.

  Note that not all of the effect devices included in the auxiliary gaming device unit 12 need be controlled by the decoration control device 610 inside the auxiliary gaming device unit 12. For example, in the embodiment of the present invention, the movable object arranged in the center case 51 is directly controlled by the effect control device 550 via the relay board 600.

As described above, the decoration control device 610 includes the I ² CI / for controlling the decoration device 620.
O Expander 615 is mounted, the I ² CI / O expander 615, and the individual address is assigned for identifying an individual I ² CI / O expander 615. In the embodiment of the present invention, as described above, the individual address of the I ² CI / O expander 615 is used as the individual address of the decoration control device 610.

The effect control device 550 can execute the effect operation by individually controlling the decoration device 620 by designating the individual address of the I ² CI / O expander 615 and transmitting the control signal. In principle, different individual addresses (indicated by “ad =” in the figure) are assigned to the respective decoration control devices 610.

  Further, the decoration control device 610 is classified into three types according to a connection form: a branch type (branch substrate), a connection type (connection substrate), and a termination type (termination substrate). The decoration device 620 can be connected to any one of the branch type, the connection type, and the terminal type decoration control device 610, and the connected decoration device 620 can be controlled.

  In the branch type decoration control device 610, a plurality of decoration control devices 610 are directly connected to the downstream side, and the received control signals are transmitted to the plurality of decoration control devices 610. The connected decoration control device 610 is connected to one decoration control device 610 on the downstream side, and transmits the received control signal to the connected decoration control device 610. The terminal-type decoration control device 610 does not connect the decoration control device 610 on the downstream side, and only controls the decoration device 620. Details of the branch type, connected type, and terminal type decoration control device 610 will be described later with reference to FIG.

  The upstream side refers to the side that transmits the electrical signal in the configuration in which the electrical signal is transmitted from the effect control device 550 to the terminal decoration control device 610 through the decoration control device 610 on the way. On the other hand, the downstream side is the side that receives this electrical signal.

  In short, when the signal cable from the production control device 550 to the decoration control device 610 at the end is traced in order, the decoration control device 610 connected to the side closer to the production control device 550 becomes the upstream side, and more terminal. The decoration control device 610 connected to the side closer to the decoration control device 610 is the downstream side. For example, the decoration control devices 610A and 610C are arranged on the upstream side of the decoration control device 610H, and the decoration control devices 610I and 610J are arranged on the downstream side of the decoration control device 610H.

  Here, in the embodiment of the present invention, as described above, the decoration control device 610 is arranged on the movable parts of the first effect member 70 and the second effect member 80 that constitute the movable effect device 58. In other words, in FIG. 6, the decoration control device 610 (first light emitting substrate 106) is disposed on the movable part (first effect base 100) of the first effect member 70, and in FIG. 7, the movable part of the second effect member 80. The decoration control device 610 (second light emitting substrate 116) is disposed on the (second effect base 110).

  At this time, if each decoration control device 610 is wired in a daisy chain as in the conventional shift register, only one of the decoration control devices 610 at the end of the daisy chain is connected to an input cable. That's it. However, it is necessary to connect an input cable and an output cable to the other decoration control device 610 configured to be connected in the middle of the daisy chain. When a plurality of cables are connected to the movable part, the decoration control device 610 (the first light emitting board 106 and the second light emitting board 116) itself moves together with the movable part, and the cable also moves. It can be difficult. Furthermore, the movement of the cable may cause a disconnection of the connection line constituting the cable, which may affect the production.

  In the embodiment of the present invention, the decoration control device 610 disposed on the first effect member 70 and the second effect member 80 is a terminal type, and the branch type decoration control device 610 is disposed upstream of these decoration control devices 610. doing. Therefore, the terminal-type decoration control device 610 (the first light-emitting board 106 and the second light-emitting board 116) sends a signal to the other decoration control devices 610 provided outside the first effect member 70 and the second effect member 80. The transmitting cable is not connected. If the decoration control device 610 is arranged in this way, only the input cable needs to be connected to the decoration control device 610 arranged in the movable part. Therefore, the wiring can be easily routed and the possibility of disconnection can be reduced as compared with the case of wiring by daisy chain.

  When the destination address of the received control signal is not addressed to itself, the decoration control device 610 transmits the received control signal if the decoration control device 610 is further connected to the downstream side. If there is no transmission destination, the received control signal is discarded.

The decoration control device 610 can control the LEDs corresponding to the 16 ports. The decoration control device 610 includes an LED mounted on the decoration control device 610 and an external decoration device substrate 625 connected to the decoration control device 610. If the total number of mounted LEDs is 16 or less, both LEDs can be controlled. In other words, in the integrated decoration control device 610 (corresponding to the main active substrate on which both the I ² CI / O expander 615 and the decoration device 620 are arranged), the decoration device substrate 625 (the I ² CI / O expander 615 is arranged). In addition, it is possible to control both the decoration device 620 provided inside and the decoration device 620 connected to the outside by further connecting a driven substrate on which the decoration device 620 is disposed.

  By doing so, it is possible to control the decoration devices 620 arranged at a distance by one decoration control device 610, and the number of decoration control devices 610 can be minimized.

The relay board 600 is connected to the first master IC 570a mounted on the effect control device 550 on the upstream side, and receives a control signal transmitted from the first master IC 570a. Further, on the downstream side, it is connected to a decoration control device 610A included in the auxiliary gaming device unit 12 (more precisely, a decoration control device 610A included in the frame base 60 which is an integrated production unit). Further, the relay board 600 is connected to a decoration device board 625 (a board provided on the side lamp 45 (see FIG. 8)) which is a separation type effect device provided in the game board 10, and is provided in the relay board 600. The decoration device 620 mounted on the decoration device substrate 625 is controlled by the I ² CI / O expander 615.

  The auxiliary gaming device unit 12 includes decoration control devices 610A to 610J. The decoration control device 610A is a branch type decoration control device, and transmits the control signal received from the first master IC 570a to the decoration control device 610B and the decoration control device 610C. In addition, a decoration device substrate 625B is connected to the decoration control device 610B, and an effect device (decoration device 620) such as an LED disposed on the decoration device substrate 625B is controlled by the decoration control device 610B.

  The decoration control device 610C is a branch type decoration control device 610, and transmits the received control signal to the decoration control device 610D and the decoration control device 610H on the downstream side. The decoration control device 610D is connected to a branch type decoration control device 610E, and further controls the decoration device 620D included in the decoration device substrate 625D.

  The decoration control device 610E is connected to a decoration control device 610F that controls the first effect member 70 and a decoration control device 610G that controls the second effect member 80. The first effect member 70 and the second effect member 80 perform an effect operation in conjunction with each other. The decoration control device 610F is disposed on the first light emitting substrate 106 included in the first effect member 70 (FIG. 6), and the decoration control device 610G is disposed on the second light emitting substrate 116 included in the second effect member 80. (FIG. 7).

  The first light emitting substrate 106 itself may function as the decoration control device 610F, and the second light emitting substrate 116 itself may function as the decoration control device 610G.

  In the embodiment of the present invention, the decoration control device 610F controls the LEDs included in the first effect member 70, and the decoration control device 610G controls the LEDs included in the second effect member 80. Note that the accessory driving first MOT 71 and the accessory driving second MOT 81 for outputting the driving force for moving the first effect member 70 and the second effect member 80 to the front of the display unit 53a are controlled by the relay board 600. Is done.

  The effect control device 550 controls the first effect unit 63 (the first effect member 70) and the second effect unit 64 (the second effect member 80) when the predetermined condition is satisfied, such as when the variable display game is executed. Perform the action. Specifically, in order to control the accessory driving first MOT 71 included in the first effect unit 63 and the accessory driving second MOT 81 included in the second effect unit 64, the individual address (“0000”) of the relay board 600 is set. Designate and send control signals to operate these motors. Furthermore, a control signal for controlling a light emitting device such as an LED included in the first effect member 70 is transmitted by designating the individual address (“0110”) of the decoration control device 610F for controlling the first effect member 70. Similarly, a control signal for controlling a light emitting device such as an LED included in the second effect member 80 is transmitted by designating the individual address (“0111”) of the decoration control device 610G for controlling the second effect member 80. After that, issue a stop condition.

The decoration control device 610H is a connection type decoration control device 610, and is further connected to a connection type decoration control device 610I and a terminal type decoration control device 610J. The terminal-type decoration control device 610J controls the decoration device 620J included in the decoration device substrate 625J.

  In the embodiment of the present invention, the decoration control device 610H and the decoration control device 610I control an effect device (LED) included in the reliability notification device 15. When the predetermined condition is satisfied, a control signal for indicating a predetermined mode is transmitted from the first master IC 570a of the production control device 550, and the production is performed in the designated mode.

  FIG. 14 is a diagram showing a configuration of the front frame 3 according to the embodiment of the present invention.

  The gaming machine 1 according to the embodiment of the present invention has a plurality of specifications, and there are a normal version gaming machine 1 and an inexpensive version gaming machine 1. The normal version gaming machine 1 includes a front frame 3 (hereinafter, referred to as a normal version front frame 3) having a standard decorative member. The low-priced gaming machine 1 includes a front frame 3 (hereinafter referred to as a low-priced front frame 3 ') that includes a decorative member configured at a lower cost than a standard decorative member. The upper side of FIG. 14 shows the configuration of the normal version front frame 3, and the lower side shows the configuration of the inexpensive version front frame 3 ′. In the gaming machine 1, only the front frame 3 of one of the specifications is shown. Is attached and connected to the production control device 550, so that only one of the normal plate front frame 3 and the inexpensive plate front frame 3 ′ is connected to the second master IC 570b.

  The normal plate front frame 3 and the inexpensive plate front frame 3 ′ are different in the number of decoration devices 620 included in the decoration members 9 a and 9 b, and also in the number of decoration control devices 610 that control the decoration device 620. Specifically, the decoration members 9a and 9b of the normal plate front frame 3 are controlled by seven decoration control devices 610, and the decoration members 9a 'and 9b' of the inexpensive plate front frame 3 'are controlled by five decoration control devices 610. Is done. Since the decorative members 9a and 9b irradiate with more LEDs than the decorative members 9a ′ and 9b ′, the normal plate front frame 3 becomes brighter than the inexpensive plate front frame 3 ′, which increases the variation of executable effects. It is also possible. Therefore, the control of the decoration device 620 when the normal plate front frame 3 is attached is different from the control of the decoration device 620 when the inexpensive plate front frame 3 ′ is attached.

  For this reason, when the same address is assigned to the individual address of the decoration control device 610 attached to the normal plate front frame 3 and the individual address of the decoration control device 610 attached to the inexpensive plate front frame 3 ′, the effect control device 550 Since the production control data to be transmitted to the decoration control device 610 needs to be different between the case of the normal version front frame 3 and the case of the inexpensive version front frame 3 ′, it is usually determined according to the front frame 3 attached to the gaming machine 1. The production control device 550 for the plate and the production control device 550 for the low cost version must be prepared. Therefore, when the manufacturer ships the gaming machine 1, the production control device 550 for the normal version and the production control device 550 for the low-priced version must be prepared, resulting in an increase in manufacturing cost.

  Therefore, in the embodiment of the present invention, different addresses are assigned to the individual addresses of the decoration control device 610 whose control is different between the normal plate front frame 3 and the inexpensive plate front frame 3 ′, and the effect control device 550 to the decoration control device. The effect control data to be transmitted to 610 is configured to be common between the case of the normal version front frame 3 and the case of the inexpensive version front frame 3 ′, so that the control for the normal version can be performed by one effect control device 550. It is configured to be able to execute control for the low cost version. By doing so, it is not necessary to prepare the production control device 550 for the normal version and the production control device 550 for the low-priced version, and the manufacturing cost can be suppressed. In the embodiment of the present invention, the configuration of the game board 10 is the same regardless of whether it is a normal version or a low-priced version.

  Hereinafter, the configurations of the normal plate front frame 3 and the inexpensive plate front frame 3 'will be described in detail.

The normal plate front frame 3 includes a simple relay board 1600 connected to the second master IC 570b. The simple relay board 1600 includes a branch type decoration control device 610K and an illumination drive motor (
13a, 14a) are connected.

  The decoration control device 610K is arranged in the lighting unit 11 and controls the decoration device 620 provided on the decoration device substrate 625K. Specifically, the LED included in the illumination unit 11 and the abnormality notification LED 29 are controlled.

  The decoration control device 610K is a branch type decoration control device, and transmits the received control signal to the decoration control device 610L and the decoration control device 610P. The decoration control devices 610 </ b> L to 610 </ b> N control the decoration member 9 a on the left side portion of the normal plate front frame 3. Further, the decoration control devices 610P to 610R control the decoration member 9b on the right side portion of the normal plate front frame 3.

  The decoration member 9a on the left side portion of the normal plate front frame 3 includes connection type decoration control devices 610L and 610M and a terminal type decoration control device 610N. The decoration control device 610L receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K and transmits it to the decoration control devices 610M and 610N.

  As described above, the decoration member 9b on the right side portion of the normal plate front frame 3 includes the connection type decoration control devices 610P and 610Q and the terminal type decoration control device 610R. The decoration control device 610P receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K and transmits the control signal to the decoration control devices 610Q and 610R.

  Also, different individual addresses are assigned to the decoration control devices 610L to 610R included in the decoration member 9a and the decoration member 9b, and different rendering operations are performed based on the control signals transmitted from the second master IC 570b. Can be executed. Specifically, “0000” is used for the individual address of the decoration control device 610K included in the lighting unit 11, and “0001” “0010” is used for the individual addresses of the decoration control devices 610L, 610M, and 610N included in the decoration member 9a. “001”, “0100”, “0101”, and “0110” are assigned to the individual addresses of the decoration control devices 610P, 610Q, and 610R included in the decoration member 9b.

  On the other hand, the low-priced front frame 3 ′ is similar to the normal plate front frame 3 in that the simple relay board 1600 connected to the second master IC 570 b and a board having substantially the same function (hereinafter referred to as the low-priced simple relay board 1600). 'And). However, in the low-priced front frame 3 ′, only the branch type decoration control device 610 </ b> S is connected to the simple relay board 1600 ′, and the cost is reduced without the illumination drive motor (13 a, 14 a).

  The decoration control device 610S is disposed in the lighting unit 11, and controls the decoration device 620 provided on the decoration device substrate 625S. Specifically, the LED included in the illumination unit 11, the abnormality notification LED 29, and the like are controlled and are the same as those of the normal plate front frame 3. The decoration control device 610S is the same substrate as the decoration control device 610K that controls the illumination unit 11 of the normal plate front frame 3, and is assigned the same individual address (“0000”). Therefore, the same control is executed in the decoration control device 610K of the normal plate front frame 3 and the decoration control device 610S of the inexpensive plate front frame 3 '.

  The decoration control device 610S is a branch type decoration control device, and transmits the received control signal to the decoration control device 610T and the decoration control device 610V. The decoration control devices 610T and 610U control the decoration member 9a 'on the left side portion of the normal plate front frame 3. Further, the decoration control devices 610V and 610W control the decoration member 9b 'on the right side portion of the normal plate front frame 3.

Further, in the low-priced front frame 3 ′, a decoration control device 610T for controlling the left decoration member 9a ′.
610U and decoration control devices 610V and 610W for controlling the decoration member 9b ′ on the right side are attached. The decoration control device 610T is the same substrate as the decoration control device 610L of the normal plate front frame 3, and is assigned the same individual address (“0001”). Similarly, the decoration control device 610V is the same substrate as the decoration control device 610P of the normal plate front frame 3, and is assigned the same individual address (“0001”). Therefore, the same control is executed in the decoration control device 610L of the normal plate front frame 3 and the decoration control device 610T of the inexpensive plate front frame 3 ′, and the decoration control device 610P of the normal plate front frame 3 and the inexpensive plate front frame 3 are controlled. In the 'decoration control device 610V, the same control is executed.

  The same individual address (“0111”) is assigned to the decoration control devices 610U and 610W. Therefore, in the low-price front frame 3 ′, the same control is executed by the decoration control devices 610 </ b> U and 610 </ b> W with the left and right decoration members, that is, the irradiation with the LED to be controlled is executed at the same timing. In addition, the decoration control devices 610U and 610W are assigned individual addresses that are not assigned to the decoration control device 610 of the normal front frame 3.

The decoration control device included in the decoration members 9a, 9b, 9a ′, and 9b ′ is used from the effect control device 550 regardless of whether the normal version front frame 3 or the inexpensive plate front frame 3 ′ is used. Production control data is transmitted to all individual addresses assigned to the I ² CI / O expander 615 of 610.

  As described above, the low price front frame 3 'corresponds to the decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means) among the decoration control devices provided. Instead, decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached. The normal plate front frame 3 is equipped with decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means), whereas the inexpensive plate front frame 3 ′ has fewer. A number of decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached.

  The decoration control device 610K and the decoration control device 610S, the decoration control device 610L and the decoration control device 610T, and the decoration control device 610V and the decoration control device 610P are common to the normal plate front frame 3 and the inexpensive plate front frame 3 ′. It is configured as a usable substrate.

  Therefore, the production control device 550 according to the embodiment of the present invention can share the control for the normal version and the control for the low cost version, and there is no need to change the control for each front frame. The manufacturing cost of the device 550 can be reduced.

  In the following description, unless otherwise specified, it is assumed that the normal version front frame is attached to the gaming machine 1 according to the embodiment of the present invention.

In the low price front frame 3 ′, the I ² CI / O expander 615 with individual addresses “0010”, “0011”, “0101” and “0110” is not used. The I ² CI / O expander 615 whose individual address is “0111” is not used. Therefore, in any front frame 3, there is an unconnected I ² CI / O expander 615 in the abnormality determination table 3300 (see FIG. 33). However, as will be described later, if data is normally transmitted between at least one I ² CI / O expander 615 registered in the abnormality determination table 3300 and the second master IC 570b, Since it is determined to be operating, the process is not interrupted due to this.

  FIG. 15 is a diagram illustrating a connection state between the effect control device 550 and the relay board 600 and the decoration control device 610 included in the game board 10 according to the embodiment of this invention.

  In FIG. 15, connection of the effect control device 550, the relay board 600, and the decoration control devices 610A, 610B, and 610C will be described. For convenience of explanation, description of the decoration control device 610 is omitted for one relay board 600 and each decoration control device (610D to 610J) connected downstream from the decoration control device 610C. The connection between the decoration control devices 610 is the same.

  The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34, a connection line SL1, and a connection line. The relay board 600 is connected by SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse.

  The connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse are as described in FIG.

  Signals for controlling the first to fourth phases of the accessory driving first MOT 71 included in the first effect unit 63 are transmitted to the connection lines M11 to M14. Signals for controlling the first to fourth phases of the accessory driving second MOT 81 included in the second effect unit 64 are transmitted to the connection lines M21 to M24. The accessory driving first MOT 71 and the accessory driving second MOT 81 use a four-phase driving stepping motor.

  The connection lines M31 to M34 are connection lines for controlling the motor. However, in the embodiment of the present invention, since the motor corresponding to the relay board 600 is not connected, the empty terminal monitor 603 for displaying the connection state is connected. Is done. The vacant terminal monitor 603 includes four LEDs corresponding to the connection lines M31 to M34, and can check whether or not each connection line is disconnected. Therefore, when some or all of the connection lines are disconnected, a part of the vacant terminal monitor 603 is not lit, so that it can be determined that the quality of the cable is bad.

  In particular, as in the gaming machine 1 according to the embodiment of the present invention, the cable 91 that connects the first master IC 570a and the relay board 600 includes a connection line GND for supplying power, a connection line Vcc, and a connection line Vled. , Connection line Vms, and connection line Vse (see FIG. 11 or FIG. 15). These wires for supplying electric power are originally used as cables having a large (thick) cross-sectional area that can secure a sufficient amount of current in order to realize a stable operation.

  However, when a flat cable such as the cable 91 is used, the cross-sectional area of each cable needs to be the same (common) because of the connection of the connectors. Therefore, it is conceivable to supply power using a plurality of connection lines instead of a cable having a large cross-sectional area. For example, six cables are used as the connection lines GND and three cables are used as the connection lines Vms. A configuration such as use can be realized.

  At this time, even if a part of the connection line for supplying power is disconnected, if all the connection lines are not disconnected, it will operate without any problem, so that the LED is turned on, Although it is possible to drive the motor, since a sufficient amount of current cannot be secured, abnormal heat generation may occur on the cable. In such a case, by connecting a power supply line to the vacant terminal monitor 603, a cable with inferior quality such that some of the connection lines are disconnected even though it seems to be operating normally at first glance is discovered. It is possible to perform replacement or perform necessary maintenance before a failure occurs.

  In addition, the relay board 600 supplies the electric power supplied from the connection line Vms to each motor in order to drive the accessory driving motor (the accessory driving first MOT 71, the accessory driving second MOT 81). The electric power supplied to the accessory driving solenoid for moving the decoration piece 46 up and down is also supplied from the connection line Vms.

  The relay board 600 is connected to a motor position detection sensor 560a for detecting the rotational position of the accessory driving motor. Connection lines SE1 to SE3 are connection lines for receiving the detection result by the motor position detection sensor 560, and the relay board 600 indicates the rotation position of the accessory driving motor detected by the motor position detection sensor 560a. It transmits to production control device 550 via SE1-3.

  The connection line SL1 and the connection line SL2 are connection lines for controlling the accessory driving solenoid. When the accessory driving solenoid is not used, the connection line SL1 and the connection line SL2 are also connected to the vacant terminal monitor 603 for displaying the connection state, similarly to the connection lines M31 to M34 described above.

  The decoration control device 610 including the relay board 600 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND (hereinafter, a bundle of these five types of connection lines is referred to as one harness). Are connected to each other.

  In addition, a decoration control device 610B and a decoration control device 610C are connected to the decoration control device 610A via a harness, and a decoration control device 610D (not shown) is connected to the decoration control device 610C via a harness.

  Each decoration control device 610 includes a connector serving as an attachment port for connecting the harness to itself. Since this connector is common to each decoration control device 610, the connection order of each connection line is common, and erroneous wiring can be prevented.

  FIG. 16 is a diagram for explaining a connection state between the effect control device 550 according to the embodiment of the present invention, the simple relay board 1600 and the decoration control device 610 included in the normal plate front frame 3.

  In FIG. 16, connection of the effect control device 550, the simple relay board 1600, and the decoration control devices 610K, 610L, and 610P will be described. For convenience of explanation, the description of the decoration control devices 610L and the decoration control devices connected downstream of the decoration control device 610P will be omitted.

  The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34, a connection line SL1, and a connection line. In addition to the SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse, the connection line that receives the button signal from the effect button 17 and the connection line that transmits the sound signal to the speaker 30 are connected to the simple relay board 1600. The

  For the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse, as described with reference to FIG. 15, the effect control device 550 and the game board 10 are connected. Similar to the case of connection, various signals are transmitted to and received from each decoration control device 610 arranged on the downstream side.

Signals for controlling the illumination driving first MOT 13a of the first movable illumination 13 included in the illumination unit 11 are transmitted to the connection lines M11 to M14. Signals for controlling the illumination drive second MOT 14a of the second movable illumination 14 included in the illumination unit 11 are transmitted to the connection lines M21 to M24.

  The connection lines M31 to M34 are connection lines for controlling the motor. However, in the embodiment of the present invention, the corresponding motor is not connected to the simple relay board 1600. An empty terminal monitor 603 to be displayed is connected.

  Further, in order to drive the illumination drive motor (the illumination drive first MOT 13a and the illumination drive second MOT 14a), the electric power supplied from the connection line Vms is supplied to each motor.

  The simple relay board 1600 is connected to a motor position detection sensor 560b for detecting the rotation position of the illumination drive motor. The simple relay board 1600 transmits the rotation position of the illumination drive motor detected by the motor position detection sensor 560b to the effect control device 550 via the connection lines SE1 to SE3.

Here, a method in which the I ² CI / O expander 615 (described later in FIG. 18) provided in the decoration control device 610 controls the decoration device 620 will be described.

The effect control device 550 determines the output mode of the effect device (decoration device 620) based on the game data input from the game control device 500. The effect control device 550, so that the determined output mode, the individual address of the decoration control device 610 to be controlled (I ²
Production control data (production control information) including the individual address of the CI / O expander 615 is output to the relay board 600. At this time, the effect control data is output from the relay board 600 to all the decoration control devices 610 to be controlled through the connection line SDA.

  In the embodiment of the present invention, the rendering device controlled by the decoration control device 610 is mainly a light emitting device such as an LED, and the light emission mode of the LED corresponds to the output mode of the rendering device. In this case, lighting / flashing / extinguishing of the LED is instructed by the effect control data, and further, the flashing cycle and the lighting brightness of the LED are instructed.

Each decoration control device 610 is previously set with a unique individual address as described above. When the presentation control data is input, the address included in the input presentation control data and the set individual address It is determined whether or not. If it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 captures the effect control data. Thus, the output mode of the corresponding decoration device 620 is controlled, and a response signal is output to the master IC (first master IC 570a, second master IC 570b) immediately after the 8th bit data is input.

  As described above, the master IC transmits the effect control data to all the decoration control devices 610 connected to the master IC, and requested in the decoration control device 610 corresponding to the individual address included in the effect control data. The rendering device can be controlled so as to be in the output mode.

Each decoration control device 610 includes I ^{2 of the} decoration control device 610 in addition to the individual address.
A reset address for initializing the CI / O expander 615 is set. This reset address is an address provided in common to all the I ² CI / O expanders 615 and cannot be used as an individual address. The reset address value cannot be changed (details will be described later).

The effect control device 550 is a decoration control device 610 (more precisely, I ² C of the decoration control device 610).
When the I / O expander 615) is initialized, initialization instruction data including the common address for reset is output to the relay board 600 or the simple relay board 1600. At this time, the initialization instruction data effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay substrate 600 or the simple relay substrate 1600.

Since a common address for reset is set in advance in each decoration control device 610, it is determined whether or not the address included in the input data matches the common address for reset. If it is determined that they match, the I ² CI / O expander 615 of the decoration control device 610 outputs a response signal to the master IC, takes in the input data as initialization instruction data, and outputs the I ² CI / O expander. The panda 615 itself is initialized.

When the I ² CI / O expander 615 is initialized, the rendering device controlled by the initialized I ² CI / O expander 615 is turned off.

As described above, the decoration control device 610 performs control based on a command from the effect control device 550, and therefore, the relationship between the effect control device 550 and the decoration control device 610 is the first master IC 570a of the effect control device 550 and the second master IC 570a. The master IC 570b is a master, and the I ² CI / O expander 615 of each decoration control device 610 is a slave.

  15 and 16, the control target of the decoration control device 610 other than the relay board 600 is a decoration device 620 that is a light emitting device such as an LED, but it is also possible to control a movable object such as a motor or a solenoid. It is. In this case, since the effect device serves as a drive source such as a motor or a solenoid, the operation mode of these drive sources corresponds to the output mode of the effect device. The effect control data includes an operation / stop instruction for the drive source, and it is also possible to specify the operation speed.

  Note that, even if the gaming machine 1 is provided with a low-priced front frame 3 ′ instead of the normal-price front frame 3, the connection state of various substrates included in the low-priced front frame 3 ′ is almost the same as FIG. It becomes the composition of.

  However, since the illumination drive motors (illumination drive first MOT 13a, illumination drive second MOT 14a) are not provided on the inexpensive front frame 3 ′, the illumination drive motor is connected to the inexpensive relay board 1600 ′. There is no connector, and the connection lines M11 to M14 and the connection lines M21 to M24 are not used. Therefore, in the low-price simple relay board 1600 ', the empty terminal monitor 603 is also connected to the connection lines M11 to M14 and the connection lines M21 to M24.

  Further, since the low-price front frame 3 'is not provided with the motor position detection sensor 560b, in the low-price simple relay board 1600', the connection lines SE1 to 3 are connected to the ground so that a signal of a certain level is obtained. However, it is configured such that it is always input to the production control device 550.

  FIG. 17 is a block diagram of the decoration control device 610 according to the embodiment of this invention.

  As described above, the decoration control device 610 according to the embodiment of the present invention is classified into three types, that is, a branch type, a connection type, and a termination type, based on the connection form. FIG. 17 shows an example in which a terminal type decoration control device 610Y is connected to a branch type decoration control device 610X. Further, a decoration device substrate 625 is connected to the decoration control device 610Y.

The branch type decoration control apparatus includes an I ² CI / O expander 615, a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615, and a signal received from the upstream connector. A connector (downstream connector) for transmitting to a plurality of decoration control devices 610 is provided. For example, like the decoration control device 610X in the figure, the I ² CI is included inside.
/ O expander 615 and LED (decoration device 620), and further includes one upstream connector 611 and two downstream connectors 612A and 612B.

The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is connected to the downstream connector 612B for output to the next decoration control device 610Y as it is. The other further branches, one connected to the I ² CI / O expander 615 and the other connected to another downstream connector 612A.

Further, a decoration device 620 to be controlled is connected to the output side of the I ² CI / O expander 615 of the decoration control device 610X. The output side of the I ² CI / O expander 615 includes ports 0 to 15 described with reference to FIG. Further, all the ports of the decoration control device 610 are connected to internal LEDs via current limiting resistors R0 to R15 described later in FIG. Note that the current control resistors R0 to R15 are also provided in the decoration control device 610.

As described above, the I ² CI / O expander 615 has an address included in the effect control data input from the effect control device 550 and an individual address set in the I ² CI / O expander 615. Only when they match, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data.

Since there is only one downstream connector, the signal received from the upstream connector is
The decoration control device that can be transmitted to only one decoration control device 610 is a connected decoration control device. For example, the decoration control device 610X described above includes only the downstream connector 612B and does not include the downstream connector 612A.

The terminal-type decoration control device has an I ² CI / O expander 615 and a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615. This signal is not transmitted to the other decoration control device 610. For example, the decoration control device 610Y in the figure includes an I ² CI / O expander 615 and an LE.
D (decoration device 620), a connection line for flowing current to the LED provided on the decoration device substrate 625 connected to the outside of the decoration control device 610Y, a connection line for supplying a power supply voltage to the LED of the decoration device substrate 625, And the decoration control apparatus 610 and the decoration apparatus board | substrate 625 are connected through the connection line which earth | grounds to a ground.

The decoration device substrate 625 is a substrate that does not include the I ² CI / O expander 615 but includes only a light emitting device such as an LED. In this case, the current limiting resistor connected to the LED provided on the decoration device board 625 is provided on the decoration device board 625, but is provided on the decoration control device 610 provided with the I ² CI / O expander 615. Also good.

It should be noted that the number of connection lines for passing current to these LEDs to be passed from the decoration control device 610 to the decoration device substrate 625 is determined in accordance with the number of LEDs provided on the decoration device substrate 625. . For example, in the case where the decoration device substrate 625 includes two LEDs, I ² CI
At least two control lines for connecting the port of the / O expander 615 and the corresponding LED, and one power supply line for supplying power supplied from Vled are required.

The I ² CI / O expander 615 provided in the decoration control device 610Y also includes an address included in the effect control data input from the effect control device 550, and the I ² CI / O.
Only when the address set in the expander 615 matches, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided on the decoration device substrate 625 are controlled by the I ² CI / O expander 615.

In this way, by providing the decoration device substrate 625 and separating some of the decoration devices (LEDs) from the decoration control device 610, even if the LEDs are arranged at remote locations, the common I ² C
It can be controlled by the I / O expander 615.

  As described above, the decoration control device 610 can control a movable object such as a solenoid or a motor instead of a light emitting device such as an LED, and will be described in detail later with reference to FIG.

FIG. 18 is a block diagram showing a configuration of the I ² CI / O expander 615 according to the embodiment of this invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA,
Filter 631 connected to connection line SDA, driver 632 connected to connection line SDA, filter 633 connected to connection line SCL, bus controller 634, output setting register 635, output controller 636, I ² CI / O expander 615 includes a driver 637 connected to each port 0-15 on the output side of 615, transistors 638A-638P connected to each port 0-15, and a reset signal generation circuit 639. Furthermore, in the embodiment of the present invention, a bus monitoring WDT (watch dock timer) 640 for determining whether or not the connection line SDA is occupied by another I ² CI / O expander 615, and I ² CI /
A self-occupied WDT 641 for determining whether or not the O expander 615 itself occupies the connection line SDA is provided.

  The filter 631 is connected to the connection line SDA, removes noise of data input from the connection line SDA, and outputs the data from which noise has been removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  The transistor 630 uses a field effect transistor (FET) to suppress power consumption. The gate of the transistor 630 is connected to the driver 632, and the drain is connected to a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

  If the voltage applied to the gate of the transistor 630 is smaller than a predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, if the voltage applied to the gate of the transistor 630 is greater than or equal to a predetermined value that causes the transistor 630 to operate, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. The voltage drops. Note that the transistor 630 has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source.

When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage of a value that allows the transistor 630 to operate to the gate of the transistor 630 so that a current flows between the drain and the source. To do. The driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

  The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which noise has been removed to the bus controller 634.

In addition, the I ² CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the I ² CI / O expander 615 is input to the bus controller 634. Further, an address for resetting the I ² CI / O expander 615 is also set in advance.

In the bus controller 634, the address of data input from the connection line SDA is I ² CI.
It is determined whether or not the address matches the unique address set in the / O expander 615. If the address matches, the data is fetched as effect control data.

The bus controller 634 determines whether the address of the data input from the connection line SDA matches the reset address set in the I ² CI / O expander 615. The data is fetched as initialization instruction data, and the I ² CI
The / O expander 615 is initialized.

  In addition, the bus controller 634 changes the signal level of the connection line SCL from LOW to HIGH, and when the signal level of the connection line SCL changes from HIGH to LOW after fetching the eighth bit data. The response signal is output from the connection line SDA to the first master IC 570a. Furthermore, when it is confirmed that the signal level of the connection line SCL changes from LOW to HIGH, and the signal level of the connection line SCL changes from HIGH to LOW again, the connection line SDA is released. In other words, the response signal is output at the timing when the signal level of the connection line SCL changes from LOW to HIGH.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 fetches the initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes a current to flow to all the ports 0 to 15. The initial state is set so that there is no.

  Based on the data set in the output setting register 635, the output controller 636 causes the directing device connected to each of the ports 0 to 15 to actually output the output state of the directing device through the port driver 637. To control. This output state is updated to the contents specified in the effect control data when the bus controller 634 fetches the effect control data from the connection line SDA.

That is, based on the effect control data received from the first master IC 570a, it is set in the output setting register 635, and when the stop condition is received, the output state of each port 0-15 is updated and reflected in the effect device. Therefore, it is not necessary to receive the LAT signal as in the shift register, that is, the production control can be performed without the need for wiring for receiving the LAT signal. In particular, the port output state may be set to a plurality of I ² CI /
This is useful when there is a need to update at the same time in the O expander 615 and a different I ² CI /
Even the production device controlled by the O expander 615 can be controlled to execute the production operation at the same time, so that the production effect can be further enhanced.

  When a current flows through a port, the driver 637 applies a voltage at which the transistors 638A to 638P connected to the port through which the current flows can operate.

  The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to a port terminal connected to a connection line to which a voltage for operating the effect device is applied as shown in FIGS. 19 and 20, and the source is grounded Has been.

  If the voltage applied to the gates of the transistors 638A to 638P is smaller than a predetermined value for operating the transistors 638A to 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than a predetermined value for operating the transistor 638, the predetermined voltage applied to the gate from the power supply Vled shown in FIG. 19 or the power supply Vmot or the power supply Vsol shown in FIG. Current flows to the source grounded through the drain of the transistor 638, so that the output state of the effect device connected to the port terminal can be controlled.

In addition, the I ² CI / O expander 615 of the decoration control device 610 can simultaneously control all effect devices (decoration devices 620 such as LEDs) connected to the port terminals of the I ² CI / O expander 615. Since it is possible, one rendering device connected to the port terminal of the I ² CI / O expander 615 can be controlled as one group.

Since the I ² CI / O expanders 615 included in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I ² CI / O expander 615 included in each decoration control device 610 is configured as a group unit control unit that can control the effect device in units of groups.

  Therefore, the effect control device 550 that controls each decoration control device 610 functions as a group control unit that controls the group unit control unit.

The reset signal generation circuit 639 is connected to a Vcc terminal connected to a connection line Vcc that supplies power to the I ² CI / O expander 615 and a RESET terminal that receives an external reset signal.

The reset signal generation circuit 639 is powered on to the I ² CI / O expander 615,
When the voltage rises to a predetermined value, a reset signal is generated, and initialization is performed by inputting the generated reset signal to the bus controller 634, the output setting register 635, and the output controller 636.

  Note that when a LOW level reset signal is input from the outside, the reset signal generation circuit 639 outputs a reset signal, and therefore, from the CPU 551 of the effect control device 550 via the NOR gate circuit 561, from the RESET terminal. A reset signal may be input. When the RESET terminal is not used, the RESET terminal may be pulled up to HIGH as shown in FIGS.

The bus monitoring WDT 640 is used to detect that another I ² CI / O expander 615 occupies the connection line SDA. The bus monitoring WDT 640 is connected between the filter 631 and the bus controller 634, takes in the signal level of the connection line SDA, and measures the time during which the signal is continuously at the LOW level. Further, the bus monitoring WDT 640 is connected to the reset signal generation circuit 639. When a predetermined time has elapsed after the connection line SDA is occupied, the bus monitoring WDT 640 operates its own reset signal generation circuit 639, and the I ² CI / The O expander 615 is initialized.

Since the connection line SDA is also connected to other I ² CI / O expanders 615, the connection line SDA is connected to all the I ² CI / O expanders 615 to which the connection line SDA is connected.
The occupation state of DA is detected. These I ² CI / O expanders 6
15 is activated, all I ² CI / O expanders 615 to which the connection line SDA is connected are initialized.

The self-occupied WDT 641 is a connection line SD by itself (I ² CI / O expander 615).
Used to detect A occupancy. The bus controller 634 operates the self-occupied WDT 641 while operating the driver 632 to drive the connection line SDA to the low level, and stops the self-occupied WDT 641 while not driving the connection line SDA to the low level. . When the self-occupied WDT 641 operates continuously for a predetermined time, the self-occupied WDT 641 generates a reset signal in the reset signal generation circuit 639 to initialize the I ² CI / O expander 615.

As a result, a period during which the bus controller 634 itself drives the connection line SDA to a low level (a period during which the I ² CI / O expander 615 occupies the connection line SDA)
It becomes possible to monitor. The self-occupied WDT 641 starts measuring time at the timing when the connection line SDA is occupied to transmit a response signal (ACK, NACK) for the data received from the master IC, and when a predetermined time elapses, the reset signal generating circuit A reset signal is generated at 639. With this configuration, when the occupation of connection line SDA is detected by self-occupied WDT 641, only its own I ² CI / O expander 615 is reset.

FIG. 19 illustrates I ^{2 of} the decoration control device 610 that controls the decoration device 620 according to the embodiment of this invention.
FIG. 6 is a circuit diagram around a CI / O expander 615.

The I ² CI / O expander 615 has an NC terminal, a RESET terminal, and an SC as input terminals.
L terminal, SDA terminal, Vcc terminal, A0 to A3 terminal, and GND terminal are provided, and PORT0 to PORT15 are provided as output terminals.

A power source supplied to the I ² CI / O expander 615 is connected to the RESET terminal via a pull-up resistor R. For this reason, the voltage applied to the reset terminal is always maintained HIGH.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

A power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

The A0 to A3 terminals are terminals for setting individual addresses in the I ² CI / O expander 615. The individual address of the I ² CI / O expander 615 is normally expressed by 4 bits. When the power of the I ² CI / O expander 615 is applied to this terminal, “1” is given to the bus controller 634. ”Is set, and when this terminal is connected to the ground,“ 0 ”is set in the bus controller 634.

Therefore, the individual address of the I ² CI / O expander 615 shown in FIG.
0 ". The GND terminal is a terminal for grounding a voltage.

  The PORT0 terminal to the PORT15 terminal are connected to a decoration device 620 including the LEDs 0 to 15 via current limiting resistors R0 to R15. Note that one LED may be connected to one port as in PORT0, but a plurality of LEDs may be connected to one port as in PORT1-15.

One I ² CI / O expander 6 if one LED is provided for every port
15 can control up to 16 LEDs. Further, when the number of LEDs connected to each port is different, if all LEDs connected in series to one port are referred to as one type of LED, one I ² CI / O expander is used. By 615, up to 16 kinds of LEDs can be controlled.

  When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 18) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. Thus, a current flows through the LED0 to LED15 connected to the PORT0 terminal to the PORT15 terminal, and each of the LED0 to LED15 lights up.

  On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows through each LED0 to LED15, and each LED0 to LED15 is not lit.

Note that the PORT0 to PORT15 terminals of the I ² CI / O expander 615 have L
Instead of the ED, it is possible to connect a motor or a solenoid and configure the effect device using the motor or the solenoid for games. Hereinafter, I ² CI / O with reference to FIG.
A case where a motor and a solenoid are controlled using the expander 615 will be described.

FIG. 20 shows an I ² CI / O expander 61 of the decoration control device 610 according to the embodiment of this invention.
FIG. 5 is a circuit diagram around 5 and shows a case where a motor and a solenoid are controlled.

  The motor used here is constituted by a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of each phase that drive the stepping motor. In the embodiment of the present invention, the signal terminals of the respective phases of the motor are connected to the PORT0 terminal to the PORT3 terminal.

  When a voltage is applied from the driver 637 to any one of the gates of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the motor, the drain to the source of the transistors 638A to 638D to which the voltage is applied Current flows to the motor, current flows to the motor connected to the PORT0 terminal to the PORT3 terminal, and the accessory driving motor is driven.

  The connection lines connecting the PORT0 to PORT3 terminals and the motor are branched, and one of the branched connection lines is connected to a power source supplied to the motor via a diode D and a Zener diode ZD.

  The PORT terminal 15 is connected to a solenoid to be used. When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT15 terminal connected to the solenoid, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied, A current flows through a solenoid connected to the PORT 15 terminal, and an effect device (not shown) driven by the solenoid is driven.

In FIG 20, although both the motors and solenoids to I ² CI / O expander 615 is connected, connected to one I ² CI / O expander 615, the motor and the solenoid at least one only The configuration may be also possible.

For example, as or provided or provided I ² CI / O expander 615 as a group controls only the stepping motor only, the I ² CI / O expander 615 as a group to control only the solenoid dedicated Also good. With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and therefore it becomes possible to group and control only the rendering devices that require high-speed processing.

  FIG. 21 is a diagram for explaining circuit configurations of the decoration control device 610, the relay board 600, and the simple relay board 1600 according to the embodiment of the present invention. In particular, connection states related to input / output of signal lines and power supply lines are shown. It is a figure for demonstrating.

  In this figure, among the decoration control device 610, the relay board 600, and the simple relay board 1600, the branch type decoration control device 610 (for example, the decoration control device 610A) will be described. Differences between the decoration control device 610, the terminal-type decoration control device 610, the relay board 600, and the simple relay board 1600 will be described.

  In the figure, description will be made with the same reference numerals as the parts provided in the above-described branch type decoration control device 610X.

The branch type decoration control device 610 includes an upstream connector 611, a downstream connector 612 (612A, 612B), and an I ² CI / O expander 615.

  The upstream connector 611 is a connector connected to the decoration control device 610 upstream from the decoration control device 610. The downstream connectors 612A and 612B are connected to the decoration control device 610 on the downstream side of the decoration control device 610.

  In order to connect the connection line SDA to the two downstream connectors 612A and 612B, the internal connection line SDA2111 extending from the upstream connector 611 branches at a branch 2101 into a first connection line SDA2121 and a second connection line SDA2131. The first connection line SDA2121 is connected to the downstream connector 612A, and the second connection line SDA2131 is connected to the downstream connector 612B.

  Similarly, the internal connection line SCL2112 extending from the upstream connector 611 branches at a branch 2102 into a first connection line SCL2122 and a second connection line SCL2132. The first connection line SCL2122 is connected to the downstream connector 612A, and the second connection line SCL2132 is connected to the downstream connector 612B.

Further, in order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA2131 branches at the branch 2103, and the branched second connection line SDA2131 is I ² C.
The SDA terminal shown in FIGS. 19 and 20 of the I / O expander 615 is connected. Further, in order to connect the connection line SCL to the I ² CI / O expander 615, the second connection line SCL21 is used.
32 branches at the branch 2104, and the branched second connection line SCL2132 is connected to the SCL terminal shown in FIGS. 19 and 20 of the I ² CI / O expander 615. Hereinafter, the I ² CI / O expander 615, the connection line SDA connected from the branch 2103 to the I ² CI / O expander 615, and the connection line S connected from the branch 2104 to the I ² CI / O expander 615.
A configuration including CL is an I ² CI / O expander unit 2181.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Further, although not shown in FIG. 21, I ² CI
The / O expander 615 outputs signal lines (see FIG. 19) of ports 0 to 15 that drive LEDs (decoration device 620) provided in the decoration control device 610.

Further, a signal output from the I ² CI / O expander 615 of the decoration control device 610 to the upstream decoration control device 610 via the connection line SDA and an I of the decoration control device 610 from the upstream decoration control device 610. ^{2 A} Zener diode ZD2141 is connected to the internal connection line SDA2111 in order to remove noise of a signal input to the CI / O expander 615 via the connection line SDA.

  Specifically, the internal connection line SDA2111 branches at the branch 2105, the branched internal connection line SDA2111 is connected to the cathode side of the Zener diode ZD2141, and the anode side of the Zener diode ZD2141 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA2111 is released by the Zener diode ZD2141.

In addition, in order to remove noise of a signal input via the connection line SCL from the upstream decoration control device 610 to the I ² CI / O expander 615 of the decoration control device 610, the internal connection line SCL2112 has a Zener. A diode ZD2142 is connected.

  Specifically, the internal connection line SCL2112 branches at a branch 2106, the branched internal connection line SCL2112 is connected to the cathode side of the Zener diode ZD2142, and the anode side of the Zener diode ZD2142 is grounded.

  For this reason, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL2112 is released by the Zener diode ZD2142.

In addition, the I ² CI / O expander 615 of the decoration control device 610 is connected to the downstream connector 6.
The signal output to the decoration control device 610 connected to 12A via the connection line SDA, and the I ² CI / of the decoration control device 610 from the decoration control device 610 connected to the downstream connector 612A
A Zener diode ZD2143 is connected to the first connection line SDA2121 in order to remove noise of a signal input to the O expander 615 via the connection line SDA.

  Specifically, the first connection line SDA2121 branches at a branch 2107, the branched first connection line SDA2121 is connected to the cathode side of the Zener diode ZD2143, and the anode side of the Zener diode ZD2143 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SDA2121 is released by the Zener diode ZD2143.

  Similarly to the Zener diode ZD2143 connected to the first connection line SDA2121, the Zener diode ZD2145 is also connected to the second connection line SDA2131.

Further, the downstream connector 612 from the I ² CI / O expander 615 of the decoration control device 610 is used.
A Zener diode ZD2144 is connected to the first connection line SCL2122 in order to remove noise of the signal input to the decoration control device 610 connected to A via the connection line SCL.

Specifically, the first connection line SCL2122 branches at the branch 2108, the branched first connection line SCL2122 is connected to the cathode side of the Zener diode ZD2144, and the anode side of the Zener diode ZD2144 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SCL2122 is released by the Zener diode ZD2144.

  Similarly to the Zener diode ZD2144 connected to the first connection line SCL2122, the Zener diode ZD2146 is also connected to the second connection line SCL2132.

Further, from the internal connection line Vcc 2171 extending from the Vcc terminal of the upstream connector 601 connected to the connection line Vcc for supplying the power supply voltage to the I ² CI / O expander 615 of the decoration control device 610 and the GND terminal of the upstream connector 601 The extended and grounded internal connection line GND 2172 is connected via a smoothing capacitor C 2161 and a bypass capacitor CP 2162.

  The smoothing capacitor C2161 is a capacitor for smoothing the voltage waveform of the power supply, and the bypass capacitor CP2162 is a capacitor for removing noise of the power supply voltage.

For this reason, the power supply voltage supplied to the I ² CI / O expander 615 of the decoration control device 610 is smoothed by the smoothing capacitor C2161, noise is removed by the bypass capacitor CP2162, and the I ² CI / O expander is removed. The panda 615 is supplied.

  Similarly, the internal connection line Vcc2173 extending from the Vcc terminal of the downstream connectors 612A and 612B and the internal connection line GND2174 extending from the GND terminal are connected via a smoothing capacitor C2161 and a bypass capacitor CP2162. As a result, the smoothed and noise-free voltage is applied to the connection line Vcc connected to the downstream decoration control device 610.

  The branch type decoration control device 610 has been described above. Next, the connection type decoration control device 610 will be described.

  In addition to the downstream connector 612A, a Zener diode ZD2143 connected to the connection line SDA, a Zener diode ZD2144 connected to the connection line SCL, an internal connection line Vcc2173, an internal connection line GND2174, a smoothing capacitor C2161, and a bypass capacitor CP2162 are provided. The configuration is a first downstream connector portion 2182.

  In addition to the downstream connector 612B, a Zener diode ZD2145 connected to the connection line SDA, a Zener diode ZD2146 connected to the connection line SCL, an internal connection line Vcc2173, an internal connection line GND2174, a smoothing capacitor C2161, and a bypass capacitor CP2162 are provided. The configuration is a second downstream connector portion 2183.

  In the case where the decoration control device 610 is a connection type, since only one downstream connector is provided in the board, the downstream connector 612A exists but the downstream connector 612B does not exist.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are configured so as not to branch at the branches 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 are not present, which is different from the branch type decoration control device 610. It becomes composition.

The connection type decoration control device 610 is different from the branch type decoration control device 610 in that there is no electronic component constituting the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the terminal type decoration control device 610 will be described.

  In the case where the decoration control device 610 is a terminal type, the downstream connector is not provided in the board, and therefore neither of the downstream connectors 612A and 612B exists.

Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 do not branch at the branches 2101, 2102, 2103, 2104, and the I ² CI / O expander 615
The configuration is different from that of the branch-type decoration control device 610 in that it is connected to.

  The terminal-type decoration control device 610 is also different from the branch-type decoration control device 610 in that there are no electronic components constituting the first downstream connector portion 2182 and the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the relay board 600 will be described.

  Since the relay board 600 is configured to include only one downstream connector in the board, similarly to the connection type decoration control device 610, the downstream connector 612A exists but the downstream connector 612B does not exist.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are configured not to branch at the branches 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 do not exist. It becomes.

  However, the relay board 600 is different from the connection type decoration control device 610 in that it includes a pull-up resistor for pulling up the voltages of the connection line SDA and the connection line SCL.

  Specifically, as shown in FIG. 21, in the relay board 600, the voltages of the upstream connection line SDA connected to the first master IC 570a and the downstream connection line SDA connected to the decoration control device 610 are set. A pull-up resistor R2151 for pulling up is connected to the first connection line SDA2121. Similarly, a pull-up resistor R2152 for pulling up the voltage of the upstream connection line SCL connected to the first master IC 570a and the downstream connection line SCL connected to the decoration control device 610 includes the first connection line. Connected to SCL2122.

  More specifically, the first connection line SDA2121 branches at the branch 2109, and the branched first connection line SDA2121 is connected to the pull-up resistor R2151. Similarly, the first connection line SCL2122 branches at the branch 2110, and the branched first connection line SCL2122 is connected to the pull-up resistor R2152. Hereinafter, the pull-up resistor R2151 for pulling up the voltage of the connection line SDA and the pull-up resistor R2152 for pulling up the voltage of the connection line SCL are collectively referred to as a pull-up resistor unit 2180.

  Next, the simple relay board 1600 will be described.

The simple relay board 1600 includes a plurality of downstream connectors (downstream connectors 612A and 612B) in the board, similarly to the branch type decoration control device 610. However, the simple relay board 1600 does not include a circuit corresponding to the I ² CI / O expander unit 2181. Instead, a circuit corresponding to the pull-up resistor unit 2180 provided in the relay board 600 is provided. This is a configuration different from the branch type decoration control device 610. Other configurations are the same as those of the branch type decoration control device 610.

  In the present embodiment, the configuration of the pull-up resistor 2180 described above is provided only on the relay board 600 and the simple relay board 1600, and is not provided in the decoration control device 610 or the effect control device 550. However, as long as the levels of the connection line SDA and the connection line SCL can be correctly generated, the decoration control device 610 and the effect control device 550 may be provided. In short, the pull-up resistors R2151 and 2152 only need to be provided at locations where the voltage Vcc can be supplied to the drain terminals of the transistors that drive the connection line SDA and the connection line SCL.

  For example, if the pull-up resistors R2151 and 2152 are provided in the first master IC 570a, it is not necessary to provide the pull-up resistor unit 2180 in the relay board 600, the simple relay board 1600, or the decoration control device 610.

  FIG. 22 is an explanatory diagram of the slave address 2200 included in the data output from the effect control device 550 to the decoration control device 610 according to the embodiment of this invention.

  The slave address 2200 includes a fixed address part 2201 composed of upper 3 bits and a variable address part 2202 composed of lower 5 bits.

The fixed address unit 2201 is preset with a value of “110” and cannot be changed by the I ² CI / O expander 615.

The variable address unit 2202 can be set by the I ² CI / O expander 615. The variable address unit 2202 includes A0 to A0 of the I ² CI / O expander 615 to be controlled.
A 4-bit I ² CI / O expander address 2203 corresponding to the pattern set at the terminal of A3, and 1-bit R / W identification data 2204 indicating whether the data is a read request or a write request It is comprised by.

  Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 2204.

FIG. 23 shows the I ² CI / O expander address table 2300 according to the embodiment of this invention.
It is explanatory drawing of.

The I ² CI / O expander address table 2300 is a table managed by the first master IC 570a. The I ² CI / O expander address table 2300 shows the correspondence between the slave address 2301 and the I ² CI / O expander address 2302.

The slave address 2301 stores the slave address of the decoration control device 610 specified by the effect control device 550 as a transmission / reception target. As described above with reference to FIG. 20, the slave address includes a fixed address portion consisting of the upper 3 bits and a 4-bit I ² CI /
It is configured by combining an O expander address and 1-bit R / W identification data.

In the I ² CI / O expander address 2302, as described above with reference to FIGS.
A 4-bit I ² CI / O expander address corresponding to each slave address is registered.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” (shaded entries in FIG. 23) are the I ² CI / O expanders 61.
5 cannot be used as a unique address for identifying each other.

  The address “1000” is used as a default value at power-on of an address (all call address) specified when a common command is output to all the decoration control devices 610. The address “1011” is a common address used when all the decoration control devices 610 connected to the first master IC 570a are unconditionally reset by software.

As described above, since there are 14 addresses that can be set in the I ² CI / O expander 615 of the decoration control device 610, the effect control device 550 controls the 14 I ² CI / O expanders 615. be able to. Since each decoration control device 610 includes PORT0 to PORT15, it is possible to control 16 (in other words, 16 types) LEDs. Therefore, the effect control device 550 can control 224 (in other words, 224 types) LEDs.

FIG. 24 is a diagram for describing work registers assigned to the output setting register 635 provided in the I ² CI / O expander 615 according to the embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615.

Work register, I ² CI / O Aix information and for performing settings that are predefined for Panda 615, I ² CI / O Aix effect device connected to the expander 615 (decoration device 620, for example, The information for specifying the output mode of LED) is stored.

  In addition, the control register stores information defining a procedure for writing data to the work register. The work register is configured to store a plurality of pieces of information in different storage areas, and a different register number is assigned to each storage area.

The register number “00h” and the register number “01h” are the I ² CI / O expander 6
This corresponds to a mode register for performing 15 initial settings. The register name “MODE1” is assigned to the storage area of the register number “00h”. The register name “MODE2” is assigned to the storage area of the register number “01h”. When a value is written in the storage areas of the register numbers “00h” and “01h”, the I ² CI / O is based on the written value.
The expander 615 is initialized.

Note that bit 3 (OCH) of the “MODE2” register is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I ² CI / O expander 615 is actually reflected in the effect device. . In the embodiment of the present invention, as described in FIG. 18, “0” is set, and when the stop condition is received, the effect control data stored in the output setting register 635 is output, and the effect device Is set to actually control the output state.

Parameters to be controlled such as LEDs included in the decoration device 620 are set in the register numbers “02h” to “11h” (register names “PWM0” to “PWM15”). When a value is written to any of the storage areas of register numbers “02h” to “11h”, I ² CI /
Among the 16 LEDs constituting the light emitting device (decoration device 620) connected to the O expander 615, the luminance of the LED corresponding to the register number in which the value is written is adjusted based on the written value. . For example, when a value is written in the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 19 is adjusted.

Note that the I ² CI / O expander 615 can also control a movable object such as a motor or a solenoid as described above. When a solenoid is connected to the I ² CI / O expander 615, the register number corresponding to the port to which the solenoid is connected is operated by energizing the solenoid or not energized. A value indicating whether to do is written. When a motor is connected to the I ² CI / O expander 615, a value indicating the target rotational position of the motor is written in the register number corresponding to the port to which the motor is connected.

  In the register number “12h” (register name “GRPPWM”) and the register number “13h” (register name “GRPFREQ”), parameters for specifying the operation pattern of the entire control target are set. When a value is written in the storage areas of the register numbers “12h” and “13h”, the blinking pattern of the entire LED (16 LEDs) is set based on the written value. Specifically, a duty cycle that is an on / off ratio of the entire LED is set in the register number “12h”, and a blinking cycle of the entire LED is set in the register number “13h”.

  In register numbers “14h” (register name “LEDOUT0”) to “17h” (register name “LEDOUT3”), the output state of the LED controlled by each port is set. Each register can set four LED output states.

  When a value is written in the storage area of the register number “14h”, the output states of the LEDs 0 to LED3 are set based on the written value. Similarly, the output state of LED4 to LED7 is stored in the storage area of register number “15h”, the output state of LED8 to LED11 is stored in the storage area of register number “16h”, and the LED12 to LED15 are stored in the storage area of register number “17h”. Output status is set.

  Sub-addresses are set in the register numbers “18h” to “1Ah” (register names “SUBADR1” to “SUBADR3”). When values are written in the storage areas of the register numbers “18h” to “1Ah”, the first subaddress to the third subaddress are set based on the written values.

  In the register number “1Bh” (register name “ALLCALLADR”), an all call address for outputting a command to all the decoration control devices 610 is set. The all call address is used, for example, when the initialization processing is executed in all the decoration control devices 610 when the power is turned on.

  FIG. 25 is an explanatory diagram of a start condition and a stop condition in which the master IC according to the embodiment of this invention outputs data via the connection line SDA and the connection line SCL.

  The connection line SCL has a signal level of HIGH when data is not transmitted. When outputting data to the decoration control device 610, the master IC changes the signal level of the connection line SCL from LOW to HIGH so that the decoration control device 610 acts as a strobe signal for taking in the data of the connection line SDA.

  The connection line SDA has a high signal level when data is not transmitted, and data is output from the connection line SDA in accordance with the clock signal of the connection line SCL.

The master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal serving as a start condition indicating that data output starts. .

The I ² CI / O expander 615 of the decoration control device 610 includes a connection line SDA and a connection line S.
When a signal serving as a start condition is input from CL, it is recognized that data output is started.

  The master IC changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal that becomes a stop condition indicating that the output of data ends. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that the output of data is finished when a signal serving as a stop condition is input. In the embodiment of the present invention, as described above, when the decoration control device 610 receives a signal that is a stop condition, control of the effect device (decoration device 620) controlled by the decoration control device 610 is started.

  FIG. 26 is a timing chart at which the decoration control device 610 to which the data output from the master IC according to the embodiment of the present invention is input outputs a response signal.

  The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

  Then, the decoration control device 610 outputs a response signal to the master IC via the connection line SDA immediately before the start condition is satisfied and immediately before the number of changes in the signal level of the connection line SCL reaches nine. In other words, the decoration control device 610 outputs a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking the 8th bit data from the connection line SDA. To do.

  As shown in FIG. 26, a response signal (ACK response signal) indicating that data reception has been successful is indicated by a LOW level, and a response signal (NACK response signal, indicating that data reception has failed), In the figure, this corresponds to no ACK output) is indicated by a HIGH level.

  Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC waits for a response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

  FIG. 27 is a timing chart of signal levels of connection line SDA and connection line SCL when the master IC according to the embodiment of the present invention outputs effect control data.

  First, when starting output of data, the master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, thereby indicating a start condition signal. And the decoration control device 610 is notified that data output is to be started.

  Next, the master IC outputs the slave address of the decoration control device 610 to be controlled, which consists of a total of 7 bits. Further, the master IC outputs information indicating whether the request is a write request, which is a read request, at the eighth bit.

  The master IC receives a response signal from the decoration control device 610 when the signal level of the connection line SCL becomes HIGH for the ninth time. Therefore, if the response signal is an ACK response signal, the signal level of the connection line SDA is LOW. If the response signal is NACK, the signal level of the connection line SDA changes to HIGH.

  Next, after outputting the address data, the master IC outputs the data with a bit number that is a multiple of eight. Further, after the eighth bit of data is output, the ninth bit of data is output after an ACK response signal is input. Thereafter, when data of a bit corresponding to a multiple of 8 is output, after confirming that an ACK response signal is input, a (multiple of 8 + 1) th bit is output and all data is output. Repeat until.

  If the master IC outputs a bit that is a multiple of 8 after the data has been output and the ACK response signal is not input even after a predetermined time has elapsed, the master IC assumes that the data transmission has failed and starts again. Send the condition. Next, the address data is output again via the connection line SDA, and the data is output again from the first bit while confirming the ACK response signal.

  The master IC outputs the signal indicating the stop condition after outputting the data of the last bit of the data and waiting for the ACK response signal to be input.

  In FIG. 27, a total of 24 bits (slave address 8 bits, data 16 bits) of data is output after the signal indicating the start condition is output until the signal indicating the stop condition is output. Depending on the size of data to be transmitted, it may be 24 bits or more, or 24 bits or less.

FIG. 28 shows the case where the master IC according to the embodiment of the present invention designates the individual address of the slave and sets the effect control data in the decoration control device 610 and the master IC and the I ² CI / O.
It is a figure explaining the format of the data transmitted / received between the expanders 615. FIG.

The 8-bit data 2801 that is output first includes an address “A0 to A6” of the decoration control device 610 that is a target of data transmission, and a 1-bit that indicates whether the data is a read request or a write request. R / W identification data is included. Among the addresses “A0 to A6”, “A4 to A6” are fixed address portions having a value “110”, and “A0 to A3” are set to terminals A0 to A3 of the I ² CI / O expander 615. (Refer to FIG. 19). The data 2801 is data corresponding to “ADDRESS” and “R / W” in FIG.

The 8-bit data 2802 to be output next includes setting data for the control register assigned to the output setting register 635 (see FIG. 18) of the I ² CI / O expander 615. Data 2802 is data corresponding to “DATA” transmitted first in FIG.

  Here, the control register will be described. The control register consists of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters for designating the writing or reading method to the work register of the output setting register 635, and the lower 5 bits “D0 to D4” are the work. This is a register address that specifies an access start position (a start position at which writing starts or a start position at which reading starts) in the register.

The auto-write parameter is accessed by the master IC including only the access start position area specified by the register address (auto-increment is prohibited) or including the area adjacent to the access start position area specified (auto-increment). (Specifically, “000”, “100”, “101”, “110”, “111”) can be set.

  When a value of “000” is set in the automatic writing parameter, auto-increment is prohibited, and only the area at the access start position specified by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is “10100”, only the storage area with the register number “14h” is accessed, and the other storage areas are not accessed. That is, it is used when only the value of the storage area of a specific register address is changed. When the values of the storage areas of a plurality of register addresses are changed continuously, the address designation can be omitted by permitting auto-increment as described below.

  When the value of “100” is set in the auto-write parameter, auto-increment is permitted, and after accessing the area at the access start position specified by the register address, access is made sequentially while moving the area in the direction of increasing the register number. repeat. Then, after accessing the storage area where the register number is “1Bh” at the end, the storage area where the register number is “00h” is accessed and accessed again sequentially while moving the area in the direction in which the register number increases. repeat. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... (Ie, all areas) are repeatedly accessed.

  When the value of “101” is set in the automatic write parameter, the register number is set after accessing the area at the access start position specified by the register address, as in the case of setting the value of “100” in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “11h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the section where the register numbers are “02h” to “11h”. The recording area (area relating to LED brightness adjustment) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. After accessing the storage area where the register number is “11h”, the area where the register number is “02h” → “03h” → ··· “11h” → “02h” → “03h” → ··· , Repeatedly access.

  When the value “110” is set in the automatic write parameter, the register number is set after accessing the area at the access start position specified by the register address, as in the case where the value “100” is set in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “12h” is accessed, and thereafter, the section where the register numbers are “12h” to “13h”. The recording area (area related to the LED blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. Then, after accessing the storage area where the register number is “13h”, the area where the register number is “12h” → “13h” → “12h” → “13h” →... Is repeatedly accessed.

When the value “111” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case of setting the value of, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the section where the register numbers are “02h” to “13h”. The recording area (area related to LED brightness and blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. After accessing the storage area where the register number is “13h”, the area where the register number is “02h” → “03h” → ··· “13h” → “02h” → “03h” → ··· , Repeatedly access.

  Here, returning to the description of FIG. 28, the work register setting data 2803 is output following the control register setting data 2802. The setting data 2803 is data corresponding to “DATA” transmitted after the second in FIG.

  When the automatic writing parameter is “000”, the setting data 2803 is 8-bit data for updating one storage area designated by the register address. When the automatic writing parameter is set to a value other than “000”, the setting data 2803 is a multiple of 8 necessary for repeatedly updating a plurality of areas starting from the storage area specified by the register address. Bit data.

FIG. 29 shows the case where the master IC according to the embodiment of the present invention designates the slave individual address and sets the effect control data in the decoration control device 610 and the master IC and the I ² CI / O.
It is the figure which applied the specific numerical value to the production control data transmitted / received between the expanders 615. FIG. 29 shows effect control data for prohibiting auto-increment and updating only one specific storage area of the work register. Specifically, the PORT0 terminal of the I ² CI / O expander 615 A case where the light emission state of the LED connected to the PORT3 terminal is updated will be described.

First, “1101100” indicating the slave address of the I ² CI / O expander 615 of the destination decoration control device 610 is assigned to the 8-bit data 2901 output first.

The 8-bit data 2902 to be output next is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and LED output data. Value to be included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

  Note that “000” is designated in the auto-write parameter to prohibit auto-increment.

Next, the output 8-bit data 2903 includes data for setting the light emission mode of the decoration device 620 controlled by the destination decoration control device 610. Specifically, data set in the LEDOUT0 register is assigned. As a result, I ² CI /
The light emission state (lighting, extinguishing, blinking, etc.) of the LED connected to the PORT0 terminal to the PORT3 terminal of the O expander 615 is designated, and the LED emits light in the designated state.

In this way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I ² CI / O expander 615 is controlled, the other PORT terminal I ² CI / O expander 615 (PORT4~PORT15) also Individual control is possible by designating the value of the control register data 2902 and setting the output data 2903. Even if a motor or a solenoid is connected to the PORT terminal, the same control is performed.

  FIG. 30 is a diagram illustrating the order in which the production control data of the master IC according to the embodiment of the present invention is transmitted. In FIG. 30, the order in which each data included in the effect control data is transmitted when auto-increment is permitted and all the storage areas of the work register are updated is defined.

  First, the master IC transmits 8-bit data (data having the same format as the data 2801 in FIG. 28) that can specify the individual address of the decoration control device 610 to be controlled.

Next, the master IC transmits data set in the control register of the output setting register 635 of the I ² CI / O expander 615 to be controlled (data having the same format as the data 2802 in FIG. 28). In FIG. 30, in order to update all the storage areas of the work register by permitting auto-increment, “100” is designated as the automatic write parameter, and the register address designating the start position of writing or reading is “00h” which is the head area of the work register is designated.

For this reason, in the I ² CI / O expander 615 of the decoration control device 610 to be controlled after receiving the control register set value, the storage area (MODE1 register) of the register number “00h” is updated first. It will be.

Next, after transmitting the control register set value, the master IC transmits a value (total of 8 bits) to be written to the MODE1 register. When the I ² CI / O expander 615 receives the write value, it updates the value of the MODE 1 register, increments the register number, and prepares to update the next “01h” storage area (MODE 2 register). .

Further, the master IC transmits values (total 8 bits) to be written to the MODE2 register, and thereafter transmits the set values in order to the remaining storage area registers whose register numbers are “02h” to “1Bh”. . Each time the I ² CI / O expander 615 receives the write value, the I ² CI / O expander 615 updates the value of the corresponding register, increments the register number, and repeats the preparation for updating the next storage area. The values of all the registers “00h” to “1Bh” assigned to are updated.

When the I ² CI / O expander 615 updates the storage area of “1Bh” which is the last of the work registers, the I ² CI / O expander 615 changes the register number to “00h” and waits for the update of the MODE1 register.

31, when the master IC of the embodiment of the present invention initializes the I ² CI / O expander 615, the format of the initialization instruction data transmitted from the master IC to the I ² CI / O expander 615 FIG.

  When the CPU 551 of the effect control device 550 instructs the master IC to initialize the decoration control device 610, the master IC transmits initialization instruction data to all the decoration control devices 610 connected to the master IC. .

  The 8-bit data 3101 output first includes a fixed address “110” shown in FIG. 29 and a reset address “1011” (see FIG. 23), which is a common address. The data 3101 corresponds to “ADDRESS” in FIG. 27, and “0” indicating writing is set in the bit of “R / W”.

  The first predetermined value “10100101” is set in the 8-bit data 3102 to be output next, and the second predetermined value “01011010” is set in the 8-bit data 3103 to be output next. The data 3102 corresponds to “DATA” transmitted first in FIG. 27, and the data 3103 corresponds to “DATA” transmitted second in FIG.

When all the I ² CI / O expanders 615 connected to the master IC receive initialization instruction data including a reset address, a first predetermined value, and a second predetermined value, the I ² CI / O expander 615 initializes itself.

The reason why both the first predetermined value and the second predetermined value are output after the reset address is output is that the master IC does not transmit the reset address “1011”, but the influence of noise or the like. This is because the I ² CI / O expander 615 erroneously fetches the reset address “1011” to prevent initialization from being executed at an incorrect timing.

Further, the reset address is an address common to all (in other words, a plurality) I ² CI / O expanders 615, unlike the individual address. Therefore, only transmit once initialization instruction data including the reset address, since all will be initialized by selecting I ² CI / O expander 615 (s), I ² CI / O Aix Compared with the method of individually selecting the panda 615 and instructing initialization, it is possible to instruct initialization at high speed.

  In FIG. 31, the first predetermined value and the second predetermined value are different from each other, but may be the same value. Further, either the first predetermined value or the second predetermined value may be transmitted once.

  FIG. 32 is a diagram illustrating the abnormality determination table 3200 of the first master IC 570a according to the embodiment of this invention.

The abnormality determination table 3200 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3200 is provided for monitoring the connection state between the first master IC 570a of the effect control device 550 and the I ² CI / O expander 615 connected to the first master IC 570a. The abnormality determination table 3200 has each I ² CI /
Information corresponding to the O expander 615 is stored.

  The abnormality determination table 3200 includes an I / O expander address 3201, a slave address 3202, an error counter 3203, a comparison value 3204, and an error flag 3205.

The I / O expander address 3201 includes an I ² connected to the first master IC 570a.
This corresponds to the addresses (see FIG. 19) set in the terminals A0 to A3 of the CI / O expander 615.

In the slave address 3202, the slave address registered in the I ² CI / O expander address table 2300 shown in FIG. 23 is registered.

The error counter 3203 is sent from the first master IC 570a to the I ² CI / O expander 6
The effect control data is transmitted to 15 and incremented when the ACK cannot be received twice consecutively from the I ² CI / O expander 615.

In the comparison value 3204, a value to be compared with the value of the error counter 3203 is registered in order to determine whether or not a failure has occurred in the I ² CI / O expander 615. Note that the value of the comparison value 3204 may be set according to the type of the rendering device to be controlled.

In the error flag 3205, an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615 is registered.

The method for determining whether or not a failure has occurred in the I ² CI / O expander 615 will be described in detail. If the value of the error counter 3203 reaches a predetermined value set in the comparison value 3204, an error will occur. “ON” is set in the flag 3205, and it is registered that a failure has occurred in the I ² CI / O expander 615 corresponding to the entry.

  In the embodiment of the present invention, as will be described later, the production control data output process (see FIG. 37) is executed in synchronization with a VDP interrupt (a period of about 33.3 ms).

As described above, ² from the first master IC 570a to the I ² CI / O expander 615
If the ACK from the I ² CI / O expander 615 cannot be received for the transmission of the presentation control data for the first time, the error counter 3003 is incremented.

Therefore, when an abnormality has occurred, the execution period of the data output process is 33.3 ms and the comparison value 3004 is “300”, so that I ² CI is 33.3 ms × 300≈10 s.
The occurrence of an abnormality relating to the / O expander 615 is detected.

  FIG. 33 is a diagram illustrating the abnormality determination table 3300 of the second master IC 570b according to the embodiment of this invention.

Similar to the abnormality determination table 3200 of the first master IC 570a, the abnormality determination table 3300 of the second master IC 570b is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3300 is provided to monitor the connection state between the second master IC 570b of the effect control device 550 and the I ² CI / O expander 615 connected to the second master IC 570b. The abnormality determination table 3300 includes each I ² CI according to the connection state.
Information corresponding to the / O expander 615 is stored. The configuration of the abnormality determination table 3300 is the same as that of the abnormality determination table 3200 of the first master IC 570a.

  In the embodiment of the present invention, since there is no decoration control device 610 connected to both the first master IC 570a and the second master IC 570b, the I / O expander address of each decoration control device 610 to be controlled is the master IC. Set for each. Therefore, in FIG. 32 and FIG. 33, the same value I / O expander address is set. Since only one address can be set as the I / O expander address, it is necessary to set a common address when a plurality of master ICs control one decoration control device 610.

The master IC according to the embodiment of the present invention includes a plurality of registers that are used to configure device operation and transmit / receive serial data. The command register (REG) 581 shown in FIGS. 11 and 12 is one of such registers, and instructs the connected decoration control device 610 to output a start condition or a stop condition.

  The effect control device 550 transmits an effect instruction to the decoration control device (slave) 610 via the master IC, and executes various effect processes. FIG. 34 shows a procedure for initializing each slave, and FIG. 35 shows an outline of a procedure for transmitting the effect control data to each slave.

  FIG. 34 illustrates information transmitted and received between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when each decoration control device (slave) according to the embodiment of the present invention is initialized (reset). It is a figure to do.

  When the slave initialization start process is started, the CPU 551 of the effect control device 550 sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG 581 (3401).

  In accordance with the information (STO, STA) set in the command REG581, the master IC first outputs a stop condition to each decoration control device (slave) 610 to be controlled, and then outputs a start condition (3411). . By outputting a stop condition, each slave is notified that data transmission has been completed, and thereafter, by outputting a start condition, preparation for receiving an input of a command is completed in each slave.

  When outputting the start condition, the master IC inputs an interrupt signal (INT) to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (1) of the transmission instruction data (3402). In the transmission resumption process (1) of the transmission instruction data, a reset address is set in the output buffer 572. The reset address is a fixed address determined in advance for resetting each slave. At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs predetermined data (reset command) to the reset address set in the output buffer 572 (3412). The reset command corresponds to the first predetermined value (data 3102) and the second predetermined value (data 3103) described in FIG.

  When the master IC outputs the reset address, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (2) of the transmission instruction data (3403). In the transmission restart process (2) of the transmission instruction data, the first half value of the reset command is set in the output buffer 572. The first half value of the reset command corresponds to the first predetermined value (data 3102) described in FIG. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the first half value of the reset command set in the output buffer 572 (3413).

  Thereafter, when the master IC outputs the first half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (3) of the transmission instruction data (3404), and sets the latter half value of the reset command in the output buffer 572. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the latter half value of the reset command set in the output buffer 572 (3414). The latter half value of the reset command corresponds to the second predetermined value (data 3103) described with reference to FIG.

Further, when the master IC outputs the second half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (4) of the transmission instruction data (3405), sets “0” to the STA of the command REG581, sets “1” to the STO, and outputs the stop condition to the master IC. Instruct.

  The master IC outputs a stop condition to each slave according to the information set in the command REG 581 (3415).

  Through the above processing, each slave is initialized. If the initialization fails (3406), the process is restarted from step 3402.

  FIG. 35 shows information transmitted and received between the CPU 551 and the master IC (first master IC 570a or second master IC 570b) when transmitting the effect control data to each decoration control device (slave) according to the embodiment of the present invention. FIG.

  When performing the effect control, the CPU 551 of the effect control device 550 first sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG581 (3501).

  The master IC outputs a stop condition to each slave based on the values (“1”) set in the STA and STO of the command REG 581, and then outputs a start condition (3511).

  When the master IC outputs a start condition to each slave, the master IC is ready to receive the presentation control data at each slave. Therefore, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets presentation control data indicating the address of the slave to be controlled and the control content in the output buffer 572 (3502). At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs the address and effect control data set in the output buffer 572 to each slave (3512). At this time, the slave corresponding to the output address executes effect processing based on the received effect control data.

  When the master IC outputs the address and the effect control data to each slave, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets “1” to the STA of the command REG 581 and “0” to the STO (3503). Thereafter, the master IC outputs a so-called restart condition that outputs a start condition again (3513).

  Subsequently, the CPU 551 and the master IC perform similar processing by designating another address (3504, 3514, 3505, 3515). When the CPU 551 completes the output of the presentation control data for the last nth slave (3506), and the master IC outputs the presentation control data to the corresponding slave (3516), the output of all the data is completed, so Output the condition. Specifically, when the master IC has finished outputting the production control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt, and the CPU 551 that generated the interrupt generates “0” in the STA of the command REG581 ", STO is set to" 1 "(3507), and then the master IC outputs a stop condition (3517).

  FIG. 36 is a diagram illustrating the stage of transmitting the effect control data from the effect control device 550 according to the embodiment of the present invention to the master IC (first master IC 570a or second master IC 570b).

  When the slave output data editing process described later is executed, the CPU 551 of the effect control device 550 secures an output data preparation area in the RAM 553 and stores the effect control data for each slave in the output data preparation area.

  In addition, the output data preparation area is further divided for each slave, and stores the production control data corresponding to the address and production content corresponding to each slave. Specifically, the address corresponds to the data of the transmission order 1 shown in FIG. 30, and the effect control data corresponds to the data of the transmission orders 2 to 30 shown in FIG.

  Further, the CPU 551 further secures an output data save area in the RAM 553 so that untransmitted effect control data is not overwritten, and saves the data stored in the output data preparation area by the slave output data save process to the output data save area. Let Thereafter, the saved data is set in the output buffer 572 of the master IC at a predetermined timing.

  The output data preparation area and the output data saving area are secured in the RAM 553 for each master IC. In the embodiment of the present invention, areas corresponding to the first master IC 570a and the second master IC 570b are secured.

  FIG. 37 is a flowchart showing a procedure of processing performed by the effect control device 550 according to the embodiment of this invention.

  The processing shown in FIG. 37 is executed by the CPU 551 of the effect control device 550.

  When the production control device 550 is turned on, the production control device 550 first executes the processing of steps 3701 to 3706, and in the processing of step 3707, the image update signal generated in the VDP 556 (synchronized with the image update cycle). The 33.3 ms-second synchronization signal) is input to the CPU 551 as an interrupt signal. Thereafter, each time the synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551 as an interrupt signal, the processing of steps 3705 to 3721 is repeatedly executed.

  First, the effect control device 550 executes initialization processing including initialization of the RAM 553 of the effect control device 550 (3701). At this time, an initialization stage number relating to the first master IC 570a described later and an initialization stage number relating to the second master IC 570b are both set to “0”.

  Then, the effect control device 550 inputs a reset pulse to the first master IC 570a and the second master IC 570b via the output I / F 558a and the NOR gate circuit 561, and initially sets the first master IC 570a and the second master IC 570b in hardware. (3702).

Subsequently, the effect control device 550 initializes the I ² CI / O expander 615 of all the decoration control devices 610 connected to the first master IC 570a in order to initialize the first master IC 5.
First slave IC 570a side slave initialization start processing for outputting initialization instruction data from 70a is executed (3703). Similarly, in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the second master IC 570b, the second master IC
The second master IC 570b side slave initialization start process for outputting initialization instruction data from 570b is executed (3704). Details of the slave initialization start process will be described with reference to FIG.

Further, the effect control device 550 waits until both the initialization stage number related to the first master IC 570 and the initialization stage number related to the second master IC 570b become “0” (3705). The initialization stage number is a number indicating the progress of the initialization process for each of the first master IC 570a and the second master IC 570b, and is “0” immediately after the presentation control device 550 is activated immediately after the power is turned on. However, when the initialization process is started, it is incremented from “1” to “4” step by step, and when the initialization process is completed, it is returned to “0” again. In the initialization instruction data transmission restart process described with reference to FIG. 42, processes corresponding to the set initialization stage number are sequentially executed.

  When the initialization of all the masters and slaves is completed, the effect control device 550 permits the reception of the synchronization signal (VDP interrupt) synchronized with the image update cycle and the reception of the timer interrupt from the VDP 556 (3706).

  As described with reference to FIG. 36, the effect control device 550 executes slave output data saving processing for saving the effect control data stored in the RAM 553 so as not to be overwritten (3707). As described above, the output data saved in the save area is set in the master IC at a predetermined timing.

  Then, in order to display the image on display device 53, effect control device 550 outputs data serving as a command to display an image on VDP 556 (3708). Furthermore, sound control data is output to the sound LSI 557 in order to output sound from the speaker 30 according to the gaming state. The sound LSI 557 causes the speaker 30 to output sound based on the input sound control data (3709).

  Next, the effect control device 550 executes slave output start processing for outputting effect control data from the first master IC 570a and the second master IC 570b to the decoration control device 610 (3710). The decoration control device 610 controlled here mainly controls a light emitter such as an LED, and is a light emission control device or a light emission control slave. Details of the slave output start processing will be described later with reference to FIG.

  When the slave output start process is completed, the effect control device 550 edits the next data output to the VDP 556 (3711), and further edits the sound control data output to the sound LSI 557 (3712).

  Further, the effect control device 550 executes a slave output data editing process for editing the effect control data to be transmitted to the decoration control device 610 that controls the light emitter (3713). In the slave output data editing process, as described with reference to FIG. 36, the production control data of each slave is generated and stored in the output data preparation area secured on the RAM 553.

  Next, the effect control device 550 refers to the abnormality determination table 3200 shown in FIG. 32, and executes an error determination process related to the light emission control slave connected to the first master IC 570a (3714).

  In the error determination process, the effect control device 550 determines whether or not the error flags 3205 of the entries corresponding to the light emission control slaves in the abnormality determination table 3200 are all “ON”, that is, an error occurs in all the light emission control slaves. It is determined whether or not. In other words, it is determined whether or not there is at least one light emission control slave in which the error flag 3205 is “OFF”. If it is determined by this error determination process that an error has occurred in all the light emission control slaves, the conditions for resetting all the light emission control slaves connected to the first master IC 570a and the first master IC 570a are satisfied. It is assumed that.

  The effect control device 550 determines whether or not the reset condition is satisfied based on the result of the error determination process in step 3714 (3715). As described above, when the error flags 3205 of all the light emission control slaves are “ON” at the time of the error determination process in step 3714, it is determined that the reset condition is satisfied.

When it is determined that the reset condition is satisfied (the result of 3715 is “Y”), the effect control device 550 initializes the first master IC 570a (3716), and all the I connected to the first master IC 570a. ² The first master IC 570a side slave initialization start process for outputting initialization instruction data simultaneously to the CI / O expander 615 (decoration control device 610) is executed (3717).

As described above, when it is determined that the reset condition is satisfied, in step 3717, all the I ² CI / O expanders 615 connected to the first master IC 570a are instructed to initialize at the same time. To do. That is, since all the I ² CI / O expanders 615 are selected and initialized at the same time, it is faster than the method of individually selecting the I ² CI / O expanders 615 and instructing the initialization. Can be initialized to I ²
The CI / O expander 615 can be quickly returned to a normal state. At this time, the CPU 551 writes the initialization instruction information to the reset REG 573 via the bus 563, thereby resetting the first master IC 570a in software.

  If it is determined that the reset condition is satisfied in the process of step 3715, an abnormality may have occurred in the first master IC 570a. Therefore, the first master IC 570a is also initialized in the process of step 3716. Yes.

  Since the first master IC 570a functions as signal level control means for controlling the signal levels of the connection lines SDA and SCL in response to a command from the CPU 551, an abnormality relating to data transmission has occurred in all the light emission control devices. In this case, an abnormality may have occurred in the first master IC 570a itself.

  Therefore, if an abnormality related to data transmission occurs in all the decoration control devices 610, the first master IC 570a is initialized by the CPU 551 (arithmetic processing means) just in case. Thus, even if an abnormality has occurred in the first master IC 570a, the first master IC 570a can be reliably controlled.

  Further, the effect control device 550 similarly executes error determination processing for the second master IC 570b (3718), and determines whether or not the reset condition is satisfied (3719). If the reset condition is satisfied, the second master IC 570b is reset (3720), and the slave initialization start processing on the second master IC 570b side for initializing the slave connected to the second master IC 570b is executed. (3721). Thereafter, it waits until a synchronization signal is input from the VDP 556 to the CPU 551.

As described above, in the process shown in FIG. 37, the first master IC 570a and the second master IC 570b of the effect control device 550 synchronize with the cycle of updating the image of the display device 53, and the I ² CI / The effect control data is transmitted to the O expander 615. And
The I ² CI / O expander 615 uses the decoration device 620 based on the received effect control data.
Therefore, the effect on the display device 53 and the effect on the decoration device 620 are harmonized and does not give the player a sense of incongruity.

In addition, the first master IC 570a and the second master IC 570a are synchronized with the cycle of updating the image of the display device 53.
Each time the decoration control device 610 receives the effect control data transmitted from the master IC 570b, the value of the work register (see FIG. 24) is updated by the I ² CI / O expander 615. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

  In addition, since the error determination process is executed in steps 3714 and 3718 in synchronization with the cycle of updating the image of the display device 53, the frequency for determining the error can be set appropriately. That is, if the error determination process is executed too frequently, the processing load on the CPU 551 of the effect control device 550 increases. Conversely, if the error determination process is executed too little, the occurrence of an abnormality can be detected at an appropriate timing. Disappear. By performing the error determination in synchronization with the cycle of updating the image of the display device 53, it becomes possible to detect the error at an appropriate timing, and to appropriately cope with the occurrence of a defect in each process.

  FIG. 38 is a flowchart illustrating a procedure of slave initialization start processing on the first master IC 570a side and slave initialization start processing on the second master IC 570b side according to the embodiment of this invention.

  The slave initialization start process on the first master IC 570a side is executed in steps 3703 and 3717 in FIG. 37, and the slave initialization start process on the second master IC 570b side is the same process executed in step 3704 or step 3721. .

  In the initialization start process on the first master IC 570a side, first, the CPU 551 of the effect control device 550 prohibits master interruption and time interruption (3801). Then, the first master IC 570a is selected as the master to be initialized (3802).

  In the slave initialization start process on the second master IC 570b side, the CPU 551 prohibits the master interrupt and the time interrupt as in the first master IC 570a side slave initialization start process (3811). Then, the second master IC 570b is selected as the master to be initialized (3812).

  In the subsequent processes, a common process is executed for the selected master for the first master IC 570a side slave initialization start process and the second master IC 570b side slave initialization start process.

  The CPU 551 sets “1” to the initialization stage number of the selected master (3803). Further, a monitoring timer for the selected master is set (3804), and timeout monitoring is started (3805).

  In response to the selected master command REG581, the CPU 551 sets “1” in the STA, “1” in the STO, “0” in the SI, and “0” in the MODE (3806).

  As described above, the STA is a bit for instructing the output of the start condition, and the STO is a bit for instructing the output of the stop condition. When “1” is set in each bit, a corresponding signal is output by the master IC. In the process of step 3806, signals of both a start condition and a stop condition are output.

SI is a bit for notifying the occurrence of the aforementioned master interrupt. When “1” is set, the master IC requests the CPU 551 to generate an interrupt, and this bit is set to “0”. The master IC that generated the interrupt is in a state of waiting for processing until changed to. When the CPU 551 sets “0” to this bit, the interrupt generated in the CPU 551 is canceled, and the master IC waiting for processing resumes the next processing to be performed. In the process of step 3806, since “0” is set, the generation of the interrupt is canceled, and the master IC that has been waiting for the process resumes the operation.

  MODE is a bit for designating a mode for transmitting data. When “1” is set, “buffer mode” is designated, and when “0” is set, “byte mode” is designated. Is done. In step 3806, since “0” is set, data is exchanged in the byte mode.

  Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3807), and returns to the caller.

  FIG. 39 is a flowchart illustrating a procedure of slave output start processing according to the embodiment of this invention.

  The slave output start process is a process executed in step 3710 shown in FIG. 37, and is a process necessary for transmitting presentation control data from each master to the light emission control slave.

  The CPU 551 first prohibits the master interrupt and the time interrupt (3901). Next, the start flag corresponding to the first master IC 570a is set to “ON” (3902). Furthermore, the monitoring timer of the first master IC 570a is set (3903), and timeout monitoring processing is started (3904). The start flag is a flag indicating whether or not the start condition is output and the transmission of the production control data is started, and is set for each master IC. The start flag is stored in the RAM 553 of the effect control device 550.

  Further, in response to the command REG 581 of the first master IC 570a, the CPU 551 sets “1” to the STA, “1” to the STO, “0” to the SI, and “1” to the MODE (3905). In the processing of step 3905, since “1” is set in MODE, data is transmitted and received in the buffer mode.

  Similarly, for the second master IC 570b, the CPU 551 sets the start flag of the second master IC 570b to ON (3906). Further, a monitoring timer is set (3907), and timeout monitoring processing is started (3908). Further, for the command REG 581 of the second master IC 570b, “1” is set in the STA, “1” in the STO, “0” in the SI, and “1” in the MODE (3909).

  The CPU 551 selects the first slave (decoration control device 610) of each master (3910). In each master IC, the order of slaves for transmitting the effect control data is set in advance. The first slave in the order is set in the process of step 3910, and the effect control data is sequentially transmitted to each slave connected to the first master IC 570a in the effect control data transmission restart process described later.

  Furthermore, the CPU 551 sets a retry counter to 0 (3911). The retry counter is a counter that is incremented when transmission fails when the production control data is transmitted to each master. When the retry counter becomes larger than a predetermined value, it can be determined that some trouble has occurred.

  Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3912), and returns to the caller.

  FIG. 40 is a flowchart illustrating a processing procedure when a transmission interruption interrupt occurs on the first master IC 570a side and the second master IC 570b side according to the embodiment of this invention.

  The transmission interruption interrupt is a so-called master interruption, and processing is executed according to the state at the time of interruption.

  First, when a master interrupt from the first master IC 570a occurs, the CPU 551 ends the time-out monitoring for the first master IC 570a (4001). Further, the initialization stage number and start flag of the first master IC 570a are acquired (4002).

  Similarly, when a master interrupt from the second master IC 570b occurs, the CPU 551 ends the time-out monitoring for the second master IC 570b (4011), and acquires the initialization stage number and start flag of the second master IC 570b. (4012).

  The CPU 551 determines whether or not the initialization stage number of the master IC to be initialized is “0” (4003). The case where the initialization stage number is “0” indicates that the initialization process is not being executed. That is, when the initialization stage number is other than “0”, it indicates that the initialization process is being executed.

  If the initialization stage number of the master IC to be initialized is not “0” (the result of 4003 is “N”), the CPU 551 is in the initialization process as described above, so the initialization instruction data A transmission resumption process is executed (4004). Details of the transmission restart processing of the initialization instruction data will be described later with reference to FIG.

  On the other hand, if the initialization stage number of the master IC to be initialized is not “0” (result of 4003 is “Y”), the CPU 551 has already completed the initialization process, and transmits the effect control data. Because it is in the middle of the transmission, a process for resuming the transmission of the effect control data is executed (4005). Details of the transmission restart processing of the effect control data will be described later with reference to FIG.

  FIG. 41 is a flowchart illustrating a processing procedure when a time-out interrupt is generated by the first master IC 570a and the second master IC 570b according to the embodiment of this invention.

  This process is a process executed to initialize each master IC when a timer interrupt occurs when the first master IC 570a or the second master IC 570b does not return after a predetermined time has elapsed. .

  When a timeout interrupt occurs in the first master IC 570a, the CPU 551 performs a soft reset on the first master IC 570a (4101). Further, a slave initialization start process (FIG. 38) on the first master IC 570a side for initializing the slave connected to the first master IC 570a is executed (4102).

  When a timeout interrupt occurs in the second master IC 570b, the CPU 551 performs a soft reset on the second master IC 570b (4111). Furthermore, slave initialization start processing (FIG. 38) on the second master IC 570b side for initializing the slave connected to the second master IC 570b is executed (4112).

  FIG. 42 is a flowchart illustrating a procedure of the transmission restart process of the initialization instruction data according to the embodiment of this invention.

  The CPU 551 first determines whether or not to continue the transmission process of the initialization instruction data based on the status code (4201), and branches the process according to the determination result (4202). The status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. In the process of step 4201, the transmission process of the initialization instruction data is continued with reference to the transmission process continuation determination table 4400 described later with reference to FIG. 44 based on the combination of the set status code and the current initialization stage number. It is determined whether or not to do. The relationship between the initialization stage number and the status code will be described in detail with reference to FIG.

  The initialization stage number is set to any value from “1” to “4” according to the processing stage when the master IC is being initialized. When completed, it is set to “0”. However, when initialization of the master IC is completed and the initialization stage number becomes “0”, the transmission restart process of the initialization instruction data is not called (the branch of step S4003 in the caller process of FIG. 40). Therefore, the description will be made on the assumption that the initialization stage numbers are “1” to “4”.

  If the determination result based on the combination of the initialization stage number and the status code is not “continuous” (the result of 4202 is “N”), the CPU 551 is not in a normal state (for example, the data transmission has failed). Therefore, the value “1” indicating the start of initialization is set as the initialization stage number (4203). Further, a monitoring timer is set, and timeout monitoring is started (4204).

  Finally, the CPU 551 outputs “1” to the STA of the command REG581 of the master IC to be processed, “1” to the STO, “0” to the SI, and “0” to the MODE so as to output the stop condition and the start condition. The setting is made (4205), and the process returns to the calling process.

  On the other hand, when the determination result based on the combination of the initialization stage number and the status code is “continuation” (the result of 4202 is “Y”), the CPU 551 is executing the initialization process normally. Then, the process branches based on the initialization stage number (4206).

  When the initialization stage number is “1”, the CPU 551 sets a reset address in the output buffer 572 of the processing target master IC (4207).

  When “1” is set in the initialization stage number, it means that a start condition is output from the master IC. Referring to the transmission processing continuation determination table 4400 of FIG. 44, the status code is set to “08h” or “10h” indicating that a start condition or a restart condition is transmitted. Therefore, when the initialization stage number is set to “1” and the status code is set to “08h” or “10h”, the processing after step 4207 is executed.

  The CPU 551 increments the initialization stage number (4208), sets a monitoring timer, and starts time-out monitoring (4209). Finally, in order to continue the processing, “0” is set in each of the STA, STO, SI, and MODE of the command REG 581 of the processing target master IC (4210), and the processing returns to the calling source processing.

  When the initialization stage number is “2”, the CPU 551 sets the first half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4211).

When the initialization stage number is set to “2”, the output buffer 572 of the master IC
This means that the reset address is set in. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code includes an ACK indicating that the slave address (here, the reset address) has been transmitted and that the signal has been normally received from each slave. “18h” indicating that the response has been made is set. However, the status code is set to “20h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Accordingly, when “2” is set as the initialization stage number and “18h” is set as the status code, the processing after step 4211 is executed.

  When a value is set in the output buffer 572, the CPU 551 executes the processing from steps 4208 to 4210 as in the case where the initialization stage number is “1”.

  If the initialization stage number is “3”, the CPU 551 sets the latter half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4212).

  When “3” is set as the initialization stage number, it means that the first half value of the reset command is set in the output buffer 572 of the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code is returned as an ACK indicating that the data set in the output buffer 572 has been transmitted and that the signal has been normally received from each slave. "28h" indicating that this is set. However, the status code is set to “30h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Accordingly, when “3” is set as the initialization stage number and “28h” is set as the status code, the processing after step 4212 is executed.

  When a value is set in the output buffer 572, the CPU 551 executes the processing from steps 4208 to 4210 as in the case where the initialization stage number is “1”.

  When “4” is set in the initialization stage number, it means that the latter half value of the reset command is set in the output buffer 572 of the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, as in the case where the initialization stage number is “3”, “28h” or “30h” is set in the status code, and “28h” is set in the status code. In this case, the processing after step 4212 is executed.

  When the initialization stage number is “4”, the processing necessary for the initialization processing is completed, so the CPU 551 sets the error flags of all the decoration control devices 610 connected to the master IC to be processed to OFF. (4213) Further, the error counter is set to 0 and initialized (4214). Then, the initialization stage number is set to “0” indicating that the initialization process is not in progress. Finally, in order to complete the initialization process and to output a stop condition from the master IC to be processed to all the decoration control devices 610 connected to the master IC, the STO of the command REG 581 of the master IC to be processed is output. “1”, STA, SI, and MODE are set to “0” (4216), and the process returns to the caller process.

  FIG. 43 is a flowchart showing a procedure of resumption of transmission processing of effect control data according to the embodiment of the present invention.

The CPU 551 first determines the process to be executed based on the status code (4301), and branches depending on whether the process is continued, the data is retransmitted, or the data transmission is stopped (4302). In the process of step 4301, based on the combination of the status code and the value set in the start flag, a process to be executed is determined with reference to a transmission process continuation determination table 4400 described later with reference to FIG.

  The start flag is a flag for controlling the timing of transmitting the presentation control data for each of the first master IC 570a and the second master IC 570b. Specifically, when the slave output start process (FIG. 39) in step 3710 of FIG. 37 is executed, the start flag is set to “ON”. Further, as described later, when the production control data is set in the output buffer 572, the start flag is set to “off”. As described above, the status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. The relationship between the start flag and the status code will be described in detail with reference to FIG.

  If the CPU 551 determines that the process is to be continued by the combination of the start flag and the status code (the result of 4302 is “continue”), the presentation control data is normally transmitted. At this time, if the start flag is “ON”, as described above, since the start condition is output, the corresponding status code is “08h” or “10h”. On the other hand, when the start flag is “off”, if the process is normally performed, “28h” indicating that data transmission has been completed normally is set in the status code.

  Therefore, the CPU 551 determines whether or not the start flag is “ON” (4303). If the start flag is “ON” (the result of 4303 is “Y”), the data prepared in the RAM 553 is set in the output buffer 572 (4304). Then, the start flag is set to “off” (4305), a monitoring timer is set, and timeout monitoring is started (4306). Finally, STA, STO and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “1” in order to transmit the data set in the output buffer 572 in the buffer mode. The setting is made (4307), and the process returns to the calling process.

  On the other hand, when the start flag is “OFF” (the result of 4303 is “N”), the CPU 551 sets the error flag corresponding to the selected slave (decoration control device 610) to “OFF” (4308). Further, an error counter is initialized (4309).

  Thereafter, the CPU 551 determines whether or not the transmission resumption process has been completed for all the slaves (4310). When the processing is completed for all the slaves (result of 4310 is “Y”), a stop condition is output, and the STO of the command REG 581 is set so that the mode for transmitting data is designated as “buffer mode”. Then, “1” is set in MODE and MODE, and “0” is set in STA and SI (4311), and the process returns to the calling process.

  If the processing has not been completed for all the slaves (the result of 4310 is “N”), the CPU 551 sets the retry counter to 0 (4312) and selects the next slave to be processed (4313). ). Then, output data to the selected slave is prepared (4314), a start flag is set to “on” (4315), a monitoring timer is set, and timeout monitoring is started (4316).

  Finally, the CPU 551 outputs a start condition and sets “1” to STA and MODE of the command REG581 and “0” to STO and SI so as to designate the mode for transmitting data as “buffer mode” (4317). ), Return to the calling process.

If it is determined that the effect control data is retransmitted by the combination of the start flag and the status code (the result of 4302 is “retransmit”), the CPU 551 increments the value of the retry counter (4318). Then, it is determined whether or not the value of the retry counter has reached the designated value (4319). The designated value at this time is set in the abnormality determination table 3200 or the abnormality determination table 3300 shown in FIG. 32 or 33, and corresponds to the comparison value 3204 corresponding to the currently selected slave.

  When the value of the retry counter has not reached the specified value (result of 4322 is “N”), the CPU 551 selects the slave again during the current selection (4320), and prepares data to be output to the selected slave. (4314), the processing after step 4315 is executed.

  On the other hand, when the value of the retry counter reaches the specified value (result of 4322 is “Y”), the CPU 551 sets “ON” to the error flag 3205 of the selected slave, and the processing after step 4310 Execute.

  In this case, the output data to the selected slave is set in the output buffer 572, but the transmission of the output data that has failed to be transmitted to the selected slave is abandoned. Then, when the next image update interrupt occurs, new output data is generated and transmitted to the slave.

  That is, the output data (production control data) that failed to be transmitted is not transmitted to the slave when the next image update interrupt occurs, and the production control data that failed to be transmitted is discarded and updated. Production control data that synchronizes with the contents of the image is generated each time and set in the output buffer 572.

  Finally, if it is determined by the combination of the start flag and the status code that the transmission restart process of the effect control data is to be stopped (the result of 4302 is “stop”), the CPU 551 returns to the calling process. When the transmission restart process of the effect control data is stopped, the connection line SDA or the connection line SCL is occupied for some reason, and furthermore, since this occupied state cannot be released, data transmission / reception cannot be performed. Is the case.

  FIG. 44 is a diagram showing an example of a transmission processing continuation determination table 4400 for determining continuation of data transmission resumption processing according to the embodiment of this invention.

  The transmission process continuation determination table 4400 stores information for determining whether to continue the data transmission restart process as described above. The data transmission restart process includes an initialization instruction data transmission restart process (FIG. 42) and an effect control data transmission restart process (FIG. 43). The transmission process continuation determination table 4400 includes a process for each case. Continuation judgment is registered.

  The transmission process continuation determination table 4400 includes a status code 4401, initialization instruction data transmission resumption process continuation determination 4402, effect control data transmission resumption process continuation determination 4403, and state 4404.

  As described above, the status code 4401 is a value indicating the state of the master IC regardless of the processing to be executed.

  A state 4404 is a state of the master IC corresponding to the status code 4401. For example, when the status code is “08H”, it indicates a state where the transmission of the start condition is completed. Further, when the status code is “10H”, it indicates that the transmission of the start condition, that is, the transmission of the restart condition is completed.

In the embodiment of the present invention, the connection line SDA or the connection line SCL is occupied for some reason, and if it cannot be released, “70H” or “78H” is set in the status code 4401.

  Next, the continuation determination 4402 of the initialization instruction data transmission restart process corresponding to the status code and the continuation determination 4403 of the effect control data transmission restart process will be described.

  In the initialization instruction data transmission restart process, the process is executed for each stage corresponding to the initialization stage number, and the continuation determination 4402 of the initialization instruction data transmission restart process is defined for each initialization stage number. Specifically, as shown in the figure, “continuation” or “resumption” is defined corresponding to the combination of the value of the initialization stage number and the value of the status code.

  When the value of the continuation determination 4402 is “continuation”, it indicates that the initialization instruction data transmission restart process is being processed normally. Specifically, when the output of the start condition is successful when the initialization stage number is 1, or when the address transmission is successful when the initialization stage number is 2, the value of the continuation determination 4402 is “continue”. become. That is, when the process executed in the initialization instruction data transmission restart process and the status code set in the status register (REG) 582 match, the value of the continuation determination 4402 becomes “continue”.

  On the other hand, when the value of the continuation determination 4402 is “restart”, it is set when the initialization instruction data transmission restart process is restarted, such as when the initialization instruction data transmission restart process is not normally processed. That is, the process executed in the initialization instruction data transmission restart process is not consistent with the status code set in the status register (REG) 582, for example, when data transmission has failed.

  In the effect control data transmission restart process, the process is executed based on the set value of the start flag, and the continuation determination 4403 of the effect control data transmission restart process is defined for each set value of the start flag. Specifically, as shown in the figure, “continuation”, “retransmission” or “cancel” is defined corresponding to the combination of the value of the start flag and the value of the status code.

  The start flag is set to ON when data is first transmitted after the start condition is output, and is set to OFF when the process is continued. That is, when the initial setting is completed, the start flag is set to OFF, and then data is continuously transmitted. When the value of the continuation determination 4403 is “continuation”, after the start condition transmission (start flag is ON) and the status code is set to “08H” or “10H”, after data transmission (start flag is OFF) Is set with a status code “28H” indicating successful data transmission.

  On the other hand, if the connection line SDA or the connection line SCL is in an occupied state for some reason and cannot be released, the data transmission / reception is stopped because the data cannot be transmitted / received. Specifically, the status code 4401 is “70H” or “78H”.

  In other cases, that is, when the status code and the start flag are not matched in a state where data can be transmitted and received, “retransmission” is set, and processing for retransmitting the presentation control data is executed.

  FIG. 45 is a flowchart illustrating a procedure of data transmission processing by the master IC according to the embodiment of this invention. This process is common to the first master IC 570a and the second master IC 570b. When the CPU 551 sets “0” in the SI bit of the command register 581 (see FIGS. 11 and 12), the interrupt process is performed. The master IC that has been waiting due to the occurrence starts the processing.

  First, the controller 574 of the master IC determines whether or not output of a stop condition is requested, that is, whether or not “1” is set in the STO of the command REG 581 (4501).

  When the output of the stop condition is requested (the result of 4501 is “Y”), the controller 574 executes the stop condition output process (4502). The stop condition output process executes a process necessary for executing the stop condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the stop condition output processing will be described later with reference to FIG.

  The controller 574 further determines whether or not the output of the start condition is requested, that is, whether or not “1” is set in the STA of the command REG581 (4503). When the output of the start condition is requested (the result of 4503 is “Y”), the start condition output process is executed (4506). The start condition output process executes a process necessary for executing the start condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the start condition output processing will be described later with reference to FIG.

  When the output of the start condition is requested (the result of 4503 is “N”), the controller 574 sets the value of STCD as the status code (4506). STCD is a variable for substituting a set status code. When a value is set for the status code, this process ends.

  When the output of the stop condition is not requested (the result of 4501 is “N”), the controller 574 sets “1” to the STA of the command REG 581 as to whether or not the output of the start condition is requested. It is determined whether or not it has been done (4505). When the output of the start condition is requested (the result of 4505 is “Y”), the start condition output process is executed (4506). Then, the STCD value set in the start condition output process is set in the status code (4507). Thereafter, a transmission interruption interrupt is generated by setting “1” to the SI of the command REG581.

  If the output of the start condition is not requested (the result of 4505 is “N”), the controller 574 executes data transmission processing to the slave (4508). Then, the STCD value set in the data transmission process to the slave is set in the status code (4507). Thereafter, a transmission interruption interrupt is generated by setting “1” to the SI of the command REG581.

  FIG. 46 is a flowchart showing a procedure of stop condition output processing according to the embodiment of the present invention.

  The stop condition is output by changing the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH. In the stop condition output process, the process is executed according to the signal level of each connection line at the start of the process.

  When starting the stop condition output process, the controller 574 branches the process according to the signal levels of the connection line SCL and the connection line SDA (4601).

  When both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH, the controller 574 turns on the transistor 578b (FIG. 11 or FIG. 12) and sets the signal level of the connection line SCL to LOW. (4602). After the processing of step 4602 is completed, or when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, the transistor 578a (FIG. 11 or FIG. 12) is turned on to establish a connection. The signal level of the line SDA is set to LOW (4603).

  The controller 574 executes an SCL release monitoring process for releasing the connection line SCL after the process of step 4603 is completed or when both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW. (4604).

  The SCL release monitoring process is a process for enabling data transmission / reception by setting the signal level of the connection line SCL at the LOW level to HIGH. Details of the SCL release monitoring process will be described later with reference to FIG. When the SCL release monitoring process ends normally, the signal level of the connection line SCL is set to HIGH. If the signal level of the connection line SCL cannot be set to HIGH and the connection line SCL cannot be released, a transmission interruption interrupt is generated.

  The controller 574 monitors the SDA release for releasing the connection line SDA after the processing of step 4604 is completed or when the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW. Processing is executed (4605).

  The SDA release monitoring process is a process of changing the signal level of the connection line SDA from LOW to HIGH. If the connection line SDA is occupied for some reason and the signal level remains LOW, it is occupied. A process of releasing the connection line SDA is included. Details of the SDA release monitoring process will be described later with reference to FIG. Note that when the SCL release monitoring process ends normally, the signal level of the connection line SDA is changed from LOW to HIGH, and at this time, the signal level of the connection line SCL is maintained at HIGH, so that the stop condition is established. To do. If the connection line SDA cannot be released, a transmission interruption interrupt is generated.

  FIG. 47 is a flowchart illustrating a procedure of SCL release monitoring processing according to the embodiment of this invention.

  When the SCL release monitoring process is started, the controller 574 releases the connection line SCL by turning off the transistor 578b (FIG. 11 or FIG. 12) (4701). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SCL release the connection line SCL, the signal level of the connection line SCL is changed to HIGH. Subsequently, it is determined whether the signal level of the connection line SCL is changed to HIGH and the connection line SCL is released (4702).

  When the signal level of the connection line SCL is HIGH (the result of 4702 is “Y”), the controller 574 returns to the caller process because the process was successful. On the other hand, if the signal level of the connection line SCL is not HIGH (the result of 4702 is “N”), it is determined whether or not the signal level of the connection line SCL has become HIGH until a predetermined time has elapsed. (4702).

  If the signal level of the connection line SCL does not become HIGH even after a predetermined time has elapsed (the result of 4703 is “Y”), the controller 574 displays “78H” indicating that the connection line SCL cannot be released as a status code. (4704) to generate a transmission interruption interrupt.

  FIG. 48 is a flowchart illustrating a procedure of SDA release monitoring processing according to the embodiment of this invention.

  When the signal level of the connection line SDA cannot be HIGH, that is, when the connection line SDA is occupied, data cannot be output via the connection line SDA. Therefore, by not applying an operable voltage to the transistor 578a by the driver 576a, the signal level of the connection SCL is changed at least nine times without turning on the transistor 578a (with the connection line SDA released).

By performing such processing, the I ² CI that has entered the read mode (details will be described later).
The / O expander 615 outputs data to the connection line SDA in accordance with the change in the signal level of the connection SCL, but in the middle of the change in the signal level of the connection SCL at least nine times, the acknowledge signal from the master IC is output. Timing to check occurs. At this time, since the connection line SDA is released, the connection line SDA becomes HIGH level, and the I ² C that has entered the read mode
Since the I / O expander 615 determines that the acknowledge signal has not been received, the data transmission is stopped and the connection line SDA is released. RCVF is a flag indicating whether or not the signal level change of the nine connections SCL has been executed.

In this manner, the connection line SDA is forcibly released from the I ² CI / O expander 615 that has entered the read mode, so that the signal level of the connection line SDA is maintained at HIGH. Hereinafter, the procedure of the SDA release monitoring process will be described.

  First, the controller 574 sets RCVF to OFF (4801). Thereafter, the transistor 578a (FIG. 11 or FIG. 12) is turned off to release the connection line SDA (4802). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SDA release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

  The controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4803). If the signal level of the connection line SDA is HIGH (the result of 4803 is “Y”), the connection line SDA can be released, and the process returns to the caller process.

  On the other hand, if the signal level of the connection line SDA is not HIGH (the result of 4803 is “N”), the controller 574 determines whether or not the signal level of the connection line SDA has become HIGH until a predetermined time has elapsed. Determination is made (4804). When a predetermined time elapses (the result of 4804 is “Y”), it is determined that the connection line SDA is in an occupied state, and processing for releasing the connection line SDA after step 4805 is executed.

  First, the controller 574 sets 0 to the value of the variable LP indicating the number of times that a signal has been input to the connection line SCL (4805). Subsequently, the SCL release monitoring process described in FIG. 47 is executed (4806). Further, the signal level of the connection line SCL changed to HIGH by the SCL release monitoring process is set to LOW by turning on the transistor 578a (4807). By the processing in steps 4806 and 4807, the signal level of the connection line SCL changes from LOW to HIGH, and further from HIGH to LOW. Further, by adding 1 to LP (4808), the number of signal level changes of the connection line SCL is counted.

  The controller 574 determines whether or not the value of LP has reached 9, that is, whether or not the number of signal level changes of the connection line SCL has reached 9 (4809). If the LP value has not reached 9 (the result of 4809 is “N”), the processing from steps 4806 to 4808 is executed again.

  When the value of LP reaches 9 (the result of 4809 is “Y”), the controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4810). If the signal level of the connection line SDA is not HIGH (the result of 4810 is “N”), it is determined whether or not the signal level of the connection line SDA has become HIGH until a predetermined time elapses ( 4811). If the signal level of the connection line SDA is not set to HIGH even after a predetermined time has elapsed (the result of 4811 is “Y”), “70H” indicating that the connection line SDA cannot be released is set in the status code. (4812) A transmission interruption interrupt is generated.

  On the other hand, when the signal level of the connection line SDA is set to HIGH (the result of 4810 is “Y”), the controller 574 turns on the transistor 578a and sets the signal level of the connection line SDA to LOW ( 4813), the SCL release monitoring process is executed (4814). Further, the transistor 578a is turned off to release the connection line SDA (4815), and RCVF is set to on (4816).

  Note that a mechanism for releasing the connection line SDA by changing the signal level of the connection line SCL nine times will be described in detail with reference to FIG.

  FIG. 49 is a flowchart showing a procedure of start condition output processing according to the embodiment of the present invention.

  The start condition is output by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. In the start condition output process, the process is executed according to the signal level of each connection line at the start of the process.

  When starting the start condition output process, the controller 574 branches the process according to the signal levels of the connection line SCL and the connection line SDA (4901).

  When the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the controller 574 turns on the transistor 578b (FIG. 11 or 12) and sets the signal level of the connection line SCL to LOW. (4902).

  The controller 574 executes the SDA release monitoring process after the process of step 4902 is completed or when both the signal level of the connection line SCL and the signal level of the connection line SDA are LOW (4903). Subsequently, it is determined whether or not the value of RCVF is ON (4904). When the execution of the SDA release monitoring process is normally completed, the signal level of the connection line SDA is set to HIGH.

  When the RCVF value is not on (the result of 4904 is “N”), or when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, the controller 574 monitors the SCL release. Processing is executed (4905). This is because when the value of RCVF is ON, the SCL release monitoring process has been executed (step 4814 in FIG. 48), and the signal level of the connection line SCL is HIGH.

  The controller 574 indicates that when the RCVF value is on (the result of 4904 is “Y”), or after the execution of the SCL release monitoring process in step 4905, the re-output of the start condition (restart condition) is completed. “10H” is set in the STCD (4907).

  When both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH, the controller 574 sets “08H” indicating that the output of the start condition is completed to the STCD (4906).

  At the time when the processing of step 4906 or step 4907 is completed, the signal level of the connection line SCL and the signal level of the connection line SDA are both set to HIGH. Therefore, the controller 574 turns on the transistor 578a (FIG. 11 or FIG. 12) and sets the signal level of the connection line SDA to LOW (4908). By performing the processing in this way, the start condition is established because the signal level of the connection line SDA is changed from HIGH to LOW while the signal level of the connection line SCL is maintained at HIGH.

  Subsequently, the controller 574 turns on the transistor 578b and sets the signal level of the connection line SCL to LOW (4909). Further, the FBF value is set to ON (4910). The FBF is a flag indicating that the start condition has been established. For example, when data is transmitted after the start condition is established, if the FBF is ON, the slave address since it is the first transmitted data. Judge. Then, by setting the FBF to OFF after receiving the address, each slave can recognize that the received data is presentation control data.

FIG. 50 is a flowchart illustrating a procedure of data transmission processing to the slave I ² CI / O expander 615 according to the embodiment of this invention.

  First, the controller 574 initializes a variable CTR for storing the number of data transmissions to 0 (5001). Subsequently, the transistor 578b (FIG. 11 or 12) is turned on, the signal level of the connection line SCL is set to LOW (5002), the transistor 578a (FIG. 11 or FIG. 12) is turned off, and the connection line SDA is turned on. Release (5003). At this time, if all other ICs (I / O expander 615, etc.) connected to the connection line SDA release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

  The controller 574 determines whether or not the signal level of the connection line SDA is HIGH (second level), that is, whether or not the connection line SDA is released (5004). When the signal level of the connection line SDA is not HIGH (the result of 5004 is “N”), the process waits until the signal level of the connection line SDA becomes HIGH. That is, if the connection line SDA is at the LOW level (first level), it is determined that the connection line SDA is in the occupied state, and data transmission to the I / O expander 615 is restricted.

  On the other hand, when the signal level of the connection line SDA is HIGH (the result of 5004 is “Y”), the controller 574 determines whether or not the value of the variable CTR is 8, that is, the number of data transmissions has reached 8. It is determined whether or not (5005).

  If the number of data transmissions has not reached eight (the result of 5005 is “N”), the controller 574 outputs data to the slave via the connection line SDA and adds 1 to the CTR (5006). ). Subsequently, an SCL release monitoring process is executed (5007), and further data is output by executing the processes after step 5002.

On the other hand, when the number of data transmissions reaches 8 (the result of 5005 is “Y”), the controller 574 outputs a response signal from the I ² CI / O expander 615 on the slave side via the connection line SDA. (5008).

The controller 574 fetches the output response signal from the connection line SDA (5009).
The SCL release monitoring process is executed (5010). Further, it is determined whether or not the content of the response signal fetched in step 5009 is “ACK” (5011).

  When the content of the response signal from the slave is “ACK” (the result of 5011 is “Y”), the controller 574 turns on the transistor 578b and sets the signal level of the connection line SCL to LOW (5012). Then, the connection line SDA is released by the slave (5013). Further, it is determined whether or not the current data transmission mode is the buffer mode (5014).

  When the current data transmission mode is the buffer mode (result of 5014 is “Y”), the controller 574 determines whether or not the transmission of the last byte is completed (5015). If transmission of the last byte is not completed and data is to be transmitted (result of 5015 is “N”), the FBF value is set to OFF, and a variable CTR indicating the number of data transmissions is set to 0. (5016). As described above, the FBF is a flag indicating that the start condition has been established, and is set to OFF after the initial data transmission, thereby indicating that the transmission of the slave address has been completed. Can be handled. Thereafter, it waits until the signal level of the connection line SDA becomes HIGH (5004), and the next data is transmitted.

  When the current data transmission mode is not the buffer mode, that is, in the byte mode (result of 5014 is “N”), or when the last byte transmission is completed (the result of 5015 is “Y ]), It is determined whether or not the FBF is set to ON (5017). If the FBF is set to ON (the result of 5017 is “Y”), the FBF is set to OFF and the status code “18H” indicating that the address transmission was successful is set to the STCD (5018). . On the other hand, when the FBF is not set to ON (result of 5017 is “N”), the status code “28H” indicating that the data transmission is successful is set in the STCD (5019).

  Further, the controller 574, when the content of the response signal from the slave is not “ACK”, that is, “NACK” indicating that data could not be received (result of 5011 is "N"), the transistor 578b is turned on, and the signal level of the connection line SCL is set to LOW (5012).

  Further, the controller 574 determines whether or not the FBF is set to ON (5021). When the FBF is set to ON (the result of 5021 is “Y”), the status code 20H indicating that the address transmission has failed is set in the STCD (5022). On the other hand, when the FBF is not set to ON (the result of 5021 is “N”), the status code 30H indicating that the data transmission has failed is set in the STCD (5023). When the above process ends, the process returns to the caller process.

51 to 53 show the I ² CI / O expander 6 on the slave side according to the embodiment of the present invention.
15 is a flowchart showing a processing procedure in FIG.

FIG. 51 is a flowchart illustrating a processing procedure in the slave-side I ² CI / O expander 615 according to the embodiment of this invention.

The slave I ² CI / O expander 615 executes various controls by the bus controller 634 as described with reference to FIG.

First, when a reset signal is generated by the reset signal generation circuit 639 (see FIG. 18, the same applies hereinafter), the bus controller 634 executes initialization processing for itself (I ² CI / O expander 615) (5101). At this time, the transistor 630 is turned off by the driver 632 and the connection line SDA is released. In addition, the driver 637 turns off all of the transistors 638A to 638P connected to the ports 0 to 15. Further, the output setting register 635 is set to a predetermined initial state. Next, the signal levels of the connection line SCL and the connection line SDA are captured. And it waits until it becomes the state 5103 in which the signal level of both the connection line SCL and the connection line SDA is HIGH (5102).

  When the connection line SCL and the connection line SDA are in the state 5103 (the result of 5102 is “Y”), the bus controller 634 waits until the signal level of either the connection line SCL or the connection line SDA changes ( 5104).

  When the signal level of the connection line SDA changes to LOW from the state 5103 (result of 5104 is “SDAＤＡ”), the bus controller 634 sets the variable CN to 0, sets the state number to 1, and sets the data Is cleared (5105). The variable CN is a counter indicating the number of times data has been received. Further, the state number is set according to a signal transmitted from the master, and corresponds to, for example, a process requested by the slave (write process, read process, etc.). Note that when the signal level of the connection line SDA changes from LOW in the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are both HIGH, this corresponds to the start condition being output from the master IC. 1 indicates that a start condition has been output.

  At this time, the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW. The bus controller 634 waits until the signal level of the connection line SCL or the connection line SDA changes (5107).

  When the signal level of the connection line SCL changes to LOW from the state 5106 (the result of 5107 is “SCL ▽”), the bus controller 634 receives the data eight times, that is, whether or not the variable CN has become 8. It is determined whether or not (5108). If the value of the variable CN is not 8 (the result of 5108 is “N”), the signal level of the connection line SCL and the connection line SDA is both LOW at this stage. Thereafter, the process waits until the signal level of the connection line SCL or the connection line SDA changes (5110).

  When the signal level of the connection line SDA changes to HIGH (the result of 5110 is “SDAΔ”), the bus controller 634 indicates that the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH. The process proceeds to 5111 and waits until the signal level of the connection line SCL or the connection line SDA changes (5112).

  When the signal level of the connection line SDA changes to LOW (the result of 5112 is “SDA ▽”), the bus controller 634 proceeds to the state 5109 until the signal level of the connection line SCL or the connection line SDA changes. Wait (5110).

  On the other hand, when the signal level of the connection line SCL changes to HIGH (the result of 5112 is “SCLΔ”), the bus controller 634 determines whether the state number is 1 or 2, that is, after the start condition is output. Or whether the requested process is a write request (5115).

When the state number is 1 or 2 (the result of 5115 is “Y”), the bus controller 634 adds 1 to the value of the variable CN and takes in the data stored in the reception buffer (5116). If the state number is not 1 or 2 (the result of 5115 is “N”), or step 511
When the processing of 6 is completed, the signal level of the connection line SCL and the connection line SDA is both HIGH 5103, and the process waits until the signal level of the connection line SCL or the connection line SDA changes (5104).

  In the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are HIGH, the bus controller 634 changes the signal level of the connection line SCL to LOW (the result of 5104 is “SCL バ ス”). It is determined whether or not 8 has been reached, that is, whether or not data has been received 8 times (5117). If the value of the variable CN is not 8 (the result of 5117 is “N”), the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH at this stage. Therefore, the processing after step 5112 is executed. On the other hand, when the value of the variable CN becomes 8 (the result of 5117 is “Y”), the processing after step 5201 shown in FIG. 52 is executed.

  In addition, in the state 5106 in which the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the bus controller 634 changes the signal level of the connection line SDA to HIGH (the result of 5107 is “SDA”). Δ ”), it is determined whether or not the state number is 2, that is, the requested process is a read request (5118). Note that the change of the signal level of the connection line SDA from HIGH in the state 5106 in which the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW corresponds to the output of the stop condition.

  If the state number is 2 (the result of 5118 is “Y”), the bus controller 634 is informed. The data stored in the preparation area is stored in the setting register (5119). When the state number is not 2 (the result of 5118 is “N”) or when the processing of step 5119 is completed, 0 is set to the state number (5120). At this time, since the signal levels of both the connection line SCL and the connection line SDA are in the high state 5103, the process waits until the signal level of the connection line SCL or the connection line SDA changes (5104) and the processing is continued. .

FIG. 52 is a flowchart showing a procedure such as address recognition processing in the slave-side I ² CI / O expander 615 according to the embodiment of this invention.

Note that the I ² CI / O expander 615 used in the present embodiment can be used regardless of whether the read mode can be generated or not. Therefore, any type of I ² CI
The flowchart will be described assuming that the / O expander 615 is provided.

  Here, the reading mode will be described.

In the present embodiment, each time transmitting data of a predetermined unit of bytes from the master IC to the I ² CI / O expander 615, the configuration for receiving a response signal 1 bit from I ² CI / O expander 615 to the master IC The production control data is transmitted from the master IC to the I ² CI / O expander 615.

By the way, it may be convenient for some gaming machines to be configured to transmit data of a predetermined unit byte from the I ² CI / O expander 615 to the master IC. For example, the I ² CI / O expander 615 may detect a detection state of various sensors related to a game and develop a gaming machine with specifications that can be transmitted to a master IC.

The I ² CI / O expander 615 used in such a gaming machine generates a “read mode” inside the I ² CI / O expander 615 in response to a request from the master IC.
Each time a data of a predetermined unit byte is transmitted from the I ² CI / O expander 615 to the master IC in accordance with the change of the SCL signal from the master IC, 1 is sent from the master IC to the I ² CI / O expander 615. It is preferable that a bit response signal is transmitted.

Specifically, the read mode is generated when the bit of the R / W identification data 2204 is “1” in the address data transmitted from the master IC to the slave I ² CI / O expander 615. This request is defined in advance as a request (hereinafter referred to as a “read request”).

  When the signal level of the connection line SCL changes to LOW with the signal levels of the connection line SCL and the connection line SDA being HIGH (the result of 5104 in FIG. 51 is “SCL ▽”), the bus controller 634 When reception is performed eight times, that is, when data reception is completed (result of 5117 is “Y”), the connection line SDA is released on the master IC side (5201).

Subsequently, the bus controller 634 determines whether or not the state number is 1, that is, whether or not it is immediately after the start condition is output (5202). If the status number is 1 (the result of 5202 is “Y”), it is confirmed whether or not the received address matches the address assigned to itself (I ² CI / O expander 615) ( 5203, 5204).

If the received address does not match its own address (the result of 5204 is “N”), the state number is set to 0 (5217), and the processing after step 5213 is executed. Here, the received address corresponds to the above-mentioned “read request”, and I ² for performing the processing.
Even when the CI / O expander 615 cannot generate the above-described read mode, the determination result in step 5204 is set to “N”.

  On the other hand, if the received address matches its own address (the result of 5204 is “Y”), it is determined whether or not the requested process is a read request (5205). If the requested process is a read request (the result of 5205 is “Y”), the processes after step 5301 in FIG. 53 are executed.

  On the other hand, if the requested process is not a read request, that is, if it is a write request (result of 5205 is “N”), the bus controller 634 sets 2 as the corresponding state number (5206).

Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting the occupation of the signal line. Further, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641 (5207). The self-occupied WDT 641 starts a timer when the bus controller 634 starts occupying the bus, and when a predetermined time elapses, the self-occupied WDT 641 itself (I ²
CI / O expander 615) is reset. By processing in this way, even when the connection line SDA is continuously occupied, the occupation can be released by reset when the time set in the self-occupied WDT 641 has elapsed. At this time, the influence on others can be minimized by resetting only itself.

  At this time, the signal levels of the connection line SCL and the connection line SDA are both LOW, and the bus controller 634 waits until the signal level of the connection line SCL changes to HIGH (5209).

When the signal level of the connection line SCL changes to HIGH, the bus controller 634 (52
The result of 09 is “SCLΔ”), a state 5210 in which the signal level of the connection line SCL is HIGH, and the signal level of the connection line SDA is LOW, and further waits until the signal level of the connection line SCL changes to LOW ( 5211).

  When the signal level of the connection line SCL changes to LOW (the result of 5209 is “SCL ▽”), the bus controller 634 releases the connection line SDA by driving the driver 632 to turn off the transistor 630, and the self-occupied WDT 641. The bus monitoring by the self-occupied WDT 641 is terminated (5212). Then, the value of the variable CN is set to 0, and the reception buffer is cleared (5213). At this time, the signal level of the connection line SCL is LOW, the signal level of the connection line SDA is HIGH, and the state 5111 in FIG. 51 is obtained, so the processing from step 5112 onward in FIG. 51 is executed.

  If the status number is not 1 in the process of step 5202 (result of 5202 is “N”), the bus controller 634 determines whether the reception is successful (5214, 5215). If the reception is successful (the result of 5215 is “Y”), the data in the reception buffer is stored in the preparation area (5216), and the processing after step 5207 is executed.

  On the other hand, when the data reception has failed (the result of 5215 is “N”), the bus controller 634 sets the state number to 0 (5217), and executes the processing after step 5213.

FIG. 53 is a flowchart illustrating a procedure of data read processing in the slave-side I ² CI / O expander 615 according to the embodiment of this invention.

  If the processing requested from the master IC is a read request (the result of 5205 in FIG. 52 is “N”), the bus controller 634 sets the state number to 3 corresponding to the read processing (5301).

  Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting the occupation of the signal line. Further, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641 (5302). At this time, both the signal levels of the connection line SCL and the connection line SDA are in the state 5303 in which they are LOW, and the bus controller 634 waits until the signal level of the connection line SCL changes to HIGH (5304).

  When the signal level of the connection line SCL changes to HIGH (the result of 5304 is “SCLΔ”), the bus controller 634 enters the state 5305 and waits until the signal level of the connection line SCL changes to LOW (5306). .

  When the signal level of the connection line SCL changes to LOW (the result of 5306 is “SCL ▽”), the bus controller 634 releases the connection line SDA by driving the driver 632 to turn off the transistor 630, and the self-occupied WDT 641. And the monitoring of the bus by the self-occupied WDT 641 is terminated (5307).

  Further, the bus controller 634 sets the value of the variable CN to 0 (5308), and outputs data to the connection line SDA (5309). At this time, when a LOW level signal is output to the connection line SDA, the self-occupied WDT 641 is operated to start monitoring the bus by the self-occupied WDT 641. When a HIGH level signal is output to the connection line SDA, the self-occupied WDT 641 is not operated (5310). This is because the bus is not occupied if the signal level of the connection line SDA is HIGH.

  At this time, the bus controller 634 waits until the signal level of the connection line SCL is LOW (5311) and the signal level of the connection line SCL changes to HIGH (5312). When the signal level of the connection line SCL changes to HIGH (the result of 5312 is “Y”), 1 is added to the value of the variable CN (5313). Then, the state 5314 in which the signal level of the connection line SCL is HIGH is entered, and the process waits until the signal level of the connection line SCL changes to LOW (5315). When the signal level of the connection line SCL changes to LOW (the result of 5315 is “SCL ▽”), when the bus is monitored by the self-occupied WDT 641, the self-occupied WDT 641 is stopped and the bus is monitored by the self-occupied WDT 641. The process ends (5316).

  The bus controller 634 determines whether or not the value of the variable CN has reached 8, that is, whether or not all eight data have been output to the connection line SDA (5317). If the output of all the data has not been completed (the result of 5317 is “N”), the next data is output to the connection line SDA (5318), and the processing after step 5310 is executed.

  On the other hand, the bus controller 634 reaches the value of the variable CN, completes transmission of all data (the result of 5317 is “Y”), drives the driver 632, and turns off the transistor 630, thereby connecting the connection line. The SDA is released (5319). However, since the processing of step 5319 is necessary only when the bus controller 634 has set the connection line SDA to the LOW level, the bus controller 634 has set the connection line SDA to the HIGH level. No need to run.

  At this time, since the signal level of the connection line SCL becomes LOW and the signal level of the connection line SDA becomes HIGH (5320), the process waits until the signal level of the connection line SCL becomes HIGH (5321).

At this time, data in units of 8 bits has already been transmitted from the I ² CI / O expander 615 to the master IC 570a (see FIG. 11 and the master IC 570b in FIG. 12). When the next data is received, the master IC 570a (570b) sends an ACK to the I ² CI / O expander 615.
Response signal is transmitted.

  When the signal level of the connection line SCL becomes HIGH (the result of 5321 is “SCLΔ”), the bus controller 634 takes in the signal level (response signal) of the connection line SDA (5322). Then, it is determined whether or not the captured response signal is ACK (LOW level), that is, whether or not the master IC is ready to receive the next data (5323).

  At this time, if the captured response signal is ACK (result of 5323 is “Y”), the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW (5324). The bus controller 634 waits until the signal level of the connection line SCL changes to LOW (5325). When the signal level of the connection line SCL changes to LOW (the result of 5325 is “SCL ▽”), the value of the variable CN is set to 0 (5326), and the processing after step 5318 is performed to output the next data. Run.

On the other hand, when the captured response signal is NACK (the result of 5323 is “N”), the bus controller 634 sets the variable CN to 0, the state number to 0, and further clears the reception buffer ( 5327). At this time, the signal levels of the connection line SCL and the connection line SDA are both HIGH, corresponding to the state 5103 in FIG. 51 and step 510 in FIG.
Step 4 is executed.

  Next, the timing at which data is exchanged between the CPU 551 of the effect control device 550 and the first master IC 570a and the second master IC 570b in the embodiment of the present invention will be described.

  FIG. 54 is a timing chart showing a state in which processing by the first master IC 570a and the second master IC 570b is executed in parallel according to an instruction from the CPU 551 of the effect control device 550 at the time of VDP interruption according to the embodiment of this invention. .

  In the embodiment of the present invention, when a VDP interrupt occurs at the timing of updating the image displayed on the display device 53, the CPU 551 of the effect control device 550 starts outputting effect control data to each master IC. When each master IC receives the effect control data from the CPU 551, the master IC performs processing such as transmitting the received effect control data to each slave independently of the other master ICs. When the output of the effect control data is completed for all the slaves, each master IC outputs a stop condition and updates the effect mode of the effect device (decoration device 620) controlled by each slave.

  In this way, the processing by the first master IC 570a and the second master IC 570b is executed in parallel, and further, the effect that is harmonized with the image display is achieved by synchronizing the update timing of the effect mode of each effect device with the VDP interrupt. Can be performed.

  More specifically, when a VDP interrupt occurs, the CPU 551 of the effect control device 550 executes a slave output start process (steps 3710 and 39 in FIG. 37) and outputs a start condition to each master IC. .

  Then, CPU 551 edits output data to each device controlled by effect control device 550. Specifically, VDP output data editing for performing an effect on the display device 53 (step 3711 in FIG. 37), speaker-related data editing for outputting sound from the speaker 30 (step 3712 in FIG. 37), and an effect device Editing of the effect control data to be output to the decoration control device 610 that controls the LED (step 3713 in FIG. 37) and data editing for controlling a driving body such as a motor are performed. If a master interrupt to the CPU 551 is generated by each master IC during the execution of these editing processes, the edited effect control data is stored in the output buffer 572 of each master IC by the effect resumption data transmission restart process (FIG. 43). Written. Then, the effect control data is output to each slave by the data transmission process by the master shown in FIG.

  Finally, when the production control data is transmitted to all the slaves to be transmitted, a stop condition is output from the master IC to the slave by the transmission restart process of the production control data (step S4311 in FIG. 43). The effect control data received by each slave is reflected in the effect mode of each effect device.

  Thereafter, the CPU 551 waits until the next VDP interrupt occurs. When the next VDP interrupt occurs, the slave output start process (steps 3710 and 39 in FIG. 37) is executed to output a start condition to each master IC, and thereafter the same process is repeated.

By such processing, the processing by the first master IC 570a and the second master IC 570b is executed in parallel, and the arithmetic processing of the CPU 551 is also executed in parallel, so that it synchronizes with the image update of the image display device 53. Such high-speed processing becomes possible, and an effect in harmony with image display can be performed.

  Next, a configuration example of the grouped effect device (decoration device 620) will be described.

FIG. 55 is a diagram showing a connection example between the I ² CI / O expander 615 of the decoration control device 610 and the decoration device 620 according to the embodiment of the present invention, and eight sets of LEDs are connected to two I ² CIs. FIG. 6 is a diagram illustrating a configuration controlled by a / O expander 615.

  It is assumed that the decoration device 620 is configured by an LED as an example. By controlling the three colors of red (R), green (G), and blue (B) as one set, it is possible to emit light in various colors. Make it possible. For example, when all red, green, and blue LEDs are colored, white light can be emitted.

In the embodiment of the present invention, one I ² CI / O expander 615 can control LEDs corresponding to 16 ports (PORT 0 to 15). Up to 5 sets can be connected.

However, in order to produce an effect that further enhances interest, there may be a case where an LED (production device) is connected to more than 16 ports. FIG. 55 illustrates a configuration in which five or more sets (eight sets) of LEDs are connected and controlled across two I ² CI / O expanders 615.

As described above, the I ² CI / O expander 615 has 16 ports (PORT 0 to 15).
) Is provided, it is possible to connect up to five sets of three-color LEDs. However, when the presentation is performed with eight sets of LEDs as one group, at least two I ² CI / O expanders 615 are required.

Therefore, in the configuration shown in FIG. 55, one I ² CI / O expander 615 controls the red and green LEDs of each set, and the other I ² CI / O expander 615 (615b)
Each set of blue LEDs is configured to be controlled. And these two I ² CIs
/ O expander 615 is controlled as the same group, and, as will be described later with reference to FIG. 56, by receiving the stop condition output from the effect control device 550 and simultaneously executing the effect control, a plurality of I ² CI / L controlled by O expander 615
This makes it possible to produce an ED without any discomfort.

  FIG. 56 is a diagram illustrating the timing at which the decoration control device 610 receives data and controls the effect device according to the embodiment of the present invention, and the case where the received data is reflected when the stop condition is output will be described. FIG.

In this figure, first, the start condition is output from the effect control device 550, then the effect control data is sequentially output from the effect control device 550 to the plurality of I ² CI / O expanders 615, and finally, the effect is displayed. A state in which a stop condition is output from the control device 550 is shown. For convenience of explanation, the I ² CI / O expander 615 of the decoration control device 610 is used.
Are provided, and each of them is a first I ² CI / O expander to a fifth I ² CI / O expander.

Here, “data 1” in the figure is the first I ² from the production control device 550.
The production control data transmitted to the CI / O expander is shown below. “Data2” to “data5” are sent from the production control device 550 to the ^{second I 2} CI / O expander to the fifth I ² CI / O expander. The effect control data transmitted to each is shown.

In the figure, “Production device (1)” indicates an LED connected to the I / O port of the first I ² CI / O expander. "-" effect device (5) "is the first 2I ² CI / O expander, second 5I ² CI / O Aix LED is connected to the expander of the I / O ports, etc., respectively correspond.

Incidentally, the effect control device 550, when transmitting the performance control data to the 1I ² CI / O expander, second 5I ² CI / O expander Each of timing for switching the selection of the I ² CI / O expander Thus, a start condition (functioning as a restart condition) is output from the effect control device 550 to the I ² CI / O expander. However, after the production control device 550 first outputs the start condition, the first I ² CI / O
The stop condition is not output until the production control data is transmitted to all of the expander to the 5th I ² CI / O expander (period indicated by T in the figure), and the stop condition is output after the elapse of this period T. Output.

In the embodiment of the present invention, the production control data is serially transmitted from the connection line SDA, so that there is a time difference in the timing at which the production control data arrives for each I ² CI / O expander. Each I ² CI / O expander temporarily secures the received effect control data in a buffer (not shown) built in the bus controller 634 (FIG. 18) when receiving the effect control data from the effect control device 550. It ’s just that.

Here, each I ² CI / O expander independently receives the LED control data at the same time as the LED
A case is assumed where processing that changes the light emission mode is performed. Since a time difference is caused in the change in the light emission mode of the LED, there is a possibility that an uncomfortable effect may be performed.

For example, when red (R), green (G), and blue (B) LEDs are connected across a plurality of I ² CI / O expanders as shown in FIG. There is a possibility that the LED emits light in a color that misleads the player.

  Specifically, the reliability notification device 15 (FIG. 2) described above is set so that the degree of expectation that is a big hit differs depending on the color of light emission, and if the reliability notification device 15 glows red, the big hit is determined. It is assumed that it is in the specification. And the case where the alerting | reporting operation | movement which makes the reliability alerting | reporting apparatus 15 light-emit in purple which does not become a big hit decision is assumed.

When performing such a notification operation, control is performed such that the red LED and the blue LED in the light emitter provided in the reliability notification device 15 are simultaneously turned on and the light emitter emits purple light. L connected across a plurality of I ² CI / O expanders as shown in FIG.
Due to the time difference when the ED emits light, if there is a moment when only the red LED is lit, it may be misunderstood that the player is a big hit and there is a risk of trouble between the game store and the player.

Therefore, in the embodiment of the present invention, when the stop condition is received from the effect control device 550, the effect control data in the buffer is overwritten in the output setting register 635, and the storage contents of the output setting register 635 are stored in the output controller 636. Is reflected on the driver 637 to change the light emission mode of the LED connected to the I ² CI / O expander.

Therefore, as shown in FIG. 56, at the time of stop condition output, the effect control data received by each I ² CI / O expander can be reflected simultaneously in the output mode of each effect device, and an effect without a sense of incongruity is performed. It becomes possible.

In the embodiment of the present invention, the timing at which the effect control data received by the I ² CI / O expander is reflected in the output mode of each effect device is the time of receiving the stop condition exemplified as the update command signal. Other update command signals may be used. An update command signal that can be expressed by a signal change of the connection lines SDA and SCL even if it is transmitted in the middle of the transmission of the production control data, not limited to the one transmitted at the end of the production control data as in the stop condition If so, it is applicable.

FIG. 57 is a diagram illustrating a procedure for releasing a bus when the I ² CI / O expander 615 occupies the bus in the embodiment of the present invention.

When a start condition is output from the master IC, the master IC starts outputting data to the slave I ² CI / O expander 615, and the STA (start flag) of the master IC is set to ON. Thereafter, the master IC sequentially transmits 8-bit data from B7 to B0 to the I ² CI / O expander 615 while sequentially changing the signal level of the connection line SCL. At this time, the I ² CI / O expander 615 on the slave side sequentially captures data corresponding to the change in the signal level of the connection line SCL.

  When 8 bits (1 byte) of data, that is, 1 time of data is transmitted, the connection line SDA is released on the master IC side (step 5201 in FIG. 52). When the connection line SDA is released, the signal level is set to HIGH. And it waits until a reply signal (ACK, NACK) is transmitted from the slave side.

The slave I ² CI / O expander 615 sets the signal level of the connection line SDA to LOW.
The response signal (ACK) is output. After that, the master IC changes the signal level of the connection line SCL from LOW to HIGH and then changes from HIGH to LOW, and the slave I ² CI / O expander 615 receives the connection line SDA. (Corresponding to steps 5207 to 5212 in FIG. 52).

Referring to FIG. 57, when the 7th bit data is transmitted on the master IC side, it is recognized on the slave side that the signal level of the connection line SCL has changed due to noise or the like, and the I ² CI / O EX on the slave side is recognized. The panda 615 recognizes that 8-bit data has been transmitted. Therefore, the slave sets the signal level to LOW in order to output the response signal (ACK) and occupies the connection line SDA. In the embodiment of the present invention, monitoring of the occupation of the connection line SDA by the slave is simultaneously started by the self-occupied WDT 641.

At this time, the master IC cannot transmit data (B0) until it is changed to HIGH because the connection line SDA is occupied by the slave I ² CI / O expander 615 and the signal level is LOW. It has become. Further, since the I ² CI / O expander 615 on the slave side is on standby until the signal level of the connection line SCL changes, the slave side I ² CI / O expander 615 is on standby until the signal level changes. Resulting in. Therefore, in the embodiment of the present invention, as described above, the I ² CI / O expander 6 on the slave side is used.
15 occupies the connection line SDA is monitored by the self-occupied WDT 641, and when a predetermined time elapses after the occupancy starts, the slave side I ² CI / O expander 615 itself is reset. This forcibly releases the connection line SDA.

When the connection line SDA is released, the master IC transmits the last data. At this time, the slave I ² CI / O expander 615 transmits a response signal (NACK) indicating that data could not be received normally. As a result, a retransmission request is notified to the master IC by the CPU 551, data can be retransmitted, and processing can be restarted.

FIG. 58 shows a state where the connection line SDA is occupied for some reason in the embodiment of the present invention, and the I ² CI / O expander 615 that detects the occupation of the connection line SDA resets itself. FIG. 6 is a diagram illustrating a procedure for attempting to release a bus.

In FIG. 57, the case where the I ² CI / O expander 615 occupying the connection line SDA releases the connection line SDA by resetting itself is described, but in FIG. 58, the entire bus is monitored, A procedure for forcibly releasing a bus when another slave (another I ² CI / O expander 615 or the like connected to the connection line SDA) does not release the bus because the connection line SDA is occupied. To do.

  The monitoring by the bus monitoring WDT 640 starts when the signal level of the connection line SDA becomes LOW level and ends when the signal level of the connection line SDA becomes HIGH level. That is, when the signal level of the connection line SDA is continuously LOW, a command for outputting a reset signal is output from the bus monitoring WDT 640 to the reset signal generation circuit 639.

As described in FIG. 57, when the bus is occupied by I ² CI / O expander 615 on the slave side, the input and output of signals between the master IC and the slave side of the I ² CI / O expander 615 It stops, and the signal level of the connection line SDA does not change (becomes waiting until the signal level changes). Therefore, when the signal level of the connection line SDA does not change for a predetermined time, all the I ² CI / O expanders 615 connected to the connection line SDA reset themselves by their respective judgments. To release the bus.

Referring to FIG. 58, after data B1 is output from the master IC, the bus is occupied by another slave. In the case of FIG. 58, since the bus is not occupied by the own slave, the slave that is actually occupied cannot be specified. Therefore, each of the slaves (I ² CI / O expander 615) connected to the connection line SDA releases the bus by resetting itself. (To be exact, I ² C connected to the connection line SDA
Only the I / O expander 615 that has a function of resetting itself performs the reset process. )
As a result, the remaining data is transmitted from the master IC, a response signal (NACK) indicating that reception has failed is output from the slave, and the data is retransmitted by responding, and the processing is continued.

FIG. 59 shows an I ² CI / O expander 615 on the slave side in the embodiment of the present invention.
If the bus is occupied by the slave side of the I ² CI by a command from the master IC
It is a figure explaining the procedure in which / O expander 615 releases a bus | bath.

When the number of changes in the signal level of the connection line SCL differs between the master side and the slave side due to noise or the like, as described above, the connection line SDA becomes the I ² CI / O expander 615 on the slave side.
And the bus is not released.

Therefore, when a predetermined time or more elapses while the bus is occupied, a timeout interrupt is generated in the CPU 551 by the monitoring timer circuit 562 (see FIGS. 10 and 41). At this time, the CPU 551 initializes the master IC by executing a soft reset. Each slave (I ² CI / O expander 615 connected to the master IC)
) To output a stop condition and a start condition.

At this time, the I ² CI / O expander 615 on the slave side first executes the stop condition output process shown in FIG. At this time, since the signal levels of the connection line SCL and the connection line SDA are both LOW, the SCL release processing is executed (4604 in FIG. 46, FIG. 47). Since the connection line SDA is occupied, the SCL release processing is executed normally, and the signal level of the connection line SCL is set to HIGH.

Subsequently, the process of step 4605 in FIG. 46 is executed, and the SDA release monitoring process (FIG. 48) is executed. In the SDA release monitoring process, the signal level of the connection line SDA is changed to HIGH in the process of step 4803. However, since it is occupied by the slave I ² CI / O expander 615, it cannot be set to HIGH. Therefore, the processing after step 4805 is executed.

At this time, the master IC changes the signal level of the connection SCL at least nine times. By doing so, the I ² CI / O expander 615 on the slave side detects the change in the signal level of the connection SCL from HIGH to LOW during the change of the signal level of the connection SCL at least nine times. The connection line SDA is released (corresponding to exiting the loop of steps 5208 to 5211 in FIG. 52).

Next, after confirming that the connection line SDA has been released, the master IC outputs a stop condition to the I ² CI / O expander 615 on the slave side, then outputs a start condition, and again transmits data. I do.

FIG. 60 is a diagram illustrating an example in which the master IC causes a read mode to occur in the slave I ² CI / O expander 615 due to an erroneous command from the master IC in the embodiment of the present invention. FIG. 6 is a diagram for explaining a procedure by which the slave I ² CI / O expander 615 releases the bus in response to the command.

In the present embodiment, the I ² CI / O expander 615 from the master IC to the slave side is used.
On the other hand, it is not intended to transmit a command for generating the read mode, but it is assumed that the I ² CI / O expander 615 makes a decision on its own due to the influence of noise or the like and shifts to the read mode. And explain.

Even when the I ² CI / O expander 615 is in the read mode, if a predetermined time or more elapses while the bus is occupied, the monitor timer circuit 562 causes the CPU 551 to time out as in the case of the write request. An interrupt occurs (see FIGS. 10 and 41). At this time, as described in FIG. 58, the CPU 551 first initializes the master IC by executing a soft reset. Then, an attempt is made to output a stop condition and a start condition to each slave (I ² CI / O expander 615 connected to the master IC). At this time, as described above, the SDA release monitoring process (FIG. 48) is executed.

When the SDA release monitoring process is executed and the signal level of the connection SCL is changed at least nine times, the I ² CI / O expander 615 outputs data to the connection line SDA in accordance with the change of the signal level of the connection SCL. In the middle of changing the signal level of the connection SCL nine times, a timing for confirming the response signal (ACK) from the master IC occurs. At this time, since the connection SDA is left open on the master IC side, the I ² CI /
When the O expander 615 captures the signal level of the connection SDA, the O expander 615 recognizes that it has received a response signal of NACK that becomes HIGH level, determines that the subsequent data transmission should be stopped, and releases the connection line SDA. To do.

According to the embodiment of the present invention, when each master IC (signal level control unit) included in the effect control device 550 (group overall control unit) transmits data to the decoration control device 610 (group unit control unit), the decoration is performed. Since a response signal is transmitted from the control device 610 to the effect control device 550, it is possible to confirm whether or not data transmission has been performed, and malfunction can be prevented.

  Further, according to the embodiment of the present invention, the effect control device 550 transmits data to the decoration control device 610 via one data line (connection line SDA), and the decoration control device 610 transmits to the effect control device 550. Since the response signal is transmitted through the same data line, the wiring between the substrates can be reduced.

  Furthermore, according to the embodiment of the present invention, a single data line is common to data transmission from the group overall control means to the group unit control means and response signal transmission from the group unit control means to the group overall control means. Since the data line is occupied by the group unit control unit and cannot be used because it is used, the initialization unit initializes the group unit control unit, thereby occupying the data line. Since the state can be canceled, communication can be prevented from being stopped.

  Further, according to the embodiment of the present invention, the group unit control means that occupies the data line itself determines the occurrence of the communication stop state and initializes itself, thereby other group unit control means. The data line can be released without affecting the process.

  Further, according to the embodiment of the present invention, when the occupation state of the data line is detected, all of the group unit control means connected to the data line initializes itself, thereby reliably connecting the data line. Can be released.

  According to the embodiment of the present invention, a command for releasing a data line can be transmitted from the group overall control means. In addition, since the start timing and output end timing of the response signal are commanded from the group overall control means, the processing of the group unit control means is simplified. Then, after a response signal starts to be output, if a problem occurs such that an output end command does not arrive, the occupancy cancel command means cancels the problem and the communication can be restored to a normal state.

  Furthermore, according to the embodiment of the present invention, even if there is an upper limit on the number of decoration control devices 610 that can be connected to one master IC, the production control device 550 is provided with a plurality of master ICs to increase the number. The decoration control device 610 can be used.

  In the embodiment of the present invention, the first master IC 570a (first signal level control means) controls the effect device provided in the game board 10, and the second master IC 570b (second signal level control means). Is configured to control the effect device provided in the front frame 3. Thus, when developing the front frame 3 and the game board 10 by making the effect device provided in the game board 10 and the effect device provided in the front frame 3 into different groups, the decoration control device. Since it is only necessary to consider the upper limit number of 610 limited to each group to be developed, it is possible to improve development efficiency, for example, by developing devices in parallel for each configuration.

Furthermore, according to the embodiment of the present invention, a master IC is selected by the CPU 551, and a plurality of decoration control devices 610 (I ² CI / O expanders 615) connected to the selected master IC are collectively initialized. Therefore, compared with a method of selecting and initializing the decoration control devices 610 one by one, high-speed initialization processing can be performed.

At this time, it is possible to perform control such that only the decoration control device 610 connected to the selected master IC is initialized and the decoration control device 610 connected to another master IC that is not selected is not initialized.

  Therefore, since only the decoration control device 610 belonging to the minimum necessary range can be initialized among all the decoration control devices 610 provided in the gaming machine, the decoration control device 610 is initialized and the effect device. The frequency at which the operation is interrupted can be reduced.

  Further, according to the embodiment of the present invention, when all the master ICs are to be reset, a hard reset is performed. Therefore, compared with a case where each master IC is soft reset one by one. Initialization can be performed at high speed.

  On the other hand, when a part of the master ICs is to be reset, the initialization is executed by a soft reset via the data bus. Therefore, it is complicated to input signals individually to the initialization signal input terminals of all the master ICs. It is sufficient to provide one port without requiring a simple circuit. In other words, all master ICs that are always executed at the time of startup can be reset at high speed, and only a part of master ICs that are executed only in an emergency can be reset with a simplified circuit. Therefore, this is particularly effective in a configuration with a large number of master ICs.

  In addition, according to the embodiment of the present invention, since the processing by the master IC operates in parallel, high-speed processing is possible. Further, since the effect mode of the effect device is controlled to be synchronized with the screen update timing, the effect of light emission in harmony with the screen display becomes possible.

  Furthermore, according to the embodiment of the present invention, the timing at which the captured data is reflected as the output mode of the effect device is determined by the signal level change (reception of the stop condition) of the timing signal line and the data line. A signal such as a conventional LAT signal becomes unnecessary. This eliminates the need for wiring for transmitting the LAT signal, and makes it possible to simplify the wiring.

  Further, according to the embodiment of the present invention, it is possible to transmit individual effect control data to the plurality of decoration control devices 610 using the same signal line, and each effect device to be controlled. It is possible to simultaneously update the production mode.

  In the embodiment of the present invention described above, luminance data for designating the light emission mode of a light emitting element such as an LED (decoration device 620), operation data of a driving body, and the like by slave output data editing processing when a VDP interrupt occurs. Production control data (slave output data) was created. In the slave output data editing process, slave output data is created for all the decoration devices 620.

  Also, all necessary processes (processes from steps 3707 to 3721 in FIG. 37) must be completed at intervals at which VDP interrupts occur. However, when the number of decoration devices 620 increases, the time required for the slave output data editing process increases, and there is a possibility that all processes executed when a VDP interrupt occurs cannot be completed.

  Therefore, by generating a timer interrupt at a predetermined interval and dividing and executing the process of creating the slave output data of the decoration device 620 when the timer interrupt occurs, the load concentration in the slave output data editing process is distributed. Let A modification example in which the processing at the time of occurrence of the VDP interrupt is executed smoothly by doing this will be described below.

In the modified example of the embodiment of the present invention, description will be made especially on effect control data (slave output data) for controlling the light emission mode of a light emitting element such as an LED. The same processing can be performed for a driving body such as a motor.

  First, FIG. 61 shows a table for storing effect control data (lighting pattern data) to be output to the slave, and FIG. 62 describes a configuration for generating a timer interrupt. Further, processing changed from the embodiment of the present invention will be described with reference to FIGS. 63 and 64. Finally, the flow of the entire process will be described with reference to FIG.

  FIG. 61 is a diagram showing an example of a lighting pattern table 6100 for storing lighting pattern data of a decoration device 620 according to a modification of the embodiment of the present invention.

  The lighting pattern table 6100 stores lighting patterns (luminance data) of the decoration device 620 (LED). The lighting pattern table 6100 is stored in the RAM 553 of the effect control device 550, for example. Since each entry of the lighting pattern table 6100 corresponds to the decoration device 620 (LED), the number of entries of the decoration device 620 (LED) is registered.

  The lighting pattern table 6100 includes an LED number 6101, an assigned group number 6102, an assigned slave number 6103, luminance data 6104, and an update completion flag 6105.

The LED number 6101 is an identifier for uniquely identifying each decoration device 620 (LED). Each decoration device 620 is managed in group units (in other words, production device units) together with other related decoration devices 620 on the basis of the arrangement and the production mode. The belonging group number 6102 is identification information of a group to which each decoration device 620 belongs. The affiliated slave number 6103 is identification information of a slave (I ² CI / O expander 615) that controls each decoration device 620.

That is, it is assumed that LEDs having the same group number are used in the same effect device. Further, LEDs having the same belonging slave number are controlled by the same I ² CI / O expander 615.

Further, the decoration device 620 (LED) controlled by the same slave (I ² CI / O expander 615) can be configured to belong to another group. For example, the LED with the LED number “8” belongs to the group “2” and the slave “2”. The LED with the LED number “9” belongs to the group “3”, but the slave “2” belongs to the group. Even if the LEDs are controlled by the same slave, they are managed so as to belong to different groups.

Luminance data 6104 is a slave (I ² CI /) that controls each decoration device 620 (LED).
This is data for setting the brightness of the LED transmitted to the O expander 615). Luminance is the intensity of light output from the LED. The larger the value of the luminance data, the greater the amount of light output from the LED.

  The update completion flag 6105 is information indicating whether or not the update of the luminance data 6104 has been completed. The update completion flag 6105 is set to “ON” when the update of the luminance data 6104 is completed when a timer interrupt occurs, and the update has been completed. If not, “OFF” is set.

As described above, the presentation control data (slave output data) is created for all the decoration devices 620 every time a VDP interrupt occurs. Then, the production control data including the light emission mode is transmitted to each slave (I ² CI / O expander 615) in the transmission interruption interrupt generated in the master output process (FIG. 45). In addition, since all slave output data is generated by one VDP interrupt, the update completion flag 6105 of each entry in the lighting pattern table 6100 is all set after the VDP interrupt is generated and before the creation of slave output data is started. Set to “OFF”. For example, it is set before the process of step 3707 in FIG.

  Then, the brightness data 6104 of each entry is updated by timer interrupt processing described later, and the update completion flag 6105 is set to “ON”. In the modification of the embodiment of the present invention, before the luminance data 6104 is updated, for example, when the next timer interruption occurs during the generation of the luminance data, the generation of the luminance data is stopped. In other words, if the creation of the brightness data is not completed before the next timer interrupt occurs, the brightness data of the next LED is created without continuing the creation. At this time, the luminance data 6104 that should be set in the interrupted timer interrupt process is not updated, and the update completion flag 6105 remains set to “OFF”. The handling of the decoration device 620 (LED) whose update completion flag 6105 is “OFF” will be described later in the processing of step 6403 in FIG.

  In the example shown in FIG. 61, a light emitting element such as an LED has been described. However, a driving body such as a motor or a solenoid can be handled in the same manner. In this case, an entry of the driving body may be added to the lighting pattern table 6100 shown in FIG. 61, or another table may be prepared.

  FIG. 62 is a block diagram showing a configuration of an effect control device 550 according to a modification of the embodiment of the present invention.

  An effect control device 550 according to a modification of the embodiment of the present invention is different from the effect control device 550 shown in FIG. 10 in that a general-purpose timer circuit 567 is provided, and the other configurations are the same. FIG. 62 shows a configuration around the general-purpose timer circuit 567. Hereinafter, the general-purpose timer circuit 567 will be described.

  The general-purpose timer circuit 567 has a built-in timer and outputs an interrupt signal (effect mode determination timing signal) to the CPU 551 at designated time intervals. The general-purpose timer circuit 567 can be used for a general purpose by specifying an arbitrary time interval.

  When the CPU 551 receives an input of an interrupt signal from the general-purpose timer circuit 567, the CPU 551 interrupts the process being executed and executes a process corresponding to the input interrupt signal. At this time, in the modification of the embodiment of the present invention, the slave output data editing process that is executed each time a timer interrupt occurs creates luminance data for one LED (FIG. 63).

  Also, since the brightness data of all LEDs must be created within the interval at which the VDP interrupt occurs, the time interval for generating the timer interrupt is more than the time obtained by dividing the VDP interrupt occurrence interval by at least the number of all LEDs Must also be short. For example, when the VDP interrupt occurs at a cycle of 33.3 ms, if the number of LEDs is 100, control is performed to generate a timer interrupt at a cycle of at least 0.3 ms.

  FIG. 63 is a flowchart showing a procedure of general-purpose timer interrupt processing when an interrupt signal is generated from general-purpose timer circuit 567 according to the modification of the embodiment of the present invention.

When the interrupt signal from the general-purpose timer circuit 567 is generated, the effect control device 550 next selects an LED for editing the luminance data (6301). This process is a process of selecting one LED registered in the lighting pattern table 6100 of FIG. 61, and the LED next to the LED number selected when the previous interrupt signal is generated from the general-purpose timer circuit 567. The number is selected.

  When the interrupt signal from the general-purpose timer circuit 567 is generated immediately after the VDP interrupt, the LED whose LED number is “1” in the lighting pattern table 6100 is selected. If the last LED number in the lighting pattern table 6100 is selected when the previous interrupt signal is generated from the general-purpose timer circuit 567, it is considered that the processing for all the LEDs has been completed. The general-purpose timer interrupt process of FIG. 63 is not executed.

  Subsequently, the luminance data of the LED to be selected is generated, and the luminance data 6104 of the corresponding entry in the lighting pattern table 6100 is updated (6302). When the update of the luminance data 6104 is completed, the corresponding update completion flag 6105 is set to “ON” (6303).

  As described above, when the next interrupt signal from the general-purpose timer circuit 567 is generated before the luminance data is updated, this processing is interrupted. By controlling in this way, even if it takes time to create the brightness data of a specific LED for some reason, the process is stopped and the brightness data of the next LED is created. Luminance data can be updated without bias.

  FIG. 64 is a flowchart showing a procedure of slave output data editing processing according to a modification of the embodiment of the present invention.

  The slave output data editing process is a process executed when a VDP interrupt occurs, and corresponds to the process of step 3713 in FIG. In the slave output data editing process described above, the production control data (slave output data) of each slave including the luminance data of each LED is generated and stored in the output data preparation area secured on the RAM 553 (see FIG. 36).

  On the other hand, in a modification of the embodiment of the present invention, luminance data is generated by timer interruption processing (FIG. 63), and the generated luminance data is stored in the lighting pattern table 6100 (FIG. 61). Then, presentation control data is generated based on the brightness data 6104 and the update completion flag 6105 of each entry, and stored in the output data preparation area secured on the RAM 553. Details will be described below.

  When the slave output data editing process is started, the effect control device 550 first checks the update completion flags 6405 of all the entries in the lighting pattern table 6100 (6401). Then, it is determined whether or not the update completion flag 6405 of all entries is “ON” (6402).

  When the update completion flag 6405 corresponding to all the LEDs is not “ON”, that is, the brightness data of at least one LED has not been created (the result of 6402 is “N”). ), The lighting pattern data (luminance data) is corrected (6403).

  The lighting pattern data (luminance data) to be corrected includes an LED related to the LED in addition to the LED whose update completion flag 6405 is “OFF”. For example, when notifying some information to the player by light emission of a plurality of LEDs, if other related LEDs are lighted as they are without turning on some of the LEDs, a color different from the color that should be output originally This is because it may cause the player to misunderstand.

The other related LED may be another LED of the group to which the LED for which luminance data could not be created belongs, or a slave (I ² CI / O export) that controls the LED for which luminance data could not be created. Other LEDs controlled by the panda 615 and the decoration control device 620) may be used.

  For example, the correction of the luminance data is set so that the LEDs for which the luminance data is not created and other related LEDs are not lit. If the number of LEDs for which luminance data could not be created is small, the luminance data for the LEDs may be recreated.

  In addition, since the brightness | luminance of LED often changes continuously, you may make it utilize previously updated brightness | luminance data as it is. In this case, the brightness of other related LEDs may be used for the data before update. At this time, the luminance data stored in the lighting pattern table 6100 has been updated, but since the luminance data (effect control data) transmitted immediately before is stored in the output data saving area, this may be used. .

  When the update completion flag 6405 corresponding to all LEDs is “ON” (the result of 6402 is “Y”), or when the correction of the lighting pattern data is completed, the effect control device 550 displays the effect control data corresponding to the luminance data. And the effect control data generated in the output data preparation area (FIG. 36) is set. The subsequent processing is the same as that of the above-described embodiment of the present invention.

  FIG. 65 is a diagram for explaining the execution timing of the master output process (data transmission command process) and the slave output data edit process according to the embodiment and the modification of the present invention. FIG. 65A shows the execution timing of the master output processing and slave output data editing processing according to the embodiment of the present invention, and FIG. 65B shows the master output processing and the modification of the embodiment of the present invention. It is a figure which shows the execution timing of a slave output data edit process.

  The time T in FIGS. 65 (A) and 65 (B) indicates the period in which the VDP interrupt occurs, and is set to 33.3 ms, for example. A time t in FIG. 65B indicates the execution interval of the slave output data editing process, that is, the interval at which the general-purpose timer circuit 567 generates an interrupt. In the slave output data editing process executed at every time t, luminance data for one decoration device 620 (LED) provided in the gaming machine is created, so the time t represents the time T and the decoration device 620 (LED). The time divided by the number of can also be set to a time shorter than this.

  The master output process corresponds to the process in which the CPU 551 instructs the first master IC 570a or the second master IC 570b to perform the data transmission process by the master shown in FIG. 45, and is common to the embodiments and modifications of the present invention. It is executed at the timing. In the master output process, when a transmission interrupt (master interrupt) occurs, a process for instructing transmission of initialization instruction data (FIG. 42) or a process for instructing transmission of effect control data (FIG. 43) is executed.

  At this time, when the interrupt process by the general-purpose timer is being executed, the process by the master interrupt is preferentially executed. By controlling in this way, data can be reliably transmitted from the master IC to each slave.

  In the slave output data editing process (step 3713 in FIG. 37) of the embodiment of the present invention shown in FIG. 65 (A), the brightness data of all the decoration devices 620 (LEDs) is created, and thereafter, in the output data preparation area. Stores data. Therefore, when the number of LEDs for creating luminance data is large, there is a possibility that the time for executing the subsequent process in the main process is insufficient.

On the other hand, in the modification of the embodiment of the present invention shown in FIG. 65 (B), the luminance data is already created by the general-purpose timer interrupt when the slave output data editing process (step 3713 in FIG. 37) is executed. Has been. When the unprocessed decoration device 620 (LED) remains, it may wait until the brightness data of the remaining LED is created, or the brightness data may be created without using the timer interrupt process. That's fine.

  Then, in the slave output data editing process (step 3713 in FIG. 37, FIG. 64) of the modified example of the embodiment of the present invention, the luminance data creation status is checked based on the update completion flag 6105 and corrected if necessary. It is only necessary to do this (step 6403 in FIG. 64).

  By configuring as described above, it is possible to secure a sufficient time for creating the control data of the effect device when the VDP interruption occurs, and it is possible to perform the effect control more smoothly. Further, even if the number of processes for determining the light emission mode of light emitting elements such as LEDs is increased, the processing load of the CPU 551 can be equalized because the processes are performed in a distributed manner during the image update period.

  The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

  Moreover, the following is mentioned as a typical thing of the viewpoint of this invention other than what was described in the claim.

  (1) When the game ball passes through a predetermined start winning area provided in the game area, a variable display game is displayed in which a plurality of identification information is displayed in a variable manner. In a gaming machine capable of generating a special game state to be granted, it corresponds to a game control means for comprehensively controlling a game in the game area, a plurality of effect devices for effecting a game, and a command from the game control means. An effect control means for controlling the plurality of effect devices, and an image display device for displaying an image relating to a game. Each of the systems of the effect devices is divided into a plurality of groups, and the divided groups are divided into groups. A group unit control unit for controlling the production device to which the group unit control unit is provided for each group, and the production control unit is configured to collectively control each of the group unit control units; And a timing signal line for transmitting a timing signal from the group control unit to the group unit control unit, and a data line for transmitting a data signal from the group control unit to the group unit control unit. Thus, data transmission is enabled between the group overall control unit and each group unit control unit, and the group overall control unit generates an image update signal for updating an image of the image display device. And sequentially changing the signal level of the timing signal line while setting the signal level of the data line to the signal level corresponding to the data to be transmitted, so that the group unit control means sequentially synchronizes with the image update signal. And transmitting means for transmitting data while performing the transmission Is connected to the group unit control unit, and the data between the group unit control unit is connected to the group unit control unit based on a command from the calculation processing unit. Signal level control means for controlling each signal level of the line and the timing signal line, and the arithmetic processing by the arithmetic processing means and the control of each signal level by the signal level control means are respectively performed in parallel. A gaming machine characterized by being executable.

  (2) The arithmetic processing means executes the process of determining the effect mode of the effect device a plurality of times and periodically while the image update signal is generated (1) The gaming machine described in 1.

(3) Processing for determining an effect mode of the effect device, comprising effect mode determination timing signal generation means for periodically generating an effect mode determination timing signal so as to have a cycle shorter than the generation cycle of the image update signal. The game machine according to (2), which is executed when the production mode determination timing signal is generated.

  (4) The rendering device includes a plurality of light emitting elements that decorate the gaming machine by emitting light, and the process of determining the rendering mode of the rendering device determines the lighting mode of the light emitting element. The gaming machine according to (2) or (3), wherein

  (5) When the transmission interrupt from the signal level control means occurs, the arithmetic processing means executes data transmission command processing for instructing the signal level control means to transmit data to the group unit control means. The gaming machine according to (4), wherein the data transmission command process is executed in preference to a process for determining a light emission mode of the light emitting element.

  (6) The arithmetic processing means performs processing for creating production control data to be transmitted to the group unit control means and setting the signal level control means for each period in which the image update signal is generated, If transmission of the effect control data to the group unit control means fails, the effect control data that failed to be transmitted is not set again in the signal level control means at the next timing of updating the image of the image display device. The game machine according to any one of (1) to (5), wherein newly created production control data is set.

  (7) The gaming machine according to any one of (1) to (6), wherein a plurality of the signal level control means are provided, and each is configured to be operable in parallel.

  According to the invention of (1), since the arithmetic processing means and the signal level control means operate in parallel, high-speed processing that is synchronized with the image update of the image display device is possible.

  According to the inventions of (2) to (4), even if the number of processes for determining the effect mode of the effect device, such as the light-emission mode of the light-emitting element, is increased and processed in an image update cycle, It is possible to prevent an increase in processing load on the arithmetic processing means.

  According to the invention of (5), priority is given to the interruption by the signal level control means, so that data can be transmitted reliably. Furthermore, even if the processing time of the signal level control means increases, it is possible to prevent the processing load on the arithmetic processing means from increasing simply by temporarily interrupting the process for determining the light emission mode of the light emitting element.

  According to the invention of (6), since the effect control data is always transmitted in accordance with the image update timing, it is possible to control the content of the image to match the effect content of the effect device.

  According to the invention of (7), since a plurality of signal level control means operate in parallel, higher speed processing becomes possible.

  As described above, the present invention can be applied to a gaming machine in which an effect control device controls an effect device via a plurality of decoration control devices.

1 gaming machine 2 body frame (outer frame)
3 Front frame (game frame)
9a, 9b Decoration member 10 Game board 12 Auxiliary game device unit 13 1st movable illumination 13a Illumination drive 1st motor (MOT)
14 Second movable illumination 14a Illumination drive second motor (MOT)
15 Reliability notification device 29 Abnormality notification LED
30 Speakers 45 Side lamps 51 Center case 53 Display device 58 Movable effect device 63 First effect unit 64 Second effect unit 70 First effect member 71 The accessory drive first motor (MOT)
80 2nd production member 81 Second article drive second motor (MOT)
500 Game control device 550 Production control device 563 General-purpose timer circuit 570a First master IC
570b Second master IC
581 Command register (REG)
582 Status register (REG)
583 Self-address setting register (REG)
600 Relay board 603 Empty terminal monitor 610 Decoration control device 615 I ² CI / O expander 620 Decoration device 625 Decoration device board 640 Bus monitoring watchdog timer (WDT)
641 Self-occupied watchdog timer (WDT)
1600 Simple relay board 3200, 3300 Abnormality determination table 6100 Lighting pattern table

Claims (1)

Game control means for overall control of the game;
A plurality of directing devices for directing games;
In response to a command from the game control means, effect control means for controlling the plurality of effect devices;
With
Dividing each of the systems of the rendering devices into a plurality of groups, and providing group unit control means for controlling the rendering devices belonging to the divided group in each group,
The production control means is configured as a group overall control means for comprehensively controlling each of the group unit control means,
Between the group supervisory controlling means and wherein each said group-unit control unit, wherein the timing signal line for transmitting a timing signal, and a data line for transmitting data signals, and the group supervisory controlling means by providing each Enables data transmission with the group unit control means,
The group overall control means is:
While repeatedly setting the signal level of the timing signal line while setting the signal level of the data line to the signal level corresponding to the data to be transmitted, the transmitter includes a transmission unit that sequentially transmits data to the group unit control unit,
The transmission means includes
Arithmetic processing means for performing arithmetic processing related to the control of the rendering device;
A signal level control unit connected to the group unit control unit and controlling each signal level of the data line and the timing signal line with the group unit control unit based on a command from the arithmetic processing unit;
Comprising
In the data transmitted by the group overall control means to the group unit control means,
Control information relating to the rendering mode of the rendering device;
Reflection regulation information that defines the timing at which the group unit control means reflects the production mode of the production device is included,
The group unit control means includes:
A first initialization means for initializing the group unit control means by inputting an initialization signal to an initialization signal input terminal provided separately from the data line;
A second initialization unit that initializes the group unit control unit in response to receiving predetermined initialization instruction data from the group overall control unit via the data line,
At the timing specified in the reflection definition information transmitted from the group overall control means, the effect mode of the effect device is reflected in the effect mode corresponding to the control information,
A gaming machine characterized in that arithmetic processing by the arithmetic processing means and control of each signal level by the signal level control means can be executed in parallel.