JP6232089B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a SiC semiconductor device having a trench gate structure.

2. Description of the Related Art Conventionally, semiconductor power devices mainly used in systems in various power electronics fields such as motor control systems and power conversion systems have attracted attention.
As this type of semiconductor power device, for example, a SiC semiconductor device having a trench gate structure has been proposed.
For example, Patent Document 1 discloses an n ⁺ type SiC substrate, an n ⁻ type epitaxial layer (drift region) formed on the SiC substrate, and a p type body region formed on the surface side of the epitaxial layer. The n ⁺ -type source region formed on the surface side in the body region, the gate trench formed so as to penetrate the source region and the body region and reach the drift region, and the inner surface of the gate trench A field effect transistor is disclosed that includes a gate insulating film and a gate electrode embedded in a gate trench.

JP 2011-134910 A

  An object of the present invention is to provide a semiconductor device that can achieve both a low on-resistance and a high withstand voltage, and can achieve a reduction in device size, an improvement in manufacturing yield, and a reduction in cost.

A semiconductor device according to an embodiment of the present invention includes a semiconductor layer made of SiC of a first conductivity type in which a gate trench and a source trench are formed, a gate insulating film formed on a side surface and a bottom surface of the gate trench, A gate electrode embedded in the gate trench and opposed to the semiconductor layer via the gate insulating film; and formed to be exposed on a surface side of the semiconductor layer; A source layer of a first conductivity type forming a part of a side surface of the source trench; and a back surface side of the semiconductor layer with respect to the source layer so as to be in contact with the source layer; And a second conductivity type channel layer forming a part of the side surface of the source trench and the back side of the semiconductor layer with respect to the channel layer A drift layer of a first conductivity type formed so as to be in contact with the channel layer and forming the bottom surface of the gate trench; and in a partial region of the gate trench, the side surface and the bottom surface of the gate trench intersect. A gate withstand voltage holding layer of a second conductivity type formed so as to cover an edge portion or in contact with only the bottom surface of the gate trench, and the depth of the gate trench and the depth of the source trench are The same .

A semiconductor device according to another embodiment of the present invention includes a semiconductor layer made of SiC of a first conductivity type in which a gate trench is formed, a gate insulating film formed on a side surface and a bottom surface of the gate trench, and the gate trench. A gate electrode facing the semiconductor layer with the gate insulating film interposed therebetween, and exposed to the surface side of the semiconductor layer, and forming a part of the side surface of the gate trench A source layer of one conductivity type, and a channel layer of a second conductivity type formed so as to be in contact with the source layer on the back side of the semiconductor layer with respect to the source layer and forming a part of the side surface of the gate trench And a first conductivity type drift formed to be in contact with the channel layer on the back side of the semiconductor layer with respect to the channel layer and forming the bottom surface of the gate trench Layer and the first portion which is formed so as to cover an edge portion of said gate trench and intersects the bottom and side surfaces, said second portion formed in contact only with the bottom surface of the gate trench of the gate trench And a second conductivity type gate withstand voltage holding layer including the first conductivity type and a second conductivity type formed in the drift layer so as to be continuous with the channel layer and extending from the channel layer toward the back surface of the semiconductor layer. Including a pillar layer.

FIGS. 1A and 1B are schematic plan views of a semiconductor device according to the first embodiment of the present invention. FIG. 1A is an overall view, and FIG. Each is shown. FIG. 2 is a cross-sectional view of the semiconductor device of FIGS. 1A and 1B and shows a cut surface taken along the section line II-II of FIG. FIG. 3 is a cross-sectional view of the semiconductor device of FIGS. 1A and 1B, and shows a cut surface taken along the section line III-III of FIG. FIG. 4 is a graph (simulation data) showing the relationship between the on-resistance R _on and the withstand voltage V _b in the semiconductor device of FIGS. 2 and 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention, and shows a cut surface at the same position as FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention, and shows a cut surface at the same position as FIG. FIG. 7 is a graph (simulation data) showing the relationship between the on-resistance R _on and the withstand voltage V _b in the semiconductor device of FIGS. 5 and 6. FIG. 8 is a schematic cross-sectional view of the semiconductor device according to the third embodiment of the present invention, and shows a cut surface at the same position as FIG. FIG. 9 is a schematic cross-sectional view of the semiconductor device according to the third embodiment of the present invention, and shows a cut surface at the same position as FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIGS. 1A and 1B are schematic plan views of a semiconductor device according to the first embodiment of the present invention. FIG. 1A is an overall view, and FIG. Each is shown. FIG. 2 is a cross-sectional view of the semiconductor device of FIGS. 1A and 1B and shows a cut surface taken along the section line II-II of FIG. FIG. 3 is a cross-sectional view of the semiconductor device of FIGS. 1A and 1B, and shows a cut surface taken along the section line III-III of FIG.

The semiconductor device 1 includes a trench gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor) employing SiC. The outer shape of the semiconductor device 1 is, for example, a chip having a square shape in plan view, as shown in FIG. As for the size of the chip-like semiconductor device 1, the length in the vertical and horizontal directions on the paper surface of FIG.
A source pad 2 is formed on the surface of the semiconductor device 1. The source pad 2 has a substantially square shape in plan view with four corners curved outward, and is formed so as to cover almost the entire surface of the semiconductor device 1. The source pad 2 has a removal region 3 near the center of one side. The removal region 3 is a region where the source pad 2 is not formed.

A gate pad 4 is disposed in the removal region 3. A gap is provided between the gate pad 4 and the source pad 2 and they are insulated from each other.
Next, the internal structure of the semiconductor device 1 will be described.
The semiconductor device 1 includes a substrate 5 made of SiC and an epitaxial layer 6 made of SiC formed on the substrate 5. The conductivity types of substrate 5 and epitaxial layer 6 are both n-type as the first conductivity type. Specifically, the substrate 5 is n ⁺ type (for example, the concentration is 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ ), and the epitaxial layer 6 is n ⁻ type (for example, lower in concentration than the substrate 5). The concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ ).

The thickness of the substrate 5 is, for example, 30 μm to 400 μm, but can be appropriately changed within the above range according to the channel mobility of the semiconductor device 1. As an example, when the channel mobility is 11 cm ² / Vs or more, the thickness of the substrate 5 is preferably 100 μm or less (and 50 μm or more). When the channel mobility is 50 cm ² / Vs or more, the thickness of the substrate 5 may be 250 μm or less (and 200 μm or more).

  For the substrate 5 having such a thickness, as long as the SiC wafer having the thickness can be obtained, the SiC wafer may be used as it is as indicated by “before thinning” in FIG. On the other hand, if it is necessary to make the substrate thinner than the SiC wafer, for example, the substrate 5 is formed from the back surface 8 (surface opposite to the surface 7 on which the epitaxial layer 6 is formed) side by a method such as grinding, dry etching, sand blasting or the like. Is thinned as shown by “after thinning” in FIG.

Conventionally, in order to prevent damage to the wafer, the substrate has been made thicker than the epitaxial layer grown thereon. On the other hand, the inventor of the present application has a ratio in which the resistance of the substrate occupies about 15 to 25% of the on-resistance R _{on in the} SiC semiconductor device having the trench gate structure, so that the strength of the semiconductor device 1 is not impaired. Thus, it has been found that if the substrate 5 is thinned, the on-resistance R _on can be effectively reduced while ensuring the strength of the semiconductor device 1.

Moreover, the thickness of the epitaxial layer 6 is 3 micrometers-100 micrometers in this embodiment, for example.
The substrate 5 has an off angle of 4 °, for example. Specifically, the surface 7 (main surface) of the substrate 5 is a surface inclined with an off angle of 4 ° in the [11-20] axial direction with respect to the (0001) plane. The off angle is not limited to this, and can be selected in the range of 0 ° to 4 °.

In the semiconductor device 1, as shown in FIG. 1A, an active region 9 and a peripheral region 10 surrounding the active region 9 are formed. The active region 9 is disposed, for example, in the central portion of the semiconductor device 1 in plan view.
A gate trench 11 is formed in the epitaxial layer 6 in the active region 9. In this embodiment, the gate trenches 11 are formed in a lattice shape as shown in FIG. However, the shape of the gate trench 11 is not limited to the lattice shape, and may be a stripe shape, a honeycomb shape, or the like.

  In this embodiment, the lattice-shaped gate trench 11 is formed, so that the epitaxial layer 6 has a rectangular parallelepiped shape (square shape in plan view) having four corner portions 12 in each window portion surrounded by the gate trench 11. A large number of unit cells 13 are formed. In the unit cell 13, the depth direction of the gate trench 11 is the gate length direction, and the circumferential direction of each unit cell 13 orthogonal to the gate length direction is the gate width direction.

Further, the gate trench 11 is formed in a U-shaped cross section so that a corner portion 16 where the side surface 14 and the bottom surface 15 intersect each other is a curved surface. In this case, the side surface 14 of the gate trench 11 is inclined at an angle of, for example, 0 ° to 4 ° with respect to the vertical surface of the surface 7 of the substrate 5 having an off angle of 0 ° to 4 °. By setting the channel portion of the side surface 14 of the gate trench 11 to substantially an off angle of 0 °, the interface state between the gate insulating film 17 (described later) and the side surface 14 of the gate trench 11 can be lowered. The mobility of the channel formed in the channel layer 26 (described later) can be increased. This can reduce channel resistance, it is possible to reduce the on-resistance R _on.

  The gate trench 11 is formed, for example, by dry etching the epitaxial layer 6 to form the outer shape of the gate trench 11 and then wet etching the inner surface thereof. Thereby, the flatness of the side surface 14 of the gate trench 11 can be improved. As a result, when current flows along the side surface 14 of the gate trench 11, collision between electrons can be reduced, so that channel mobility can be increased.

A gate insulating film 17 made of an insulator such as SiO ₂ is formed on the inner surface (side surface 14, bottom surface 15, and corner portion 16) of the gate trench 11 so as to cover the entire region.
The gate insulating film 17 includes a bottom portion 18 in contact with the bottom surface 15 of the gate trench 11 and a side portion 19 in contact with the side surface 14 of the gate trench 11, and the bottom portion 18 is thicker than the side portion 19. For example, the thickness of the side portion 19 is 400 mm to 800 mm, while the thickness of the bottom portion 18 is 1000 mm to 3000 mm. By thickening the bottom portion 18 in contact with the bottom surface 15 of the gate trench 11 where a large electric field is likely to be applied when the semiconductor device 1 is turned off, electric field concentration on the bottom portion 18 of the gate insulating film 17 can be prevented.

  In order to provide a difference in thickness between the bottom portion 18 and the side portion 19 of the gate insulating film 17, for example, after the formation of the gate trench 11, first, until the inside of the gate trench 11 is filled by a method such as a CVD method. An insulating material is deposited to form an insulating layer. Then, the surface of the insulating layer (etch back surface) is made to recede to the back surface side of the epitaxial layer 6 by a method such as etch back. As a result, the portion of the insulating layer in contact with the side surface 14 of the gate trench 11 is removed, and the insulating layer remaining on the bottom surface 15 is left as the bottom portion 18. Thereafter, the side portion 19 may be formed on the exposed side surface 14 of the gate trench 11 by a method such as thermal oxidation. Through the above steps, the gate insulating film 17 having a thickness difference between the bottom 18 and the side 19 can be formed.

A gate electrode 20 made of a conductive material such as polysilicon is embedded in the gate trench 11. The gate electrode 20 faces the epitaxial layer 6 through the gate insulating film 17.
A source trench 21 is formed at the center of each unit cell 13. In this embodiment, the source trench 21 has a quadrangular shape in plan view, and the depth of the source trench 21 is the same as that of the gate trench 11. Similarly to the gate trench 11, the source trench 21 is also formed in a U-shaped cross section so that a corner portion 24 where the side surface 22 and the bottom surface 23 intersect is a curved surface.

In each unit cell 13, a source layer 25, a channel layer 26 and a drift layer 27 are formed in order from the front surface side to the back surface side of the epitaxial layer 6, and these layers 25 to 27 are in contact with each other. Regarding the conductivity types of these layers 25 to 27, the source layer 25 and the drift layer 27 are n-type as the first conductivity type, and the channel layer 26 is p-type as the second conductivity type. Specifically, the source layer 25 is n ⁺ type (for example, the concentration is 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ ), and the channel layer 26 is p-type (for example, the concentration is 1.0 ×). 10 ¹⁶ cm ^{−3 to} 1.0 × 10 ¹⁹ cm ⁻³ ), and the drift layer 27 has a lower concentration of n ⁻ type than the source layer 25 (for example, the concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm). ^-3 ).

  The source layer 25 forms part of the side surface 14 of the gate trench 11 and part of the side surface 22 of the source trench 21. Similarly, the channel layer 26 forms part of the side surface 14 of the gate trench 11 and part of the side surface 22 of the source trench 21. The drift layer 27 forms the corner portion 16 and the bottom surface 15 of the gate trench 11 and the corner portion 24 and the bottom surface 23 of the source trench 21.

  These layers 25 to 27 may be formed by ion implantation and activation treatment after the epitaxial layer 6 is grown on the substrate 5, or the drift layer 27 and the channel layer 26 in order from the surface 7 side of the substrate 5. Alternatively, the source layer 25 may be formed by direct epitaxial growth. Of these methods, the latter method using epitaxial growth is preferable because the interface state between the gate insulating film 17 and the side surface 14 of the gate trench 11 can be lowered.

In the epitaxial layer 6, a gate withstand voltage holding layer 28 and a source withstand voltage holding layer 29 are formed as a withstand voltage holding layer. The conductivity types of these layers 28 and 29 are both p-type as the second conductivity type. Specifically, the gate withstand voltage holding layer 28 and the source withstand voltage holding layer 29 are p-type (for example, the concentration is 1.0 × 10 ¹⁶ cm ^{−3 to} 1.0 × 10 ¹⁹ cm ⁻³ ).

The gate withstand voltage holding layer 28 is formed along the lattice-shaped gate trench 11, and is formed in the first portion 32 formed at the intersection 30 of the gate trench 11 and the straight portion 31 of the gate trench 11. The second portion 33 is integrally included.
The first portion 32 of the gate withstand voltage holding layer 28 is formed so as to reach from the bottom surface 15 of the gate trench 11 at the intersection 30 to the channel layer 26 immediately above the corner portion 16 through the corner portion 16 of the gate trench 11. . That is, the first portion 32 is formed in a square shape slightly larger than the intersecting portion 30 of the gate trench 11 in plan view, and each corner of each of the four unit cells 13 facing the intersecting portion 30 is formed. Each part enters the part 12. The thickness T ₁ along the direction from the bottom surface 15 of the gate trench 11 toward the substrate 5 in the first portion 32 is, for example, about 0.8 μm.

The second portion 33 of the gate withstand voltage holding layer 28 is formed in a straight line having a constant width connecting the adjacent first portions 32, and only on the bottom surface 15 so as not to overlap the corner portion 16 of the gate trench 11. Is formed. The second portion 33 has a width (for example, 1.8 μm) narrower than the width of the linear portion 31 of the gate trench 11 (the distance between the side surfaces 14 of the gate trench 11 facing each other (for example, 1 μm)). In addition, the thickness T ₂ along the direction from the bottom surface 15 of the gate trench 11 toward the substrate 5 in the second portion 33 is smaller than the thickness T ₁ of the first portion 32 (ie, T ₁ > T ₂ ), For example, it is about 0.7 μm.

The source withstand voltage holding layer 29 is formed so as to reach from the bottom surface 23 of the source trench 21 through the corner portion 24 of the source trench 21 to the channel layer 26 immediately above the corner portion 24. In the source withstand voltage holding layer 29, the thickness T ₃ along the direction from the bottom surface 23 of the source trench 21 toward the substrate 5 is the same as the thickness T ₁ of the first portion 32 of the gate withstand voltage holding layer 28 ( For example, about 0.8 μm).

A channel contact layer 34 is formed on the surface 23 of the source withstand voltage holding layer 29 on the bottom surface 23 of each source trench 21. The conductivity type of the channel contact layer 34 is p-type as the second conductivity type. Specifically, the channel contact layer 34 is p ⁺ type (for example, the impurity concentration is 1.0 × 10 ¹⁸ cm ^{−3 to} 2.0 × 10 ²¹ cm ⁻³ ).
In the peripheral region 10, the surface layer portion of the epitaxial layer 6 has a plurality of p-type guard rings 35 spaced from the active region 9 so as to surround the unit cells 13 (active regions 9) arranged in a matrix. (In this embodiment, four) are formed. These guard rings 35 can be formed by the same ion implantation step as the step of forming the p-type channel layer 26.

On the epitaxial layer 6, an interlayer insulating film 36 made of an insulator such as SiO ₂ is laminated so as to cover the gate electrode 20.
A contact hole 37 having a diameter larger than that of the source trench 21 is formed in the interlayer insulating film 36 and the gate insulating film 17. As a result, the entire source trench 21 of each unit cell 13 and the peripheral edge of the source trench 21 in the epitaxial layer 6 are exposed in the contact hole 37, and the surface of the epitaxial layer 6 and the bottom surface 23 of the source trench 21 are exposed. A step corresponding to the height difference is formed.

  A source electrode 38 is formed on the interlayer insulating film 36. The source electrode 38 enters the source trenches 21 of all the unit cells 13 through the contact holes 37 all together, and in each unit cell 13, the channel contact layer 34, the source It is in contact with the withstand voltage holding layer 29, the channel layer 26 and the source layer 25. That is, the source electrode 38 is a common wiring for all the unit cells 13.

  An interlayer insulating film (not shown) is formed on the source electrode 38, and the source electrode 38 is connected to the source pad 2 (see FIG. 1A) via the interlayer insulating film (not shown). ) Is electrically connected. On the other hand, the gate pad 4 (see FIG. 1A) is electrically connected to the gate electrode 20 through a gate wiring (not shown) routed on the interlayer insulating film (not shown). ing.

The source electrode 38 has a structure in which, for example, a Ti / TiN layer and an Al layer are laminated in order from the contact side with the epitaxial layer 6.
A drain electrode 39 is formed on the back surface 8 of the substrate 5 so as to cover the entire area. The drain electrode 39 is a common electrode for all the unit cells 13. As the drain electrode 39, for example, a stacked structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au, and Ag are stacked in order from the substrate 5 side can be applied.

  For example, the drain electrode 39 is formed by first depositing Ni with a thickness of about 600 mm on the back surface 8 of the substrate 5. Next, the substrate 5 is subjected to a laser annealing process, whereby Ni is silicided to form a contact layer for the substrate 5. By adopting the laser annealing process, unlike the normal annealing process, the source electrode 38 can be prevented from being placed in a high temperature environment, so that the melting of the source electrode 38 can be prevented. After the contact layer is formed, an electrode having a total thickness of 1 μm may be formed in the order of Ti, Ni, Au, and Ag.

Next, since a prototype for examining the relationship between the on-resistance R _on and the withstand voltage V _b of the semiconductor device 1 of FIGS.
Specifically, the semiconductor device 1 having a thickness of the substrate 5 of 100 μm was manufactured. Then, by changing the impurity concentration of the epitaxial layer 6, as the withstand voltage _{V b} of the semiconductor device 1 becomes 600V and 1200V, respectively, were measured on-resistance _{R on} of the time. As a result, the on-resistance R _on when the withstand voltage V _b = 600 V was 0.79 mΩ · cm ² , and the on-resistance R _on when the withstand voltage V _b = 1200 V was 1.41 mΩ · cm ² . The drain saturation current (I _DSS ) when measuring the withstand voltage V _b was 100 μA, and the current density J _D when measuring the on-resistance R _on was 100 A / cm ² .

A simulation for examining the relationship between the on-resistance R _on and the withstand voltage V _b of the semiconductor device 1 of FIGS. 2 and 3 will be described.
Specifically, the thickness of the substrate 5 for each of the four patterns of semiconductor devices in which channel mobility (Ch mobility) is set to 11 cm ² / Vs, 30 cm ² / Vs, 50 cm ² / Vs, and 100 cm ² / Vs. A simulation was performed for each of the condition (Sub thinning) set to 100 μm and the condition where the thickness of the substrate 5 was set to 250 μm, and a total of eight simulation examples 1 to 8 were performed.

In each of the simulation examples 1 to 8, the impurity concentration of the epitaxial layer 6 is changed so as to have a predetermined withstand voltage _Vb (the smaller the measurement No, the higher the impurity concentration of the epitaxial layer 6; the larger the measurement No, the higher the epitaxial layer 6). impurity concentration is thin), and were simulated on-resistance R _on of the time. Then, the on-resistance R _on and a variable y, by expressing a function of the breakdown voltage V _b and the variable x, was examined what relationship holds between the withstand voltage V _b and the resistance R _on. The drain saturation current (I _DSS ) when measuring the withstand voltage V _b was 100 μA, and the current density J _D when measuring the on-resistance R _on was 100 A / cm ² .

  The results are shown in Table 1 below and FIG.

In FIG. 4, the graphs obtained by connecting the plots of Examples 1 to 8 are graphs of Example 5, Example 6, Example 1 = Example 7, Example 8, Example 2, Example 3, and Example 4 in order from the top.
Among these Examples 1 to 8, the graph of Example 1 satisfies y ₁ = 9 × 10 ⁻⁷ x ₁ ² −0.0004x ₁ +0.7001 (1 ′), and the graph of Example 7 has y ₂ = 9 × 10 ⁻⁷ x ₂ ² −0.0004x ₂ +0.6984 ( _{2 ′} ) is satisfied, and the graph of Example 3 shows y ₃ = 9 × 10 ⁻⁷ x ₃ ² −0.0004x ₃ +0.4434. 3 ′) is satisfied.

From the above results, it has been found that according to the semiconductor device 1 of the first embodiment, the relational expression (1) that cannot be expressed in the conventional semiconductor device is established.
y ≦ 9 × 10 ⁻⁷ x ² −0.0004x + 0.7001 = y ₁ (1)
When this relational expression (1) is satisfied, in the prior was able to be both improved reduced and the withstand voltage V _b of the resistance R _on which was the relationship of trade-off.

As a result, when a product having the same resistance as that of the conventional product (a product having the same on-resistance R _on ) is manufactured, a sufficient withstand voltage V _b can be secured while reducing the area of the active region 9 of the substrate 5 and the epitaxial layer 6. Therefore, the device size can be reduced, and the semiconductor module including the semiconductor device 1 can also be reduced in size. As a result, the number of chips obtained from one substrate 5 can be increased, so that the manufacturing yield can be improved and the manufacturing cost can be reduced.

On the other hand, in case of manufacturing a semiconductor device having the same active area as conventional products, since the on-resistance R _on is reduced as compared with the conventional products, thereby improving the current capacity.
Further, when the thickness of the substrate 5 is 100 μm or less (Example 1 to Example 4), even if the channel mobility is increased in order to reduce the channel resistance, the above relational expression is satisfied as long as the channel mobility is 11 cm ² / Vs or more. (1) can be established. Therefore, the epitaxial layer 6 can be formed relatively thick, and the impurity concentration of the epitaxial layer 6 can be reduced. Therefore, it is possible to achieve high even with the same on-resistance R _on withstand voltage V _b.

On the other hand, even when the thickness of the substrate 5 is 250 μm, if the channel mobility is 50 cm ² / Vs or more (Examples 7 to 8), the relational expression (1) can be established. In this case, even if the substrate 5 is made thin in order to reduce the resistance of the substrate 5, it may be 250 μm or less, so that a practically sufficient strength can be imparted to the substrate. As a result, in the manufacturing process of the semiconductor device 1, the substrate 5 can be efficiently handled and diced.

  In the semiconductor device 1, a drain voltage is applied between the source electrode 38 and the drain electrode 39 (between the source and drain) with the source electrode 38 grounded. In this state, when a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 20, a channel is formed along the channel layer 26 that forms the side wall of each unit cell 13. Thereby, a current flows from the drain electrode 39 to the source electrode 38, and each unit cell 13 is turned on.

On the other hand, if each unit cell 13 is turned off (that is, the gate voltage is 0 V) and the voltage is still applied between the source and the drain, the gate interposed between the gate electrode 20 and the epitaxial layer 6 is provided. An electric field is applied to the insulating film 17.
This electric field is generated due to a potential difference between the gate electrode 20 and the epitaxial layer 6. On the bottom surface 15 of the gate trench 11, equipotential surfaces with a very high potential are distributed with the gate electrode 20 as a reference (0 V), and the interval between the equipotential surfaces is small, so a very large electric field is generated. For example, if the drain voltage is 900 V, an equipotential surface of 900 V is distributed in the vicinity of the back surface 8 of the substrate 5 in contact with the drain electrode 39, and the voltage drop increases from the back surface 8 of the substrate 5 toward the surface side of the epitaxial layer 6. However, an equipotential surface of about several tens of volts is distributed near the bottom surface 15 of the gate trench 11. Therefore, a very large electric field is generated on the bottom surface 15 of the gate trench 11 toward the gate electrode 20 side. In particular, as in this embodiment, when the gate trenches 11 are formed in a lattice shape and the rectangular columnar unit cells 13 are arranged in the windows of the lattice-like gate trenches 11, each of the unit cells 13 In the vicinity of the corner portion 16 of the gate trench 11 formed in the corner portion 12, the dielectric breakdown of the gate insulating film 17 is particularly likely to occur.

Specifically, the distance D ₁ (see FIG. 2) between the source trenches 21 adjacent to each other on the diagonal line of the intersecting portion 30 of the gate trench 11 is equal to the distance between the source trenches 21 adjacent to each other across the straight portion 31 of the gate trench 11. It becomes larger than the distance D ₂ (see FIG. 3) (for example, in this embodiment, D ₁ is 1.4 times D ₂ ). Therefore, an equipotential surface enters immediately below the corner portion 16 of the intersecting portion 30 of the gate trench 11 having a relatively wide space, and the equipotential surfaces are densely formed. As a result, the dielectric breakdown of the gate insulating film 17 is particularly likely to occur near the corner portion 16 of the gate trench 11.

  Therefore, in the semiconductor device 1 of this embodiment, the gate withstand voltage holding layer 28 (first portion 32) is formed in the corner portion 16 of the intersecting portion 30 of the gate trench 11. Thereby, a depletion layer generated by the junction (pn junction) between the first portion 32 and the drift layer 27 can be generated in the vicinity of the intersection 30 of the gate trench 11. Further, in the semiconductor device 1, a source withstand voltage holding layer 29 is formed in the corner portion 24 of the source trench 21 formed in each unit cell 13. Therefore, the depletion layer generated by the junction (pn junction) between the source withstand voltage holding layer 29 and the drift layer 27 can be expanded toward the corner portion 16 of the intersection 30 of the gate trench 11 surrounding the source trench 21.

  Due to the presence of these depletion layers, it is possible to prevent an equipotential surface from entering between the corner portion 16 of the intersecting portion 30 of the gate trench 11 and the corner portion 24 of the source trench 21, and away from the gate insulating film 17. . As a result, it is possible to prevent the equipotential surfaces from being concentrated in the vicinity of the corner portion 16 of the intersecting portion 30 of the gate trench 11. As a result, the electric field applied to the gate insulating film 17 can be reduced, so that dielectric breakdown can be prevented.

  In the semiconductor device 1, the first portion 32 is formed so as to reach the channel layer 26 immediately above the corner portion 16 through the corner portion 16, but no channel is formed in the corner portion 12 of the unit cell 13. Even if it is formed, the current flowing through the channel is very small. Therefore, by forming the gate withstand voltage holding layer 28 (first portion 32) so as to reach the portion of the channel layer 26 immediately above the corner portion 16, the performance of the gate insulating film 17 is hardly affected. The destruction prevention effect can be further improved.

  On the other hand, a gate withstand voltage holding layer 28 (second portion 33) having a width narrower than the width of the straight portion 31 is formed in the straight portion 31 of the gate trench 11. Thereby, a depletion layer generated by the junction (pn junction) between the second portion 33 and the drift layer 27 can be generated along the straight portion 31 of the gate trench 11. Therefore, the electric field generated immediately below the straight portion 31 of the gate trench 11 can be relaxed by the depletion layer. As a result, the electric field generated in the gate insulating film 17 can be alleviated uniformly.

Moreover, the gate withstand voltage holding layer 28 (second portion 33) is not formed on the side surface 14 of the straight portion 31 of the gate trench 11 (that is, the portion where the channel is formed in the unit cell 13). Therefore, the channel characteristics can be controlled with high accuracy.
FIG. 5 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention, and shows a cut surface at the same position as FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention, and shows a cut surface at the same position as FIG. 5 and FIG. 6, parts corresponding to the respective parts shown in FIG. 2 and FIG. 3 are denoted by the same reference numerals as those given to those parts, and the description thereof is omitted.

In the semiconductor device 51 according to the second embodiment, the source trench 21 is not formed. In this embodiment, the channel contact layer 34 formed on the bottom surface 23 of the source trench 21 is formed on the surface of the epitaxial layer 6.
In the semiconductor device 51, the p-type pillar layer 52 is formed in the drift layer 27.
The p-type pillar layer 52 is formed in an inner region of the channel layer 26 of each unit cell 13. More specifically, in this embodiment, the p-type pillar layer 52 is formed in a region substantially in the center of the channel layer 26, for example, similar to the channel layer 26 (in the layout of FIG. 1B, a square in plan view). Has been. The p-type pillar layer 52 is formed to be continuous with the channel layer 26, and extends toward the substrate 5 in the drift layer 27 to a position deeper than the channel layer 26. That is, the p-type pillar layer 52 is formed in a substantially columnar shape (substantially a square columnar shape in the layout of FIG. 1B).

As a result, the epitaxial layer 6 includes p-type pillar layers 52 arranged at an appropriate pitch and n ⁻ -type drift layers 27 sandwiched between adjacent p-type pillar layers 52 of the epitaxial layer 6. A super junction (SJ) structure is formed by being alternately arranged in the direction along the surface.
Next, a simulation for examining the relationship between the on-resistance R _on and the withstand voltage V _b of the semiconductor device 51 of FIGS. 5 and 6 will be described.

Specifically, the thickness of the substrate 5 for each of the four patterns of semiconductor devices in which channel mobility (Ch mobility) is set to 11 cm ² / Vs, 30 cm ² / Vs, 50 cm ² / Vs, and 100 cm ² / Vs. A simulation was performed for each of the condition (Sub thinning) set to 100 μm and the condition where the thickness of the substrate 5 was set to 250 μm, and a total of eight simulation examples 9 to 16 were performed.

In each of the simulation examples 9 to 16, the impurity concentration of the epitaxial layer 6 is changed so as to have a predetermined withstand voltage _Vb (the smaller the measurement No, the higher the impurity concentration of the epitaxial layer 6; the larger the measurement No, the higher the epitaxial layer 6). impurity concentration is thin), and were simulated on-resistance R _on of the time. Then, the on-resistance R _on and a variable y, by expressing a function of the breakdown voltage V _b and the variable x, was examined what relationship holds between the withstand voltage V _b and the resistance R _on. The drain saturation current (I _DSS ) when measuring the withstand voltage V _b was 100 μA, and the current density J _D when measuring the on-resistance R _on was 100 A / cm ² .

  The results are shown in Table 2 below and FIG.

In FIG. 7, graphs obtained by connecting plots of Examples 9 to 16 are graphs of Example 13, Example 14, Example 9 = Example 15, Example 16, Example 10, Example 11, and Example 12 in order from the top.
Among these Examples 1 to 8, the graph of Example 13 satisfies y ₄ = 2 × 10 ⁻⁷ x ₄ ² −0.0002x ₄ +0.9551 ( _{4 ′} ), and the graph of Example 9 has y ₅ = 2. X10 ⁻⁷ x ₅ ² −0.0002x ₅ +0.7001 (5 ′) is satisfied, and the graph of Example 15 shows y ₆ = 2 × 10 ⁻⁷ x ₆ ² −0.0002x ₆ +0.6984 (6) ′), And the graph of Example 11 satisfies y ₇ = 2 × 10 ⁻⁷ x ₇ ² −0.0002x ₇ +0.4434 (7 ′).

From the above results, it has been found that according to the semiconductor device 51 of the second embodiment, the relational expression (4) that cannot be expressed in the conventional semiconductor device is satisfied.
y ≦ 2 × 10 ⁻⁷ x ² −0.0002x + 0.9551 = y ₄ (4)
Then, if this equation (4) is satisfied, in the prior it was able to be both improved reduced and the withstand voltage V _b of the resistance R _on which was the relationship of trade-off.

As a result, when a product having the same resistance as that of the conventional product (a product having the same on-resistance R _on ) is manufactured, a sufficient withstand voltage V _b can be secured while reducing the area of the active region 9 of the substrate 5 and the epitaxial layer 6. Therefore, the device size can be reduced, and the semiconductor module including the semiconductor device 1 can also be reduced in size. As a result, the number of chips obtained from one substrate 5 can be increased, so that the manufacturing yield can be improved and the manufacturing cost can be reduced.

On the other hand, in case of manufacturing a semiconductor device having the same active area as conventional products, since the on-resistance R _on is reduced as compared with the conventional products, thereby improving the current capacity.
Furthermore, according to the semiconductor device 51, since the super junction structure is formed in the epitaxial layer 6 by the p-type pillar layer 52 and the n ⁻ -type drift layer 27 (Examples 9 to 16), the channel mobility is 11 cm ^2. The relational expression (4) can be established by setting the thickness of the substrate to 250 μm or less.

That is, even if the channel mobility is increased, it may be 11 cm ² / Vs or more, and even if the substrate 5 is thinned, it may be 250 μm or less. Therefore, the epitaxial layer 6 can be kept relatively thick and the impurity concentration can be reduced. In contrast, practically sufficient strength can be imparted.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.

  For example, in the present invention, by combining the configurations of the semiconductor device 1 of the first embodiment and the semiconductor device 51 of the second embodiment, as shown in FIGS. 8 and 9, the source trench 21 and the p-type pillar layer 52 ( It can also be implemented by a semiconductor device 81 having a super junction structure. In this semiconductor device 81, the p-type pillar layer 52 is configured by the source withstand voltage holding layer 29 of the first embodiment extending toward the substrate 5 to a position deeper than the channel layer 26.

Moreover, the structure which reversed the conductivity type of each semiconductor part of the semiconductor devices 1, 51, 81 may be adopted. For example, in the semiconductor devices 1, 51, 81, the p-type portion may be n-type and the n-type portion may be p-type.
Each unit cell 13 is not limited to a rectangular parallelepiped shape (quadrangular columnar shape), and may be other polygonal columnar shapes such as a triangular prism shape, a pentagonal column shape, and a hexagonal column shape.

  The semiconductor power device of the present invention is, for example, a power used for an inverter circuit constituting a drive circuit for driving an electric motor used as a power source for an electric vehicle (including a hybrid vehicle), a train, an industrial robot, and the like. Can be incorporated into modules. It can also be incorporated into a power module used in an inverter circuit that converts electric power generated by a solar cell, wind power generator, or other power generation device (especially an in-house power generation device) to match the power of a commercial power source.

In addition, the above-described embodiment is merely an example of the form in which the relational expressions (1) and (4) representing the relationship between the on-resistance R _on (y) and the withstand voltage V _b (x) in the present invention are established, The present invention can be modified in various ways within the scope of the matters described in the claims.
In addition to the invention described in the claims, the following features can be extracted from the contents of the above-described embodiment.
(Claim 1) A substrate made of SiC of a first conductivity type, an epitaxial layer made of SiC of the first conductivity type formed on the substrate and having a gate trench formed thereon, and formed on side and bottom surfaces of the gate trench. A gate electrode embedded in the gate trench and opposed to the epitaxial layer through the gate insulating film, and exposed to the surface side of the epitaxial layer. A source layer of a first conductivity type that forms a part of the side surface; and a source layer on the back side of the epitaxial layer with respect to the source layer, and a part of the side surface of the gate trench. A channel layer of a second conductivity type to be formed, and a shape in contact with the channel layer on the back side of the epitaxial layer with respect to the channel layer Is, and a first conductivity type drift layer that forms the bottom surface of the gate trench, the on-resistance R _on and a variable y, when showing the withstand voltage V _b by a function whose variable x, the following equation A semiconductor device characterized in that (1) holds.

y ≦ 9 × 10 ⁻⁷ x ² −0.0004x + 0.7001 (1)
According to the semiconductor device of item 1, when the on-resistance R _on (mΩ · cm ² ) is a variable y and the function is expressed by a function having a withstand voltage V _b (V) as the variable x, the relational expression (1) is Therefore, it is possible to achieve both the reduction of the on-resistance R _on and the improvement of the withstand voltage V _b , which have conventionally been in a trade-off relationship.

Thus, when the conventional equal-resistance product (on-resistance R _on the same product) to produce, since it ensures a sufficient withstand voltage while reducing the active area of the substrate and the epitaxial layer, the device size small As a result, a semiconductor module including the semiconductor device of the present invention can be reduced in size. As a result, the number of chips obtained from one substrate can be increased, so that the manufacturing yield can be improved and the manufacturing cost can be reduced.

On the other hand, in case of manufacturing a semiconductor device having the same active area as conventional products, since the on-resistance R _on is reduced as compared with the conventional products, thereby improving the current capacity.
For example, in the semiconductor device, when the mobility of a channel formed in the channel layer in the epitaxial layer is 11 cm ² / Vs or more, the thickness of the substrate is preferably 100 μm or less (Item 2).

In the SiC semiconductor device having the trench gate structure as described above, the ratio of the substrate resistance to the on-resistance R _on is about 15 to 25%. Therefore, the on-resistance R _on can be effectively reduced by setting the thickness of the substrate to 100 μm or less. Therefore, even if the channel mobility is increased in order to reduce the channel resistance, it may be 11 cm ² / Vs or more, so that the epitaxial layer can be formed relatively thick or the impurity concentration of the epitaxial layer can be reduced. . Therefore, a high withstand voltage can be realized.

In the semiconductor device, it is preferable that the following relational expression (2) holds for the on-resistance R _on and the withstand voltage V _b (Section 3).
y ≦ 9 × 10 ⁻⁷ x ² −0.0004x + 0.6984 (2)
In this configuration, for example, when the mobility of a channel formed in the channel layer in the epitaxial layer is 50 cm ² / Vs or more, the thickness of the substrate may be 250 μm or less (Item 4).

By setting the channel mobility to 50 cm ² / Vs or higher, the channel resistance can be sufficiently reduced. Therefore, even if the substrate is thinned in order to reduce the resistance of the substrate, it may be 250 μm or less, and thus a practically sufficient strength can be imparted to the substrate. As a result, substrate handling and dicing can be performed efficiently in the manufacturing process of the semiconductor device.

In the semiconductor device, it is more preferable that the following relational expression (3) holds for the on-resistance R _on and the withstand voltage V _b (Section 5).
y ≦ 9 × 10 ⁻⁷ x ² −0.0004x + 0.4434 (3)
In this configuration, for example, when the mobility of a channel formed in the channel layer in the epitaxial layer is 50 cm ² / Vs or more, the thickness of the substrate is preferably 100 μm or less (Item 6).
(Section 7) A semiconductor device includes a substrate made of first conductivity type SiC, an epitaxial layer made of SiC of the first conductivity type formed on the substrate and having a gate trench formed thereon, side surfaces of the gate trench, and A gate insulating film formed on the bottom surface, a gate electrode embedded in the gate trench and opposed to the epitaxial layer via the gate insulating film, and formed to be exposed to the surface side of the epitaxial layer; A source layer of a first conductivity type that forms a part of the side surface of the gate trench; and a back surface side of the epitaxial layer with respect to the source layer so as to contact the source layer, and the side surface of the gate trench A channel layer of a second conductivity type that forms part of the channel layer, and the channel layer on the back side of the epitaxial layer with respect to the channel layer. It is formed to include a first conductive type drift layer that forms the bottom surface of the gate trench, the on-resistance R _on and a variable y, when showing the withstand voltage V _b as a function of the variable x The following relational expression (4) is established.

y ≦ 2 × 10 ⁻⁷ x ² −0.0002x + 0.9551 (4)
According to the semiconductor device of Item 7, when the on-resistance R _on is represented by a function having the variable y and the withstand voltage V _b is represented by the variable x, the relational expression (4) is established. It is possible to achieve both the reduction of the on-resistance R _on and the improvement of the withstand voltage V _b .
This makes it possible to secure a sufficient withstand voltage V _b while reducing the active area of the substrate and the epitaxial layer when manufacturing the same resistance product as the conventional product (the product having the same on-resistance R _on ). The semiconductor module including the semiconductor device of the present invention can be reduced in size. As a result, the number of chips obtained from one substrate can be increased, so that the manufacturing yield can be improved and the manufacturing cost can be reduced.

On the other hand, in the case of manufacturing a semiconductor device having the same active area as conventional products, since the on-resistance R _on is reduced as compared with the conventional products, thereby improving the current capacity.
For example, the semiconductor device according to item 7 further includes a second conductivity type pillar layer formed in the drift layer so as to be continuous with the channel layer and extending from the channel layer toward the back surface of the epitaxial layer. In this case, the mobility of a channel formed in the channel layer in the epitaxial layer may be 11 cm ² / Vs or more, and the thickness of the substrate may be 250 μm or less (Item 8).

According to this configuration, since the super junction structure including the second conductivity type pillar layer and the first conductivity type drift layer is formed in the epitaxial layer, the channel mobility is set to 11 cm ² / Vs or more, and The relational expression (4) can be established by setting the thickness to 250 μm or less.
That is, even if the mobility of the channel is increased, it may be 11 cm ² / Vs or more, and even if the substrate is thinned, it may be 250 μm or less. Thus, a practically sufficient strength can be imparted.

In the semiconductor device of item 7, it is preferable that the following relational expression (5) holds for the on-resistance R _on and the withstand voltage V _b (item 9).
y ≦ 2 × 10 ⁻⁷ x ² −0.0002x + 0.7001 (5)
In this configuration, for example, when the semiconductor device further includes a second conductivity type pillar layer formed in the drift layer so as to be continuous with the channel layer and extending from the channel layer toward the back surface of the epitaxial layer, It is preferable that the mobility of a channel formed in the channel layer in the layer is 11 cm ² / Vs or more and the thickness of the substrate is 100 μm or less (Item 10).

According to this configuration, since the super junction structure including the second conductivity type pillar layer and the first conductivity type drift layer is formed in the epitaxial layer, the channel mobility is set to 11 cm ² / Vs or more, and The relational expression (5) can be established by setting the thickness to 100 μm or less.
In the semiconductor device according to item 7, it is more preferable that the following relational expression (6) holds for the on-resistance R _on and the withstand voltage V _b (item 11).

y ≦ 2 × 10 ⁻⁷ x ² −0.0002x + 0.6984 (6)
In this configuration, for example, when the semiconductor device further includes a second conductivity type pillar layer formed in the drift layer so as to be continuous with the channel layer and extending from the channel layer toward the back surface of the epitaxial layer, It is preferable that the mobility of a channel formed in the channel layer in the layer is 50 cm ² / Vs or more and the thickness of the substrate is 250 μm or less (Item 12).

According to this configuration, since the super junction structure including the second conductivity type pillar layer and the first conductivity type drift layer is formed in the epitaxial layer, the channel mobility is set to 50 cm ² / Vs or more, and The relational expression (6) can be established by setting the thickness to 250 μm or less.
In the semiconductor device according to item 7, it is particularly preferable that the following relational expression (7) holds for the on-resistance R _on and the withstand voltage V _b (item 13).

y ≦ 2 × 10 ⁻⁷ x ² −0.0002x + 0.4434 (7)
In this configuration, when the semiconductor layer further includes a second conductivity type pillar layer formed in the drift layer so as to be continuous with the channel layer and extending from the channel layer toward the back surface of the epitaxial layer, The mobility of the channel formed in the channel layer is preferably 50 cm ² / Vs or more, and the thickness of the substrate is preferably 100 μm or less (Item 14).

According to this configuration, since the super junction structure including the second conductivity type pillar layer and the first conductivity type drift layer is formed in the epitaxial layer, the channel mobility is set to 50 cm ² / Vs or more, and By making the thickness 100 μm or less, the relational expression (7) can be established.
The semiconductor device preferably further includes a withstand voltage holding layer of a second conductivity type formed on the bottom surface of the gate trench in the epitaxial layer (Item 15).

  According to this configuration, a depletion layer generated by the junction (pn junction) between the withstand voltage holding layer and the drift layer can be generated in the vicinity of the gate trench. The presence of this depletion layer makes it possible to keep the high potential equipotential surface with respect to the gate electrode away from the gate insulating film. As a result, the electric field applied to the gate insulating film can be reduced and dielectric breakdown can be prevented, so that the withstand voltage can be further improved.

In the semiconductor device, the gate insulating film includes a bottom portion in contact with the bottom surface of the gate trench and a side portion in contact with the side surface of the gate trench, and the bottom portion of the gate insulating film includes the gate insulating film. It is preferably thicker than the side portion of the film (Item 16).
By thickening the portion in contact with the bottom surface of the gate trench where a large electric field is likely to be applied when the semiconductor device is turned off, electric field concentration on the bottom portion of the gate insulating film can be prevented.

In the semiconductor device, it is preferable that an off angle of the substrate is 0 ° to 4 ° (Item 17).
According to this configuration, since the interface state between the gate insulating film and the side surface of the gate trench can be lowered, the mobility of the channel formed in the channel layer can be increased. This can reduce channel resistance, it is possible to reduce the on-resistance R _on. Further, when the off angle of the substrate is in the range of 0 ° to 2 °, the channel resistance can be further reduced and the on-resistance R _on can be further reduced.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Source pad 3 Removal area | region 4 Gate pad 5 Substrate 6 Epitaxial layer 7 (Substrate) surface 8 (Substrate) back surface 9 Active region 10 Peripheral region 11 Gate trench 12 Corner part (Unit cell) 13 Unit cell 14 Side surface (of gate trench) 15 Bottom surface of (gate trench) 16 Corner portion (of gate trench) 17 Gate insulating film 18 Bottom portion of (gate insulating film) 19 Side portion of (gate insulating film) 20 Gate electrode 21 Source trench 22 ( Side 23 of source trench 23 Bottom of source trench 24 Corner portion of source trench 25 Source layer 26 Channel layer 27 Drift layer 28 Gate withstand voltage holding layer 29 Source withstand voltage holding layer 30 Intersection 31 of gate trench Linear part (of gate trench) 32 (Gate withstand voltage) Lifting layers) of the first portion 33 (the gate withstand voltage holding layer) second portion 34 channel contact layer 35 guard ring 36 interlayer insulating film 37 contact hole 38 source electrode 39 drain electrode 51 semiconductor device 52 p-type pillar layer 81 semiconductor device

Claims (13)

A semiconductor layer made of SiC of the first conductivity type in which a gate trench and a source trench are formed;
A gate insulating film formed on side and bottom surfaces of the gate trench;
A gate electrode embedded in the gate trench and facing the semiconductor layer via the gate insulating film;
A source layer of a first conductivity type formed so as to be exposed on a surface side of the semiconductor layer and forming a part of the side surface of the gate trench and a part of the side surface of the source trench;
A second conductivity type formed on the back side of the semiconductor layer with respect to the source layer so as to be in contact with the source layer, and forming a part of the side surface of the gate trench and a part of the side surface of the source trench. A channel layer;
A drift layer of a first conductivity type formed so as to be in contact with the channel layer on the back side of the semiconductor layer with respect to the channel layer, and forming the bottom surface of the gate trench;
A second conductivity type gate formed so as to cover an edge portion of the gate trench where the side surface and the bottom surface intersect with each other in a partial region of the gate trench or to be in contact with only the bottom surface of the gate trench. Including a withstand voltage holding layer,
The semiconductor device, wherein a depth of the gate trench and a depth of the source trench are the same. A semiconductor layer made of SiC of the first conductivity type in which a gate trench is formed;
A gate insulating film formed on side and bottom surfaces of the gate trench;
A gate electrode embedded in the gate trench and facing the semiconductor layer via the gate insulating film;
A source layer of a first conductivity type formed so as to be exposed on a surface side of the semiconductor layer and forming a part of the side surface of the gate trench;
A channel layer of a second conductivity type formed so as to be in contact with the source layer on the back side of the semiconductor layer with respect to the source layer, and forming a part of the side surface of the gate trench;
A drift layer of a first conductivity type formed so as to be in contact with the channel layer on the back side of the semiconductor layer with respect to the channel layer, and forming the bottom surface of the gate trench;
A first portion formed so as to cover an edge portion of the gate trench where the side surface and the bottom surface of the gate trench intersect, and a second portion formed so as to contact only the bottom surface of the gate trench. A gate conductivity holding layer of a second conductivity type;
And a second conductivity type pillar layer formed in the drift layer so as to be continuous with the channel layer and extending from the channel layer toward the back surface of the semiconductor layer. The mobility of a channel formed in the channel layer in the semiconductor layer is not less 11cm 2 / ^Vs or more, the thickness of the substrate is 100μm or less, the semiconductor device according to claim 1 or 2. The mobility of a channel formed in the channel layer in the semiconductor layer is not less 50 cm 2 / ^Vs or more, the thickness of the substrate is 250μm or less, the semiconductor device according to claim 1 or 2. The mobility of a channel formed in the channel layer in the semiconductor layer is not less 50 cm 2 / ^Vs or more, the thickness of the substrate is 100μm or less, the semiconductor device according to claim 1 or 2. 3. The semiconductor device according to claim 2 , wherein a mobility of a channel formed in the channel layer in the semiconductor layer is 11 cm ² / Vs or more, and a thickness of the substrate is 250 μm or less. The gate insulating film includes a bottom portion in contact with the bottom surface of the gate trench, and a side portion in contact with the side surface of the gate trench,
It said bottom of said gate insulating film is thicker than the side of the gate insulating film, a semiconductor device according to any one of claims 1 to 6. A thickness of the bottom portion of the gate insulating film is 1000 to 3000 mm;
The semiconductor device according to claim 7 , wherein a thickness of the side portion of the gate insulating film is 400 to 800 mm. The semiconductor layer comprises a substrate off-angle of 0 ° to 4 °, the semiconductor device according to any one of claims 1-8. The semiconductor layer is partitioned by the lattice-shaped gate trenches, and includes a plurality of polygonal columnar unit cells having a plurality of corners,
2. The semiconductor device according to claim 1, wherein the gate withstand voltage holding layer is formed at a corner edge portion of the gate trench formed at the corner portion of the unit cell in an edge portion of the gate trench. The semiconductor device according to claim 2 , wherein the pillar layer is formed deeper than the gate withstand voltage holding layer with reference to the surface of the semiconductor layer. The semiconductor device according to claim 11 , comprising a source trench formed above the pillar layer. The gate trench is formed in a lattice shape having an intersecting portion and a straight portion,
The semiconductor layer is partitioned by the lattice-shaped gate trenches, and includes a plurality of polygonal columnar unit cells having a plurality of corners,
The gate withstand voltage holding layer is
A first portion formed at a corner edge portion of the gate trench formed at the corner portion of the unit cell at an intersection of the lattice-shaped gate trench;
Formed on the bottom surface of the linear portion of the grid the gate trench has a width narrower than the straight portion of the gate trench, and a second portion connecting said first portion adjacent claim 1 the semiconductor device according to.

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