JP6228045B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  A pachinko gaming machine or a spinning-type gaming machine (hereinafter referred to as “pachislot”), which is a kind of gaming machine, can perform various controls by being supplied with voltage. In the gaming machine described in Patent Document 1, when the supply voltage drops below a predetermined value, a power supply stop process corresponding to the backup process is performed, and when the supply voltage recovers to the reference value again, a game corresponding to the return process is performed. State recovery processing is performed.

JP 2008-253829 A

  By the way, when the supply voltage is not stable, such as when an instantaneous power failure occurs, it is assumed that the situation where the supply voltage is equal to or lower than a predetermined value and the situation where the supply voltage is restored to the reference value alternately occur. In such a situation where the supply voltage is not stable, if the recovery process is performed simply because the supply voltage has recovered to the reference value, the backup process is performed again without completing the recovery process. There is a risk that various processes such as these may not be performed normally.

  This invention was made paying attention to the problem which exists in such a prior art, and the objective is to provide the game machine which can suppress that various processes are not performed normally. It is in.

Game machine for solving the above problems includes information storage means capable of storing and holding control information relating to a game, a power-off processing including a backup process for storing stores control information in the information storage unit, a game a return process for returning to the state capable of performing a game control means capable of, and a first signal output means connected to the control signal to be outputted to the game control means and the two-way, at least the Second signal output means connected to the first signal output means so that a control signal can be output , wherein the first control signal that can be output from the game control means to the first signal output means is in the first state or The second signal output means can output a second control signal that can be in the first state or the second state, and the supply voltage is reduced. Reached the specified value Triggering the second control signal to the first state, the first signal output means can output a third control signal that can be in the first state or the second state, said third control signal in response to said second control signal becomes the first state when the first control signal is in the first state is a first state, said game control means, supply The return process can be performed when the voltage has recovered to a reference value exceeding the predetermined value, and the power-off process is performed when the third control signal is in the first state. On the other hand, the first control signal is changed from the first state to the second state, and then the backup process is performed in the power-off process, and after waiting for a predetermined period, the return process is started. The gist is to make it possible.

For the gaming machine, the game control means changes the first control signal from the first state to the second state in response to the third control signal becoming the first state, and at least the Until the return process is started, the first control signal may be set to the second state .

  According to the present invention, it is possible to prevent various processes from being performed normally.

The front view which shows the machine surface side of a pachislot. The block diagram which shows the electrical structure of a pachislot. The figure which shows the storage area of RAM. The flowchart which shows a game progress main process. The figure which shows an output port. The flowchart which shows INT interruption processing. The flowchart which shows a power-off process. The flowchart which shows a power supply return process. The flowchart which shows a power-on process. The flowchart which shows a power-on process. The figure which shows the output mode of the NMI signal according to the NMI permission signal and the power-off signal. The figure which shows the transition of the output condition of a NMI permission signal, a power-off signal, and a NMI signal. The figure which shows the change of the supply voltage when a momentary power failure generate | occur | produces, and a predetermined period.

Hereinafter, one embodiment of the gaming machine will be described with reference to FIGS.
A pachislot machine 10 as a gaming machine shown in FIG. 1 includes a main body 11 as a rectangular parallelepiped equipment container having an open front surface, a front door 12 pivotally supported so as to be capable of rotating and opening with respect to the left side edge of the main body, It has. The main body 11 is located behind the front door 12 and is supported so that the front door 12 can be opened and closed. Further, the front door 12 is provided with a locking device 12a as a locking means capable of regulating the opening of the front door 12. In the pachislot 10, it is possible to open the front door 12 by operating the locking device 12a. The main body 11 is provided with a front door opening sensor KS (shown in FIG. 2) that can detect that the front door 12 is open. In the present embodiment, the state where the front door 12 is open corresponds to the open state of the front door 12, and the state where the front door 12 is closed corresponds to the closed state of the front door 12.

  An effect display device 14 is disposed on the front upper portion of the front door 12. As the effect display device 14, for example, a liquid crystal display type display device, a dot matrix type display device, or the like is used. In addition, the pachislot 10 is provided with a decorative lamp La as a light emitting means for performing a light emitting effect. Further, the pachislot 10 is provided with a speaker Sp as sound output means for performing sound effects.

  Further, the pachislot 10 is provided with a central panel 15. The central panel 15 is provided with a see-through window 16 through which the drum unit 13 disposed inside the pachislot 10 can be seen through.

  The drum unit 13 includes a left reel 13L, a middle reel 13C, and a right reel 13R as rotating bodies. The reels 13L, 13C, 13R constituting the drum unit 13 are arranged side by side. When the pachislot 10 is viewed from the front, the left reel 13L is on the leftmost side, and the middle reel is on the right side of the left reel 13L. A right reel 13R is arranged to the right of 13C and the middle reel 13C.

  Symbols are arranged on each reel 13L, 13C, 13R. Twenty-one symbols are arranged on the left reel 13L. Also, 21 symbols are arranged on the middle reel 13C and the right reel 13R, as with the left reel 13L. In addition, the arrangement | positioning of the symbol in each reel 13L, 13C, 13R differs.

  Each reel 13L, 13C, 13R is configured to rotate and stop in the vertical direction independently by a stepping motor provided corresponding to each reel. Then, as the reels 13L, 13C, and 13R rotate, various symbols are displayed (varied) in the see-through window 16 while continuously changing.

  When the rotation of the reels 13L, 13C, and 13R is stopped, the three consecutive symbols in the reels 13L, 13C, and 13R are stopped and displayed at the upper, middle, and lower positions in the see-through window 16. The left reel 13L is provided with a reel sensor SE1 (shown in FIG. 2) for detecting the rotational position of the left reel 13L. The middle reel 13C is provided with a reel sensor SE2 (shown in FIG. 2) for detecting the rotational position of the middle reel 13C. Similarly, the right reel 13R is provided with a reel sensor SE3 (shown in FIG. 2) for detecting the rotational position of the right reel 13R.

  As shown in FIG. 1, a winning line NL (indicated by a two-dot chain line in FIG. 1) is formed in the symbol display area that can be seen through the see-through window 16. Yes. When the symbol combination stopped and displayed on the symbol stop line is a symbol combination (display result) for which a prize is determined, the winning line NL is an effective line to which a prize determined for the symbol combination is given.

  The see-through window 16 has nine symbol stop positions arranged in three rows and three columns so as to correspond to the upper, middle and lower stages in the vertical direction and to correspond to the left reel 13L, the middle reel 13C and the right reel 13R in the horizontal direction. The symbol is stopped and displayed. The winning line NL is formed by connecting a symbol stop position located in the middle stage of each row.

  In addition, the pachislot 10 is provided with various information display units 17 for informing information related to the variable game. The various information display unit 17 is configured by a throwable display lamp, a replay display lamp, a weight display lamp, a status lamp, a bet number display unit, a stored number display unit, and a prize number display unit.

  The insertable display lamp is turned on when the bet number of the variable game can be set or when a medal as a game medium can be inserted into the pachi-slot 10. The insertable display lamp is turned off when the variable game is started, or when the maximum bet number (MAXBET) is set and the stored data (credit) reaches the upper limit number of credits. The re-game display lamp is turned on when a re-game is given.

  The wait display lamp is turned on when a start operation is detected before the wait time elapses, and is turned off after the wait time elapses. The wait time is a period (time) that is set to restrict the floating game from progressing too quickly. When a start operation is detected during the wait time, each reel The rotation of 13L, 13C, 13R is set to start. In addition, after the wait time has elapsed, an enabling condition for validating the operation of the stop button for deriving the lottery result of the internal lottery is established.

  The status lamp is turned on and off as the changing game progresses. Further, the betting number display unit is composed of three lamps, and the lamps are turned on according to the betting number (the betting number) of the variable game. One lamp is lit for 1 bet (1 BET), 2 lamps are lit for 2 bets (2 BET), and all lamps are lit for 3 bets (3 BET). The stored number display section displays the number of credits stored and stored inside the machine. The award number display unit displays the number of award medals associated with the symbol combination when a symbol combination for which a medal payout is determined as a prize is stopped on the winning line NL.

  A medal slot 18 is disposed at a lower right position of the center panel 15. The medal inserted from the medal slot 18 passes through a medal selector 19 provided inside. The medal selector 19 is formed so as to branch into a storage passage 19a and a discharge passage 19b. Further, at the branch point of the storage passage 19a and the discharge passage 19b in the medal selector 19, a medal inserted from the medal insertion port 18 and passing through the medal selector 19 is guided to either the storage passage 19a or the discharge passage 19b. A medal blocker MB is provided as a guidance device operable to perform (sort).

  The medal blocker MB is configured to be operable by a blocker solenoid BS (shown in FIG. 2). The medal blocker MB operates (displaces) so as to guide the inserted medal to the storage passage 19a when a medal blocker operation signal (control signal) is output to the blocker solenoid BS. On the other hand, the medal blocker MB operates to guide the inserted medal to the discharge passage 19b when no medal blocker operation signal is output to the blocker solenoid BS.

  In addition, a medal sensor SE4 that detects inserted medals is disposed in the storage passage 19a. The medal sensor SE4 is disposed downstream of the medal blocker MB in the storage passage 19a. And the medal which passed the storage channel | path 19a is stored in the hopper 26 for storing the inserted medal. Therefore, when the medal blocker MB is operated so as to guide the inserted medal to the storage passage 19a, the medal inserted from the medal insertion port 18 passes through the storage passage 19a of the medal selector 19 and passes through the hopper 26. Stored.

  On the other hand, no medal sensor for detecting inserted medals is disposed in the discharge passage 19b. And the medal which passed the discharge channel | path 19b is discharged | emitted by the medal discharge port 24 for discharging | emitting a medal to the exterior of the pachislot 10. Therefore, when the medal blocker MB operates so as to guide the inserted medal to the discharge passage 19b, the medal inserted from the medal insertion port 18 passes through the discharge passage 19b of the medal selector 19, and the center of the pachislot 10 It is discharged from a medal discharge port 24 formed below. That is, medals are returned without being stored inside the pachi-slot 10.

  As described above, the medal sensor SE4 is disposed in the storage passage 19a, while the medal sensor is not disposed in the discharge passage 19b. Therefore, guiding the inserted medal to the storage passage 19a corresponds to guiding the inserted medal to be detected by the medal sensor SE4. On the other hand, guiding the inserted medal to the discharge passage 19b corresponds to guiding the inserted medal to be returned without being detected by the medal sensor SE4. In the present embodiment, the state where the medal blocker MB is operated so as to guide the inserted medal to the storage passage 19a corresponds to the guiding device being in the first state. On the other hand, the state in which the medal blocker MB is operated so as to guide the inserted medal to the discharge passage 19b corresponds to the guiding device being in the second state. In the present embodiment, the medal sensor SE4 functions as insertion detection means.

  The hopper 26 has a function of storing medals and a function of paying out medals. When a payout device operation signal is output to the hopper 26, the hopper 26 is operated and the stored medals are paid out. In the present embodiment, the hopper 26 that pays out medals as game media functions as a payout device. In the present embodiment, the state in which the hopper 26 operates to pay out medals as game media corresponds to the first state of the payout device. On the other hand, the state where the hopper 26 does not operate corresponds to the second state of the dispensing device.

  The medals paid out from the hopper 26 pass through the discharge passage 19b and are discharged from the medal discharge port 24. Thereby, a medal is awarded to the player. Incidentally, the fact that a medal inserted from the medal insertion slot 18 passes through the discharge passage 19b as it is and is discharged from the medal discharge opening 24 corresponds to the return of the medal to the player. On the other hand, a medal stored in the hopper 26 passing through the discharge passage 19b and being discharged from the medal discharge port 24 is equivalent to giving a medal to the player.

  A MAXBET button 20 is provided at the lower left position of the center panel 15. The MAXBET button 20 is a button that is operated when a bet is set as the maximum bet number of bets allowed in a single variable game.

  A settlement switch 21 is provided at the lower left position of the MAXBET button 20. The settlement switch 21 is a switch operated when paying back a medal betted or a stored and stored credit at the start of a variable game.

  Also, a start lever 22 is provided at the right position of the checkout switch 21 as a start operation means that is operated when starting the variable game. In this embodiment, the reels 13L, 13C, and 13R are started to rotate by operating the start lever 22 after the setting of the bet number is completed.

  At the right position of the start lever 22, stop buttons 23L, 23C, and 23R as stop operation means are provided. The stop button 23L is a button for stopping the rotating left reel 13L. The stop button 23C is a button for stopping the rotating middle reel 13C. The stop button 23R is a button for stopping the rotating right reel 13R. Thus, the stop button 23L corresponds to the left reel 13L, the stop button 23C corresponds to the middle reel 13C, and the stop button 23R corresponds to the right reel 13R. In addition, a tray 25 for receiving medals discharged from the medal outlet 24 is provided below the medal outlet 24.

Next, an operation for a player to play a variable game and operation modes of various devices associated with the operation will be described.
In a state where medals can be inserted into the floating game or the MAXBET button 20 can be operated, the bet number can be set by operating the MAXBET button 20. Depending on the operation of the MAXBET button 20, a credit corresponding to the maximum bet number that can be set in the target variable game is set as the bet number from the stored credits.

  Further, in the pachislot machine 10, when the medal blocker MB is operated to guide the medal inserted from the medal insertion slot 18 to the storage passage 19 a, the medal corresponding to the number of bets is inserted from the medal insertion slot 18. It is also possible to set the number of bets. At this time, the number of bets for one bet is set by inserting one medal, and the number of bets for three bets is set by inserting three medals. When medals exceeding the maximum number of bets that can be set in the target variable game are inserted from the medal insertion slot 18, they are stored as credits. On the other hand, as described above, when the medal blocker MB is operating in a state where the medal blocker MB guides the medal inserted from the medal insertion slot 18 to the discharge passage 19b, the number of bets cannot be set. Returned.

  When the MAXBET button 20 is operated, the maximum bet number is set and the winning line NL is set to be valid. The winning line NL becomes effective when the combination of symbols stopped and displayed on the winning line NL becomes effective, and the control according to the combination of symbols stopped and displayed on the winning line NL (award medal grant etc.) Is done.

  When the number of bets is set as described above and the operation of the start lever 22 can be accepted, that is, when the start lever 22 is operated in a state where the game can be started, the reels 13L, 13C, and 13R are rotated and seen through. In the window 16, a plurality of kinds of symbols are displayed so as to fluctuate. Thereafter, when the enabling condition is satisfied after the reels 13L, 13C, and 13R start to rotate, the operation of the stop buttons 23L, 23C, and 23R is accepted. Subsequently, when the stop buttons 23L, 23C, and 23R are operated, the rotation of the reels corresponding to the operated stop buttons is stopped, and the symbols are stopped and displayed on the upper, middle, and lower rows of the corresponding row in the fluoroscopic window 16. Is done.

  When the symbol combination stopped and displayed on the winning line NL when the rotation of all the reels 13L, 13C, and 13R is stopped is a symbol combination for which a prize is determined, the symbol combination is determined. Awards are awarded. In the present embodiment, when the symbol combination is stopped and displayed on the winning line NL, the symbols displayed at the other symbol display positions are naturally determined. For this reason, in any case where nine symbols visible from the fluoroscopic window 16 are collectively defined as a display result and when a symbol combination stopped on the winning line NL is defined as a display result, the fluoroscopic window 16 Corresponds to the result display section.

  A one-time variable game is triggered by the start operation by setting the number of bets and the operation of the start lever 22, and by the stop operation including the operation of the stop buttons 23L, 23C, 23R, all the reels 13L, 13C, 13R are started. The process ends when the rotation stops and the symbol combination (display result) is displayed. By the way, if the symbol combination displayed with all the reels stopped rotating is a symbol combination for which a prize such as a medal payout or replay is determined, the rotation of all the reels stops and the symbol combination becomes After being displayed, the awarding of medals determined for the symbol combination and the awarding of replays are completed, and one variation game is completed.

  An operable setting device 28 is provided on the back surface of the front door 12. The setting device 28 provided on the back surface of the front door 12 is accommodated inside the main body 11 when the front door 12 is closed.

  The setting device 28 is configured to be operable by using a predetermined key. In the following description, the operation of the setting device 28 means that the setting device 28 is operated using a predetermined key. In the pachi-slot 10 of the present embodiment, it is allowed to change the setting of the pachi-slot 10 by operating the setting device 28.

  The pachi-slot 10 is a multi-stage (a total of six stages from “1” to “6”) associated with different payout rates (a plurality of probabilities of giving profits to the player). A game is played under these settings. The payout rate may vary depending on, for example, the probability that at least a part of the symbol combinations for which a prize is determined is allowed to be displayed, or the probability of transition to an advantageous gaming state advantageous to the player. it can. In the pachi-slot 10 of the present embodiment, the degree of advantage varies depending on the setting of the pachi-slot 10.

  An operable switch 29 is provided on the back surface of the front door 12. The operation switch 29 provided on the back surface of the front door 12 is accommodated inside the main body 11 when the front door 12 is closed.

Next, in the pachi-slot 10 of this embodiment, the symbol combination that is stopped and displayed on the winning line NL will be described.
In the pachi-slot 10 of the present embodiment, the symbol combinations for which a prize is determined include a cherry stop eye, a watermelon stop eye, a bell stop eye, a single piece stop eye, a replay stop eye, and a bonus stop eye. Incidentally, in the pachi-slot 10 of the present embodiment, the symbol combinations for which no prize is determined have a discontinuity from the bell spilled eyes. In the following description, the bell spilled eyes and the discontinuous eyes are collectively referred to as “disengagement stop eyes”.

  When the symbol combination classified as the cherry stop eye is stopped and displayed on the winning line NL, four medals are awarded as prize medals. When a symbol combination classified as a watermelon stop eye is stopped and displayed on the winning line NL, six medals are awarded as award medals.

  When the symbol combination classified as the bell stop eye is stopped and displayed on the winning line NL, eight medals are awarded as award medals. Further, when the symbol combination classified as the one-piece winning stop is stopped and displayed on the winning line NL, one medal is awarded as a prize medal.

  When the symbol combination classified as the replay stop eye is stopped and displayed on the winning line NL, the replay is given. When a re-game is awarded, the player can play the next variable game by automatically setting the maximum bet number inside the pachislot machine 10 without betting the bet number. When a replay is awarded, it guarantees a certain profit that the next variable game can be played without consuming medals, and no prize medal is awarded.

  When a symbol combination classified as a bonus stop eye is stopped and displayed on the winning line NL, a bonus game is generated (given). The bonus game ends with the end of the variable game in which the number of paid-out medals exceeds the predetermined maximum number of payouts (“2” in the present embodiment).

  Next, winning information (so-called condition device combination) in the pachi-slot 10 of the present embodiment will be described. The winning information in the pachislot 10 of the present embodiment includes eleventh winning information, twenty-first winning information, thirty-first winning information to thirty-fifth winning information, forty-first winning information and 51st winning information.

  When the eleventh winning information is won, regardless of the stop button operated first among the three stop buttons, the cherry stop eye is stopped and displayed on the winning line NL, and four medals are awarded as prize medals. Is done. This is equivalent to allowing the display of the cherry stop eye by winning the eleventh winning information.

  When winning the 21st winning information, regardless of which stop button is operated first among the three stop buttons, the watermelon stop eye is stopped and displayed on the winning line NL and 6 medals are awarded as prize medals. Is done. This corresponds to allowing the display of the watermelon stop eye to be permitted by winning the 21st winning information.

  When winning the 31st winning information, the bell stop eye is stopped on the winning line NL regardless of the stop button operated first among the three stop buttons, and eight medals are given as prize medals. Is done. This corresponds to allowing the bell stop eye to be displayed by winning the 31st winning information.

  When winning the 32nd winning information to the 35th winning information, the combination of symbols that are stopped and displayed on the winning line NL differs depending on the stop button that is operated first. For example, when winning the 32nd winning information, if the stop button 23L is operated first among the three stop buttons, the bell spilled eyes are stopped on the winning line NL and no prize is awarded. Also, when winning the 32nd winning information, if the stop button 23C among the three stop buttons is operated first, the bell stop eye is stopped on the winning line NL, and eight medals are displayed. Awarded as a medal. In addition, when winning the 32nd winning information, if the stop button 23R is operated first among the three stop buttons, the first combination stoppage is stopped and displayed on the pay line NL. Medals are awarded as prize medals. This corresponds to that the display of the bell stop eye and the one-piece combination stop is permitted by winning of the winning information of any of the 32nd winning information to the 35th winning information.

  When the forty-first winning information is won, the replay stop eye is stopped on the winning line NL regardless of the stop button operated first among the three stop buttons, and the replay is given. This corresponds to allowing the display of the replay stop eye to be permitted by winning the forty-first winning information.

  When winning the 51st winning information, only when each stop button is operated at a predetermined timing, the bonus stop eye is stopped on the winning line NL and a bonus game is awarded. This is equivalent to allowing the bonus stop eye to be displayed by winning the 51st winning information.

  When the bonus stop eye is allowed to be stopped and displayed, the bonus winning information indicating that the bonus stop eye is allowed to be stopped and displayed as a display result is carried over until the bonus stop eye is stopped and displayed. The bonus winning information corresponds to control information indicating that a bonus game is determined to be given.

  Incidentally, in the pachislot 10 of the present embodiment, in a situation where bonus winning information is carried over, it is possible to stop and display a bonus stop eye when any winning information is not won. However, in the pachislot machine 10 of the present embodiment, the probability that the winning information will not be won is extremely low, and in principle, the game is played in a situation where bonus winning information is carried over.

  Thus, in the pachislot 10 of this embodiment, by winning the winning information, one of the cherry stop eyes, the watermelon stop eyes, the bell stop eyes, the one-piece combination stop eyes, the replay stop eyes, and the bonus stop eyes is selected. It is allowed to be displayed.

Next, as shown in FIG. 2, the electrical configuration of the pachislot 10 will be described.
The pachislot 10 is equipped with a power supply board 30 that converts the power supply voltage of the game arcade to a predetermined supply voltage and supplies it to various components constituting the pachislot 10. Further, the pachislot 10 is equipped with a main control board 40 as a main control unit. Further, the main control board 40 executes various processes, calculates various control signals (control commands) according to the processing results, and outputs the control signals. In addition, the pachislot 10 is equipped with a sub control board 41 as a sub control unit that executes production control according to the gaming state. The sub control board 41 receives various control signals output from the main control board 40 and executes predetermined control based on the control signals.

Hereinafter, the power supply substrate 30 will be described.
The power supply board 30 is provided with a power supply circuit 30 a that converts the power supply voltage of the game arcade to the supply voltage to the pachislot 10. The power supply circuit 30 a is connected to the main control board 40 and the sub control board 41.

  Further, the power supply substrate 30 is provided with a power-off monitoring circuit 30b. The power-off monitoring circuit 30b is connected to the power circuit 30a. The power-off monitoring circuit 30b monitors the voltage value of the supply voltage from the power circuit 30a. Specifically, the power-off monitoring circuit 30b monitors whether the supply voltage has decreased (decreased) to a predetermined value. The power-off monitoring circuit 30b outputs a power-off signal when the supply voltage is equal to or lower than a predetermined value. The power-off signal output from the power-off monitoring circuit 30b is output to the signal circuit LE disposed on the main control board 40 and the sub-control board 41. When the supply voltage drops below a predetermined value by the power-off monitoring circuit 30b, “1” is set in a predetermined area of the input port provided on the main control board 40, so that a power-off signal is sent to the signal circuit LE. When it is input and “0” is set in the predetermined area, no power-off signal is input to the signal circuit LE. After the power-off signal is input, “0” is set in a predetermined area of the input port. Incidentally, the situation where the supply voltage decreases to a predetermined value is, for example, a situation where the power is turned off or a power failure occurs.

  Further, the power supply board 30 includes a backup power supply 30c made of, for example, an electric double layer capacitor. The backup power supply 30c is connected to the power supply circuit 30a. The supply voltage from the power supply circuit 30a is supplied to the backup power supply 30c. The main control RAM 40c of the main control board 40 and the sub control RAM 41c of the sub control board 41 store the stored contents (by the power supplied from the backup power supply 30c when the supply voltage decreases or when there is no supply voltage ( Control information).

Next, the main control board 40 will be described.
As shown in FIG. 2, on the main control board 40, a main control CPU 40a for executing control operations in a predetermined order, a main control ROM 40b for storing a control program for the main control CPU 40a, and writing of necessary data In addition, a main control RAM 40c capable of reading is provided.

  The main control board 40 is provided with an input port. When “1” is set in the input port area, a control signal corresponding to the area is input to the main control CPU 40a. Further, when a control signal corresponding to an area where “1” is set is input to the main control CPU 40a at the input port, “0” is set in the area where “1” is set.

  The main control board 40 is provided with an output port. The main control board 40 of the present embodiment is provided with output ports from a first output port to a twelfth output port. Each output port is composed of a total of 8 bits from the 0th bit to the 7th bit. When “1” is set in the output port area, the control signal corresponding to the area is output from the main control CPU 40a. Further, when a control signal corresponding to an area where “1” is set is output from the main control CPU 40a at the output port, “0” is set in the area where “1” is set.

  The main control board 40 is provided with a signal circuit LE. For example, an integrated circuit is used as the signal circuit LE. The signal circuit LE is connected to the main control CPU 40a so as to be able to output control signals in both directions. That is, the signal circuit LE is connected to the main control CPU 40a so as to transmit information using the control signal. In other words, the signal circuit LE and the main control CPU 40a are connected so that mutual control signals can be input and output.

  Further, the signal circuit LE is connected so that at least a control signal can be output from the power-off monitoring circuit 30b of the power supply substrate 30 to the signal circuit LE. That is, the signal circuit LE is connected so that information can be transmitted using at least a control signal from the power-off monitoring circuit 30b of the power supply substrate 30.

  Specifically, the signal circuit LE can receive an NMI enable signal output from the main control CPU 40a and a power-off signal output from the power-off monitoring circuit 30b, and can output an NMI signal to the main control CPU 40a. The main control CPU 40a and the power-off monitoring circuit 30b are connected so that output is possible. Incidentally, the NMI permission signal can take a state where it is output and a state where it is not output. Similarly, the power-off signal can be output or not output. Further, the NMI signal can take a state where it is output and a state where it is not output.

  The signal circuit LE outputs the NMI signal to the main control CPU 40a only when the power-off signal is input when the NMI permission signal is input. In other words, the signal circuit LE outputs the NMI signal to the main control CPU 40a only when the NMI permission signal is input when the power-off signal is input. That is, the signal circuit LE outputs the NMI signal to the main control CPU 40a when the NMI permission signal and the power-off signal are input at the same time.

  The main control CPU 40a is connected to reels 13L, 13C, and 13R constituting the drum unit 13, reel sensors SE1 to SE3, medal sensor SE4, and hopper 26. Various information display units 17 are connected to the main control board 40. Further, a MAXBET button 20, a settlement switch 21, a start lever 22, and stop buttons 23L, 23C, and 23R are connected to the main control board 40. Further, the setting device 28, the operation switch 29, and the front door opening sensor KS are connected to the main control CPU 40a.

  A first position signal is input from the reel sensor SE1 to the main control CPU 40a according to the rotation position of the rotating left reel 13L. A second position signal is input from the reel sensor SE2 to the main control CPU 40a in accordance with the rotation position of the middle reel 13C that is rotating. Similarly, a third position signal is input to the main control CPU 40a from the reel sensor SE3 according to the rotation position of the rotating right reel 13R. Then, the main control CPU 40a controls the rotation and stop of the reels 13L, 13C, 13R based on the first to third position signals.

  Each time the medal sensor SE4 detects a medal, a medal detection signal indicating that a medal has been detected is input to the main control CPU 40a. Further, when the MAXBET button 20 is operated, a control signal indicating that the MAXBET button 20 has been operated is input to the main control CPU 40a. Further, when the settlement switch 21 is operated, a control signal indicating that the settlement switch 21 has been operated is input to the main control CPU 40a.

  When the medal sensor SE4 detects a medal, a medal detection signal is input to the main control CPU 40a by setting “1” in a predetermined area of the input port of the main control board 40. Similarly, when the MAXBET button 20 is operated, “1” is set in a predetermined area of the input port of the main control board 40, so that a control signal indicating that the MAXBET button 20 has been operated to the main control CPU 40 a. Is entered. When the settlement switch 21 is operated, “1” is set in a predetermined area of the input port of the main control board 40, so that a control signal indicating that the settlement switch 21 is operated is sent to the main control CPU 40a. Entered.

  When the start lever 22 is operated, a control signal indicating that the start lever 22 has been operated is input to the main control CPU 40a. Further, when any one of the stop buttons 23L, 23C, 23R is operated, a control signal indicating that the operation has been performed is input to the main control CPU 40a.

  When the start lever 22 is operated, “1” is set in a predetermined area of the input port of the main control board 40, so that a control signal indicating that the start lever 22 is operated is input to the main control CPU 40a. The When the stop button 23L is operated, “1” is set in a predetermined area of the input port of the main control board 40, so that a control signal indicating that the stop button 23L is operated is sent to the main control CPU 40a. Entered. Similarly, when the stop button 23C is operated, “1” is set in a predetermined area of the input port of the main control board 40, thereby indicating that the main control CPU 40a has operated the stop button 23C. Is entered. When the stop button 23R is operated, “1” is set in a predetermined area of the input port of the main control board 40, so that a control signal indicating that the stop button 23R is operated is sent to the main control CPU 40a. Entered.

  Further, when the setting device 28 is operated, a control signal indicating that the setting device 28 has been operated is input to the main control CPU 40a. When the setting device 28 is operated, a control signal indicating that the setting device 28 has been operated is input to the main control CPU 40 a by setting “1” in a predetermined area of the input port of the main control board 40. The

  Further, when the operation switch 29 is operated, a control signal indicating that the operation switch 29 has been operated is input to the main control CPU 40a. When the operation switch 29 is operated, “1” is set in a predetermined area of the input port of the main control board 40, so that a control signal indicating that the operation switch 29 is operated is input to the main control CPU 40a. The

  A main control program is stored in the main control ROM 40b. In addition, the main control ROM 40b stores a winning information table in which the winning probability for each winning information is determined as an allocation range of winning information determination random numbers. In the pachi-slot 10 of the present embodiment, a winning information determination table that is referred to for each setting of the pachi-slot 10 is stored in the main control ROM 40b. Further, in the pachi-slot 10, the winning information table referred to for each setting of the pachi-slot 10 is further stored in the main control ROM 40b for each internal control state. The winning information determination table is used in winning information lottery (so-called role lottery). The winning information determination random number is generated in the main control board 40. The random number used as the winning information determination random number may be a hardware random number or a software random number.

  In the winning information lottery, the type of winning or winning information is determined. That is, since the type of the winning information is determined by the winning information lottery, it is equivalent to determining whether or not the winning information lottery allows the display of the symbol combination (predetermined display result) in which the prize is determined. To do. Furthermore, in the winning information lottery, this corresponds to determining the type of display result that is allowed to be displayed. The main control CPU 40a controls the internal control state. Depending on the type of internal control state, the main control CPU 40a performs various processes (for example, winning information lottery).

  As shown in FIG. 3, the storage area of the main control RAM 40c in this embodiment is divided into a work area, an unused area, and a stack area. The storage area of the main control RAM 40c of the present embodiment is a storage area corresponding to addresses “7E00H to 7FFFH”. In this embodiment, the storage area corresponding to the address “7E00H to 7EDFH” is the work area, the storage area corresponding to the address “7EE0H to 7FB7H” is the unused area, and the storage area corresponding to the address “7FB8H to 7FFFH” is It is a stack area.

Next, the sub control board 41 will be described.
As shown in FIG. 2, the sub-control board 41 includes a sub-control CPU 41a that executes control operations in a predetermined procedure, a sub-control ROM 41b that stores a control program for the sub-control CPU 41a, and writing of necessary data. A sub-control RAM 41c capable of reading is provided. The effect display device 14 is connected to the sub control CPU 41a. In addition, a decoration lamp La is connected to the sub control CPU 41a. Further, a speaker Sp is connected to the sub control CPU 41a.

  A sub control program is stored in the sub control ROM 41b. The sub-control ROM 41b also has a display effect pattern showing the display effect mode of the effect display device 14, a sound effect pattern showing the sound output mode of the speaker Sp, and a light emission effect pattern showing the light emission mode of the decoration lamp La. Is remembered.

  The sub-control RAM 41c stores (sets) various information that is appropriately rewritten during the operation of the pachi-slot 10. Specifically, the secondary control RAM 41c stores secondary status information (such as a flag) relating to the internal control status by the secondary control CPU 41a.

Hereinafter, the process (game progress main process) related to the variable game executed by the main control CPU 40a based on the main control program will be described.
As shown in FIG. 4, in the game progress main process, the main control CPU 40a prohibits the INT interrupt process (step S11). The INT interrupt process is a process that is performed every predetermined cycle if the INT interrupt process is permitted. The INT interrupt process will be described in detail later.

  Subsequently, the main control CPU 40a initializes a storage area other than the work area in the storage area of the main control RAM 40c (step S12). In step S12, the main control CPU 40a sets “0 (zero)” in the storage area corresponding to the addresses “7EE0H to 7FFFH” in the storage area of the main control RAM 40c. Thereafter, the main control CPU 40a permits the INT interrupt process (step S13).

  Further, the main control CPU 40a starts receiving medals bet (step S14). Next, the main control CPU 40a checks the internal control state (step S15). Thereafter, the main control CPU 40a determines whether or not it is a re-game operation (step S16). The determination process in step S16 corresponds to a determination process as to whether or not a symbol combination for which re-playing has been determined as a prize has been won (stopped display on the winning line NL) in the immediately preceding symbol variation game. If the determination result of step S16 is affirmative, the main control CPU 40a sets the maximum bet number to the bet number stored in the main control RAM 40c, and then proceeds to the process of step S18.

  If the determination result in step S16 is negative, medal management is performed (step S17). In step S17, the main control CPU 40a outputs a medal blocker operation signal, and operates the medal blocker MB so as to guide the inserted medal to the storage passage 19a.

  As shown in FIG. 5, a medal blocker operation signal corresponding to a control signal for operating the medal blocker MB is associated with the fourth bit area of the tenth output port. By setting “1” in the fourth bit area of the tenth output port, a medal blocker operation signal is output to the blocker solenoid BS of the medal blocker MB. On the other hand, by setting “0” instead of “1” in the fourth bit area of the tenth output port, the output of the medal blocker operation signal to the blocker solenoid BS of the medal blocker MB is stopped. In the present embodiment, the fourth bit area of the tenth output port corresponds to an output area for outputting a control signal for controlling the guidance device to the first state.

  Incidentally, an area corresponding to the fifth bit of the tenth output port is associated with a dispenser operation signal corresponding to a control signal for operating the hopper 26. By setting “1” in the fifth bit area of the tenth output port, the dispenser operation signal is output to the hopper 26. On the other hand, when “0” is set in place of “1” in the fifth bit area of the tenth output port, the output of the dispensing device operation signal to the hopper 26 is stopped. In the present embodiment, the fifth bit area of the tenth output port corresponds to an output area for outputting a control signal for controlling the dispensing device to the first state.

  An NMI permission signal is associated with the third bit area of the first output port. By setting “1” in the third bit area of the first output port, the NMI permission signal is output to the signal circuit LE. On the other hand, by setting “0” instead of “1” in the third bit area of the first output port, the output of the NMI permission signal to the signal circuit LE is stopped.

  Further, as shown in FIG. 4, in step S17, the main control CPU 40a is stored in the main control RAM 40c based on the input of the medal detection signal from the medal sensor SE4 and the input of the control signal from the MAXBET button 20. Set the number of bets. Therefore, when the medal detection signal from the medal sensor SE4 is input in step S17, the main control CPU 40a adds 1 to the bet number stored in the main control RAM 40c. In step S17, when the control signal from the MAXBET button 20 is input, the main control CPU 40a adds a value to the bet number so that the bet number stored in the main control RAM 40c becomes the maximum bet number. The credit is subtracted by the added amount.

  Further, when the determination result of step S16 is affirmative and when the process of step S17 is terminated, the main control CPU 40a determines whether or not the bet number matches the maximum bet number (step S18). In step S18, the main control CPU 40a determines whether or not the variable game can be started. As described above, in the pachislot machine 10 of the present embodiment, the variable game start enabling condition for enabling the start of the variable game is established by placing the maximum bet number. If the determination result of step S18 is negative, the main control CPU 40a proceeds to the process of step S15.

  If the determination result in step S18 is affirmative, the main control CPU 40a determines whether or not a start operation has been accepted (step S19). In step S19, the main control CPU 40a determines whether or not a control signal from the start lever 22 has been input. If the determination result of step S19 is negative, the main control CPU 40a proceeds to the process of step S15. Thus, in this embodiment, the main control CPU 40a that accepts the start operation functions as a start operation accepting unit.

  On the other hand, if the determination result of step S19 is affirmative, the main control CPU 40a performs an internal lottery process (step S20). In the pachi-slot 10 of the present embodiment, a winning information lottery is performed in the internal lottery process. Specifically, in the internal lottery process, the main control CPU 40a acquires the value of the winning information determination random number. Thereafter, the main control CPU 40a refers to the winning information table corresponding to the setting of the pachislot 10 and corresponds to the current internal control state, and performs the winning information lottery using the acquired winning information determination random number value. . When any winning information is won in the winning information lottery of step S20, the main control CPU 40a uses control information related to winning information capable of specifying at least one of the winning winning information and an allowed symbol combination for main control. The data is stored in a storage area corresponding to a predetermined address in the RAM 40c. Further, when the 51st winning information is won, the main control CPU 40a stores bonus winning information in a storage area corresponding to a predetermined address of the main control RAM 40c.

  If the determination result in step S19 is affirmative, the main control CPU 40a displaces the medal blocker MB to a state in which the inserted medal is guided to the discharge passage 19b without outputting a control signal to the blocker solenoid BS. Let

  Thereafter, the main control CPU 40a determines whether or not the wait time has elapsed (step S21). When the determination result of step S21 is negative, the main control CPU 40a waits until the wait time elapses, that is, until the determination result of step S21 becomes affirmative. If the determination result of step S21 is affirmative, the main control CPU 40a proceeds to the process of step S22.

  In step S22, the main control CPU 40a sets a wait time. In step S22, the main control CPU 40a sets the wait time to be determined in step S21 when the next variable game is performed.

  After setting the wait time, the main control CPU 40a outputs a control signal to each stepping motor to start rotation (rotation) of each reel 13L, 13C, 13R (step S23). The main control CPU 40 a controls the rotation of the stepping motor by setting “1” or “0” in a predetermined area of the output port of the main control board 40.

  Thereafter, the main control CPU 40a determines whether or not the rotation speeds of all the reels have reached a constant speed (step S24). If the determination result in step S24 is negative, the main control CPU 40a waits until all reels rotate at a constant speed, that is, until the determination result in step S24 becomes affirmative.

  If the determination result in step S24 is affirmative, the main control CPU 40a determines whether or not a stop operation has been accepted (step S25). In step S25, the main control CPU 40a determines whether or not an operation signal is input from the stop button corresponding to the rotating reel. If the determination result of step S25 is negative, the main control CPU 40a proceeds to the process of step S27. Thus, in the present embodiment, the main control CPU 40a capable of accepting a stop operation functions as a stop operation accepting unit.

  On the other hand, if the determination result in step S25 is affirmative, the main control CPU 40a performs rotation stop processing and selects control data for stop control for stopping the rotation of the reel corresponding to the operated stop button. (Step S26). If the determination result in step S25 is affirmative, the main control CPU 40a outputs a control signal corresponding to the operated stop button to the sub control CPU 41a, indicating that the stop button has been operated, and which stop button The sub-control CPU 41a is made aware of whether or not an operation has been performed.

  In step S26, the main control CPU 40a performs stop control for stopping the rotation of the reel corresponding to the operated stop button within a predetermined range (maximum of 4 symbols) from the timing when the stop button is operated. Select the control data. In step S26, the main control CPU 40a receives the stop control control data stored in the main control ROM 40b according to the lottery result of the winning information lottery, the stop button operation order, the stop button operation timing, and the like. select. As described above, when the determination result in step S24 is affirmative, the operation of the stop button for deriving the lottery result of the winning information lottery becomes valid, and the validation condition is satisfied. In the present embodiment, the main control CPU 40a that stops the reel rotation and stops and displays the symbol combination corresponding to the lottery result of the winning information lottery functions as a stop control unit.

  When the determination result of step S25 is negative and when the process of step S26 is terminated, the main control CPU 40a determines whether or not all the reels are stopped (step S27). When the determination result of step S27 is negative, the main control CPU 40a proceeds to the process of step S25.

  On the other hand, if the determination result of step S27 is affirmative, the main control CPU 40a performs display result determination (step S28). In step S28, the main control CPU 40a determines whether or not the symbol combination that is stopped and displayed on the winning line NL is a symbol combination for which a prize is determined, and if it is a symbol combination for which a prize is determined. Judge the winning symbol combination. Specifically, the main control CPU 40a determines whether or not the symbol combination corresponding to the lottery result of the winning information lottery in the internal lottery process is actually stopped and displayed on the winning line NL. The type of the symbol combination is determined. In step S28, if the symbol combination for which replay is determined is stopped and displayed on the winning line NL, the main control CPU 40a activates replay.

  In the following description, determining that the symbol combination for which a prize is determined on the winning line NL is stopped and displayed is referred to as “determining the winning of the symbol combination for which a prize is determined”. Further, in the following description, the fact that the symbol combination for which a prize is determined is displayed on the winning line NL is referred to as “the symbol combination for which a prize is determined wins”.

  Subsequent to step S28, the main control CPU 40a determines whether or not to pay out medals (step S29). In step S29, the main control CPU 40a determines whether or not a symbol combination for which a medal payout has been determined as a prize has been won. If the determination result of step S29 is negative, the main control CPU 40a proceeds to the process of step S31.

  On the other hand, if the determination result in step S29 is affirmative, the main control CPU 40a pays out the number of medals determined for the winning symbol combination (step S30). In step S30, the main control CPU 40a adds the number of medals to be paid out to the credit. Incidentally, when the credit upper limit number is exceeded when added to the credit, the main control CPU 40a outputs a control signal to the hopper 26 in order to drive the hopper 26 so as to pay out medals corresponding to the credit upper limit number. To do.

  When the determination result of step S29 is negative and when the process of step S30 is terminated, the main control CPU 40a ends the variable game (step S31). In step S31, the main control CPU 40a shifts the internal control state, or outputs a winning instruction command indicating that a symbol combination with a prize on the winning line NL is stopped and displayed to the sub-control CPU 41a. I do. Thereafter, the main control CPU 40a ends the game progress main process related to the execution of one variable game, and proceeds to the process of step S11 again.

Next, the INT interrupt process will be described.
As shown in FIG. 6, in the INT interrupt process, the main control CPU 40a prohibits the INT interrupt process (step S101). In step S101, the main control CPU 40a restricts the INT interrupt process from being performed again when the INT interrupt process is being performed.

  Thereafter, the main control CPU 40a saves the register in the main control board 40 (step S102). In step S102, the main control CPU 40a stores the stored contents of the register in the stack area of the main control RAM 40c.

  Subsequently, the main control CPU 40a performs timer measurement (step S103). In step S103, the main control CPU 40a performs timer measurement using the timer function. Thereafter, the main control CPU 40a outputs a control signal determined to be output to the sub control CPU 41a (step S104).

  When the process of step S104 is completed, the main control CPU 40a reads the input port and inputs control signals from various sensors and the like (step S105). Thereafter, the main control CPU 40a sets rotation control data for controlling the rotation speed of the reel in the output port (step S106). In step S106, the main control CPU 40a sets “1” or “0” in an area corresponding to each stepping motor of the output port, and accelerates, maintains, or decelerates the rotational speed of each reel 13L, 13C, 13R. Control. In step S106, when the control data for stop control is determined, the main control CPU 40a sets "1" or "0" in the area corresponding to each stepping motor of the output port based on the control data for stop control. To do.

  Thereafter, the main control CPU 40a outputs a control signal from the main control CPU 40a from the output port (via the output port) (step S107). Thereafter, the main control CPU 40a performs display control of various LEDs by controlling the display of the various information display units 17 (step S108).

  Subsequently, the main control CPU 40a restores the register (step S109). In step S109, the main control CPU 40a restores the stored contents of the register stored in the stack area of the main control RAM 40c in step S102 to the register. The main control CPU 40a permits the INT interrupt process (step S110), ends the INT interrupt process, and returns to the game progress main process.

  The main control CPU 40a controls the internal control state. In this embodiment, when the bonus stop eye is won, the main control CPU 40a shifts from an internal control state that is not a bonus game to an internal control state that is a bonus game. At this time, the main control CPU 40a erases the bonus winning information stored in the main control RAM 40c. Further, when the bonus game ends, the main control CPU 40a shifts from the internal control state that is a bonus game to the internal control state that is not a bonus game. Incidentally, in the pachislot machine 10 of the present embodiment, even if a bonus game is generated, there are few benefits for the player to acquire.

Next, a description will be given of processing related to a variable game executed by the sub control CPU 41a based on the sub control program.
When the sub-control CPU 41a inputs various commands such as a variable game start command and a winning instruction command, the display content of the effect display device 14 and the sound of the speaker Sp are executed so as to execute various effects based on the content instructed by the command. The output mode and the light emission mode of the decorative lamp La are controlled.

  When the sub-control CPU 41a does not input a winning instruction command, the sub-control CPU 41a grasps that a symbol combination for which no prize is determined is stopped and displayed on the winning line NL. Further, since the sub-control CPU 41a can grasp the stop status of each reel 13L, 13C, 13R, it is understood from the stop status that the symbol combination for which no prize is determined is stopped and displayed on the winning line NL. it can. The sub-control CPU 41a performs control for causing various effects each time a variable game start command is input.

  Further, the sub control CPU 41a may control an advantageous gaming state that is advantageous to the player. In the advantageous gaming state, the sub-control CPU 41a operates the stop button to stop and display the bell stop eye when the winning of any one of the 32nd winning information to the 35th winning information is instructed. The display content of the effect display device 14 is controlled so as to execute a navigation effect for navigating the order. This increases the probability that the bell stop eye is stopped and displayed on the winning line NL.

  In the pachi-slot 10 of the present embodiment, when the supply voltage becomes equal to or lower than a predetermined value, the power-off process is performed by the main control CPU 40a. In the power-off process, a backup process for storing and holding the storage contents of the main control RAM 40c corresponding to the information storage means and the registers is also performed. The main control CPU 40a performs a power-off process in response to the input of the NMI signal from the signal circuit LE.

Hereinafter, the power-off process will be described.
As shown in FIG. 7, in the power-off process, the main control CPU 40a saves the AF register (step S201). In step S201, the main control CPU 40a stores the storage contents of the AF register in the stack area of the main control RAM 40c.

  Subsequently, the main control CPU 40a turns off the first output port and the tenth output port (step S202). In step S202, the main control CPU 40a sets “0” in an area corresponding to each bit of the first output port, and restricts the output of the control signal from the first output port. This restricts the output of the NMI permission signal from the third bit area of the first output port. That is, the state transitions from a state where the NMI permission signal is output to a state where the NMI permission signal is not output.

  Further, in step S202, the main control CPU 40a sets “0” in the storage area corresponding to each bit of the tenth output port, and restricts the control signal from being output from the tenth output port. This restricts the medal blocker operation signal from being output from the fourth bit area of the tenth output port, and outputs the payout device operation signal from the fifth bit area of the tenth output port. To regulate.

  Subsequently, the main control CPU 40a stores the interrupt state when the power is turned off (step S203). In step S203, the main control CPU 40a stores, in the AF register, interrupt status information that can specify whether or not the INT interrupt processing is permitted when the NMI signal is input, and then stores the state of the AF register. The stored contents are stored in the stack area of the main control RAM 40c.

  Thereafter, the main control CPU 40a saves registers other than the AF register (step S204). Specifically, the main control CPU 40a stores the stored contents of registers other than the AF register in the stack area of the main control RAM 40c.

  Then, the main control CPU 40a stores a stack pointer capable of specifying the address of the stack area where the control information is stored next in the storage area of the predetermined address (7E69H) of the work area of the main control RAM 40c (step S205). .

  Thereafter, the main control CPU 40a sets a power-off process completion flag in the storage area of the predetermined address (7E1AH) in the work area of the main control RAM 40c (step S206). In step S206, the main control CPU 40a stores “FFH (regulation information)” when the processes of steps S201 to S205 are normally performed, and the processes of steps S201 to S205 are not normally performed. In this case, “information other than FFH” is stored.

  Then, the main control CPU 40a erases the checksum data stored in the storage area of the predetermined address (7E68H) in the work area of the main control RAM 40c (step S207). Thereafter, the main control CPU 40a calculates the checksum of the main control RAM 40c (step S208). In step S208, the main control CPU 40a calculates a checksum for all storage areas (7E00H to 7FFFH) of the main control RAM 40c.

  Subsequently, the main control CPU 40a multiplies the checksum calculated in step S208 by -1 (step S209). Thereafter, the main control CPU 40a stores the value (control information) after multiplication in step S209 in the storage area of the predetermined address (7E68H) of the work area of the main control RAM 40c as checksum data (step S210). ).

  After finishing the process of step S210, the main control CPU 40a turns off the output ports other than the first output port and the tenth output port (step S211). In step S211, the main control CPU 40a turns off the second output port to the ninth output port and the eleventh output port to the thirteenth output port. Subsequently, the main control CPU 40a prohibits access to the main control RAM 40c (step S212).

  Thereafter, the main control CPU 40a performs standby processing (step S213). In step S213, the main control CPU 40a performs arithmetic processing and waits for a predetermined period. Specifically, the main control CPU 40a performs an arithmetic process of subtracting one by one until the value stored in the A register becomes “0 (zero)”, and then stores a predetermined value in the C register. The calculation process of subtracting one by one until the value becomes “0 (zero)” is performed. By performing the calculation process in step S213, a predetermined period is reached. In the present embodiment, the A register and the C register correspond to a predetermined storage area. Among them, the A register corresponds to a first storage area, and the C register corresponds to a second storage area. The main control CPU 40a waiting for a predetermined period functions as game control means.

  In the pachislot machine 10 of the present embodiment, the value stored in the A register before performing the standby process in step S213 (the value stored in the A register when performing the standby process) is a specified value, and the standby It is not a value that can change each time processing is performed. In the present embodiment, the time required for the calculation process in step S213 is “about 1 second”. This is a time longer than the time required from the unstable state where the supply voltage becomes unstable to the stable state where the supply voltage becomes stable when an instantaneous power failure occurs. That is, the predetermined period of waiting is determined by a time longer than the time required for the supply voltage to change from an unstable state to a stable state. Incidentally, since the timer function cannot be used in the situation where the process of step S213 is performed, it is possible to wait for a predetermined period without using the timer function by performing the arithmetic process.

  After performing standby processing in step S213 and waiting for a predetermined period, the main control CPU 40a determines whether or not the supply voltage has been recovered (step S214). In step S214, the main control CPU 40a determines whether or not the supply voltage has recovered to a reference value determined by a value exceeding a predetermined value that triggers the output of the power-off signal. The main control CPU 40a repeats the determination process of step S214 until the determination result of step S214 becomes affirmative or until the supply voltage becomes “0 (zero)”.

  If the determination result of step S214 is affirmative, the main control CPU 40a permits access to the main control RAM 40c (step S215). Thereafter, the main control CPU 40a performs power supply restoration processing.

  As described above, when the determination result in step S214 is affirmative, the power recovery process is started. Therefore, the state in which the determination process in step S214 is repeated corresponds to a state in which the power recovery process corresponding to the recovery process can be started. In the present embodiment, the processing in steps S203 to S210 corresponds to backup processing for storing and holding the main control RAM 40c corresponding to the information storage means and the storage contents (control information) of the registers.

  In the present embodiment, the power-off signal that is output when the supply voltage becomes a predetermined value or less corresponds to the second control signal. In this embodiment, the state where the power-off signal is output corresponds to the first state of the second control signal, and the state where the power-off signal is not output is the second state of the second control signal. Equivalent to. In this embodiment, the power-off monitoring circuit 30b that outputs a power-off signal functions as a second signal output unit.

  In the present embodiment, the NMI permission signal corresponds to the first control signal. In this embodiment, the state where the NMI permission signal is output corresponds to the first state of the first control signal, and the state where the NMI permission signal is not output is the second state of the first control signal. Equivalent to. In the present embodiment, the main control CPU 40a that performs the power-off process and outputs the NMI permission signal functions as a game control means.

  In the present embodiment, the NMI signal corresponds to the third control signal. In the present embodiment, the state where the NMI signal is output corresponds to the first state of the third control signal, and the state where the NMI signal is not output corresponds to the second state of the third control signal. . In the present embodiment, the signal circuit LE that outputs the NMI signal functions as a first signal output unit.

Next, the power recovery process will be described.
As shown in FIG. 8, in the power recovery process, the main control CPU 40a determines whether or not the processes in steps S201 to S205 in the power-off process have been performed normally (step S301). In step S301, the main control CPU 40a refers to the power-off processing completion flag stored in the storage area of the predetermined address (7E1AH) in the work area of the main control RAM 40c. When the information (FFH) indicating that the processing in steps S201 to S205 has been normally performed is stored as the power-off processing completion flag, the main control CPU 40a affirms the determination result in step S301. . On the other hand, when information (information other than FFH) indicating that the processing in steps S201 to S205 has not been normally performed is stored as the power-off processing completion flag, the main control CPU 40a determines that the determination result in step S301. Is negated.

  If the determination result of step S301 is affirmative, the main control CPU 40a determines whether or not the usage amount of the stack area of the main control RAM 40c is a normal usage amount (step S302). In step S302, the main control CPU 40a determines whether or not the usage amount of the stack area of the main control RAM 40c is a normal usage amount based on the position indicated by the stack pointer. In the pachi-slot 10 of this embodiment, the normal usage amount of the stack area after the power-off process is “66”. Therefore, if the usage amount of the stack area is “66”, the main control CPU 40a affirms the determination result of step S302. On the other hand, when the usage amount of the stack area is not “66” (when it is “65 or less” or “67 or more”), the main control CPU 40a denies the determination result of step S302.

  If the determination result of step S302 is affirmative, the main control CPU 40a calculates a checksum of the main control RAM 40c (step S303). In step S303, the main control CPU 40a calculates a checksum for all the storage areas (7E00H to 7FFFH) of the main control RAM 40c as in the process of step S208.

  Subsequently, the main control CPU 40a determines whether or not the calculated checksum is normal (step S304). In step S304, the main control CPU 40a sums the checksum calculated in step S303 and the checksum data stored in the storage area of the predetermined address (7E68H) in the work area of the main control RAM 40c in step S210. Is determined to be “0 (zero)”. Incidentally, the checksum data stored in the storage area of the predetermined address in the work area is a value after being multiplied by “−1” in the process of step S209. For this reason, the fact that the sum of the checksum calculated in step S303 and the checksum data stored in the work area becomes “0 (zero)” is calculated in the checksum calculated in step S303 and in step S208. This is equivalent to having the same checksum.

  If the determination result in step S304 is affirmative, the main control CPU 40a restores the stack pointer (step S305). Subsequently, the main control CPU 40a refers to the setting information that can specify the setting of the pachislot 10 stored in the storage area of the predetermined address (7E00H) of the work area of the main control RAM 40c, and the setting of the pachislot 10 is performed. It is determined whether or not it is normal (step S306). In step S306, the main control CPU 40a determines whether or not the setting can be taken as the setting of the pachi-slot 10.

  When the determination result of step S306 is negative, the main control CPU 40a sets a power-off recovery error flag (step S307). In step S307, the main control CPU 40a stores in the main control RAM 40c that the game cannot be returned to a state in which a game can be performed in the state before the power-off process by setting the power-off recovery error flag. Thereafter, the main control CPU 40a stops various processes by stopping the error.

  When the determination results in step S301, step S302, and step S304 are negative, the main control CPU 40a proceeds to the process of step S307 and stops the error, as in the case where the determination result in step S306 is negative.

  On the other hand, if the determination result of step S306 is affirmative, the main control CPU 40a initializes the storage area excluding the work area of the main control RAM 40c and the maximum use area of the stack area (step S308). In step S308, the main control CPU 40a sets “0” in the storage area of the addresses “7EE0H to 7FBBH” of the main control RAM 40c, and initializes the storage area. Thereafter, the main control CPU 40a restores registers other than the AF register (step S309).

  Subsequently, the main control CPU 40a refers to the interrupt state when the power is turned off (when the supply voltage becomes a predetermined value or less), and determines whether or not the INT interrupt processing is permitted (see FIG. Step S310). In step S310, the main control CPU 40a refers to the interrupt state information stored in step S203, and determines whether or not the INT interrupt process is permitted.

  If the determination result of step S310 is affirmative, the main control CPU 40a permits the output of the NMI permission signal (step S311). In step S311, the main control CPU 40a sets “1” in the third bit area of the first output port. In step S311, the main control CPU 40a permits the output of the NMI permission signal using the AF register.

  Subsequently, the main control CPU 40a restores the AF register (step S312). Thereafter, the main control CPU 40a permits the INT interrupt process (step S313), and returns to the game progress main process when the power is turned off. Thereby, it returns to the state which can play a game.

  On the other hand, when the determination result of step S310 is negative, the main control CPU 40a permits the output of the NMI permission signal as in step S311 (step S314). Thereafter, the main control CPU 40a restores the AF register (step S315) and returns to the game progress main process when the power is turned off. Thereby, it returns to the state which can play a game.

  Next, a power-on process performed by the main control CPU 40a when the power to the pachislot machine 10 is turned on will be described with reference to FIGS. The main control CPU 40a performs power-on processing when the supply voltage reaches the reference value from the state where there is no supply voltage (recovery of the supply voltage), that is, when the power is turned on.

  As shown in FIG. 9, in the power-on process, the main control CPU 40a sets a stack pointer (step S401). Subsequently, the main control CPU 40a executes initial setting of the main control CPU 40a (step S402).

  Thereafter, the main control CPU 40a determines whether or not the front door 12 is opened (step S403). If the determination result of step S403 is negative, the main control CPU 40a performs a power recovery process.

  On the other hand, if the determination result of step S403 is affirmative, it is determined whether or not the setting device 28 is being operated. If the determination result of step S404 is negative, the main control CPU 40a proceeds to the determination process of step S405.

  In step S405, the main control CPU 40a determines whether or not the operation switch 29 is operated. When the determination result of step S405 is negative, the main control CPU 40a performs a power recovery process. Thus, in this embodiment, the determination process of step S404 or step S405 is performed on the condition that the determination result of step S403 is affirmative, that is, the front door 12 is opened.

  On the other hand, when the determination result of step S405 is affirmative, the main control CPU 40a determines whether or not the processing of step S201 to step S205 in the power-off processing has been normally performed as in step S301 (step S406). If the determination result in step S406 is negative, the main control CPU 40a performs a power recovery process.

  If the determination result in step S406 is affirmative, the main control CPU 40a specifies the setting of the pachislot 10 stored in the area of the predetermined address (7E00H) in the work area of the main control RAM 40c, as in step S306. With reference to the possible setting information, it is determined whether the setting of the pachislot 10 is normal (step S407).

  If the determination result of step S407 is negative, the main control CPU 40a sets a power-off recovery error flag (step S408). In step S408, as in step S307, the main control CPU 40a stores in the main control RAM 40c that it is not possible to return to a state in which a game can be performed in the state before the power-off processing by setting the power-off recovery error flag. To do. Thereafter, the main control CPU 40a stops various processes by stopping the error.

  On the other hand, when the determination result of step S407 is affirmative, the main control CPU 40a initializes a storage area other than the storage area (7E00H) in which the setting information of the main control RAM 40c is stored (step S409). As described above, when the operation switch 29 is operated in a state where the setting device 28 is not operated (when the determination result of step S405 is affirmative), the storage area that is not the storage area in which the setting information is stored is displayed as “ It is initialized by setting “0”. By performing the process of step S409, the power failure recovery error flag is also erased, so that the error is released. In the present embodiment, “0” corresponding to the regulation information is set in the storage area, so that the storage content of the storage area becomes the prescribed storage content.

  In step S409, the main control CPU 40a initializes the storage area other than the storage area in which the setting information of the main control RAM 40c is stored, so that the stored setting information is maintained. As described above, in the present embodiment, operating the operation switch 29 without operating the setting device 28 corresponds to the second operation mode. And the operation switch 29 operated when operating in the second operation mode functions as an operation means for operating in the second operation mode.

  Subsequently, the main control CPU 40a permits the output of the NMI permission signal (step S410). In step S410, the main control CPU 40a sets “1” in the third bit area of the first output port, as in step S311. Subsequently, the main control CPU 40a permits the INT interrupt process (step S411), and returns to the game progress main process when the power is turned off. Thereby, it returns to the state which can play a game. In this way, in the second operation mode in which only the operation switch 29 is operated, when the operation switch 29 as the operation means is operated, the stored contents excluding the setting information stored and held are changed to the specified stored contents ( In this embodiment, “0”) is returned to a state in which a game can be performed.

  On the other hand, as shown in FIG. 10, when the determination result of step S404 is affirmative, the main control CPU 40a is stored in the storage area of the predetermined address (7E00H) in the work area of the main control RAM 40c, as in step S407. It is determined whether or not the setting of the pachislot 10 is normal with reference to setting information that can specify the setting of the pachislot 10 that is currently set (step S412).

  If the determination result of step S412 is affirmative, the main control CPU 40a proceeds to the process of step S414. On the other hand, when the determination result of step S412 is negative, the main control CPU 40a sets a predetermined setting as the setting of the pachislot 10 (step S413). In step S413, the main control CPU 40a sets the setting that is least advantageous to the player as the setting of the pachislot 10. Thereafter, the main control CPU 40a proceeds to the process of step S414.

  In step S414, the main control CPU 40a initializes a predetermined storage area of the main control RAM 40c. When the determination result of step S412 is affirmative and the process of step S414 is performed, the main control CPU 40a addresses “7E07H to 7FFFH” other than the storage area in which the setting information, the control information regarding the winning information, and the bonus winning information are stored. “0” is stored in the storage area corresponding to, and the storage area is initialized. On the other hand, when the determination result of step S412 is negative and the process of step S414 is performed, the main control CPU 40a stores “0” in the storage area corresponding to the addresses “7E01H to 7FFFH” other than the storage area in which the setting information is stored. ”Is stored and the storage area is initialized. Incidentally, when “information other than FFH” is stored as the power-off processing completion flag in step S414, the main control CPU 40a corresponds to addresses “7E01H to 7FFFH” other than the storage area in which the setting information is stored. “0” is stored in the storage area, and the storage area is initialized. By performing the process of step S414, the power failure recovery error flag is also erased, so that the error is released.

  Thereafter, the main control CPU 40a permits the output of the NMI permission signal as in step S410 (step S415). Subsequently, the main control CPU 40a permits the INT interrupt process (step S416).

  When the process of step S416 is completed, the main control CPU 40a performs a setting change process (step S417). In the setting change process, a process for changing the setting of the pachislot machine 10 (the setting of the gaming machine) is performed.

  In the setting change processing, the main control CPU 40a changes the setting that can be set as the setting of the pachislot 10 step by step every time the operation switch 29 is operated. When the start lever 22 is operated, the main control CPU 40a sets the setting selected as the setting that can be set as the setting of the pachislot 10 when the start lever 22 is operated as the setting of the pachislot 10. Decide what to do. After that, when the operation of the setting device 28 ends, the main control CPU 40a stores setting information that can specify the determined setting of the pachislot 10 in a storage area corresponding to the address “7E00H” of the main control RAM 40c. Finish the change process.

  After performing the process of step S417, the main control CPU 40a prohibits the INT interrupt process (step S418). Subsequently, the main control CPU 40a initializes a storage area corresponding to the addresses “7E0BH to 7FFFH” among the storage areas of the main control RAM 40c (step S419). In step S419, the main control CPU 40a initializes a storage area other than the storage area in which the setting information, the information related to the winning information, the bonus winning information, and the information related to the external signal are stored. Incidentally, in step S419, the main control CPU 40a sets “0” in the storage area corresponding to the address “7E0BH to 7FFFH”, and initializes the storage area. The setting information stored at this time is setting information that can specify the setting of the pachislot machine 10 reset in step S417, and is not the setting information stored and held in the power-off process.

  As described above, in this embodiment, the setting of the gaming machine can be changed by operating the setting device 28, the operation switch 29, and the start lever 22. The operation of the setting device 28, the operation switch 29, and the start lever 22 corresponds to the first operation mode. The setting device 28, the operation switch 29, and the start lever 22 that are operated when operating in the first operation mode function as operation means for operating in the first operation mode. Further, the operation switch 29 operated in either case of operating in the first operating mode or operating in the second operating mode corresponds to a specific operating means.

  Thereafter, the main control CPU 40a permits the output of the NMI permission signal as in step S410 (step S420). Subsequently, the main control CPU 40a permits the INT interrupt process (step S421), and returns to the game progress main process when the power is turned off. Thereby, it returns to the state which can play a game. In this way, in the first operation mode in which the setting device 28, the operation switch 29, and the start lever 22 are operated, when the setting device 28, the operation switch 29, and the start lever 22 as operation means are operated, the operation is performed. The stored contents excluding the setting information that can specify the setting of the gaming machine set in the above are set to the prescribed stored contents, and the game is returned to a state in which a game can be performed.

  Here, based on FIG. 11, the output aspect of the NMI signal according to the NMI permission signal and the power-off signal in the pachi-slot 10 of the present embodiment will be described. In the drawing, a situation where various signals are output is indicated as “◯ (output)”, and a situation where various signals are not output is indicated as “× (non-output)”.

  As shown in FIG. 11, in the situation where the NMI permission signal is not outputted, the NMI signal is not outputted regardless of whether the power-off signal is outputted or not, so the NMI signal is sent to the main control CPU 40a. Is not entered.

  Further, in the situation where the NMI permission signal is output, in the situation where the power-off signal is not output, the NMI signal is not output, so the NMI signal is not input to the main control CPU 40a. On the other hand, in the situation where the NMI permission signal is output, in the situation where the power-off signal is output, the NMI signal is output, so the NMI signal is input to the main control CPU 40a.

Here, based on FIG. 12, the transition of the output state of the NMI permission signal, the power-off signal, and the NMI signal will be described along with the processing performed by the main control CPU 40a.
As shown in FIG. 12, in the situation where the main control CPU 40a is performing the game progress main process or the INT interrupt process, the NMI permission signal is output, but the power-off signal is not output.

  In the period T, when the supply voltage decreases to a predetermined value or less, the NMI signal is input to the main control CPU 40a as the power-off signal is output. Thereby, the main control CPU 40a starts the power-off process, and at time t11 when the process of step S202 in the power-off process is performed, the NMI permission signal is not output, and the output of the NMI signal is also restricted.

  As a result, even when the power-off signal is output again at timing t12 after timing t11, the NMI enable signal is not output, so the NMI signal is not input to the main control CPU 40a. . Therefore, the power-off process is not started again by the output of the power-off signal at timing t12.

  Thereafter, when the supply voltage recovers and the power recovery process is performed, the NMI permission signal is output again at timing t13 when the process of step S311 or step S314 in the power recovery process is performed. As a result, when the power-off signal is input again, the power-off process is resumed.

Next, based on FIG. 13, a change in supply voltage when an instantaneous power failure occurs and a predetermined period of waiting in the power-off process will be described.
As shown in FIG. 13, the main control CPU 40a starts the power-off process when the NMI signal is input to the main control CPU 40a at the timing t21 when the supply voltage drops below a predetermined value.

  Thereafter, it is assumed that the main control CPU 40a performs the standby process in step S213 in the power-off process and waits for a predetermined period from timing t31. As a result, the main control CPU 40a starts the power recovery process after timing t32 after the supply voltage is restored from the unstable state (unstable state) to the stable state (stable state). be able to.

  Incidentally, when the standby process in step S213 is not performed and the standby process is not performed for a predetermined period, the power recovery process is performed from the timing t41 when the supply voltage is restored to the reference value. However, when the supply voltage drops below the predetermined value again at the timing t22, the power-off signal is output, so that the power-off process is performed again.

  Similarly, when the supply voltage recovers to the reference value at timing t42, the power recovery process is performed, and when the supply voltage decreases again to the predetermined value or less again at timing t23, the power supply disconnection process is performed. For this reason, when the power recovery process is performed at the timing t43 when the supply voltage recovers again to the reference value, the stored contents stored in the main control RAM 40c at that time and the power-off process started from the timing t21 are performed. Therefore, there is a possibility that a difference occurs between the stored contents stored in the main control RAM 40c. For example, if the power-off process is performed before the stored contents (control information) stored and held in the main control RAM 40c are restored, the stored contents in a state in which nothing is restored are stored in the main control RAM 40c. There is a possibility that the stored contents are erased and the stored contents originally stored are retained.

  In the present embodiment, by performing the standby process in step S213 of the power-off process, there is a possibility that the power-recovery process can be performed after the supply voltage is stabilized even if an unstable state of the supply voltage occurs. Highly, it is possible to suppress the possibility of a difference between the contents to be stored and held and the contents actually stored and held as described above.

As described above in detail, the present embodiment has the following effects.
(1) The signal circuit LE as the first signal output means corresponds to the second control signal when the NMI permission signal corresponding to the first control signal is output (in the first state). When the power-off signal is output (becomes the first state), an NMI signal corresponding to the third control signal is output (set to the first state). Then, the main control CPU 40a as the game control means stops the output of the NMI permission signal when performing the power-off process triggered by the output of the NMI signal (the first control signal is set to the first state). To the second state). Thereby, even if the power-off signal is output again, the NMI signal is not output from the signal circuit LE. For this reason, it is possible to prevent the power-off process from being performed normally by, for example, performing the power-off process again by outputting the NMI signal again.

  (2) When the supply voltage is restored to the reference value during the power-off process, a power-return process corresponding to the return process is performed. At least the first control is performed until the power-return process is started. The NMI permission signal corresponding to the signal is not output (set to the second state). Thereby, it can suppress that a power-off process is not normally performed by performing a power-off process redundantly.

  (3) When the power-off process is performed before the predetermined process (in the above embodiment, the processes in steps S301 to S310) is performed in the power-return process corresponding to the return process, the power-off process is performed. Therefore, there is a possibility that the power-off process cannot be normally performed. For this reason, the NMI permission signal corresponding to the first control signal is not output (set to the second state) until the predetermined processing is performed. Thereby, when the power-off process is performed during the power-return process, the power-off process can be prevented from being normally performed.

  In particular, when the power-off process is performed before the stored content (control information) stored in the main control RAM 40c is restored to the register or the like, the stored content stored is erased. There is a possibility. For this reason, by restricting that the power-off process is performed again until at least a part of the stored content is restored to the main control RAM 40c or each register corresponding to the information storage means, It is possible to suppress that the power-off process is not normally performed because the stored contents that were initially stored are erased by repeating the power recovery process and the power-off process.

  (4) The first state of the first control signal is a state where the NMI permission signal is output, and the second state of the first control signal is a state where the NMI permission signal is not output. In such a configuration (hereinafter referred to as “first configuration”), when the NMI permission signal is input, a power-off signal corresponding to the second control signal is output (becomes the first state). ), An NMI signal corresponding to the third control signal is output (becomes the first state). On the other hand, when the NMI signal is output, the output of the NMI signal is restricted by not outputting the NMI permission signal.

  In addition to the first configuration, the NMI signal is output when the power-off signal is output when the NMI permission signal is not input, while the NMI signal is output when the NMI signal is output. A configuration (hereinafter referred to as “second configuration”) that restricts the output of the NMI signal by the output of “.” Is also conceivable.

Here, the first configuration and the second configuration will be compared.
For example, it is assumed that when the output of the NMI signal is restricted, the main control CPU 40a as the game control means does not perform the control related to the NMI permission signal for some reason. In this case, in the second configuration, when the NMI permission signal is output and the output of the NMI signal is restricted, the NMI permission signal is not output because the control related to the NMI permission signal is not performed. If this happens, the NMI signal may be output again.

  However, in the first configuration, even if the control related to the NMI permission signal is not performed in the situation where the NMI permission signal is not output, the situation where the NMI permission signal is not output continues, so the output of the NMI signal is also restricted. to continue. Therefore, the first configuration can prevent the NMI signal from being output again and the power-off process from being normally performed, as compared with the second configuration.

  (5) A situation in which an NMI permission signal is not output from a situation in which an NMI permission signal corresponding to the first control signal is output prior to performing the processing in steps S203 to S210 corresponding to the backup processing (first Transition from the state to the second state). As a result, it is possible to prevent the NMI signal from being output during the backup process (becomes the first state) and the power-off process not being performed normally. Further, it is possible to prevent an error such as performing the backup process again during the backup process. And if it can suppress that an error generate | occur | produces, the accuracy of management of a game medium will improve as a result.

  (6) After performing the processing of step S203 to step S210 corresponding to the backup processing, after waiting for a predetermined period, the power recovery processing corresponding to the recovery processing can be started. In this way, by waiting for a predetermined period, it is possible to wait until the supply voltage is stabilized, and it is possible to perform the power recovery process after the supply voltage is stabilized. For this reason, it is possible to suppress the power recovery process from being performed in a state where the supply voltage is not stable compared to the case of not waiting for a predetermined period, and to suppress various processes such as the power recovery process and the backup process from being performed normally. Can do. Further, by performing the backup process before waiting for a predetermined period, even if the supply voltage does not recover as it is, the storage content (control information) can be stored in the main control RAM 40c.

  (7) It is configured to wait for a predetermined period by performing arithmetic processing. This makes it possible to wait for a predetermined period even in a situation where the timer function cannot be used, such as when performing power-off processing.

  (8) Waiting for a predetermined period by performing arithmetic processing for subtracting the values stored in the A and C registers of the main control RAM 40c and registers as information storage means. In this way, a predetermined period of time is awaited by a calculation process that has no other effect so as to subtract the value stored in the predetermined storage area. As a result, it is possible to prevent an error from occurring during standby and prevent various processes such as the power recovery process and the backup process corresponding to the recovery process from being performed normally.

  (9) The storage area to be subjected to the calculation process to be subtracted when waiting for a predetermined period includes an A register corresponding to the first storage area and a C register corresponding to the second storage area. In the A register, arithmetic processing for subtracting the value stored before waiting (when waiting) is performed. On the other hand, in the C register, when waiting, a specific value is stored and an arithmetic process for subtracting the specific value is performed. For this reason, if the value stored in the A register before the standby does not change, the specific value stored in the C register may be adjusted to adjust the predetermined period of standby. It is possible to easily adjust the predetermined period while suppressing the control not being performed.

  (10) When the setting device 28, the operation switch 29, and the start lever 22 are operated (when the operation means is operated in the first operation mode), the setting of the pachislot machine 10 set by the operation (setting of the gaming machine) ) Is stored in the main control RAM 40c as information storage means. On the other hand, when only the operation switch 29 is operated (when the operation means is operated in the second operation mode), the stored setting information is stored as it is in the main control RAM 40c.

  That is, by operating the setting device 28, the operation switch 29, and the start lever 22, it is possible to return to a state in which a game can be performed while changing the setting of the pachislot 10. On the other hand, if only the operation switch 29 is operated, it is possible to return to a state in which a game can be performed while maintaining the setting of the pachislot 10. As described above, the operation mode can be selected according to whether or not the setting of the pachislot machine 10 is changed along with the return to the state in which a game can be performed, and convenience is improved.

  (11) A setting device 28 and an operation switch 29 are arranged at a position where the front door 12 cannot be operated unless the front door 12 is opened (if the front door 12 is not opened). Then, on the condition that the front door 12 is opened, the setting device 28, the operation switch 29, and the start lever 22 can be operated to return to a state in which a game can be performed. As a result, it is possible to improve the convenience and return to a state in which a game can be performed by an illegal act such as the setting device 28 or the operation switch 29 being operated without the front door 12 being opened. Can be suppressed.

  (12) The operation switch 29 corresponding to a specific operation means changes the setting of the pachislot 10 when returning to a state where the game can be performed while changing the setting of the pachislot 10 (setting of the gaming machine). The operation is performed in either case of returning to a state where the game can be performed without any change. In this way, when returning to a state in which a game can be performed, the operation switch 29 is commonly used regardless of whether or not the setting of the pachislot 10 is changed. For this reason, since the kind of operation means can be reduced rather than the case where an operation means is provided separately, it can contribute to a manufacturing cost reduction and can also save the effort concerning arrangement design of an operation means.

  (13) Before performing steps S203 to S210 corresponding to the backup processing, the output of the payout device operation signal is restricted (the payout device is set to the second state), and the medal as the game medium is paid out. stop. As a result, it is possible to suppress the occurrence of an error such as game media being paid out during backup processing, and the accuracy of management of game media is improved.

  (14) Prior to performing steps S203 to S210 corresponding to the backup processing, the output of the medal blocker operation signal is restricted (the guidance device is set to the second state), and the inserted game medium (medal) Return so that is not detected. As a result, it is possible to suppress the occurrence of an error such as a credit not increasing even if a game medium is inserted during the backup process, and the management accuracy of the game medium is improved.

  (15) Before performing steps S203 to S210 corresponding to the backup processing, the output of the payout device operation signal is restricted to stop the game medium (medal) payout instruction, and the medal blocker operation signal The output is restricted and returned so that the inserted game media is not detected. This prevents errors such as game media being paid out during backup processing, etc., and causes errors such as credits not increasing even if game media are inserted during backup processing. And the accuracy of management of game media is improved.

  (16) Area related to output of payout device operation signal (output area for outputting control signal for controlling payout device to first state) and area related to output of medal blocker operation signal (guide device) And an output region for outputting a control signal for controlling to the first state) are associated with the same tenth output port. As a result, if the output of the control signal at the tenth output port is prohibited, “the instruction to pay out the game medium is stopped (the payout device is in the second state)” and “the medal blocker MB is inserted. It is possible to perform both of “acting to guide the medal to the discharge passage 19b (the guiding device is in the second state)”. Furthermore, since control signal output can be prohibited in units of output ports, control can be simplified as compared with the case where control signal output is prohibited for each output port area.

  (17) In a situation where the setting of the pachislot 10 (the setting of the gaming machine) is not normal, a predetermined setting is set as the setting of the pachislot 10. For this reason, it is possible to prevent an unexpected state from occurring, for example, a setting with a higher (or lower) advantage than the planned setting of the pachislot 10.

  (18) In the pachislot machine 10 in which a game is mainly performed in a situation where bonus winning information is stored, the bonus winning information is not erased in the processing of step S409 or step S419. For this reason, it is possible to reduce the game during the period from the return to the state where the game can be performed until the 51st winning information is won (the period until the bonus winning information is stored). That is, when the game is returned to a state in which the game can be performed, it is possible to reduce the waste of the game by returning to the state in which the game is mainly performed.

In addition, the said embodiment can be actualized in another embodiment (another example) as follows.
In the above embodiment, the situation in which the NMI enable signal is output may be replaced with the situation in which the NMI enable signal is not output, and the situation in which the NMI enable signal is not output may be replaced with the situation in which the NMI enable signal is output. In this case, the state where the NMI permission signal is not output corresponds to the first state of the first control signal, and the state where the NMI permission signal is output corresponds to the second state of the first control signal.

  In the above embodiment, the situation where the power-off signal is output may be replaced with a situation where the power-off signal is not output, and the situation where the power-off signal is not output may be replaced with a situation where the power-off signal is output. In this case, the state where the power-off signal is not output corresponds to the first state of the second control signal, and the state where the power-off signal is output corresponds to the second state of the second control signal.

  In the above embodiment, the situation in which the NMI signal is output may be replaced with a situation in which the NMI signal is not output, and the situation in which the NMI signal is not output may be replaced with a situation in which the NMI signal is output. In this case, the state where the NMI signal is not output corresponds to the first state of the third control signal, and the state where the NMI signal is output corresponds to the second state of the third control signal.

In the above embodiment, the signal circuit LE may be connected so that a control signal can be output from the signal circuit LE to the power-off monitoring circuit 30b.
In the above-described embodiment, the setting device 28 and the operation switch 29 may be configured to be accommodated inside the main body 11 by being provided inside the main body 11 as the equipment container.

  In the above embodiment, when the medal blocker operation signal is output to the blocker solenoid BS, the medal blocker MB operates so as to guide the inserted medal to the discharge passage 19b. On the other hand, the medal blocker operation signal may not be output to the blocker solenoid BS, so that the medal blocker MB may be operated to guide the inserted medal to the storage passage 19a. When configured in this way, in the above-described embodiment, the medal blocker operation signal is not output in a situation where the medal blocker operation signal is output. In addition, in the above embodiment, in a situation where the medal blocker operation signal is not output, it is preferable that the medal blocker operation signal is output.

  -In the power-off process of the said embodiment, you may interchange the process of step S201 and the process of step S202. And the process of step S201 and the process of step S203-step S210 can also be defined as a backup process.

  The value stored in the A register before performing the standby process in step S213 in the power-off process of the above embodiment may not be a specified value. For example, a different value may be stored in the A register each time. In this case, whatever value is set in the A register, it is preferable that a value that reaches a predetermined period by performing arithmetic processing is set in the C register as a specific value.

  In the standby process in step S213 in the power-off process of the above embodiment, the specific value stored in the C register may be changed each time. For example, you may comprise so that a specific value may be set according to the fall state of supply voltage.

  In the standby process of step S213 in the power-off process of the above embodiment, until the supply voltage becomes stable by performing an arithmetic process that subtracts the value stored in one of the A register and the C register If the configuration can wait, both the A register and the C register need not be used.

  In the above embodiment, the area associated with the medal blocker operation signal (the output area for outputting the control signal for controlling the guidance device to the first state) and the payout apparatus operation signal are associated with each other. The area (output area for outputting a control signal for controlling the dispensing device to the first state) may not be associated with the same output port.

  In the above embodiment, in addition to the area associated with the medal blocker activation signal and the area associated with the payout device activation signal, the area associated with the NMI permission signal is also associated with the same output port. Also good. For example, when the region associated with the NMI permission signal is associated with the tenth output port, if the output port to be turned off in step S202 is only the tenth output port, the control burden in step S202 is reduced. be able to.

  -In the above embodiment, if the output of the payout device activation signal is restricted before the backup process is performed, the management of the game medium is not required even if the output of the medal blocker activation signal is not regulated before the backup process is performed. Can improve the accuracy. Similarly, if the output of the medal blocker activation signal is regulated before the backup processing is performed, the accuracy of management of the game medium can be controlled without regulating the output of the payout device activation signal before performing the backup processing. Can be improved.

  In the above embodiment, the medal blocker MB is activated so that the inserted medal is guided to the discharge passage 19b by inputting the medal blocker operation signal to the blocker solenoid BS. On the other hand, the medal blocker MB may be configured to operate so as to guide the inserted medal to the storage passage 19a when the medal blocker operation signal is not input to the blocker solenoid BS.

  In the above embodiment, the hopper 26 operates so as not to pay out medals when the payout device operation signal is input, while the hopper 26 performs payout of medals when the payout device operation signal is not input. It may be configured to operate.

  In the above embodiment, the operating means that is operated when changing the setting of the pachislot 10 to return to a state in which a game can be performed, and the state in which a game can be performed without changing the setting of the pachislot 10 The operating means that is operated when returning to the state may be completely different operating means. Further, these operation means do not need to be disposed at a position that can be accommodated in the main body 11 as the equipment container, for example, at the front side of the pachislot 10 and at a position that can be operated by the player. May be.

  In the above embodiment, the operation means when the operation means is operated in the first operation mode and the operation means when the operation means are operated in the second operation mode may be the same. Then, the first operation mode and the second operation mode may be configured such that the operation methods of the operation means (for example, the operation order, the number of operations, the operation direction, the operation timing, etc.) are different.

  -In the above embodiment, even if the front door 12 is not opened, when the setting device 28, the operation switch 29, the start lever 22 or the like is operated, the game can be returned to a state in which a game can be performed. Also good.

-In the said embodiment, you may change arbitrarily the step of the setting of the pachislot 10 (setting of a gaming machine). For example, it may be one stage, three stages or ten stages.
In the above embodiment, in a spinning-type gaming machine with a specification (for example, an ART machine) that can acquire medals in a bonus game, the bonus winning information may also be deleted in the processing of step S409 or step S419. Good. For example, in a revolving type gaming machine with a specification that can acquire medals in bonus games, when the setting of the pachislot 10 is changed or only the operation switch 29 is operated, the game is performed with the bonus winning information stored and held. If the game is returned to a state where it can be performed, it becomes an advantageous situation for the player from the start of the game. In this case, the game is not interesting, and there is a possibility that it may be disadvantageous to the game arcade. However, in the process of step S409 or step S419, if the bonus winning information is also deleted, it is possible to suppress the lack of interest in the game and to give a disadvantage to the game hall. Can also be suppressed.

In the above embodiment, the predetermined value and the reference value may be the same value.
In the above embodiment, after the backup process is performed, the state where the NMI permission signal is output may be changed to the state where the NMI permission signal is not output. For example, the process of step S202 may be performed after the process of step S210 is completed.

  In the above embodiment, the sub-control CPU 41a of the sub-control board 41 is also similar to the main control CPU 40a of the main control board 40 in processing related to storing and holding the storage contents (control information) of the sub-control RAM 41c (for example, A power-off process or a power-return process may be performed. In the case of such a configuration, it is possible to store and hold control contents managed by the sub control CPU 41a.

  In the above embodiment, the signal circuit LE can interpret the input power-off signal as being output to the main control CPU 40a of the main control board 40 as an electrical signal that becomes an NMI signal. In this case, the signal circuit LE allows the input power-off signal to be output to the main control CPU 40a when the NMI enable signal is input, while the input power-off signal is not input when the NMI enable signal is not input. This corresponds to restricting the output of a signal to the main control CPU 40a. That is, the signal circuit LE corresponding to the first signal output means permits the output of the second control signal to the game control means when the first control signal is in the first state, while the first control signal When the signal is in the second state, this corresponds to restricting the output of the second control signal to the game control means.

  In the power recovery process of the above embodiment, the timing for permitting the output of the NMI permission signal may be changed. For example, the output of the NMI permission signal may be permitted after the process of step S313 or step S315 in the power recovery process, or the output of the NMI permission signal may be permitted before the process of step S310 in the power recovery process. Good.

  In the power-on process of the above embodiment, the timing for permitting the output of the NMI permission signal may be changed. For example, the output of the NMI permission signal may be permitted after the process of step S411 or step S421 in the power-on process, or the output of the NMI permission signal is permitted before the process of step S409 or step S419 in the power-on process. May be.

  The navigation effect in the above embodiment is not limited to navigating the stop button operated first, but is an effect of navigating the stop button operated first (first) and the stop button operated second. May be. Such a navigation effect corresponds to navigating the stop button operated for the third time (last) by navigating the stop button operated for the first time and the second time. That is, this corresponds to navigating the entire operation order of the stop buttons 23L, 23C, and 23R.

  In the above embodiment, the navigation effect is not limited to being performed by the effect display device 14, but may be configured to be performed by the speaker Sp. Alternatively, the stop buttons 23L, 23C, and 23R may be configured to incorporate a light emitter and execute a navigation effect using the light emitter. Further, the navigation effect may be configured to be executed using a plurality of effect execution means (in the above, the effect display device 14, the speaker Sp, and the light emitter incorporated in the stop button).

The above embodiment may be applied to a spinning-type game machine (pachislot machine) to which no bonus game is given.
The above-described embodiment may be embodied in a spinning-type game machine (pachislot) that uses a game ball (pachinko ball) as a game medium.

-The above-mentioned embodiment may be embodied not only in a swivel type gaming machine (pachislot) but also in a pachinko gaming machine.
-In the above-mentioned embodiment, you may provide the BET button which can bet 1 from credit by operating.

  -In the said embodiment, you may change arbitrarily the probability of winning each winning information. For example, the probability of winning the 21st winning information may be higher than the probability of winning the 11th winning information in the winning information lottery, or may be higher than the probability of winning the 21st winning information in the winning information lottery. The probability of winning eleven winning information may be increased.

Next, a technical idea that can be grasped from the above embodiment and another example will be added below.
(A) The game control means has a timer function, and the predetermined period is reached by performing a predetermined arithmetic process without using the timer function.

(B) When waiting for the predetermined period, the value stored in the first storage area is a specified value.
(C) The predetermined period is a time longer than the time required for the supply voltage to transition from the unstable state to the stable state.

  NL ... winning line, BS ... blocker solenoid, MB ... medal blocker, KS ... front door open sensor, LE ... signal circuit, La ... decorative lamp, Sp ... speaker, SE4 ... medal sensor, 10 ... pachislot, 11 ... main body, 12 ... front door, 13 ... drum unit, 13L ... left reel, 13C ... middle reel, 13R ... right reel, 14 ... effect display device, 16 ... see-through window, 22 ... start lever, 23L, 23C, 23R ... stop button, 26 ... Hopper, 28 ... setting device, 29 ... operating switch, 30 ... power supply board, 30a ... power supply circuit, 30b ... power cut-off monitoring circuit, 30c ... backup power supply, 40 ... main control board, 40a ... main control CPU, 40b ... Main control ROM, 40c ... Main control RAM, 41 ... Sub control board, 41a ... Sub control CPU, 41b ... Sub control ROM 41c ... sub-control for RAM.

Claims (2)

And information storage means that can store holds control information about the game,
And power-off processing including a backup process for storing stores control information in the information storage unit, and return processing for returning to the capable of performing a game state, a game control means capable of,
First signal output means connected to the game control means so as to be able to output control signals bidirectionally;
A second signal output means connected to be able to output a control signal to at least the first signal output means ,
The first control signal that can be output from the game control means to the first signal output means can be in a first state or a second state,
The second signal output means can output a second control signal that can be in the first state or the second state, and the second signal output means is triggered by the fact that the supply voltage decreases and reaches a predetermined value. 2 control signal to the first state,
The first signal output means can output a third control signal that can be in the first state or the second state, and the second signal when the first control signal is in the first state. The third control signal is set to the first state when the control signal is in the first state,
The game control means includes
A possible supply voltage to perform the returning process triggered by the restored to the reference value exceeding the predetermined value,
When the third control signal enters the first state, the power-off process is performed while the first control signal is changed from the first state to the second state, and then the power-off process is performed. In the game machine, after performing the backup process, after waiting for a predetermined period, it is possible to start the return process. The game control means starts at least the return process after changing the first control signal from the first state to the second state when the third control signal becomes the first state. The gaming machine according to claim 1, wherein the first control signal is set to the second state until it is done .