JP6216563B2 - Data output circuit, PLL device and data output method - Google Patents

Description

  The present invention relates to a data output circuit, and more particularly to a data output circuit that takes in each piece of sequentially supplied data pieces and supplies it to a device, a PLL device including such a data output circuit, and a data output method.

  A PLL (phase locked loop) circuit that can control the output frequency via a serial peripheral interface (hereinafter referred to as SPI) as a programmable device that can perform operation settings in accordance with user specifications after manufacture. It is known (see, for example, Patent Document 1). In such a PLL circuit, the frequency division number of the frequency divider circuit is set (referred to as a first setting) based on the frequency division setting data supplied as serial data. Further, in this PLL circuit, the loop gain of the PLL circuit is set (referred to as a second setting) based on a predetermined n-bit series value in the frequency division setting data. Therefore, when both the first and second settings described above are required to operate the PLL circuit, first the first (or second) described above is set according to the setting data supplied as serial data. This is followed by the second (or first) setting.

JP 2001-16102 A

  By the way, if the series of settings as described above are performed during the operation of the PLL circuit, the PLL circuit reflects only the first setting during the period from the first setting to the next setting. In addition, an unintended operation state occurs. Therefore, if the following settings are made for the PLL circuit in such a state, it may take a considerable amount of time for the PLL circuit to reach a desired operating state, resulting in a decrease in operating efficiency. There was a fear. In addition, an unintended frequency may be output until all settings are completed, which may cause an unexpected malfunction. An object of the present invention is to provide a data output circuit, a PLL device, and a data output method capable of outputting a plurality of data pieces supplied in a serial form to an operating device without reducing the operation efficiency. And

A data output circuit according to the present invention is a data output circuit for fetching and outputting the first and second data pieces from a serial data signal in which a first data piece and a second data piece are arranged in order, A first new data register that takes in the first data piece from a data signal and stores it as a first new data piece, and takes in the first new data piece stored in the first new data register as a first A first existing data register that stores as an existing data piece, a second new data register that takes in the second data piece from the serial data signal and stores it as a second new data piece, and stores it in the second new data register A second existing data register that takes in the second new data piece being stored and stores it as a second existing data piece; During the new data acquisition period from when the first new data register starts to acquire the first data piece to when the second new data register ends the acquisition of the second data piece, the first and second (2) Stop the fetch of the first and second new data pieces by the existing data register and output the first and second existing data pieces as the first and second data pieces, and end the new data fetch period. after and an output control section for outputting the first and second new data simultaneously as said first and second data piece.

  The PLL device according to the present invention includes a VCO that generates an oscillation signal having a frequency corresponding to a control voltage, a frequency dividing circuit that generates a frequency-divided signal obtained by frequency-dividing the oscillation signal, the frequency-divided signal, and a reference oscillation signal. A phase comparator for detecting a phase difference between the first line, a charge pump for applying an output current to the first line over a period corresponding to the phase difference, and generating the control voltage by smoothing the voltage on the first line A serial data signal including a PLL circuit including a loop filter, a first data piece indicating a frequency division ratio of the frequency divider, and a second data piece indicating a current value of the output current. A data output circuit that takes in the first and second data pieces and outputs them to the PLL circuit, wherein the data output circuit takes the first data pieces from the serial data signal. A first new data register that stores this as a first new data piece, and a first existing data that takes in the first new data piece stored in the first new data register and stores it as a first existing data piece A data register, a second new data register that takes in the second data piece from the serial data signal and stores it as a second new data piece, and the second new data piece stored in the second new data register A second existing data register that stores this as a second existing data piece and the second new data register after the first new data register starts taking in the first data piece. During the new data capture period until the capture of the first and second existing data registers, the first and second existing data registers are used. The capturing of the new data piece is stopped and the first and second existing data pieces are output as the first and second data pieces, and the first and second new data are stored after the end of the new data capturing period. And an output control unit that outputs the first and second data pieces synchronously.

The data output method according to the present invention is a data output method for fetching and outputting the first and second data pieces from a serial data signal in which a first data piece and a second data piece are sequentially arranged, The first data piece is taken from the serial data signal and stored in the first new data register as a first new data piece, and subsequently the second data piece is taken from the serial data signal and used as the second new data piece. The second new data register is stored, the first new data piece stored in the first new data register is fetched and stored in the first existing data register as the first existing data piece, and the second new data register is stored. The second new data piece stored in the data register is fetched and used as the second existing data piece. During the new data capture period from when the first new data register starts capturing the first data fragment until the second new data register finishes capturing the second data fragment. , Stopping the fetching of the first and second new data pieces by the first and second existing data registers, and outputting the first and second existing data pieces as the first and second data pieces, The first and second new data are output simultaneously as the first and second data pieces after the end of the data capture period.

It is a block diagram which shows a part of internal structure of the information processing apparatus containing the data output circuit 100 based on this invention. It is a time chart which shows the format of the serial data signal SDS. It is a time chart which shows the data format of each of the blocks B1-B3 in the serial data signal SDS. 3 is a time chart showing an example of an internal operation in the data output circuit 100. FIG. 10 is a block diagram showing a modification of the data output circuit 100. 6 is a time chart showing a data format of each of blocks B4 and B5 in a serial data signal SDS, which is additionally used in the data output circuit 100 shown in FIG. 6 is a time chart showing an example of an internal operation in the data output circuit 100 shown in FIG. 5. 1 is a block diagram showing a configuration of a PLL device including a data output circuit 100 according to the present invention. FIG. 9 is a time chart showing a data format of each of blocks B2c to B2f in a serial data signal SDS, which is additionally used in the data output circuit 100 shown in FIG.

  FIG. 1 is a block diagram showing a part of an internal configuration of an information processing apparatus including a data output circuit 100 according to the present invention.

  In FIG. 1, a programmable device 200 (hereinafter referred to as PDV 200) is one of functional devices that constitute the information processing apparatus, and includes, for example, a PLL circuit, a timer, a sensor, or an arithmetic processing unit. In the PDV 200, the first operation parameter is set according to the first setting data PDa supplied from the data output circuit 100, and the second operation parameter is set according to the second setting data PDb. For example, when the PDV 200 is a PLL circuit, the first operating parameter is, for example, a frequency dividing ratio of the frequency dividing circuit, and the setting data PDa indicates a value for setting the frequency dividing ratio. Further, the second operation parameter is, for example, a reference frequency, and the setting data PDb indicates a value for setting the reference frequency.

  The controller 300 controls the main operation (not described) of the information processing apparatus, and is provided in a semiconductor chip different from the data output circuit 100, for example. When the controller 300 needs to change the first or second operation parameter for the PDV 200 during the execution of the control, the controller 300 outputs the serial data signal SDS, the enable signal EN, and the clock signal CLK as follows. This is supplied to the data output circuit 100.

  As shown in FIG. 2, the serial data signal SDS has a data bit sequence DS, an address bit sequence AS, a write / read control bit WRB, and a write execution bit LB, each of which is composed of a 1-bit serial bit sequence. It is a signal that makes one block. The data bit series DS represents output control data OD (described later), hold control data HD (described later), and one of the setting data PDa and PDb described above as serial data. The address bit series AS is address data that designates one of a first and second data buffer (described later), an output control register (described later), and a hold register (described later) as a write target. It is expressed as serial data. The write / read control bit WRB represents an instruction to write or read with 1 bit. In this embodiment, since reading to the controller 300 is not performed, the write / read control bit WRB indicates only writing. Further, the write execution bit LB represents one bit of an instruction as to whether or not to write to the data buffer, the output control register or the hold register.

  The controller 300 enables the operation of the data output circuit 100 while the above-described DS, AS, WRB, and LB send serial data signals SDS for one block arranged in order as shown in FIG. An enable signal EN of logic level 0 is supplied to the data output circuit 100. Further, as shown in FIG. 2, the controller 300 supplies the data output circuit 100 with a clock signal CLK synchronized with each bit of the DS, AS, WRB, and LB.

  The data output circuit 100 is formed on a semiconductor chip different from the controller 300, and includes a serial interface unit 10, data buffers 20a and 20b, and an output control register 30, as shown in FIG.

  The serial interface unit 10 is enabled according to a logic level 0 enable signal EN supplied from the controller 300 via an external terminal. At this time, the serial interface unit 10 performs the following operation in synchronization with the serial data signal SDS and the clock signal CLK supplied from the controller 300 via the external terminals.

  That is, first, the serial interface unit 10 sequentially captures the data bit series DS, address bit series AS, write / read control bit WRB, and write execution bit LB in the serial data signal SDS in synchronization with the clock signal CLK. . Then, the serial interface unit 10 converts the above-described data bit series DS into parallel data, and uses this as write data QD, as a data buffer 20a as a first buffer, a data buffer 20b as a second buffer, and an output. This is supplied to the control register 30. Further, the serial interface unit 10 converts the address bit sequence AS described above into parallel address data, and for one of the data buffers 20a and 20b and the output control register 30 designated by the address data, A write signal for writing the write data QD is supplied at the fetch timing of the write execution bit LB. That is, the serial interface unit 10 supplies the write signal W1 to the data buffer 20a when the address data indicates the data buffer 20a, and the write signal W2 when the address data indicates the data buffer 20b. 20b. Further, the serial interface unit 10 supplies the write signal Wc to the output control register 30 when the address data indicates the output control register 30.

  The data buffer 20a includes a new data register 21a, a selector 22a, an existing data register 23a, and an output selector 24a. Only when the write signal W1 is supplied, the new data register 21a captures and stores the write data QD at the edge timing of the clock signal CLK described above, and stores this data as new setting data SDa and the output of the selector 22a. This is supplied to the selector 24a. The selector 22a selects one of the setting data TDa supplied from the existing data register 23a and the above-described new setting data SDa according to the output selection signal SEL, and uses this as the setting data RDa to set the existing data register 23a. To supply. That is, the selector 22a selects the setting data TDa and SDa among the setting data TDa and SDa while the output selection signal SEL is at the logic level 1 that prompts the output of new setting data, and uses this as setting data RDa. To supply. On the other hand, while the output selection signal SEL prompts the output of the existing setting data and is at the logic level 0 indicating that the new setting data is being taken in, the selector 22a selects TDa among the setting data TDa and SDa. This is supplied as setting data RDa to the existing data register 23a. That is, during the period when the output selection signal SEL is at the logic level 0, the selector 22a stops supplying the new setting data SDa stored in the new data register 21a to the existing data register 23a. The existing data register 23a takes in the setting data RDa at the edge timing of the clock signal CLK, and supplies this to the selector 22a and the output selector 24a as the existing setting data TDa. The output selector 24a selects one of the setting data TDa and SDa according to the output selection signal SEL, and supplies this to the PDV 200 as the setting data PDa. That is, the output selector 24a selects the new setting data SDa from the setting data TDa and SDa while the output selection signal SEL is at the logic level 1 that prompts the output of the new setting data, and uses this as the setting data PDa. To the PDV 200. On the other hand, while the output selection signal SEL prompts the output of the existing setting data and is at the logic level 0 representing the period for taking in the new setting data, the output selector 24a selects the existing setting from the setting data TDa and SDa. Data TDa is selected and supplied to the PDV 200 as setting data PDa.

  The data buffer 20b includes a new data register 21b, a selector 22b, an existing data register 23b, and an output selector 24b. Only when the write signal W2 is supplied, the new data register 21b captures and stores the write data QD at the edge timing of the clock signal CLK described above, and stores the write data QD as new setting data SDb and the output This is supplied to the selector 24b. The selector 22b selects one of the setting data TDb supplied from the existing data register 23b and the above-described new setting data SDb according to the output selection signal SEL, and uses this as the setting data RDb to set the existing data register 23b. To supply. That is, the selector 22b selects the setting data TDb and SDb among the setting data TDb and SDb and outputs the setting data RDb as the existing data register 23b while the output selection signal SEL is at the logic level 1 that prompts the output of new setting data. To supply. On the other hand, while the output selection signal SEL prompts the output of the existing setting data and is at the logic level 0 indicating that the new setting data is being taken in, the selector 22b selects TDb among the setting data TDb and SDb. This is supplied to the existing data register 23b as setting data RDb. That is, during the period when the output selection signal SEL is at the logic level 0, the selector 22b stops supplying the new setting data SDb stored in the new data register 21b to the existing data register 23b. The existing data register 23b takes in the setting data RDb at the edge timing of the clock signal CLK, and supplies this to the selector 22b and the output selector 24b as the existing setting data TDb. The output selector 24b selects one of the setting data TDb and SDb according to the output selection signal SEL, and supplies this to the PDV 200 as the setting data PDb. In other words, the output selector 24b selects the new setting data SDb from the setting data TDb and SDb while the output selection signal SEL is at the logic level 1 that prompts the output of the new setting data. It supplies to PDV200 as PDb. On the other hand, while the output selection signal SEL prompts the output of the existing setting data and is at the logic level 0 representing the period of taking in the new setting data, the output selector 24b selects the existing setting from the setting data TDb and SDb. Data TDb is selected and supplied to the PDV 200 as setting data PDb.

  The output control register 30 takes in and stores the write data QD at the edge timing of the clock signal CLK only when the write signal Wc is supplied. Note that the write data QD written to the output control register 30 in response to the write signal Wc is based on the output control data OD. In other words, it represents a value indicating a command prompting the output of new setting data (hereinafter referred to as a new setting data output command) or a command prompting the output of existing setting data (hereinafter referred to as an existing setting data output command) and The output control data OD having a value representing the capture period is captured and stored in the output control register 30. The output control register 30 supplies a logic level 1 output selection signal SEL to the data buffers 20a and 20b when the write data QD stored as described above indicates a new setting data output command. On the other hand, when the write data QD is an existing setting data output command and indicates that a new setting data is being fetched, the output control register 30 sends the output selection signal SEL of logic level 0 to the data buffer 20a and 20b.

  With the configuration described above, the data output circuit 100 receives the setting data PDa and PDb for determining the first and second operating parameters of the PDV 200 by the clock signal CLK and the serial data signal SDS, and converts these setting data into parallel data. The result is output to PDV200.

  Hereinafter, the operation of the data output circuit 100 will be described in detail. First, the controller 300 supplies a serial data signal SDS composed of a series of blocks B1 to B3 shown in FIG. 3 to the data output circuit 100 as shown in FIG. As shown in FIG. 3, the block B1 includes a data bit sequence DS based on [00] h output control data OD indicating an existing setting data output command, and an address bit sequence based on address data designating the output control register 30. AS, a write / read control bit WRB for designating write processing, and a write execution bit LB for prompting execution. The block B2a includes a data bit sequence DS based on setting data PDa for setting the first operation parameter of the PDV 200, an address bit sequence AS based on address data designating the data buffer 20a, and a write / read control bit designating write processing. WRB is composed of a write execution bit LB that prompts execution. The block B2b includes a data bit sequence DS based on setting data PDb for setting the second operation parameter of the PDV 200, an address bit sequence AS based on address data designating the data buffer 20b, and a write / read control bit designating write processing. WRB is composed of a write execution bit LB that prompts execution. Block B3 is a data bit sequence DS based on [01] h output control data OD indicating a new setting data output command, an address bit sequence AS based on address data designating the output control register 30, and a write designating write processing. It consists of a read control bit WRB and a write execution bit LB that prompts execution.

  As shown in FIG. 4, first, when the block B1 is supplied as the serial data signal SDS, the output control register 30 of the data output circuit 100 takes in the value [00] h indicated by the output control data OD, A logic level 0 output selection signal SEL corresponding to this value is supplied to the data buffers 20a and 20b.

  Here, the data buffer 20a (20b) stores and holds the data in the existing data register 23a (23b) over the period during which the output selection signal SEL of the logic level 0 is supplied, that is, the new data capture period TK shown in FIG. The setting data TDa (TDb) that has been set, that is, the existing setting data is output to the PDV 200. For example, as shown in FIG. 4, in the data buffer 20a, when [55] h is stored and held as the existing setting data in the existing data register 23a, the output selection signal SEL is in the logic level 0 state. [55] h stored and held in the existing data register 23a is supplied to the PDV 200 as setting data PDa over the new data capture period TK. In addition, as shown in FIG. 4, the data buffer 20b has an interval of the above-described new data capture period TK when [CC] h is stored and held as the existing setting data in the existing data register 23b. [CC] h stored and held in the existing data register 23b is supplied to the PDV 200 as setting data PDb. Further, over the new data fetch period TK, the existing data register 23a (23b) of the data buffer 20a (20b) fetches the new setting data SDa (SDb) stored in the new data register 21a (21b). Stopped.

  Next, when the block B2a is supplied as the serial data signal SDS to the data output circuit 100, the new data register 21a provided in the data buffer 20a takes in the setting data PDa included in the block B2a and overwrites it. To do. As a result, the existing setting data stored and held in the new data register 21a is switched to a new value. For example, as shown in FIG. 4, when [55] h is stored in the new data register 21a as existing setting data, a block B2a indicating [AA] h is supplied as new setting data PDa. The new data register 21a of the data buffer 20a transitions from the storage state of [55] h to the new storage state of [AA] h. However, during the new data acquisition period TK in which the output selection signal SEL is at the logic level 0, the existing data register 23a is in a state of stopping the acquisition of the new setting data SDa stored in the new data register 21a. Further, during this time, [55] h as the existing setting data stored and held in the existing data register 23 a is continuously output to the PDV 200. That is, although [AA] h is written as new setting data in the new data register 21a, until the output selection signal SEL transitions to the logic level 1, that is, the new data capture period TK shown in FIG. Until the process is completed, a new setting data is not output to the PDV 200, and a so-called output waiting state is entered.

  Next, when the block B2b is supplied as the serial data signal SDS to the data output circuit 100, the new data register 21b provided in the data buffer 20b takes in the setting data PDb included in the block B2b and overwrites it. To do. As a result, the existing setting data stored and held in the new data register 21b is switched to a new value. For example, as shown in FIG. 4, when [CC] h is stored in the new data register 21b as existing setting data, a block B2b indicating [33] h is supplied as new setting data PDb. The new data register 21b of the data buffer 20b transitions from the storage state of [CC] h to the new storage state of [33] h. However, during the new data capture period TK in which the output selection signal SEL is at the logic level 0, the existing data register 23b is in a state where the capture of the new setting data SDb stored in the new data register 21b is stopped. Further, during this time, [CC] h as the existing setting data stored and held in the existing data register 23 b is continuously output to the PDV 200. That is, although [33] h is written as new setting data in the new data register 21b, the time until the output selection signal SEL transitions to the logic level 1 state, that is, the new data capture period TK shown in FIG. Until the process is completed, a new setting data is not output to the PDV 200, and a so-called output waiting state is entered.

  Next, when the block B3 is supplied to the data output circuit 100 as the serial data signal SDS, the output control register 30 of the data output circuit 100 takes in the value [01] h indicated by the output control data OD, A logic level 1 output selection signal SEL corresponding to this value is supplied to the data buffers 20a and 20b. As described above, when the output selection signal SEL transits from the logic level 0 to the logic level 1, that is, when the new data fetch period TK ends, the data buffer 20a (20b) has its own new data register 21a (21b). The setting data SDa (SDb) stored in the memory, that is, the newly written setting data is output to the PDV 200. For example, as shown in FIG. 4, the data buffer 20a is configured to use the new setting written in the new data register 21a in place of [55] h that is the existing setting data stored and held in the existing data register 23a. The data [AA] h is output to the PDV 200 as setting data PDa. Further, in synchronization with the output timing of the setting data PDa, the data buffer 20b stores and holds in the new data register 21b instead of [CC] h which is the existing setting data stored and held in the existing data register 23b. [33] h, which is the new setting data, is output to the PDV 200 as setting data PDb. Therefore, the new setting data PDa and PDb sequentially supplied to the data output circuit 100 as serial data are output to the PDV 200 simultaneously (simultaneously) as shown in FIG. Here, as shown in FIG. 4, after the new data capture period TK, while the output selection signal SEL at the logic level 1 is being supplied, the setting data SDa (from the new data register 21a (21b) is sent. SDb) is supplied to the existing data register 23a (23b) via the selector 22a (22b). As a result, the existing data register 23a (23b) of the data buffer 20a (20b) receives the setting data SDa (SDb) stored in the new data register 21a (21b) as shown in FIG. Is taken in at the timing of and stored. That is, the new setting data SDa (SDb) newly written in the new data register 21a (21b) is stored and held in the existing data register 23a (23b), so that the above-described existing setting data TDa (TDb) and It becomes.

  As described above, the data output circuit 100 according to the present invention receives the serial data signal (SDS) in which the first data piece (PDa) and the second data piece (PDb) are sequentially arranged, and from this serial data signal. As described below, the first and second data pieces are fetched and synchronized to be output to the PDV 200. That is, first, the first new data register (21a) fetches the first data piece from the serial data signal and stores it as the first new data piece (SDa), and the second new data register (21b) The second data piece is taken from the serial data signal and stored as a second new data piece (SDb). Here, the first existing data register (23a) takes in the first new data piece and stores it as the first existing data piece (TDa), and the second existing data register (23b) stores the second new data piece. The piece is fetched and stored as a second existing data piece (TDb). At this time, the output control unit (10, 30, 24a, 24b) waits until the second new data register finishes taking in the second data piece after the first new data register starts taking in the first data piece. During the new data acquisition period (TK), the first and second existing data pieces are stopped from being taken in by the first and second existing data registers, and the first and second existing data pieces are changed to the first and second data. Output as a piece. Then, after the end of the new data capturing period, the output control unit outputs the first and second new data in synchronization as the first and second data pieces.

  In short, the data output circuit 100 receives a first data piece (PDa) and a second data piece (PDb) for setting the first and second operation parameters of the PDV 200 in order during a new data acquisition period ( TK) continues to output the existing setting data that has been output to the PDV 200 until that time, that is, the first and second existing data pieces, to the PDV 200. Then, after the end of the new data acquisition period, the new first data piece (PDa) and the second data piece (PDb) acquired as described above are synchronously output to the PDV 200.

  Thereby, since the first and second operation parameters are simultaneously set in the PDV 200, the temporary unstable operation of the PDV 200 due to the sequential setting of each operation parameter is avoided. Therefore, it is possible to shorten the time required for the PDV 200 to transition to a desired operation state reflecting all settings according to the setting change, and to increase the operation efficiency of the entire system.

  When only one of the setting data PDa and PDb is set for the PDV 200, only one of the setting data may be supplied to the data output circuit 100 by the serial data signal SDS. For example, when only the setting data PDa is changed, the controller 300 supplies the data output circuit 100 with a serial data signal SDS composed of a series of blocks B1, B2a, and B3 shown in FIG. On the other hand, when only the setting data PDb is changed, the controller 300 supplies the data output circuit 100 with a serial data signal SDS composed of a series of blocks B1, B2b and B3 shown in FIG.

  Therefore, according to the data output circuit 100, when only a part of the setting data is changed, each setting data is parallelized using a shift register having a bit length corresponding to the total number of bits of all the setting data PDa and PDb. The processing time can be shortened as compared with the case where a configuration in which data is converted and output is employed. In other words, when such a shift register is used, even when only a part of the setting data is changed, other setting data must be inserted in a dummy and sequentially written in the shift register. Compared to the data output circuit 100, the processing time becomes longer.

  In addition, the data output circuit 100 shown in FIG. 1 can simultaneously supply the setting data PDa and PDb to the PDV 200 regardless of the total bit length of the setting data PDa and PDb. Therefore, according to the data output circuit 100, simultaneous output is possible as compared with the case where the setting data PDa and PDb are supplied to the PDV 200 by so-called software, in which the bit length that can be accessed simultaneously is limited by the bit length of the data bus. It is possible to increase the total bit length of possible setting data or the number of accessible operation parameters.

  In the above embodiment, as shown in FIG. 4, after the setting data PDa and PDb are synchronously output simultaneously (simultaneously), the new setting data SDa (21b) stored in the new data register 21a (21b) By copying SDb) to the existing data register 23a (23b), this is handled as existing setting data TDa (TDb). However, by stopping such copying, the existing setting data, that is, the previous setting data may be stored and held in the existing data registers 23a and 23b as they are. Thereby, the newest data register 21a (21b) stores and holds the latest setting data as SDa (SDb), and the existing data register 23a (23b) stores and holds the previous setting data as TDa (TDb). Will be.

  FIG. 5 is a block diagram showing a modification of the data output circuit 100 made in view of this point. In the configuration shown in FIG. 5, the hold register 40 and the AND gate 50 are newly provided, and other configurations except that the serial interface unit 11 is adopted instead of the serial interface unit 10 are the same as those shown in FIG. 1. Are the same. Therefore, the operation will be described below with a focus on the serial interface unit 11, the hold register 40, and the AND gate 50.

  In FIG. 5, the serial interface unit 11 performs the following operation in synchronization with the logic level 0 enable signal EN, the serial data signal SDS, and the clock signal CLK supplied from the controller 300 via the external terminals.

  That is, first, the serial interface unit 11 sequentially captures the data bit series DS, the address bit series AS, the write / read control bit WRB, and the write execution bit LB in the serial data signal SDS in synchronization with the clock signal CLK. . Then, the serial interface unit 11 converts the data bit series DS described above into parallel data, and supplies this to the data buffers 20a and 20b, the output control register 30 and the hold register 40 as write data QD. Further, the serial interface unit 11 converts the address bit series AS described above into parallel address data, and one of the data buffers 20a and 20b, the output control register 30 and the hold register 40 designated by the address data. On the other hand, a write signal for writing the write data QD is supplied at the fetch timing of the write execution bit LB. That is, the serial interface unit 11 supplies the write signal W1 to the data buffer 20a when the address data indicates the data buffer 20a, and the write signal W2 when the address data indicates the data buffer 20b. 20b. The serial interface unit 10 supplies the write signal Wc to the output control register 30 when the address data indicates the output control register 30, and the write signal Wd when the address data indicates the hold register 40. This is supplied to the hold register 40.

  The hold register 40 fetches and stores the write data QD at the edge timing of the clock signal CLK only when the write signal Wd is supplied from the serial interface unit 11. The write data QD written to the hold register 40 in response to the write signal Wd is hold control data HD. The hold control data HD is a hold command for storing the existing setting data in the existing data register 23a (23b) as the previous setting data even after the end of the new data capture period TK, or canceling this hold command. Indicates a hold release command. The hold register 40 supplies the AND gate 50 with a hold gate signal HG of logic level 1 when the written data QD written indicates a hold command, and when it indicates a hold release command.

  While the hold gate signal HG of logic level 0 indicating the hold release command is supplied, the AND gate 50 uses the output selection signal SEL sent from the output control register 30 as the output selection signal SL as it is, and the data buffer 20a and 20b is supplied to selectors 22a and 22b. On the other hand, while the logic level 1 hold gate signal HG indicating the hold command is being supplied, the AND gate 50 outputs the logic level 0 output selection signal SL to the selector 22a regardless of the logic level of the output selection signal SEL. 22b.

  The operation in the configuration shown in FIG. 5 will be described below.

  In order to operate the data output circuit 100 having the configuration shown in FIG. 5, the controller 300 receives the serial data signal SDS represented by the blocks B4 and B5 shown in FIG. 6 in addition to the blocks B1 to B3 shown in FIG. This is supplied to the output circuit 100. For example, as shown in FIG. 7, the controller 300 supplies the data output circuit 100 with a serial data signal SDS composed of a series of blocks B4, B1, B2a, B2b, B5, B3, and B1. The block B4 shown in FIG. 6 designates a data bit series DS based on [00] h hold control data HD indicating a hold release command, an address bit series AS based on address data designating the hold register 40, and a write process. A write / read control bit WRB to be executed, and a write execution bit LB for urging the execution of processing. Also, the block B5 shown in FIG. 6 designates a data bit series DS based on [01] h hold control data HD indicating a hold command, an address bit series AS based on address data designating the hold register 40, and a writing process. It consists of a write / read control bit WRB and a write execution bit LB that prompts the execution of processing.

  In FIG. 7, first, when the block B4 described above is supplied as the serial data signal SDS, the hold register 40 of the data output circuit 100 takes in the value [00] h indicated by the hold control data HD, and sets this value. A corresponding logic level 0 hold gate signal HG is supplied to the AND gate 50. As a result, the output selection signal SEL sent from the output control register 30 is supplied to the selectors 22a and 22b of the data buffers 20a and 20b as it is as the output selection signal SL via the AND gate 50. That is, during this time, the data output circuit 100 shown in FIG. 5 has substantially the same configuration as the data output circuit 100 shown in FIG. Therefore, as shown in FIG. 7, when the serial data signal SDS of the series of blocks B1, B2a, and B2b is supplied thereafter, new data registers 21a and 21b of the data buffers 20a and 20b are provided as in FIG. Then, new setting data SDa (for example, [AA] h) and SDb (for example, [33] h) are sequentially taken in and stored. During this time, the existing setting data TDa (for example, [55] h) is stored and held in the existing data register 23a of the data buffer 20a, and the existing setting data TDb ( For example, it is assumed that [CC] h) is stored and held.

  When the serial data signal SDS representing the block B5 is subsequently supplied to the block B2b, the hold register 40 of the data output circuit 100 takes in the value [01] h indicated by the hold control data HD. A hold gate signal HG having a logic level 1 corresponding to is supplied to the AND gate 50. As a result, the AND gate 50 is in a state of supplying the output selection signal SL of the logic level 0 to the selectors 22a and 22b of the data buffers 20a and 20b irrespective of the output selection signal SEL sent from the output control register 30. Therefore, while the hold gate signal HG is at the logic level 1, the existing data register 23a (23b) of the data buffer 20a (20b) receives the new setting data SDa (SDb) sent from the new data register 21a (21b). ) Is stopped. Therefore, during the period in which the hold gate signal HG is at the logic level 1, as shown in FIG. 7, the existing data register 23a continues to store and hold the existing setting data TDa (eg, [55] h). The data register 23b continues to store and hold the existing setting data TDb (for example, [CC] h).

  Then, as shown in FIG. 7, when the serial data signal SDS representing the block B3 is supplied, the output control register 30 takes in the value [01] h indicated by the output control data OD and corresponds to this value. A logic level 1 output selection signal SEL is supplied to the data buffers 20a and 20b. As a result, the data buffer 20a is stored in the new data register 21a in place of the existing setting data (for example, [55] h) stored and held in the existing data register 23a, as shown in FIG. New setting data (for example, [AA] h) is output to the PDV 200 as the first setting data PDa. Further, simultaneously with the operation of the data buffer 20a, the data buffer 20b is replaced with new setting data (for example, [CC] h) stored and held in the existing data register 23b as shown in FIG. The new setting data (eg, [33] h) stored in the data register 21b is output to the PDV 200 as the second setting data PDb.

  Then, as shown in FIG. 7, when the serial data signal SDS representing the block B1 is supplied, the output control register 30 of the data output circuit 100 takes in the value [00] h indicated by the output control data OD, A logic level 0 output selection signal SEL corresponding to this value is supplied to the data buffers 20a and 20b. As a result, the data buffer 20a is stored and held in the existing data register 23a instead of the new setting data (for example, [AA] h) stored in the new data register 21a, as shown in FIG. Existing setting data (for example, [55] h) is output to the PDV 200 as the first setting data PDa. Further, simultaneously with the operation of the data buffer 20a, the data buffer 20b replaces the new setting data (for example, [33] h) stored in the new data register 21b with the existing data as shown in FIG. The existing setting data (for example, [CC] h) stored and held in the register 23b is output to the PDV 200 as the second setting data PDb.

  As described above, according to the data output circuit shown in FIG. 5, after the operation parameter of the PDV 200 is changed by the simultaneous output of the new setting data PDa and PDb, only the processing based on the block B1 is executed, and the previous setting data TDa. And the operating parameter setting state by TDb. Therefore, in returning each setting data to the previous value, according to the configuration shown in FIG. 5, after changing the operation parameter, the series of processes based on the blocks B2a to B3 are executed again to change the setting data to the previous value. The processing time can be shortened as compared with the case of returning to the value.

  In the above embodiment, the operation of the data output circuit according to the present invention has been described by taking as an example the case where two setting data PDa and PDb are output to the PDV 200 as operation parameters for two systems of the PDV 200. The same applies to the case where three or more setting data PDs are output. Further, the data output circuit 100 and the PDV 200 may be formed on the same semiconductor chip.

  FIG. 8 is a block diagram showing a configuration of a PLL device including the data output circuit 100 made in view of such a point. The PLL device shown in FIG. 8 has a PLL synthesizer 2000 formed as a PDV. A PLL synthesizer 2000 includes a reference counter (hereinafter referred to as an RF counter) 201, a phase frequency detection circuit 202 as a phase comparator, a charge pump circuit 203, a loop filter 204, a VCO (Voltage controlled oscillator) 205, and a frequency divider circuit 206. Become.

  The RF counter 201 supplies a reference oscillation signal RC obtained by dividing the frequency of the reference oscillation signal REF supplied via the external terminal to 1 / R (R is a natural number) to the phase frequency detection circuit 202. Note that “R” for determining the frequency division ratio in the RF counter 201 is the frequency division number specified by the setting data PDd supplied from the data output circuit 100. The phase frequency detection circuit 202 detects a phase difference between the reference oscillation signal RC and the frequency division signal DIV supplied from the frequency division circuit 206. At this time, if the phase of the frequency-divided signal DIV is delayed with respect to the reference oscillation signal RC, the phase frequency detection circuit 202 has a phase difference signal UP having a logic level 1 pulse width corresponding to the phase difference between the two. Is supplied to the charge pump circuit 203. On the other hand, when the phase of the divided signal DIV is advanced with respect to the reference oscillation signal RC, the phase frequency detection circuit 202 outputs the phase difference signal DN having a pulse width of logic level 1 corresponding to the phase difference between the two. The charge pump circuit 203 is supplied.

  When the phase difference signal UP of logic level 1 is supplied, the charge pump circuit 203 supplies a positive charge pump output current to the output line L1, thereby increasing the voltage on the output line L1. On the other hand, when the phase difference signal DN of logic level 1 is supplied, the charge pump circuit 203 supplies the negative charge pump output current to the output line L1, thereby reducing the voltage on the output line L1. Let Note that the charge pump output current sent out by the charge pump circuit 203 has a charge pump current value CI designated by the setting data PDe supplied from the data output circuit 100. That is, the charge pump circuit 203 generates a positive or negative charge pump output current having a charge pump current value CI specified by the setting data PDe, and supplies this to the output line L1. With the above-described operation, the charge pump circuit 203 generates the phase difference voltage FV corresponding to the phase difference between the reference oscillation signal RC and the divided signal DIV on the output line L 1, and supplies this to the loop filter 204. The loop filter 204 smoothes the phase difference voltage FV to generate a control voltage CV from which switching noise associated with the switching operation in the charge pump circuit 203 is removed, and supplies this to the VCO 205.

  The VCO 205 generates an oscillation signal FIN having a frequency corresponding to the control voltage CV, supplies it to the frequency divider circuit 206, and outputs it externally. Note that the free-running oscillation frequency of the VCO 205 is the free-running oscillation frequency ff specified by the setting data PDf supplied from the data output circuit 100.

  The frequency dividing circuit 206 includes a dual modulus prescaler (hereinafter referred to as DMP) 206a, a program counter (hereinafter referred to as PC counter) 206b, and a swallow counter (hereinafter referred to as SW counter) 206c. The DMP 206a switches the frequency division ratio from 1 / P to 1 / (P + 1) or 1 / (P + 1) to 1 / P (P is a natural number) in accordance with the frequency division switching signal CH supplied from the SW counter. A divided oscillation signal PS obtained by dividing the oscillation signal FIN by the division ratio is supplied to the PC counter 206b and the SW counter 206c. The “P” that determines the frequency division ratio in the DMP 206 a is the frequency division number specified by the setting data PDa supplied from the data output circuit 100. The PC counter 206b supplies a signal obtained by dividing the frequency-divided oscillation signal PS by 1 / N (N is a natural number) to the phase frequency detection circuit 202 as the frequency-divided signal DIV, and also outputs the frequency-divided signal DIV. A start signal STA is generated at the timing of the rising edge (or falling edge) and supplied to the SW counter 206c. In the PC counter 206b, “N” for determining the frequency division ratio is the frequency division number specified by the setting data PDb supplied from the data output circuit 100. The SW counter 206c resets the count number to 0 in response to the start signal STA, and counts the number of pulses of the divided oscillation signal PS therefrom. At this time, when the count number reaches the count number A specified by the setting data PDc supplied from the data output circuit 100, the SW counter 206c stops counting the number of pulses as described above and also performs the frequency division described above. A switching signal CH is generated and supplied to the DMP 206a.

  With the above-described configuration, the frequency dividing circuit 206 supplies the phase frequency detection circuit 202 with the frequency divided signal DIV obtained by dividing the oscillation signal FIN by 1 / (N * P + A).

  On the other hand, the data output circuit 100 shown in FIG. 8 is newly provided with data buffers 20c to 20f for fetching and outputting the setting data PDc to PDf, and a serial interface unit 10a instead of the serial interface unit 10 described above. Except for the point that is adopted, the other configuration is the same as that shown in FIG. Note that the internal configurations of the data buffers 20a to 20f shown in FIG. 8 are all the same as the internal configuration of the data buffer 20a or 20b shown in FIG.

  Here, when all the setting data PDa to PDf described above are changed, serial data obtained by sequentially inserting the blocks B2c to B2f shown in FIG. 9 between the block B2b and the block B5 shown in FIG. The signal SDS is supplied to the data output circuit 100 shown in FIG. At this time, when the block B2c is supplied as the serial data signal SDS, the serial interface unit 10a receives the write signal W3 from the data buffer 20c because the address data indicated by the address bit series AS indicates the data buffer 20c. To supply. Next, when the block B2d is supplied as the serial data signal SDS, the serial interface unit 10a sends the write signal W4 to the data buffer 20d because the address data indicated by the address bit series AS indicates the data buffer 20d. To supply. Next, when the block B2e is supplied as the serial data signal SDS, the serial interface unit 10a sends the write signal W5 to the data buffer 20e because the address data indicated by the address bit series AS indicates the data buffer 20e. To supply. When the block B2f is supplied as the serial data signal SDS, the serial interface unit 10a sends the write signal W6 to the data buffer 20f because the address data indicated by the address bit series AS indicates the data buffer 20f. Supply.

  Therefore, according to the series of blocks B2a to B2f in the serial data signal SDS, the data buffer 20a is set data PDa, 20b is PDb, 20c is PDc, 20d is PDd, 20e is PDe, 20f is PDf, and 20f is PDf sequentially and individually Captured and stored in each new data register. During the new data fetch period TK of the setting data PDa to PDf, each of the data buffers 20a to 20f stores the existing data stored and held in the respective existing data registers, that is, the previous setting data. Output to the PLL synthesizer as PDf. Then, according to the block B3 in the serial data signal SDS, the data buffers 20a to 20f simultaneously output new setting data stored in the respective new data registers to the PLL synthesizer as setting data PDa to PDf. is there.

  In the above embodiment, the operation of the data output circuit 100 has been described by taking as an example the case where all of the six setting data PDa to PDf are changed. However, only one of these PDa to PDf, or five or less. It is also possible to change only a plurality. For example, when only PDc and PDe among the six setting data PDa to PDf are changed, a series in which the blocks B2c and B2e shown in FIG. 9 are arranged in order between the blocks B1 and B3 shown in FIG. The inserted serial data signal SDS may be supplied to the data output circuit 100.

10 Serial interface units 20a and 20b Data buffers 21a and 21b New data registers 23a and 23b Existing data registers 24a and 24b Output selector 30 Output control register 100 Data output circuit 200 PDV

Claims (6)

A data output circuit for fetching and outputting the first and second data pieces from a serial data signal in which a first data piece and a second data piece are sequentially arranged;
A first new data register that takes in the first data piece from the serial data signal and stores it as a first new data piece;
A first existing data register that takes in the first new data piece stored in the first new data register and stores it as a first existing data piece;
A second new data register that captures the second data piece from the serial data signal and stores it as a second new data piece;
A second existing data register that takes in the second new data piece stored in the second new data register and stores it as a second existing data piece;
During the new data capture period from when the first new data register starts capturing the first data piece until the second new data register finishes capturing the second data fragment, Stop the fetching of the first and second new data pieces by the second existing data register, and output the first and second existing data pieces as the first and second data pieces, An output control unit that outputs the first and second new data simultaneously as the first and second data pieces after completion; The serial data signal includes a first output control data piece at a time point preceding the first data piece, and a second output control data piece at a time point subsequent to the second data piece. And
The output control unit
The first and second output control data pieces are acquired from the serial data signal and stored, and the period from the acquisition of the first output control data piece to the acquisition of the second output control data piece is the new data acquisition. The output selection signal indicating the existing data output command is generated during the new data capturing period, and the output selection signal indicating the new data output command is generated after capturing the second output control data piece. An output control register to
A first output selector for selecting one of the first new data piece and the first existing data piece and outputting it as the first data piece;
A second output selector that selects one of the second new data piece and the second existing data piece and outputs it as the second data piece;
The first and second existing data registers stop capturing the first and second new data pieces when the output selection signal indicates the existing data output command;
The first and second output selectors output the first and second existing data pieces as the first and second data pieces when the output selection signal indicates the existing data output command, while the output When the selection signal indicates the new data output command, the first and second output selectors replace the first and second existing data pieces with the first and second new data instead of the first and second existing data pieces. 2. The data output circuit according to claim 1, wherein the data output circuit outputs the data synchronously as a piece. The serial data signal includes a hold control data piece at a time point that follows the second data piece and precedes the second output control data piece,
The output control unit includes a hold register that captures and stores the hold control data piece from the serial data signal, and sends a hold gate signal in response to the capture of the hold control data piece,
The first and second existing data registers stop capturing the first and second new data pieces continuously after the end of the new data capturing period while the hold gate signal is being transmitted. The data output circuit according to claim 2 . The first and second new data registers, the first and second existing data registers, the output control register, the hold register, and the output control unit operate in synchronization with an externally supplied clock signal. The data output circuit according to claim 3 . A VCO that generates an oscillation signal having a frequency according to a control voltage, a frequency dividing circuit that generates a frequency-divided signal obtained by dividing the oscillation signal, a phase comparator that detects a phase difference between the frequency-divided signal and a reference oscillation signal, A PLL circuit comprising a charge pump for applying an output current to the first line over a period according to the phase difference, and a loop filter for generating the control voltage by smoothing the voltage on the first line;
The first and second data pieces are fetched from a serial data signal in which a first data piece indicating a frequency division ratio of the frequency divider circuit and a second data piece indicating a current value of the output current are sequentially arranged. A PLL device including a data output circuit for outputting to the PLL circuit,
The data output circuit takes in the first data piece from the serial data signal and stores it as a first new data piece;
A first existing data register that takes in the first new data piece stored in the first new data register and stores it as a first existing data piece;
A second new data register that captures the second data piece from the serial data signal and stores it as a second new data piece;
A second existing data register that takes in the second new data piece stored in the second new data register and stores it as a second existing data piece;
During the new data capture period from when the first new data register starts capturing the first data piece until the second new data register finishes capturing the second data fragment, Stop the fetching of the first and second new data pieces by the second existing data register, and output the first and second existing data pieces as the first and second data pieces, An output control unit that outputs the first and second new data synchronously as the first and second data pieces after completion. A data output method for fetching and outputting the first and second data pieces from a serial data signal in which a first data piece and a second data piece are sequentially arranged,
The first data piece is taken from the serial data signal and stored in the first new data register as a first new data piece, and subsequently the second data piece is taken from the serial data signal and used as the second new data piece. Store in the second new data register,
The first new data piece stored in the first new data register is fetched and stored in the first existing data register as a first existing data piece, and the first new data register stored in the second new data register is stored. 2 Take in a new data piece and store it in the second existing data register as a second existing data piece,
During the new data capture period from when the first new data register starts capturing the first data piece until the second new data register finishes capturing the second data fragment, Stop the fetching of the first and second new data pieces by the second existing data register, and output the first and second existing data pieces as the first and second data pieces, A data output method comprising: outputting the first and second new data simultaneously as the first and second data pieces after completion.

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