JP6214085B2 - Amplifier circuit - Google Patents

Description

  The present invention relates to an amplifier circuit, for example, an amplifier circuit that controls a gate bias voltage according to a drain idle current.

  In recent mobile phone base stations and the like, a high-output and high-efficiency high-frequency amplifier circuit is required. A high-frequency amplifier circuit using a nitride semiconductor FET (Field Effect Transistor) such as GaN instead of an amplifier circuit using silicon or GaAs has begun to be used. An amplifier circuit using a nitride semiconductor is capable of high voltage operation and high current density operation, and can select a substrate with high thermal conductivity. Thus, an amplifier circuit using a nitride semiconductor is excellent as a high-output high-frequency amplifier circuit.

  On the other hand, in particular, in an amplifier circuit using a nitride semiconductor, it is known that the drain idle current fluctuates due to, for example, a stress that inputs a large power. Here, the drain idle current refers to a current that flows through the drain without inputting a high-frequency signal to the gate terminal. This phenomenon is called drain idle current drift. It is known that when the drain idle current drifts, the gain decreases and / or the distortion characteristics deteriorate. Patent Document 1 describes a technique for suppressing a decrease in gain or distortion characteristics by controlling a gate bias voltage when a drain idle current drift occurs in an amplifier circuit using a nitride semiconductor. ing.

JP2013-9200A

  However, when a drain idle current drift (hereinafter also referred to as a drain current drift) occurs, noise is generated in the control circuit that controls the gate bias voltage. If noise is superimposed on the gate bias voltage, the distortion characteristics may be degraded. On the other hand, if a noise cut capacitor is used to remove noise, high-speed feedback to the gate bias voltage cannot be performed.

  The present invention has been made in view of the above-described problems, and enables high-speed feedback to the gate bias voltage when the drain idle current drifts, and suppresses noise from being superimposed on the gate bias voltage. With the goal.

  The present invention includes a power amplifier including an FET in which a high-frequency signal is input to a gate terminal, a detection unit that detects a drain idle current of the FET and outputs a first voltage corresponding to the drain idle current, and the first A generating unit that generates a second voltage having a fixed value independently of the voltage; and an output unit that outputs a bias voltage to the gate terminal of the FET using the higher one of the first voltage and the second voltage as an output voltage. And an amplifier circuit.

  In the above configuration, the output section outputs an output node that outputs the output voltage, a first output circuit that outputs the first voltage to the output node, and a second output that outputs the second voltage to the output node. And a circuit.

  In the above configuration, a resistor having one end connected to the output node and the other end connected to the power supply of the second voltage is provided, and the first output circuit has a resistance of the resistor when the first voltage is higher than the output voltage. The output impedance is lower than the first voltage, the output impedance is higher than the resistance value when the output voltage is higher than the first voltage, and the second output circuit is lower than the resistance value when the second voltage is higher than the output voltage. An output impedance is obtained, and when the output voltage is higher than the second voltage, the output impedance is higher than the resistance value.

  In the above configuration, a resistor having one end connected to the output node and the other end connected to the power source of the second voltage, the first output circuit has the first voltage input to a positive input terminal, and the output terminal A first differential amplifier circuit connected to a negative input terminal and an output terminal of the output unit via a first diode in a forward direction; the second output circuit receives the second voltage at a positive input terminal; The output terminal may include a second differential amplifier circuit connected to the negative input terminal and the output terminal of the output unit via the second diode in the forward direction.

  In the above configuration, the drain idle current is a drain idle current of an FET included in a main amplifier of a Doherty amplifier circuit, and the output voltage is a gate bias voltage of an FET included in the main amplifier. it can.

  In the above configuration, the drain idle current is a drain idle current of an FET included in the main amplifier in a Doherty amplifier circuit including a main amplifier and a peak amplifier, and the output voltage is an FET voltage included in the main amplifier. A configuration with a gate bias voltage may be employed.

  The said structure WHEREIN: It can be set as the structure which comprises the envelope controller which controls the drain voltage of the said power amplifier.

  According to the present invention, when a drain idle current drift occurs, high-speed feedback to the gate bias voltage is possible, and superposition of noise to the gate bias voltage can be suppressed.

1 is a cross-sectional view of an FET used in Example 1. FIG. FIG. 2 is a circuit diagram of an amplifier circuit according to the first embodiment. FIG. 3 is a circuit diagram of an amplifier circuit according to Comparative Example 1. FIG. 4 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example when there is no drain current drift. FIG. 5 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example in the case where there is a drain current drift. FIG. 6 is a schematic diagram showing the drain current and the like with respect to time in Comparative Example 1, and is an example when there is a drain current drift. FIG. 7 is a circuit diagram of an amplifier circuit according to the second embodiment. FIG. 8 is another example of the output unit. FIG. 9 is a block diagram of an amplifier circuit according to the third embodiment. FIG. 10 is a block diagram of an amplifier circuit according to the fourth embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a cross-sectional view of an FET used in Example 1. FIG. As shown in FIG. 1, a buffer layer 42, an electron transit layer 44, an electron supply layer 46, and a cap layer 48 are sequentially formed on a substrate 40 to form a nitride semiconductor layer 50. The substrate 40 is a substrate made of, for example, SiC, sapphire, or Si. The buffer layer 42 is an AlN layer having a film thickness of 300 nm, for example. The electron transit layer 44 is a GaN layer having a film thickness of 1000 nm, for example. The electron supply layer 46 is, for example, an n-type AlGaN layer having a thickness of 20 nm. The cap layer 48 is, for example, an n-type GaN layer having a thickness of 5 nm. A gate electrode 54, a source electrode 52 and a drain electrode 56 are formed on the nitride semiconductor layer 50. The gate electrode 54 is disposed between the source electrode 52 and the drain electrode 56 on the upper surface of the nitride semiconductor layer 50. The source electrode 52 and the drain electrode 56 are formed of, for example, a Ta layer and an Al layer from the nitride semiconductor layer 50 side. The gate electrode 54 is formed of, for example, a Ni layer and an Au layer from the nitride semiconductor layer 50 side. An insulating film 58 made of, for example, a silicon nitride film is formed on the nitride semiconductor layer 50 so as to cover the gate electrode 54. The nitride semiconductor layer 50 is not limited to the above layers. For example, InGaN, AlInGaN, InAlN, or the like can be used as the nitride semiconductor layer 50.

  For example, in the FET using the nitride semiconductor layer 50 shown in FIG. 1, different materials of the substrate 40 and the nitride semiconductor layer 50 are bonded. For this reason, a deep electron trap is formed in the nitride semiconductor layer 50 near the bonding surface or the bonding surface. The electron trap captures or emits electrons, thereby causing a drain current drift. Deep electron traps are thought to be formed by vacancies or impurities resulting from the bonding of dissimilar materials. Thus, the drain current drift is a phenomenon peculiar to the semiconductor device using the nitride semiconductor layer 50. The following embodiments are not limited to an amplifier circuit using a nitride semiconductor layer, but can be applied to an amplifier circuit having a change with time.

  FIG. 2 is a circuit diagram of an amplifier circuit according to the first embodiment. The amplifier circuit 100 mainly includes a power amplifier 11, a detection unit 12, an output unit 14, and a generation unit 16. The power amplifier 11 includes an FET 10 made of a nitride semiconductor. The source terminal S of the FET 10 is grounded. A high frequency signal is input to the gate terminal G from the input terminal Tin. A gate bias voltage Vg is applied to the input terminal Tin from the output unit 14 via the choke inductor L1. A terminating capacitor C1 is connected between the node between the inductor L1 and the output unit 14 and the ground.

  The drain terminal D of the FET 10 outputs an amplified high frequency signal to the output terminal Tout. A drain bias voltage VD is applied to the output terminal Tout via the choke inductor L2. A noise removing capacitor C2 is connected between the node between the inductor L2 and the drain power supply and the ground. A resistor R1 is connected in series between the inductor L2 and the drain power supply.

  The detector 12 detects the drain idle current of the FET 10 as the drain current Id from the potential difference between both ends of the resistor R1. The detection unit 12 generates a voltage Va (first voltage) corresponding to the drain current Id detected using the reference voltage VR, and outputs the voltage Va to the output unit 14.

  The generation unit 16 generates a fixed value voltage VREF (second voltage) independently of the voltage Va. The generation unit 16 includes a power supply 17 and a noise removing capacitor C3. The power supply 17 generates a fixed voltage VREF. The capacitor C3 is connected between the output of the power supply 17 and the ground.

  The output unit 14 outputs the higher one of the input voltage Va and voltage VREF to the gate terminal G of the FET 10 as an output voltage. The output voltage is output as the gate bias voltage Vg of the FET 10.

  Comparative Example 1 will be described for comparison with Example 1. FIG. 3 is a circuit diagram of an amplifier circuit according to Comparative Example 1. As illustrated in FIG. 3, the amplifier circuit 110 includes a control unit 30 and an output unit 32. When the detected drain current Id is smaller than a predetermined value, the control unit 30 outputs a voltage Vb corresponding to the drain current Id to the output unit 32. On the other hand, when the detected drain current Id is greater than or equal to a predetermined value, the fixed value voltage VR is output to the output unit 32 as the voltage Vb. The output unit 32 applies the output voltage Vb of the control unit 30 to the gate terminal G of the FET 10 of the power amplifier 11 as the gate bias voltage Vg. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  FIG. 4 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example when there is no drain current drift. Referring to FIG. 4, drain current Id corresponds to a drain idle current. The threshold voltage Vth is the threshold voltage of the FET 10. The voltage Va, the voltage VREF, and the gate bias voltage Vg are DC component voltages that are sufficiently low in frequency with respect to the high-frequency signal. At time t0, the drain current Id, the threshold voltage Vth, the voltage Va, the voltage VREF, and the gate bias voltage Vg are, for example, 150 mA, −2.5 V, −2 V, −2 V, and −2 V, respectively.

  A high-power high-frequency signal is input to the input terminal Tin between times t1 and t2. Between times t1 and t2, the drain current Id increases because the direct current component of the drain current increases. For this reason, the output voltage Va of the detection part 12 becomes -2.3V, for example. Since no drain current drift occurs, the threshold voltage Vth is constant at −2.5V. The voltage VREF is a fixed value of −2V. The gate bias voltage Vg is −2V. Since the drain current Id has not drifted after time t2, each value returns to the value at time t0.

  In FIG. 4, the drain current Id increases between times t1 and t2 when a high-power signal is input. For this reason, the output voltage Va of the detection part 12 changes from -2V to -2.3V, for example. However, the output unit 14 outputs a voltage VREF higher than the voltage Va as the gate bias voltage Vg. Therefore, the gate bias voltage Vg does not change between times t1 and t2 when a high-power signal is input. If the gate bias voltage Vg changes between times t1 and t2 when a high-power signal is input, the maximum output voltage of the amplifier circuit 100, the gain, or the error rate may be degraded. . According to the first embodiment, since the gate bias voltage Vg does not change between the times t1 and t2, it is possible to suppress a decrease in output power, a gain, an error rate, or the like of the amplifier circuit 100.

  FIG. 5 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example in the case where there is a drain current drift. Referring to FIG. 5, drain current Id corresponds to a drain idle current. The voltage Va, the voltage VREF, and the gate bias voltage Vg are DC component voltages that are sufficiently low in frequency with respect to the high-frequency signal. The drain current Id, threshold voltage Vth, voltage Va, voltage VREF, and gate bias voltage Vg from time t0 to t2 are the same as in FIG. At time t2, the high power high frequency signal is turned off. After time t2, the threshold voltage Vth becomes −2.2V, for example, due to drain current drift, and then gradually returns to −2.5V. Since the drain current Id becomes small, the detection unit 12 detects a decrease in the drain current Id and outputs, for example, −1.7 V as the output voltage Va. Since the voltage Va is higher than the voltage VREF, the output unit 14 outputs the voltage Va as the gate bias voltage Vg. Thereby, the gate bias voltage Vg is fed back so that the drain current Id of the FET 10 becomes large, and the drain current Id does not change. As the threshold voltage Vth gradually returns from −2.2 V to −2.5 V, for example, the voltages Va and Vg gradually return from −1.7 V to −2 V, for example.

  FIG. 6 is a schematic diagram showing the drain current and the like with respect to time in Comparative Example 1, and is an example when there is a drain current drift. The voltage Vb is the output voltage of the control unit 30, and the voltage Vg is the output voltage of the output unit 32. When the drain current Id is smaller than a predetermined value, the control unit 30 outputs a voltage Vb corresponding to the drain current Id to the output unit 32, and when the drain current Id is equal to or larger than the predetermined value, for example, −2V is set as a fixed voltage. Output as voltage Vb. Therefore, ideally, it is preferable to be the same as that of FIG. 5 of the first embodiment as indicated by the solid line in the drain current Id of FIG.

  However, in Comparative Example 1, the capacitance of the capacitor C1 is increased in order to remove noise generated in the control unit 30 and the like. As a result, the gate bias voltage Vg rises slowly as indicated by the broken line after time t2. For this reason, the drain current Id decreases after time t2 as indicated by a broken line.

  As described above, in Comparative Example 1, when the capacitance of the capacitor C1 is increased, noise caused by the detection unit 12, the control unit 30, and the like can be removed. For example, the capacitance of the capacitor C1 is set to several tens of nF to 1 μF. For example, when the capacitance of the capacitor C1 is 100 nF and the output resistance of the output unit 32 is 100Ω, the output delay time of the output unit 32 is 10 μs. As a result, the drain current Id decreases immediately after the time t2. Therefore, the gain reduction and / or distortion characteristics in the amplifier circuit 110 deteriorate. On the other hand, if the capacitance of the capacitor C1 is reduced, a decrease in the drain current Id can be suppressed, but noise is superimposed on the gate bias voltage Vg. Thereby, the distortion characteristic in the amplifier circuit 110 deteriorates.

  In the first embodiment, the capacitor C1 is used for terminating the inductor L1, and when the high frequency signal is about 1 GHz, the capacitance of the capacitor C1 is 10 pF to 100 pF. The generation unit 16 generates a low noise voltage VREF. For example, the noise of the voltage VREF can be suppressed by increasing the capacitance of the capacitor C3. Thereby, noise superimposed on the gate bias voltage Vg can be suppressed from time t0 to time t2 in FIG. By reducing the capacitance of the capacitor C1, feedback from the detection unit 12 and the output unit 14 can be made to respond at high speed after time t2. For example, when the capacitance of the capacitor C1 is 100 pF, the delay time of the output unit 14 can be 10 nsec. Therefore, it is possible to suppress the drain current Id from decreasing immediately after the time t2.

  Also in the first embodiment, noise generated by the detection unit 12 after time t2 cannot be removed. However, the voltage Va generated by the detector 12 is output as the gate bias voltage Vg when the drain current drift occurs. The period during which the drain current drift occurs is shorter than the entire period, and the drain current drift does not occur during the entire period. When the drain current drift does not occur, the low noise voltage VREF becomes the gate bias voltage Vg.

  According to the first embodiment, the output unit 14 outputs a bias voltage to the gate terminal G of the power amplifier 11 with the higher one of the voltage Va output from the detection unit 12 and the fixed value voltage VREF as the gate bias voltage Vg. Thus, when a drain current drift occurs, high-speed feedback to the gate bias voltage Vg is possible, and it is possible to suppress noise from being superimposed on the gate bias voltage Vg.

  A capacitor C1 (first capacitor) is connected between the output terminal of the output unit 14 and the ground (reference potential). A capacitor C3 (second capacitor) is connected between the output terminal of the generator 16 and the ground (reference potential). Capacitor C3 preferably has a larger capacitance than capacitor C1. Thereby, noise superimposed on the gate bias voltage Vg while the voltage VREF is supplied as the gate bias voltage Vg can be suppressed. The capacitor C2 is for terminating the inductor L2, and the capacitances of the capacitors C1 and C2 are approximately the same.

  FIG. 7 is a circuit diagram of an amplifier circuit according to the second embodiment. As shown in FIG. 7, in the amplifier circuit 102, the detection unit 12 includes a differential amplifier circuit 28 and resistors R11 to R14. The resistor R11 is connected between the positive input terminal of the differential amplifier circuit 28 and a node between the resistor R1 and the inductor L2. The resistor R12 is connected between the negative input terminal of the differential amplifier circuit 28 and the drain voltage VD. The resistor R13 is connected between the output terminal and the negative input terminal of the differential amplifier circuit 28. The resistor R14 is connected between the positive input terminal of the differential amplifier circuit 28 and the node between the resistors R2 and R3. The resistors R2 and R3 are directly connected between the voltage VR and the ground. When the drain current Id increases, the output voltage Va changes to the negative side, and when the drain current Id decreases, the output voltage Va changes to the positive side. The resistors R2 and R3 adjust the voltage output to the positive input terminal of the differential amplifier circuit 28 by resistance division. The voltage may be adjusted by other methods. The resistance values of the resistors R11 to R14 are set equal, for example. The amplification factor and the like of the differential amplifier circuit 22 can be changed by making the resistance values of the resistors R11 to R14 different.

  The output unit 14 includes output circuits 20 and 24 and an output node N1 to which outputs of the output circuits 20 and 24 are connected in common. The output circuit 20 includes a differential amplifier circuit 22 (first differential amplifier circuit) and a diode D1 (first diode). The output voltage Va of the detection unit 12 is input to the positive input terminal of the differential amplifier circuit 22. The anode of the diode D1 is connected to the output terminal of the differential amplifier circuit 22. The negative input terminal of the differential amplifier circuit 22 is connected to the cathode of the diode D1. That is, the output terminal of the differential amplifier circuit 22 inputs the diode D1 in the forward direction to the negative input terminal.

  The output circuit 24 includes a differential amplifier circuit 26 (second differential amplifier circuit) and a diode D2 (second diode). The output voltage VREF of the generation unit 16 is input to the positive input terminal of the differential amplifier circuit 26. The anode of the diode D2 is connected to the output terminal of the differential amplifier circuit 26. The negative input terminal of the differential amplifier circuit 26 is connected to the cathode of the diode D2. The cathode of the diode D2 outputs the output of the output circuit 24 to the node N1. That is, the output terminal of the differential amplifier circuit 26 inputs the diode D1 in the forward direction to the negative input terminal. One end of the resistor R4 is connected to the node N1, and the other end is connected to a power source having a voltage Ve lower than the voltage VREF.

  Although the output circuits 20 and 24 are voltage follower circuits, the diodes D1 and D2 are connected so that the output directions of the output circuits 20 and 24 are forward. Thereby, when the output voltage of the output circuits 20 and 24 is higher than the voltage of the node N1, the output impedance Z1 of the output circuits 20 and 24 is low. When the output voltages of the output circuits 20 and 24 are lower than the voltage at the node N1, the output impedance Z2 of the output circuits 20 and 24 becomes higher in the reverse direction of the diodes D1 and D2. The resistance value of the resistor R4 is set higher than Z1 and lower than Z2. Thus, when the voltage at the node N1 is higher than the voltage Va, the output circuit 10 cannot output current to the node N1. When the voltage at the node N1 is higher than VREF, the output circuit 24 cannot output current to the node N1. Therefore, the node N1 becomes the higher voltage of the voltages Va and VREF.

  According to the second embodiment, the output circuit 20 has an output impedance lower than the resistance value of the resistor R4 when the voltage Va is higher than the voltage of the node N1, and is higher than the resistance value of the resistor R4 when the voltage of the node N1 is higher than the voltage Va. High output impedance. The output circuit 24 has an output impedance lower than the resistance value of the resistor R4 when the voltage VREF is higher than the voltage at the node N1, and has an output impedance higher than the resistance value of the resistor R4 when the voltage at the node N1 is higher than the voltage VREF. . As a result, the output unit 14 can output a higher voltage of the voltages Va and VREF to the node N1.

  FIG. 8 is another example of the output unit. As shown in FIG. 8, the output circuit 20 includes transistors 36 and 38 and a resistor R5. The transistor 36 is a pnp bipolar transistor, and the transistor 38 is an npn bipolar transistor. The emitter of the transistor 36 is connected to a high voltage power supply via a resistor R5. A voltage Va is input to the base. The collector is connected to a low voltage power source. The emitter of the transistor 38 is connected to the node N1. The base is connected to the emitter of the transistor 36. The collector is connected to a high voltage power source. The transistor 36 is connected to the collector ground, and the output impedance from the emitter is low. The transistor 38 has a base-emitter connected in the forward direction in the direction of the node N1.

  The output circuit 24 includes transistors 37 and 39 and a resistor R6. The transistors 37 and 39 and the resistor R6 are connected in the same manner as the transistors 36 and 38 and the resistor R5 of the output circuit 20, respectively. Thus, the output circuits 20 and 24 can be formed by using two transistors.

  The output circuit 20 of FIG. 8 has an output impedance lower than the resistance value of the resistor R4 when the voltage Va is higher than the voltage of the node N1, and an output impedance higher than the resistance value of the resistor R4 when the voltage of the node N1 is higher than the voltage Va. Become. The output circuit 24 has an output impedance lower than the resistance value of the resistor R4 when the voltage VREF is higher than the voltage at the node N1, and has an output impedance higher than the resistance value of the resistor R4 when the voltage at the node N1 is higher than the voltage VREF. .

  Example 3 is an example in which the amplifier circuit according to Example 1 or 2 is applied to a Doherty amplifier circuit. FIG. 9 is a block diagram of an amplifier circuit according to the third embodiment. As illustrated in FIG. 9, the amplifier circuit 104 is a Doherty amplifier circuit including a main amplifier 60, a peak amplifier 62, ¼ wavelength phase lines 64 and 66, and a circuit 70. The input terminal Tin is electrically connected to the input of the main amplifier 60 and is electrically connected to the input of the peak amplifier 62 via the quarter wavelength phase line 66. The output terminal Tout is electrically connected to the output of the main amplifier 60 via the quarter wavelength phase line 64 and is electrically connected to the output of the peak amplifier 62. The main amplifier 60 is, for example, a class A or class AB amplifier, and always amplifies an input signal input to the input terminal Tin. The peak amplifier 62 is, for example, a class C amplifier, and amplifies the input signal when the input signal is equal to or higher than a predetermined power. Therefore, drain idle current flows through the main amplifier 60, but idle current does not flow through the peak amplifier 62. For this reason, it is mainly the main amplifier 60 that causes a drift of the drain current.

  The circuit 70 corresponds to the resistor R1, the detection unit 12, the output unit 14, and the generation unit 16 of the first embodiment. The resistor R1 and the detection unit 12 of the circuit 70 detect the drain current of the main amplifier 60. The output unit 14 and the generation unit 16 of the circuit 70 control the gate bias voltage of the main amplifier 60. Thereby, even in the Doherty amplifier circuit, it is possible to suppress a decrease in gain due to the drain current drift.

  The fourth embodiment is an example in which the amplifier circuit according to the first or second embodiment is applied to an envelope tracking system amplifier circuit. FIG. 10 is a block diagram of an amplifier circuit according to the fourth embodiment. As shown in FIG. 10, in the amplifier circuit 106, the input terminal Tin is electrically connected to the input of the power amplifier 72. The output terminal Tout is electrically connected to the output of the power amplifier 72. The envelope controller 74 controls the drain voltage of the power amplifier 72. The resistor R1 and the detection unit 12 of the circuit 70 detect the drain current of the power amplifier 72. The output unit 14 and the generation unit 16 of the circuit 70 control the gate bias voltage of the power amplifier 72.

  In the envelope tracking method, the envelope controller 74 controls the drain voltage of the power amplifier 72 at high speed in accordance with the envelope of the modulation signal (the amplitude of the modulation signal wave). When the drain voltage is changed from a high voltage (for example, 50 V) to a low voltage (for example, 10 V), the drain current drifts due to the high voltage stress, and the bias point shifts at the time of the low voltage. Therefore, by using the circuit 70, the drain current drift at the time of a low voltage can be compensated and the bias point can be kept constant. The detecting unit 12 detects a potential difference between both ends of the resistor R1. For this reason, even if the absolute value of the drain voltage changes, the detector 12 can operate in the same manner as in the first or second embodiment depending on the magnitude of the drain current.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 FET
DESCRIPTION OF SYMBOLS 11 Power amplifier 12 Detection part 14 Output part 16 Generation | occurrence | production part 20, 24 Output circuit 22, 26 Differential amplifier circuit 60 Main amplifier 62 Peak amplifier 70 Circuit 74 Envelope controller

Claims (4)

A power amplifier including a FET in which a high-frequency signal is input to the gate terminal;
Detecting a drain idle current of the FET and outputting a first voltage corresponding to the drain idle current to an output unit ;
An inductor having one end connected to the gate terminal and the other end connected to an output terminal that outputs the output voltage of the output unit;
A first capacitor connected between the other end of the inductor and a reference potential;
A generating unit that is connected to a second capacitor having a capacitance larger than that of the first capacitor and that generates a fixed second voltage independently of the first voltage;
Equipped with,
The output unit outputs the first voltage to the gate terminal via the inductor when the drain idle current drift occurs, and outputs the second voltage to the inductor when the drain idle current drift does not occur. And an output to the gate terminal . The output unit is
A first output circuit for outputting the first voltage to the output terminal ;
A second output circuit for outputting the second voltage to the output terminal ;
The amplifier circuit according to claim 1, further comprising: A resistor having one end connected to the output terminal and the other end connected to the power source of the second voltage;
The first output circuit has an output impedance lower than a resistance value of the resistor when the first voltage is higher than the output voltage, and an output impedance higher than the resistance value when the output voltage is higher than the first voltage;
The second output circuit has an output impedance lower than the resistance value when the second voltage is higher than the output voltage, and an output impedance higher than the resistance value when the output voltage is higher than the second voltage. The amplifier circuit according to claim 2. A resistor having one end connected to the output terminal and the other end connected to the power source of the second voltage;
The first output circuit has a first differential amplifier circuit in which the first voltage is input to a positive input terminal, and an output terminal is connected to a negative input terminal and an output terminal of the output unit via a first diode in a forward direction. With
In the second output circuit, the second voltage is input to the positive input terminal, and the output terminal is connected to the negative input terminal and the output terminal of the output unit via the second diode in the forward direction. The amplifier circuit according to claim 2, further comprising:

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