JP2015041998A - Amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispense with a complicated adjustment of an operating point of compensation for a drain current drift, and suppress an abnormality in compensation caused by a change in the operating point of compensation for a drain current drift due to a change in a FET characteristic.SOLUTION: An amplification circuit includes: a power amplifier 11 comprising a FET 10 having a gate terminal in which a high frequency signal is input; a detection section 12 for detecting a drain idle current of the power amplifier and outputting a first voltage depending on the drain idle current; and an output section 15 that, when the first voltage falls, generates a gate bias voltage depending on the first voltage from the first voltage in a first response time and outputs it to the gate terminal of the power amplifier, and, when the first voltage rises, generates a gate bias voltage depending on the first voltage from the first voltage in a second response time shorter than the first response time and outputs it to the gate terminal.

Description

  The present invention relates to an amplifier circuit, for example, an amplifier circuit that controls a gate bias voltage according to a drain idle current.

  In recent mobile phone base stations and the like, a high-output and high-efficiency high-frequency amplifier circuit is required. A high-frequency amplifier circuit using a nitride semiconductor FET (Field Effect Transistor) such as GaN instead of an amplifier circuit using silicon or GaAs has begun to be used. An amplifier circuit using a nitride semiconductor is capable of high voltage operation and high current density operation, and can select a substrate with high thermal conductivity. Thus, an amplifier circuit using a nitride semiconductor is excellent as a high-output high-frequency amplifier circuit.

  On the other hand, in particular, in an amplifier circuit using a nitride semiconductor, it is known that the drain idle current fluctuates due to, for example, a stress that inputs high power. Here, the drain idle current refers to a current that flows through the drain without inputting a high-frequency signal to the gate terminal. This phenomenon is called drain idle current drift. It is known that when the drain idle current drifts, the gain decreases and / or the distortion characteristics deteriorate. Patent Document 1 describes a technique for suppressing a decrease in gain or distortion characteristics by controlling a gate bias voltage when a drain idle current drift occurs in an amplifier circuit using a nitride semiconductor. ing.

JP2013-9200A

  However, in Patent Document 1, the drain current reference value for compensating for the drain idle current drift (hereinafter also referred to as the drain current draft) is subjected to complicated adjustment using a switch. In addition, when the characteristics of the nitride semiconductor FET change with temperature and / or aging, the drain current reference value for compensating the drain current drift may change, and the drain current drift may not be compensated normally. is there.

  The present invention has been made in view of the above problems, and an object of the present invention is to make it possible to suppress abnormality in drain current drift compensation.

  The present invention provides a power amplifier including a FET having a nitride semiconductor layer and a high-frequency signal input to a gate terminal, a drain idle current of the power amplifier, and a first voltage corresponding to the drain idle current A detection unit that outputs a gate bias voltage corresponding to the first voltage in a first response time from the first voltage when the first voltage drops, and outputs the gate bias voltage to the gate terminal of the power amplifier, An output unit configured to generate the gate bias voltage corresponding to the first voltage from the first voltage in a second response time shorter than the first response time when the first voltage increases, and to output the gate bias voltage to the gate terminal; And an amplifier circuit characterized by comprising:

  In the above-described configuration, the high-frequency signal may have a high power period in which power is higher than other periods, and the first response time may be shorter than the high power period.

  In the above configuration, the drain idle current is a drain idle current of an FET included in a main amplifier of a Doherty amplifier circuit, and the gate bias voltage is a gate bias voltage of an FET included in the main amplifier. Can do.

  The said structure WHEREIN: It can be set as the structure which comprises the envelope controller which controls the drain voltage of the said power amplifier.

  According to the present invention, it is possible to suppress abnormality in drain current drift compensation.

1 is a cross-sectional view of an FET used in Example 1. FIG. FIG. 2 is a circuit diagram of an amplifier circuit according to the first embodiment. FIG. 3 is a circuit diagram of an amplifier circuit according to Comparative Example 1. FIG. 4 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example when there is no drain current drift. FIG. 5 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example in the case where there is a drain current drift. FIG. 6 is a schematic diagram showing the drain current and the like with respect to time in Comparative Example 1, and is an example when there is a drain current drift. FIG. 7 is a schematic diagram showing the drain current with respect to time in Comparative Example 1. FIG. 8 is a circuit diagram of an amplifier circuit according to the second embodiment. FIG. 9A to FIG. 9C are other examples of the output unit. FIG. 10A and FIG. 10B are still another example of the output unit. FIG. 11A and FIG. 11B are still other examples of the output unit. FIG. 12 is a block diagram of an amplifier circuit according to the third embodiment. FIG. 13 is a block diagram of an amplifier circuit according to the fourth embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a cross-sectional view of an FET used in Example 1. FIG. As shown in FIG. 1, a buffer layer 42, an electron transit layer 44, an electron supply layer 46, and a cap layer 48 are sequentially formed on a substrate 40 to form a nitride semiconductor layer 50. The substrate 40 is a substrate made of, for example, SiC, sapphire, or Si. The buffer layer 42 is an AlN layer having a film thickness of 300 nm, for example. The electron transit layer 44 is a GaN layer having a film thickness of 1000 nm, for example. The electron supply layer 46 is, for example, an n-type AlGaN layer having a thickness of 20 nm. The cap layer 48 is, for example, an n-type GaN layer having a thickness of 5 nm. A gate electrode 54, a source electrode 52 and a drain electrode 56 are formed on the nitride semiconductor layer 50. The gate electrode 54 is disposed between the source electrode 52 and the drain electrode 56 on the upper surface of the nitride semiconductor layer 50. The source electrode 52 and the drain electrode 56 are formed of, for example, a Ta layer and an Al layer from the nitride semiconductor layer 50 side. The gate electrode 54 is formed of, for example, a Ni layer and an Au layer from the nitride semiconductor layer 50 side. An insulating film 58 made of, for example, a silicon nitride film is formed on the nitride semiconductor layer 50 so as to cover the gate electrode 54. The nitride semiconductor layer 50 is not limited to the above layers. For example, InGaN, AlInGaN, InAlN, or the like can be used as the nitride semiconductor layer 50.

  For example, in the FET using the nitride semiconductor layer 50 shown in FIG. 1, different materials of the substrate 40 and the nitride semiconductor layer 50 are bonded. For this reason, a deep electron trap is formed in the nitride semiconductor layer 50 near the bonding surface or the bonding surface. The electron trap captures or emits electrons, thereby causing a drain current drift. Deep electron traps are thought to be formed by vacancies or impurities resulting from the bonding of dissimilar materials. Thus, the drain current drift is a phenomenon peculiar to the semiconductor device using the nitride semiconductor layer 50. The following embodiments are not limited to an amplifier circuit using a nitride semiconductor layer, but can be applied to an amplifier circuit having a change with time.

  FIG. 2 is a circuit diagram of an amplifier circuit according to the first embodiment. The amplifier circuit 100 mainly includes a power amplifier 11, a detection unit 12, and an output unit 15. The power amplifier 11 is formed from an FET 10 made of a nitride semiconductor. The source terminal S of the FET 10 is grounded. A high frequency signal is input to the gate terminal G from the input terminal Tin. A gate bias voltage Vg is applied to the input terminal Tin from the output unit 15 via the choke inductor L1. A terminating capacitor C1 is connected between a node between the inductor L1 and the output unit 15 and the ground.

  The drain terminal D of the FET 10 outputs an amplified high frequency signal to the output terminal Tout. A drain idle voltage VD is applied to the output terminal Tout via the choke inductor L2. A noise removing capacitor C2 is connected between the node between the inductor L2 and the drain power supply and the ground. A resistor R1 is connected in series between the inductor L2 and the drain power supply.

  The detector 12 detects the drain idle current of the FET 10 as the drain current Id from the potential difference between both ends of the resistor R1. The detection unit 12 generates a voltage Va (first voltage) corresponding to the detected drain current Id using the reference voltage VR, and outputs the voltage Va to the output unit 15.

  The output unit 15 includes a first circuit 14 and a second circuit 16. The first circuit 14 generates a voltage Vb (second voltage) from the voltage Va in the first response time when the voltage Va decreases, and has a second response time faster than the first response time when the voltage Va increases. In response, the voltage Vb is generated from the voltage Va. The second circuit 16 outputs the voltage Vb to the gate terminal G of the FET 10 as the gate bias voltage Vg.

  Comparative Example 1 will be described for comparison with Example 1. FIG. 3 is a circuit diagram of an amplifier circuit according to Comparative Example 1. As illustrated in FIG. 3, the amplifier circuit 110 includes a control unit 30, an output unit 32, and a switch 34. When the detected drain current Id is smaller than the reference value, the control unit 30 outputs a voltage Vb corresponding to the drain current Id to the output unit 32. On the other hand, when the detected drain current Id is greater than or equal to the reference value, the fixed value voltage VR is output to the output unit 32 as the voltage Vb. The output unit 32 applies the output voltage Vb of the control unit 30 to the gate terminal G of the FET 10 of the power amplifier 11 as the gate bias voltage Vg. The switch 34 selects either the output of the output unit 32 or the voltage VR and outputs it to the gate terminal G of the FET 10. The switch 18 applies the voltage VR to the gate terminal G in order to adjust the reference value of the drain current when the initial adjustment of the amplifier circuit 110 or the FET characteristic changes with time. During the operation of the amplifier circuit 110, the switch 18 outputs the output of the output unit 32 to the gate terminal G. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  FIG. 4 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example when there is no drain current drift. The drain current Id corresponds to the drain idle current. The threshold voltage Vth is the threshold voltage of the FET 10. The voltage Va, the voltage Vb, and the gate bias voltage Vg are DC component voltages that are sufficiently low in frequency with respect to the high-frequency signal. At time t0, the drain current Id, the threshold voltage Vth, the voltage Va, the voltage Vb, and the gate bias voltage Vg are, for example, 150 mA, −2.5 V, −2 V, −2 V, and −2 V, respectively.

  A high-power high-frequency signal is input to the input terminal Tin between times t1 and t2. Between times t1 and t2, the drain current Id increases because the direct current component of the drain current increases. For this reason, the output voltage Va of the detection part 12 becomes -2.3V, for example. Since no drain current drift occurs, the threshold voltage Vth is constant at −2.5V. The voltage Vb responds with a first response time. Since the first response time is sufficiently longer than the period between t1 and t2, the voltage Vb hardly decreases from −2V at time t2. The gate bias voltage Vg is almost the same as the voltage Vb, and is almost −2V. The drain current Id does not drift after time t2. When the voltage Va returns to -2V, the voltage Vb responds with a second response time. Since the second response time is faster than the first response time, the voltages Vb and Vg return to −2 V immediately after time t2.

  In FIG. 4, the drain current Id increases between times t1 and t2 when a high-power signal is input. For this reason, the output voltage Va of the detection part 12 changes from -2V to -2.3V, for example. However, the first circuit 14 outputs approximately −2 V as the voltage Vb. Therefore, the gate bias voltage Vg hardly changes between times t1 and t2 when a high-power signal is input. If the gate bias voltage Vg changes between times t1 and t2 when a high-power signal is input, the maximum output voltage of the amplifier circuit 100, the gain, or the error rate may be degraded. . According to the first embodiment, since the gate bias voltage Vg hardly changes between the times t1 and t2, it is possible to suppress a decrease in output power of the amplifier circuit 100, a decrease in gain, a deterioration in error rate, or the like.

  FIG. 5 is a schematic diagram showing the drain current and the like with respect to time in Example 1, and is an example in the case where there is a drain current drift. The drain current Id corresponds to the drain idle current. The voltage Va, the voltage Vb, and the gate bias voltage Vg are DC component voltages that are sufficiently low in frequency with respect to the high-frequency signal. The drain current Id, the threshold voltage Vth, the voltage Va, the voltage Vb, and the gate bias voltage Vg from time t0 to t2 are the same as those in FIG. At time t2, the high power high frequency signal is turned off. After time t2, the threshold voltage Vth becomes −2.2V, for example, due to drain current drift, and then gradually returns to −2.5V. Since the drain current Id becomes small, the detection unit 12 detects a decrease in the drain current Id and outputs, for example, −1.7 V as the voltage Va. Since the second response time when the voltage Va rises is fast, the voltage Vb immediately follows the voltage Va. As a result, the gate bias voltage Vg is fed back so that the drain current Id of the FET 10 increases, and as a result, the drain current Id does not change. As the threshold voltage Vth gradually returns from −2.2V to −2.5V, for example, the voltages Va, Vb, and Vg gradually return from −1.7V to −2V, for example.

  FIG. 6 is a schematic diagram showing the drain current and the like with respect to time in Comparative Example 1, and is an example when there is a drain current drift. The voltage Vb is the output voltage of the control unit 30, and the voltage Vg is the output voltage of the output unit 32. When the drain current Id is smaller than a reference value (for example, 150 mA), the control unit 30 outputs a voltage Vb corresponding to the drain current Id to the output unit 32, and when the drain current Id is greater than or equal to the reference value, For example, -2V is output as the voltage Vb. Between times t0 and t2, the drain current Id is greater than or equal to the reference value. Therefore, the voltages Vb and Vg are constant at −2 V until time t2. When the drain current drift occurs after time t2, the drain current Id tends to be smaller than the reference value. Therefore, the voltages Vb and Vg are substantially the voltage Va. Thereby, the drain current drift is compensated and the drain current Id hardly changes.

  FIG. 7 is a schematic diagram showing the drain current with respect to time in Comparative Example 1. In FIG. 7, a solid line 80 is the same as the drain current Id in FIG. A broken line 81 indicates a case where the characteristics of the FET 10 change with temperature and / or change with time, and the drain idle current increases. Like the one-dot chain line 82, it is preferable that the drain current is constant even if the drain current drift occurs. If the drain current drift is not compensated, the drain current greatly decreases immediately after time t2, as indicated by the dotted line 83. In the first comparative example, the reference value for determining whether the control unit 30 makes the voltage Vb constant or the voltage Va constant is constant. For this reason, even if a drain current drift occurs, a feedback for compensating the drain current drift is not applied in a part of the period. Therefore, as indicated by a broken line 81, a part of the drift of the drain current remains immediately after time t2. As a result, the gain of the amplifier circuit 110 is lowered and the distortion characteristics are deteriorated.

  According to the first embodiment, when the voltage Va decreases, the output unit 15 generates the gate bias voltage Vg corresponding to the voltage Va from the voltage Va in the first response time, and outputs it to the gate terminal G. When the voltage Va increases, the output unit 15 generates a gate bias voltage Vg corresponding to the voltage Va from the voltage Va with a second response time shorter than the first response time, and outputs the gate bias voltage Vg to the gate terminal G. Accordingly, when considering a time longer than the first response time, the drift current becomes a substantially constant current. Therefore, the drain idle current is kept almost constant even if the FET characteristics change with temperature and / or with time. Therefore, it is possible to suppress the drain current drift compensation from becoming abnormal due to a change in FET characteristics as indicated by a broken line 81 in FIG. Therefore, it is possible to suppress degradation and deterioration of distortion characteristics. Further, unlike the first comparative example, it is not necessary to set a complicated reference value using the switch 18.

  In addition, the second response time is longer than a period during which high power is input to the high-frequency signal (a period between t1 and t2). Thereby, it can suppress that voltage Vb and Vg fall by time t2. The second response time is preferably, for example, 100 milliseconds or longer.

  Furthermore, the first response time is shorter than the period during which high power is input to the high-frequency signal. That is, the high-frequency signal has a high power period in which the power is higher than that in other periods, and the first response time is shorter than the high power period. Thereby, the voltages Vb and Vg can sufficiently follow the response of the drain current drift. The first response time is preferably 1 μsec or less, for example.

  FIG. 8 is a circuit diagram of an amplifier circuit according to the second embodiment. As shown in FIG. 8, the detection unit 12 includes a differential amplifier circuit 28 and resistors R11 to R14. The resistor R11 is connected between the positive input terminal of the differential amplifier circuit 28 and a node between the resistor R1 and the inductor L2. The resistor R12 is connected between the negative input terminal of the differential amplifier circuit 28 and the drain voltage VD. The resistor R13 is connected between the output terminal and the negative input terminal of the differential amplifier circuit 28. The resistor R14 is connected between the positive input terminal of the differential amplifier circuit 28 and the node between the resistors R2 and R3. The resistors R2 and R3 are directly connected between the voltage VR and the ground. When the drain current Id increases, the output voltage Va changes to the negative side, and when the drain current Id decreases, the output voltage Va changes to the positive side. The resistors R2 and R3 adjust the voltage output to the positive input terminal of the differential amplifier circuit 28 by resistance division. The voltage may be adjusted by other methods. The resistance values of the resistors R11 to R14 are set equal, for example. The amplification factor and the like of the differential amplifier circuit 22 can be changed by making the resistance values of the resistors R11 to R14 different.

  The first circuit 14 includes a differential amplifier circuit 22, a diode D1, a resistor R4, and a capacitor C3. The voltage Va is input to the positive input terminal of the differential amplifier circuit 22. The anode of the diode D1 and one end of the resistor R4 are commonly connected to the output terminal of the differential amplifier circuit 22. The cathode of the diode D1 and the other end of the resistor R4 are commonly connected to the negative input terminal of the differential amplifier circuit 22, connected to the ground via the capacitor C3, and output the voltage Vb.

  When the voltage Va increases, the voltage Va becomes higher than the voltage Vb. Therefore, a current flows in the forward direction of the diode D1, and the capacitor C3 is charged. The forward impedance of the diode D1 is sufficiently lower than the resistance value of the resistor R4. As a result, the voltage Vb follows the voltage Va and responds with a fast response time. On the other hand, when the voltage Va decreases, the voltage Va becomes lower than the voltage Vb. Therefore, current flows not through the diode D1 but through the resistor R4, and the capacitor C3 is discharged. Therefore, the voltage Vb follows and responds to the voltage Va with a slow response time. Thus, the first circuit 14 follows the voltage Va with an asymmetric response speed and generates the voltage Vb.

  The second circuit 16 includes a differential amplifier circuit 24 and resistors R5 and R6. The voltage Vb is input to the positive input terminal of the differential amplifier circuit 24 via the resistor R5. The output terminal of the differential amplifier circuit 24 is connected to the negative input terminal of the differential amplifier circuit 24 via a resistor R6. As described above, the second circuit 16 functions as a voltage follower circuit. Therefore, the second circuit 16 outputs the voltage Vb as the gate bias voltage Vg. Further, the output impedance of the second circuit 16 can be made lower than the output impedance of the first circuit 14.

  FIG. 9A to FIG. 9C are other examples of the output unit. As shown in FIG. 9A, the charge / discharge function of the capacitor C3 in FIG. 8 and the noise removal function of the capacitor C1 are combined with one capacitor C1. As described above, the second circuit 16 may be omitted. As a result, the output unit 15 is simplified, and the mounting area and cost can be reduced.

  As shown in FIG. 9B, the diode D1 may be connected in series to the output of the differential amplifier circuit 20, and the resistor R7 and the capacitor C3 may be connected to the negative voltage VR. When charging the capacitor C3, the current flows in the forward direction of the diode D1, so the response time is fast. When the capacitor C3 is discharged, no current flows through the diode D1, and is discharged to the negative voltage VR via the resistor R7. Therefore, the response time becomes long. Although illustration of the resistor in the second circuit 16 is omitted, the second circuit 16 has the same configuration as FIG. As shown in FIG. 9C, the second circuit 16 in FIG. 9B may be omitted, and the capacitor C1 may also function as the capacitors C1 and C3 in FIG. 9B.

  FIG. 10A and FIG. 10B are still another example of the output unit. As shown in FIG. 10A, the first circuit 14 includes pnp bipolar transistors 36 and 39, npn bipolar transistors 37 and 38, and resistors R20 to R22. The voltage Va is input to the bases of the transistors 36 and 37. The emitter of the transistor 36 is connected to a high voltage power supply via a resistor R20. The collector of the transistor 36 is connected to a low voltage power source. The emitter of the transistor 37 is connected to a low voltage power supply via a resistor R21. The collector of the transistor 37 is connected to a high voltage power source. The base of the transistor 38 is connected to the emitter of the transistor 36. The collector of the transistor 38 is connected to a high voltage power source. The base of the transistor 39 is connected to the emitter of the transistor 37. The collector of the transistor 39 is connected to a low voltage power source. The emitters of the transistors 38 and 39 are commonly connected to the output terminal of the first circuit 14. The emitter of the transistor 39 is connected to the output terminal via the resistor R22. The capacitor C3 is connected between the output terminal and the ground.

  The transistors 36 to 39 function as a voltage follower, and the transistors 38 and 39 pass current so that the voltage Vb becomes the same as the voltage Va. When the voltage Va increases, the transistor 38 charges the capacitor C3 at high speed. When the voltage Va decreases, the transistor 39 charges the capacitor C3. However, due to the resistor R22, the discharge of the capacitor C3 is slow. As a result, the first response time can be made slower than the second response time. Although illustration of the resistor in the second circuit 16 is omitted, the second circuit 16 has the same configuration as FIG. As shown in FIG. 10B, the second circuit 16 in FIG. 10A may be omitted, and the capacitor C1 may also function as the capacitors C1 and C3 in FIG.

  FIG. 11A and FIG. 11B are still other examples of the output unit. FIG. 11A is a circuit in which the transistor 38, the resistor R22, and the transistor 39 in FIG. 10A are replaced with a plurality of transistors 38 and transistors 39. The emitter of the transistor 36 is connected to the bases of the plurality of transistors 38. The emitter of the transistor 37 is connected to the base of the transistor 39. The resistor R22 is not connected to the emitter of the transistor 39. Other configurations are the same as those in FIG. When charging the capacitor C3, since the plurality of transistors 38 are driven, the capacitor C3 is charged at high speed. When discharging the capacitor C3, the number of transistors 39 (for example, one) smaller than that of the transistor 38 is driven, so that the capacitor C3 is discharged at low speed. As a result, the first response time can be made slower than the second response time. Although illustration of the resistor in the second circuit 16 is omitted, the second circuit 16 has the same configuration as FIG. As shown in FIG. 11B, the second circuit 16 in FIG. 11A may be omitted, and the capacitor C1 may also function as the capacitors C1 and C3 in FIG.

  As shown in FIG. 9A to FIG. 11B, any circuit can be used as the output unit 15.

  Example 3 is an example in which the amplifier circuit according to Example 1 or 2 is applied to a Doherty amplifier circuit. FIG. 12 is a block diagram of an amplifier circuit according to the third embodiment. As shown in FIG. 12, the amplifier circuit 104 is a Doherty amplifier circuit including a main amplifier 60, a peak amplifier 62, quarter-wave phase lines 64 and 66, and a circuit 70. The input terminal Tin is electrically connected to the input of the main amplifier 60 and is electrically connected to the input of the peak amplifier 62 via the quarter wavelength phase line 66. The output terminal Tout is electrically connected to the output of the main amplifier 60 via the quarter wavelength phase line 64 and is electrically connected to the output of the peak amplifier 62. The main amplifier 60 is, for example, a class A or class AB amplifier, and always amplifies an input signal input to the input terminal Tin. The peak amplifier 62 is, for example, a class C amplifier, and amplifies the input signal when the input signal is equal to or higher than a predetermined power. Therefore, drain idle current flows through the main amplifier 60, but idle current does not flow through the peak amplifier 62. For this reason, it is mainly the main amplifier 60 that causes a drift of the drain current.

  The circuit 70 corresponds to the resistor R1, the detection unit 12, and the output unit 15 of the first embodiment. The resistor R1 and the detection unit 12 of the circuit 70 detect the drain current of the main amplifier 60. The output unit 15 of the circuit 70 controls the gate bias voltage of the main amplifier 60. Thereby, even in the Doherty amplifier circuit, it is possible to suppress a decrease in gain due to the drain current drift.

  The fourth embodiment is an example in which the amplifier circuit according to the first or second embodiment is applied to an envelope tracking system amplifier circuit. FIG. 13 is a block diagram of an amplifier circuit according to the fourth embodiment. As shown in FIG. 13, in the amplifier circuit 106, the input terminal Tin is electrically connected to the input of the power amplifier 72. The output terminal Tout is electrically connected to the output of the power amplifier 72. The envelope controller 74 controls the drain voltage of the power amplifier 72. The resistor R1 and the detection unit 12 of the circuit 70 detect the drain current of the power amplifier 72. The output unit 15 of the circuit 70 controls the gate bias voltage of the power amplifier 72.

  In the envelope tracking method, the envelope controller 74 controls the drain voltage of the power amplifier 72 at high speed in accordance with the envelope of the modulation signal (the amplitude of the modulation signal wave). When the drain voltage is changed from a high voltage (for example, 50 V) to a low voltage (for example, 10 V), the drain current drifts due to the high voltage stress, and the bias point shifts at the time of the low voltage. Therefore, by using the circuit 70, the drain current drift at the time of a low voltage can be compensated and the bias point can be kept constant. The detecting unit 12 detects a potential difference between both ends of the resistor R1. For this reason, even if the absolute value of the drain voltage changes, the detector 12 can operate in the same manner as in the first or second embodiment depending on the magnitude of the drain current.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 FET
DESCRIPTION OF SYMBOLS 11 Power amplifier 12 Detection part 14 1st circuit 15 Output part 16 2nd circuit 60 Main amplifier 62 Peak amplifier 70 Circuit 74 Envelope controller

Claims (4)

A power amplifier including a FET in which a high-frequency signal is input to the gate terminal;
A detector that detects a drain idle current of the FET and outputs a first voltage corresponding to the drain idle current;
When the first voltage decreases, a gate bias voltage corresponding to the first voltage is generated from the first voltage in a first response time and output to the gate terminal of the FET, and the first voltage increases An output unit that generates the gate bias voltage according to the first voltage from the first voltage in a second response time shorter than the first response time, and outputs the gate bias voltage to the gate terminal;
An amplifying circuit comprising:   2. The amplifier circuit according to claim 1, wherein the high-frequency signal has a high power period in which power is larger than that of another period, and the first response time is shorter than the high power period.   2. The drain idle current is a drain idle current of an FET included in a main amplifier of a Doherty amplifier circuit, and the gate bias voltage is a gate bias voltage of an FET included in the main amplifier. Or the amplifier circuit of 2.   The amplifier circuit according to claim 1, further comprising an envelope controller that controls a drain voltage of the power amplifier.

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