JP6211999B2 - Nitride semiconductor layer, nitride semiconductor device, and method of manufacturing nitride semiconductor layer - Google Patents

Nitride semiconductor layer, nitride semiconductor device, and method of manufacturing nitride semiconductor layer Download PDF

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Publication number
JP6211999B2
JP6211999B2 JP2014130358A JP2014130358A JP6211999B2 JP 6211999 B2 JP6211999 B2 JP 6211999B2 JP 2014130358 A JP2014130358 A JP 2014130358A JP 2014130358 A JP2014130358 A JP 2014130358A JP 6211999 B2 JP6211999 B2 JP 6211999B2
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Prior art keywords
nitride semiconductor
semiconductor layer
layer
axis
substrate
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JP2016009795A (en
Inventor
年輝 彦坂
年輝 彦坂
浩志 大野
浩志 大野
布上　真也
真也 布上
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Toshiba Corp
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Toshiba Corp
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Priority to JP2014130358A priority Critical patent/JP6211999B2/en
Priority to US14/701,621 priority patent/US9515146B2/en
Priority to KR1020150065290A priority patent/KR20160001619A/en
Priority to CN201510245637.1A priority patent/CN105280775A/en
Publication of JP2016009795A publication Critical patent/JP2016009795A/en
Priority to HK16104183.1A priority patent/HK1216207A1/en
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Description

本発明の実施形態は、窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法に関する。   Embodiments described herein relate generally to a nitride semiconductor layer, a nitride semiconductor device, and a method for manufacturing a nitride semiconductor layer.

窒化物半導体を用いた半導体発光装置（例えば、発光ダイオード）が、表示装置や照明などに用いられている。この他、窒化物半導体は、高速電子デバイスやパワーデバイスに利用されている。窒化物半導体層を、格子定数または熱膨張係数が異なる基板上に形成すると、基板の反りやクラックが発生しやすい。性能の向上とともに、反りを小さくしクラックを抑制し、高生産性を実現する技術が望まれる。   A semiconductor light emitting device (for example, a light emitting diode) using a nitride semiconductor is used for a display device, illumination, or the like. In addition, nitride semiconductors are used for high-speed electronic devices and power devices. When the nitride semiconductor layer is formed on a substrate having a different lattice constant or thermal expansion coefficient, the substrate is likely to warp or crack. There is a demand for a technology that realizes high productivity with improved performance, reduced warpage and cracking.

特開２００７−２８１１４０号公報JP 2007-281140 A

本発明の実施形態は、高生産性の窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法を提供する。   Embodiments of the present invention provide a highly productive nitride semiconductor layer, a nitride semiconductor device, and a method for manufacturing a nitride semiconductor layer.

本発明の実施形態によれば、第１面に沿って広がる窒化物半導体層が提供される。前記窒化物半導体層は、第１領域と、第２領域と、を含む。前記第１面に対して平行な第１方向における前記第１領域の長さは、前記第１面に対して平行で前記第１方向に対して垂直な第２方向における前記第１領域の長さよりも長い。前記第２領域は、前記第２方向において前記第１領域と並ぶ。前記第１方向における前記第２領域の長さは、前記第２方向における前記第２領域の長さよりも長い。前記第１領域及び前記第２領域のｃ軸は、前記第２方向に対して傾斜する。前記ｃ軸は、前記第１面に対して垂直な第３方向と交差する。前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜する。
本発明の別の実施形態によれば、窒化物半導体装置は、基板と、前記複数の斜面から成長された窒化物半導体層と、を含む。前記基板は、上面と、前記上面に対して傾斜する複数の斜面と、を含む主面を有する。前記上面に対して平行な第１方向における前記複数の斜面のそれぞれの長さは、前記上面に対して平行で前記第１方向に対して垂直な第２方向における前記複数の斜面のそれぞれの長さよりも長い。前記複数の斜面は前記第２方向に並ぶ。前記窒化物半導体層のｃ軸は、前記第２方向に対して傾斜する。前記ｃ軸は、前記上面に対して垂直な第３方向と交差する。前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜する。
本発明の別の実施形態によれば、窒化物半導体装置は、窒化物半導体層を含む。前記窒化物半導体層は、上面と、前記上面に対して傾斜する複数の斜面と、を含む主面を有する基板であって、前記上面に対して平行な第１方向における前記複数の斜面のそれぞれの長さは、前記上面に対して平行で前記第１方向に対して垂直な第２方向における前記複数の斜面のそれぞれの長さよりも長く、前記複数の斜面は前記第２方向に並ぶ、前記基板の前記複数の斜面から、前記窒化物半導体層は成長される。前記窒化物半導体層のｃ軸は、前記第２方向に対して傾斜する。前記ｃ軸は、前記上面に対して垂直な第３方向と交差する。前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜する。
本発明の別の実施形態によれば、窒化物半導体層の製造方法は、基板を用意することを含む。前記基板は、上面と、前記上面に対して傾斜する複数の斜面と、を含む主面を有する。前記上面に対して平行な第１方向における前記複数の斜面のそれぞれの長さは、前記上面に対して平行で前記第１方向に対して垂直な第２方向における前記複数の斜面のそれぞれの長さよりも長い。前記複数の斜面は前記第２方向に並ぶ。窒化物半導体層の製造方法は、前記複数の斜面からエピタキシャル成長により窒化物半導体層を成長させることを含む。前記窒化物半導体層のｃ軸は、前記第２方向に対して傾斜する。前記ｃ軸は、前記上面に対して垂直な第３方向と交差する。前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜する。 According to the embodiment of the present invention, a nitride semiconductor layer extending along the first surface is provided. The nitride semiconductor layer includes a first region and a second region. The length of the first region in the first direction parallel to the first surface is the length of the first region in the second direction parallel to the first surface and perpendicular to the first direction. Longer than that. The second region is aligned with the first region in the second direction. The length of the second region in the first direction is longer than the length of the second region in the second direction. The c-axis of the first region and the second region is inclined with respect to the second direction. The c-axis intersects a third direction perpendicular to the first surface. The c-axis is inclined with respect to a plane including the second direction and the third direction.
According to another embodiment of the present invention, a nitride semiconductor device includes a substrate and a nitride semiconductor layer grown from the plurality of slopes. The substrate has a main surface including an upper surface and a plurality of inclined surfaces inclined with respect to the upper surface. The lengths of the plurality of slopes in the first direction parallel to the top surface are the lengths of the plurality of slopes in the second direction parallel to the top surface and perpendicular to the first direction. Longer than that. The plurality of slopes are arranged in the second direction. The c-axis of the nitride semiconductor layer is inclined with respect to the second direction. The c-axis intersects a third direction perpendicular to the upper surface. The c-axis is inclined with respect to a plane including the second direction and the third direction.
According to another embodiment of the present invention, a nitride semiconductor device includes a nitride semiconductor layer. The nitride semiconductor layer is a substrate having a main surface including an upper surface and a plurality of inclined surfaces inclined with respect to the upper surface, and each of the plurality of inclined surfaces in a first direction parallel to the upper surface. Is longer than each of the plurality of slopes in a second direction parallel to the upper surface and perpendicular to the first direction, and the plurality of slopes are arranged in the second direction, The nitride semiconductor layer is grown from the plurality of slopes of the substrate. The c-axis of the nitride semiconductor layer is inclined with respect to the second direction. The c-axis intersects a third direction perpendicular to the upper surface. The c-axis is inclined with respect to a plane including the second direction and the third direction.
According to another embodiment of the present invention, a method for manufacturing a nitride semiconductor layer includes providing a substrate. The substrate has a main surface including an upper surface and a plurality of inclined surfaces inclined with respect to the upper surface. The lengths of the plurality of slopes in the first direction parallel to the top surface are the lengths of the plurality of slopes in the second direction parallel to the top surface and perpendicular to the first direction. Longer than that. The plurality of slopes are arranged in the second direction. The method for manufacturing a nitride semiconductor layer includes growing the nitride semiconductor layer from the plurality of inclined surfaces by epitaxial growth. The c-axis of the nitride semiconductor layer is inclined with respect to the second direction. The c-axis intersects a third direction perpendicular to the upper surface. The c-axis is inclined with respect to a plane including the second direction and the third direction.

図１（ａ）及び図１（ｂ）は、第１の実施形態に係る窒化物半導体装置を示す模式的斜視図である。FIG. 1A and FIG. 1B are schematic perspective views showing the nitride semiconductor device according to the first embodiment. 第１の実施形態に係る窒化物半導体装置を示す模式的断面図である。1 is a schematic cross-sectional view showing a nitride semiconductor device according to a first embodiment. 図３（ａ）〜図３（ｃ）は、第１の実施形態に係る窒化物半導体装置の製造方法を示す工程順模式的断面図である。FIG. 3A to FIG. 3C are schematic cross-sectional views in order of steps showing the method for manufacturing the nitride semiconductor device according to the first embodiment. 図４（ａ）〜図４（ｃ）は、窒化物半導体装置に関する実験結果を示す電子顕微鏡写真像である。FIG. 4A to FIG. 4C are electron microscope photographic images showing experimental results regarding the nitride semiconductor device. 図５（ａ）及び図５（ｂ）は、窒化物半導体装置に関する実験結果を示す電子顕微鏡写真像である。FIG. 5A and FIG. 5B are electron micrograph images showing experimental results regarding the nitride semiconductor device. 図６（ａ）〜図６（ｄ）は、窒化物半導体装置の特性を示すグラフ図である。FIG. 6A to FIG. 6D are graphs showing characteristics of the nitride semiconductor device. 図７（ａ）〜図７（ｄ）は、窒化物半導体装置を示す電子顕微鏡写真像及び模式図である。FIG. 7A to FIG. 7D are an electron micrograph image and a schematic diagram showing a nitride semiconductor device. 図８（ａ）〜図８（ｄ）は、窒化物半導体装置を示す電子顕微鏡写真像である。FIG. 8A to FIG. 8D are electron micrograph images showing nitride semiconductor devices. 図９（ａ）〜図９（ｊ）は、窒化物半導体装置を示す電子顕微鏡写真像及び模式的斜視図である。FIG. 9A to FIG. 9J are an electron micrograph image and a schematic perspective view showing the nitride semiconductor device. 図１０（ａ）〜図１０（ｄ）は、第１の実施形態に係る窒化物半導体装置を示す模式的断面図である。FIG. 10A to FIG. 10D are schematic cross-sectional views showing the nitride semiconductor device according to the first embodiment. 第１の実施形態に係る別の窒化物半導体装置を示す模式的断面図である。FIG. 5 is a schematic cross-sectional view showing another nitride semiconductor device according to the first embodiment. 窒化物半導体装置を示す電子顕微鏡写真像である。It is an electron micrograph image which shows a nitride semiconductor device. 第２の実施形態に係る窒化物半導体層の製造方法を示すフローチャート図である。It is a flowchart figure which shows the manufacturing method of the nitride semiconductor layer which concerns on 2nd Embodiment.

以下に、本発明の各実施の形態について図面を参照しつつ説明する。
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
なお、本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。 Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

（第１の実施形態）
本実施形態は、窒化物半導体装置に係る。実施形態に係る窒化物半導体装置は、半導体発光装置、半導体受光装置、及び、電子装置などを含む。半導体発光装置は、例えば、発光ダイオード（ＬＥＤ）及びレーザダイオード（ＬＤ）などを含む。半導体受光装置は、フォトダイオード（ＰＤ）などを含む。電子装置は、例えば、高電子移動度トランジスタ（ＨＥＭＴ）、ヘテロ接合バイポーラトランジスタ（ＨＢＴ）、電界効果トランジスタ（ＦＥＴ）及びショットキーバリアダイオード（ＳＢＤ）などを含む。 (First embodiment)
The present embodiment relates to a nitride semiconductor device. The nitride semiconductor device according to the embodiment includes a semiconductor light emitting device, a semiconductor light receiving device, and an electronic device. The semiconductor light emitting device includes, for example, a light emitting diode (LED) and a laser diode (LD). The semiconductor light receiving device includes a photodiode (PD) and the like. The electronic device includes, for example, a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a field effect transistor (FET), and a Schottky barrier diode (SBD).

図１（ａ）及び図１（ｂ）は、第１の実施形態に係る窒化物半導体装置を例示する模式的斜視図である。
図１（ａ）に示すように、実施形態に係る窒化物半導体装置１１０は、基板４０と、窒化物半導体層１５と、を含む。 FIG. 1A and FIG. 1B are schematic perspective views illustrating the nitride semiconductor device according to the first embodiment.
As shown in FIG. 1A, the nitride semiconductor device 110 according to the embodiment includes a substrate 40 and a nitride semiconductor layer 15.

窒化物半導体層１５は、第１面１５ｆ（例えばＸ−Ｙ平面）に沿って広がる。第１面１５ｆは、平面である。窒化物半導体層１５の巨視的な主面が、第１面１５ｆに対応する。窒化物半導体層１５の主面は、Ｘ−Ｙ平面に対して平行である。窒化物半導体層１５は、第１領域１５ａと、第２領域１５ｂと、を含む。   The nitride semiconductor layer 15 extends along the first surface 15f (for example, the XY plane). The first surface 15f is a plane. The macroscopic main surface of the nitride semiconductor layer 15 corresponds to the first surface 15f. The main surface of the nitride semiconductor layer 15 is parallel to the XY plane. The nitride semiconductor layer 15 includes a first region 15a and a second region 15b.

Ｘ−Ｙ平面に対して平行な１つの方向をＸ軸方向とする。Ｘ−Ｙ平面に対して平行で、Ｘ軸方向に対して垂直な方向をＹ軸方向とする。Ｘ−Ｙ平面に対して垂直な方向をＺ軸方向とする。Ｘ軸方向を第１方向Ｄ１とする。Ｙ軸方向を第２方向Ｄ２とする。Ｚ軸方向を第３方向Ｄ３とする。   One direction parallel to the XY plane is defined as an X-axis direction. A direction parallel to the XY plane and perpendicular to the X-axis direction is taken as a Y-axis direction. A direction perpendicular to the XY plane is taken as a Z-axis direction. The X-axis direction is defined as a first direction D1. The Y axis direction is defined as a second direction D2. The Z-axis direction is defined as a third direction D3.

第１領域１５ａ及び第２領域１５ｂのそれぞれは、第１方向Ｄ１に沿って延びる。第１方向Ｄ１は、第１面１５ｆに対して平行である。第２領域１５ｂは、第１面１５ｆ内で、第１領域１５ａと並ぶ。第２領域１５ｂは、第２方向Ｄ２において第１領域１５ａと並ぶ。第２領域１５ｂは、第１領域１５ａと接する。   Each of the first region 15a and the second region 15b extends along the first direction D1. The first direction D1 is parallel to the first surface 15f. The second region 15b is aligned with the first region 15a in the first surface 15f. The second region 15b is aligned with the first region 15a in the second direction D2. The second region 15b is in contact with the first region 15a.

第１方向Ｄ１における第１領域１５ａの長さは、第２方向Ｄ２における第１領域１５ａの長さよりも長い。第１方向Ｄ１における第２領域１５ｂの長さは、第２方向Ｄ２における第２領域１５ｂの長さよりも長い。   The length of the first region 15a in the first direction D1 is longer than the length of the first region 15a in the second direction D2. The length of the second region 15b in the first direction D1 is longer than the length of the second region 15b in the second direction D2.

例えば、第１方向Ｄ１における第１領域１５ａの長さは、第３方向Ｄ３における第１領域１５ａの長さよりも長い。例えば、第１方向Ｄ１における第２領域１５ｂの長さは、第３方向Ｄ３における第２領域１５ｂの長さよりも長い。   For example, the length of the first region 15a in the first direction D1 is longer than the length of the first region 15a in the third direction D3. For example, the length of the second region 15b in the first direction D1 is longer than the length of the second region 15b in the third direction D3.

第１領域１５ａと第２領域１５ｂとの間の境界１７は、例えば、断面をＴＥＭ（透過形電子顕微鏡）による観察を行うことで観測される場合がある。この他、境界１７は、表面（第１面１５ｆ）を原子間力顕微鏡（ＡＦＭ）やカソードルミネッセンス（ＣＬ)による観察を行うことで観測される場合がある。   The boundary 17 between the first region 15a and the second region 15b may be observed by, for example, observing the cross section with a TEM (transmission electron microscope). In addition, the boundary 17 may be observed by observing the surface (first surface 15f) with an atomic force microscope (AFM) or cathodoluminescence (CL).

窒化物半導体層１５は、ｃ軸１６を有する。第１領域１５ａは、ｃ軸１６ａを有する。第２領域１５ｂは、ｃ軸１６ｂを有する。ｃ軸１６ａは、ｃ軸１６ｂに対して実質的に平行である。ｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂ）の方向は、例えばＸ線回折により観測できる。第１領域１５ａのｃ軸１６ａと、第２領域１５ｂのｃ軸と、は、互いに平行である。ＴＥＭ像などにおいて、第１領域１５ａで観察される像の明暗の方向は、第２領域１５ｂで観察される像の明暗の方向に対して平行である。例えば、窒化物半導体層１５の巨視的なｃ軸１６の方向がＸ線回折により観測される。このとき、この巨視的な方向が、ｃ軸１６ａの方向及びｃ軸１６ｂの方向と一致するとみなして良い。   The nitride semiconductor layer 15 has a c-axis 16. The first region 15a has a c-axis 16a. The second region 15b has a c-axis 16b. The c-axis 16a is substantially parallel to the c-axis 16b. The direction of the c-axis 16 (c-axis 16a and c-axis 16b) can be observed by, for example, X-ray diffraction. The c-axis 16a of the first region 15a and the c-axis of the second region 15b are parallel to each other. In a TEM image or the like, the brightness direction of the image observed in the first region 15a is parallel to the brightness direction of the image observed in the second region 15b. For example, the macroscopic c-axis 16 direction of the nitride semiconductor layer 15 is observed by X-ray diffraction. At this time, this macroscopic direction may be regarded as coincident with the direction of the c-axis 16a and the direction of the c-axis 16b.

窒化物半導体層１５のｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）は、第１方向Ｄ１に対して傾斜している。ｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）は、第１方向Ｄ１に対して平行ではなく、垂直でもない。
窒化物半導体層１５のｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）は、第２方向Ｄ２に対して傾斜している。ｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）は、第２方向Ｄ２に対して平行ではなく、垂直でもない。 The c-axis 16 (each of the c-axis 16a and the c-axis 16b) of the nitride semiconductor layer 15 is inclined with respect to the first direction D1. The c-axis 16 (each of the c-axis 16a and the c-axis 16b) is neither parallel nor perpendicular to the first direction D1.
The c-axis 16 (each of the c-axis 16a and the c-axis 16b) of the nitride semiconductor layer 15 is inclined with respect to the second direction D2. The c-axis 16 (each of the c-axis 16a and the c-axis 16b) is neither parallel nor perpendicular to the second direction D2.

窒化物半導体層１５のｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）を第１面１５ｆに投影した方向（軸）は、第２方向Ｄ２に対して傾斜している。第１領域１５ａのｃ軸１６ａを第１面１５ｆに投影した方向と、第２方向Ｄ２と、の間の角度θ２は、例えば、５度以上８５度以下である。第２領域１５ｂのｃ軸１６ｂを第１面１５ｆに投影した方向と、第２方向Ｄ２と、の間の角度θ２は、例えば、５度以上８５度以下である。   The direction (axis) in which the c-axis 16 (each of the c-axis 16a and the c-axis 16b) of the nitride semiconductor layer 15 is projected on the first surface 15f is inclined with respect to the second direction D2. An angle θ2 between the direction in which the c-axis 16a of the first region 15a is projected on the first surface 15f and the second direction D2 is, for example, not less than 5 degrees and not more than 85 degrees. The angle θ2 between the direction in which the c-axis 16b of the second region 15b is projected onto the first surface 15f and the second direction D2 is, for example, not less than 5 degrees and not more than 85 degrees.

このように、第１領域１５ａのｃ軸１６ａ、及び、第２領域１５ｂのｃ軸１６ｂのそれぞれを第１面１５ｆに投影した方向（軸）のそれぞれは、それらの境界１７の延在方向（第１方向Ｄ１）に対して傾斜している。第１領域１５ａのｃ軸１６ａ、及び、第２領域１５ｂのそれぞれをｃ軸１６ｂの第１面１５ｆに投影した方向（軸）のそれぞれは、境界１７の延在方向（第１方向Ｄ１）に対して垂直な第２方向Ｄ２に対して傾斜している。   Thus, the direction (axis) in which each of the c-axis 16a of the first region 15a and the c-axis 16b of the second region 15b is projected onto the first surface 15f is the extending direction of the boundary 17 ( It is inclined with respect to the first direction D1). The direction (axis) in which the c-axis 16a of the first region 15a and the second region 15b are projected onto the first surface 15f of the c-axis 16b is in the extending direction of the boundary 17 (first direction D1). It inclines with respect to the 2nd direction D2 perpendicular | vertical.

窒化物半導体層１５のｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）は、第３方向Ｄ３（第１面１５ｆに対して垂直な方向（軸））と交差する。窒化物半導体層１５のｃ軸１６は、第３方向Ｄ３に対して、実質的に垂直、または、傾斜している。   The c-axis 16 (each of the c-axis 16a and the c-axis 16b) of the nitride semiconductor layer 15 intersects the third direction D3 (direction (axis) perpendicular to the first surface 15f). The c-axis 16 of the nitride semiconductor layer 15 is substantially perpendicular or inclined with respect to the third direction D3.

この例では、窒化物半導体層１５のｃ軸１６（ｃ軸１６ａ及びｃ軸１６ｂのそれぞれ）は、第１面１５ｆに対して傾斜する。第１領域１５ａのｃ軸１６ａと、第１面１５ｆと、の間の角度θ１は、０度以上８５度以下である。第２領域１５ｂのｃ軸１６ｂと、第１面１５ｆと、の間の角度θ１は、例えば、０度以上８５度以下である。主面１５ｆは、例えばｃ面とは異なる。主面１５ｆは、ｃ面にオフ角を設けた結晶面（オフ基板、ミスカット基板）とは、異なる。例えば、主面１５ｆは、半極性面である。または、例えば、主面１５ｆは、非極性面である。   In this example, the c-axis 16 (each of the c-axis 16a and the c-axis 16b) of the nitride semiconductor layer 15 is inclined with respect to the first surface 15f. An angle θ1 between the c-axis 16a of the first region 15a and the first surface 15f is not less than 0 degrees and not more than 85 degrees. An angle θ1 between the c-axis 16b of the second region 15b and the first surface 15f is, for example, not less than 0 degrees and not more than 85 degrees. The main surface 15f is different from, for example, the c-plane. The main surface 15f is different from a crystal plane (off substrate, miscut substrate) provided with an off angle on the c plane. For example, the main surface 15f is a semipolar surface. Alternatively, for example, the main surface 15f is a nonpolar surface.

このような窒化物半導体層１５は、斜面を有する基板４０を用いた結晶成長により、得られる。   Such a nitride semiconductor layer 15 is obtained by crystal growth using a substrate 40 having a slope.

図１（ｂ）は、基板４０を例示する模式的斜視図である。
基板４０は、主面４０ａを有する。主面４０ａは、基板４０の巨視的な主面である。主面４０ａは、第１面１５ｆに対して、実質的に平行である。基板４０は、主面４０ａに沿って広がる。 FIG. 1B is a schematic perspective view illustrating the substrate 40.
The substrate 40 has a main surface 40a. The main surface 40 a is a macroscopic main surface of the substrate 40. The main surface 40a is substantially parallel to the first surface 15f. The substrate 40 extends along the main surface 40a.

主面４０ａは、上面４０ｕ（頂面）と、複数の斜面４１と、を含む。複数の斜面４１のそれぞれは、上面４０ｕに対して傾斜する。巨視的な主面４０ａは、上面４０ｕに対して平行であると見なす。複数の斜面４１は、第１面１５ｆに対して傾斜している。複数の斜面４１は、第２方向Ｄ２において並ぶ。   The main surface 40a includes an upper surface 40u (top surface) and a plurality of inclined surfaces 41. Each of the plurality of inclined surfaces 41 is inclined with respect to the upper surface 40u. The macroscopic main surface 40a is considered to be parallel to the upper surface 40u. The plurality of inclined surfaces 41 are inclined with respect to the first surface 15f. The plurality of inclined surfaces 41 are arranged in the second direction D2.

斜面４１は、例えば、斜面４１ａと、斜面４１ｂと、を含む。斜面４１ｂは、第２方向Ｄ２において斜面４１ａと離間する。   The inclined surface 41 includes, for example, an inclined surface 41a and an inclined surface 41b. The slope 41b is separated from the slope 41a in the second direction D2.

複数の斜面４１（例えば、斜面４１ａ及び斜面４１ｂ）のそれぞれの第１方向Ｄ１に沿った長さは、複数の斜面４１（斜面４１ａ及び斜面４１ｂ）のそれぞれの第２方向Ｄ２に沿った長さよりも長い。複数の斜面４１（例えば、斜面４１ａ及び斜面４１ｂ）のそれぞれの第１方向Ｄ１に沿った長さは、複数の斜面４１（斜面４１ａ及び４１ｂ）のそれぞれの第３方向Ｄ３に沿った長さよりも長い。   The length along the first direction D1 of each of the plurality of slopes 41 (for example, the slope 41a and the slope 41b) is longer than the length along the second direction D2 of each of the plurality of slopes 41 (the slope 41a and the slope 41b). Also long. The length along the first direction D1 of each of the plurality of slopes 41 (for example, the slope 41a and the slope 41b) is larger than the length along the third direction D3 of each of the plurality of slopes 41 (slopes 41a and 41b). long.

窒化物半導体層１５は、これらの複数の斜面４１から成長されている。この窒化物半導体層１５のｃ軸１６は、基板４０の上面４０ｕ（主面４０ａ）に対して傾斜している。このｃ軸１６は、第３方向Ｄ３（上面４０ｕに対して垂直な方向）と交差する。   The nitride semiconductor layer 15 is grown from the plurality of inclined surfaces 41. The c-axis 16 of the nitride semiconductor layer 15 is inclined with respect to the upper surface 40 u (main surface 40 a) of the substrate 40. The c-axis 16 intersects the third direction D3 (direction perpendicular to the upper surface 40u).

この例では、基板４０は、複数の凹部４５を有する。複数の凹部４５は、第２方向Ｄ２において並ぶ。複数の斜面４１のそれぞれは、複数の凹部４５のそれぞれの側面の一部である。   In this example, the substrate 40 has a plurality of recesses 45. The plurality of recesses 45 are arranged in the second direction D2. Each of the plurality of slopes 41 is a part of the side surface of each of the plurality of recesses 45.

例えば、複数の凹部４５は、第１凹部４５ａと第２凹部４５ｂとを含む。第１凹部４５ａ及び第２凹部４５ｂは、第１方向Ｄ１に沿って延在する。複数の凹部４５（第１凹部４５ａ及び第２凹部４５ｂなど）のそれぞれの第１方向Ｄ１の長さは、複数の凹部４５のそれぞれの第２方向Ｄ２の長さよりも長い。複数の凹部４５（第１凹部４５ａ及び第２凹部４５ｂなど）のそれぞれの第１方向Ｄ１の長さは、複数の凹部４５のそれぞれの第３方向Ｄ３の長さよりも長い。   For example, the plurality of recesses 45 include a first recess 45a and a second recess 45b. The first recess 45a and the second recess 45b extend along the first direction D1. The length of each of the plurality of recesses 45 (such as the first recess 45a and the second recess 45b) in the first direction D1 is longer than the length of each of the plurality of recesses 45 in the second direction D2. The length of each of the plurality of recesses 45 (such as the first recess 45a and the second recess 45b) in the first direction D1 is longer than the length of each of the plurality of recesses 45 in the third direction D3.

第１凹部４５ａは、側面４６ａｓと側面４６ａｒと底面４６ａｔとを有する。側面４６ａｒは、側面４６ａｓと対向する。底面４６ａｔは、側面４６ａｓ及び側面４６ａｒと接続される。   The first recess 45a has a side surface 46as, a side surface 46ar, and a bottom surface 46at. The side surface 46ar faces the side surface 46as. The bottom surface 46at is connected to the side surface 46as and the side surface 46ar.

第２凹部４５ｂは、側面４６ｂｓと側面４６ｂｒと底面４６ｂｔとを有する。側面４６ｂｒは、側面４６ｂｓと対向する。底面４６ｂｔは、側面４６ｂｓ及び側面４６ｂｒと接続される。   The second recess 45b has a side surface 46bs, a side surface 46br, and a bottom surface 46bt. The side surface 46br faces the side surface 46bs. The bottom surface 46bt is connected to the side surface 46bs and the side surface 46br.

側面４６ａｓ、側面４６ａｒ、側面４６ｂｓ及び側面４６ｂｒは、第１方向Ｄ１に対して平行である。   The side surface 46as, the side surface 46ar, the side surface 46bs, and the side surface 46br are parallel to the first direction D1.

側面４６ａｓと側面４６ｂｓとの間に、側面４６ａｒが配置される。側面４６ａｒと側面４６ｂｒとの間に側面４６ｂｓが配置される。側面４６ａｓと側面４６ａｒとは、互いに向かい合う。側面４６ｂｓと側面４６ｂｒとは、互いに向かい合う。   A side surface 46ar is disposed between the side surface 46as and the side surface 46bs. Side surface 46bs is arranged between side surface 46ar and side surface 46br. The side surface 46as and the side surface 46ar face each other. The side surface 46bs and the side surface 46br face each other.

この例では、側面４６ａｒは、側面４６ａｓに対して実質的に平行である。側面４６ｂｒは、側面４６ｂｓに対して実質的に平行である。   In this example, the side surface 46ar is substantially parallel to the side surface 46as. The side surface 46br is substantially parallel to the side surface 46bs.

このように、基板４０において、複数の凹部４５のそれぞれは、互いに向かい合う第１側面及び第２側面を含む。第１側面は、例えば、側面４６ａｓ及び側面４６ｂｓである。第２側面は、例えば、側面４６ａｒ及び側面４６ｂｒである。   Thus, in the substrate 40, each of the plurality of recesses 45 includes the first side surface and the second side surface facing each other. The first side surface is, for example, a side surface 46as and a side surface 46bs. The second side surface is, for example, a side surface 46ar and a side surface 46br.

複数の斜面４１のそれぞれは、複数の凹部４５のそれぞれの第１側面（側面４６ａｓ及び側面４６ｂｓ）である。   Each of the plurality of inclined surfaces 41 is a first side surface (side surface 46as and side surface 46bs) of each of the plurality of concave portions 45.

この例では、第２側面（側面４６ａｒ及び側面４６ｂｒなど）は、第１側面（側面４６ａｓ及び側面４６ｂｓ）に対して平行である。   In this example, the second side surface (the side surface 46ar and the side surface 46br) is parallel to the first side surface (the side surface 46as and the side surface 46bs).

実施形態においては、後述するように、凹部４５の延在方向（第１方向Ｄ１）を、基板４０の結晶方位に対して所定の角度で傾斜させる。すなわち、斜面４１（例えば、側面４６ａｓ及び側面４６ｂｓ）の延在方向（第１方向Ｄ１）を、基板４０の結晶方位に対して所定の角度で傾斜させる。このような斜面４１から結晶成長させることで、窒化物半導体層１５のｃ軸１６は、第２方向Ｄ２に対して傾斜する。   In the embodiment, as will be described later, the extending direction of the recess 45 (first direction D1) is inclined at a predetermined angle with respect to the crystal orientation of the substrate 40. That is, the extending direction (first direction D1) of the inclined surface 41 (for example, the side surface 46as and the side surface 46bs) is inclined at a predetermined angle with respect to the crystal orientation of the substrate 40. By crystal growth from such a slope 41, the c-axis 16 of the nitride semiconductor layer 15 is inclined with respect to the second direction D2.

そして、斜面４１は、第３方向Ｄ３に対して傾斜している。斜面４１から成長した窒化物半導体層１５において、ｃ軸１６は、第３方向Ｄ３に対して交差する。ｃ軸１６は、第３方向Ｄ３に対して傾斜する。   The inclined surface 41 is inclined with respect to the third direction D3. In the nitride semiconductor layer 15 grown from the inclined surface 41, the c-axis 16 intersects the third direction D3. The c-axis 16 is inclined with respect to the third direction D3.

このような基板４０の斜面４１（例えば、側面４６ａｓ及び側面４６ｂｓ）から結晶成長させることで、実施形態に係る窒化物半導体層１５が得られる。   The nitride semiconductor layer 15 according to the embodiment is obtained by crystal growth from the inclined surface 41 (for example, the side surface 46as and the side surface 46bs) of the substrate 40.

基板４０には、例えば、シリコン、サファイア、スピネル、ＧａＡｓ、ＩｎＰ、ＺｎＯ、Ｇｅ、ＳｉＧｅ及び、ＳｉＣのいずれかが用いられる。例えば、基板４０の格子定数が、窒化物半導体層１５の格子定数とは異なる。基板４０の熱膨張係数は、窒化物半導体層１５の熱膨張係数とは異なる。   For the substrate 40, for example, any one of silicon, sapphire, spinel, GaAs, InP, ZnO, Ge, SiGe, and SiC is used. For example, the lattice constant of the substrate 40 is different from the lattice constant of the nitride semiconductor layer 15. The thermal expansion coefficient of the substrate 40 is different from the thermal expansion coefficient of the nitride semiconductor layer 15.

基板４０が、窒化物半導体層１５とは異なる格子定数及び熱膨張係数の少なくともいずれかを有するときには、基板４０の反りが大きくなりやすい。基板４０の反りが過度に大きくなると、クラックが生じやすい。   When the substrate 40 has at least one of a lattice constant and a thermal expansion coefficient different from those of the nitride semiconductor layer 15, the warp of the substrate 40 is likely to increase. If the warpage of the substrate 40 becomes excessively large, cracks are likely to occur.

一方、主面がｃ面の窒化物半導体層においては、ヘテロ構造を形成した場合に、大きな分極電界が生じ、装置の性能に影響を与える。主面がｃ面とは異なる面（半極性面または無極性面）である場合は、例えば、機能層に生じる内部電界が抑制され、装置の性能が向上する。しかしながら、半極性面や無極性面の結晶を、格子定数または熱膨張係数の異なる基板上に形成した場合には、基板の反りやクラックが特に発生しやすいことが分かった。   On the other hand, in the nitride semiconductor layer whose principal surface is the c-plane, when a heterostructure is formed, a large polarization electric field is generated, which affects the performance of the device. When the main surface is a surface (semipolar surface or nonpolar surface) different from the c-plane, for example, an internal electric field generated in the functional layer is suppressed, and the performance of the device is improved. However, it has been found that when a crystal of a semipolar plane or a nonpolar plane is formed on a substrate having a different lattice constant or thermal expansion coefficient, the substrate is likely to warp or crack.

本願発明者の検討によると、このような反りやクラックの発生は、窒化物半導体層の特性のＸ−Ｙ平面内の異方性に依存することが分かった。例えば、窒化物半導体層において、ａ軸方向の熱膨張係数は、ｃ軸方向の熱膨張係数とは異なる。このとき、半極性面や無極性面の結晶を用いた場合は、Ｘ−Ｙ平面内に、ａ軸の成分とｃ軸の成分と、が存在する。このため、Ｘ−Ｙ平面内の２つの方向の熱膨張係数が、互いに異なる。すなわち、熱膨張係数に面内の異方性が生じる。このため、反りにも異方性が生じ易くなる。１つの方向における反りが大きくなる。このため、特にクラックが生じやすくなる。   According to the study of the present inventor, it has been found that the occurrence of such warpage and cracks depends on the anisotropy in the XY plane of the characteristics of the nitride semiconductor layer. For example, in the nitride semiconductor layer, the thermal expansion coefficient in the a-axis direction is different from the thermal expansion coefficient in the c-axis direction. At this time, when a semipolar or nonpolar crystal is used, there are an a-axis component and a c-axis component in the XY plane. For this reason, the thermal expansion coefficients in the two directions in the XY plane are different from each other. That is, in-plane anisotropy occurs in the thermal expansion coefficient. For this reason, anisotropy also tends to occur in the warp. Warpage in one direction increases. For this reason, it becomes easy to produce a crack especially.

実施形態においては、窒化物半導体層１５のｃ軸１６は、第３方向Ｄ３と交差する。すなわち、窒化物半導体層として、半極性面または無極性面の窒化物半導体を用いる。これにより、内部電界が抑制される。例えば、機能層に生じる内部電界が抑制される。このとき、窒化物半導体層１５のｃ軸１６を、第１方向Ｄ１に対して傾斜させる。これにより、例えば、熱膨張係数の面内異方性が抑制される。これにより、反りが抑制され、クラックも抑制される。装置の特性を向上させつつ、生産において高い歩留まりが得られる。   In the embodiment, the c-axis 16 of the nitride semiconductor layer 15 intersects the third direction D3. That is, as the nitride semiconductor layer, a semipolar or nonpolar nitride semiconductor is used. Thereby, an internal electric field is suppressed. For example, an internal electric field generated in the functional layer is suppressed. At this time, the c-axis 16 of the nitride semiconductor layer 15 is inclined with respect to the first direction D1. Thereby, for example, in-plane anisotropy of the thermal expansion coefficient is suppressed. Thereby, a curvature is suppressed and a crack is also suppressed. A high yield can be obtained in production while improving the characteristics of the apparatus.

窒化物半導体層１５は、複数の斜面４１のそれぞれから成長した結晶が合体して形成される。複数の結晶のそれぞれが、複数の領域（例えば第１領域１５ａ及び第２領域１５ｂなど）のそれぞれとなる。これらの複数の領域の境界１７において、結晶が合体する。結晶が合体する境界１７においては、応力が生じる。例えば、境界１７と交差する方向に引っ張り応力が生じる。もし、境界１７において、熱膨張係数の異方性が大きい場合は、境界１７において、１つの方向に大きな応力が加わる。その結果、反りやクラックが生じやすい。   The nitride semiconductor layer 15 is formed by combining crystals grown from each of the plurality of inclined surfaces 41. Each of the plurality of crystals becomes each of a plurality of regions (for example, the first region 15a and the second region 15b). Crystals coalesce at the boundaries 17 of these multiple regions. Stress is generated at the boundary 17 where the crystals merge. For example, a tensile stress is generated in a direction crossing the boundary 17. If the anisotropy of the thermal expansion coefficient is large at the boundary 17, a large stress is applied in one direction at the boundary 17. As a result, warpage and cracks are likely to occur.

本実施形態に係る窒化物半導体層１５においては、２つの領域（例えば第１領域１５ａ及び第２領域１５ｂ）の境界１７の延在方向（第１方向Ｄ１）に対して、ｃ軸１６を傾斜させる。すなわち、第２方向Ｄ２に対して、ｃ軸１６を傾斜させる。これにより、境界１７において生じる熱膨張係数の異方性を小さくできる。実施形態によれば、応力が緩和され、反りが抑制でき、クラックが抑制できる。   In the nitride semiconductor layer 15 according to the present embodiment, the c-axis 16 is inclined with respect to the extending direction (first direction D1) of the boundary 17 between two regions (for example, the first region 15a and the second region 15b). Let That is, the c-axis 16 is inclined with respect to the second direction D2. Thereby, the anisotropy of the thermal expansion coefficient which arises in the boundary 17 can be made small. According to the embodiment, stress is relaxed, warpage can be suppressed, and cracks can be suppressed.

実施形態によれば、高生産性の窒化物半導体層及び窒化物半導体装置が得られる。
熱膨張係数の異方性については、後述する。 According to the embodiment, a highly productive nitride semiconductor layer and nitride semiconductor device can be obtained.
The anisotropy of the thermal expansion coefficient will be described later.

図２は、第１の実施形態に係る窒化物半導体装置を例示する模式的断面図である。
図２に示した例では、窒化物半導体層１５は、例えば、下地層５０と、機能層１０と、を含む。この例では、窒化物半導体層１５は、バッファ層６０をさらに含む。 FIG. 2 is a schematic cross-sectional view illustrating the nitride semiconductor device according to the first embodiment.
In the example illustrated in FIG. 2, the nitride semiconductor layer 15 includes, for example, a foundation layer 50 and a functional layer 10. In this example, the nitride semiconductor layer 15 further includes a buffer layer 60.

基板４０は、例えば、（１１３）面のシリコン基板である。   The substrate 40 is, for example, a (113) plane silicon substrate.

基板４０は、複数の凹部４５を有する。複数の凹部４５のそれぞれには、複数の斜面４１が設けられる。   The substrate 40 has a plurality of recesses 45. A plurality of slopes 41 are provided in each of the plurality of recesses 45.

基板４０の一部（複数の斜面４１）の上にバッファ層６０が設けられる。バッファ層６０の上に下地層５０が設けられる。下地層５０の上に機能層１０が設けられる。基板４０の上に、バッファ層６０、下地層５０、及び、機能層１０がこの順で順次形成される。これらの形成においてエピタキシャル成長が行われる。バッファ層６０、下地層５０及び機能層１０は、窒化物半導体である。   A buffer layer 60 is provided on a part of the substrate 40 (a plurality of inclined surfaces 41). A base layer 50 is provided on the buffer layer 60. The functional layer 10 is provided on the foundation layer 50. On the substrate 40, the buffer layer 60, the base layer 50, and the functional layer 10 are sequentially formed in this order. In these formations, epitaxial growth is performed. The buffer layer 60, the foundation layer 50, and the functional layer 10 are nitride semiconductors.

基板４０の凹部４５を除く上面４０ｕに、マスク層６４が設けられても良い。マスク層６４には、例えば、酸化シリコン膜（ＳｉＯ２）や窒化シリコン膜（ＳｉＮｘ）が用いられる。マスク層６４の上の少なくとも一部の上には、バッファ層６０が設けられない場合がある。バッファ層６０の上、及び、マスク層６４の上に、下地層５０が設けられる。 A mask layer 64 may be provided on the upper surface 40 u excluding the recess 45 of the substrate 40. For the mask layer 64, for example, a silicon oxide film (SiO 2) or a silicon nitride film (SiN x ) is used. The buffer layer 60 may not be provided on at least a part of the mask layer 64. An underlayer 50 is provided on the buffer layer 60 and the mask layer 64.

バッファ層６０は、例えば、ＡｌＮ層を含む。ＡｌＮ層の厚さは、例えば約１００ナノメートル（ｎｍ）である。ＡｌＮ層は、基板４０に接する。   The buffer layer 60 includes, for example, an AlN layer. The thickness of the AlN layer is, for example, about 100 nanometers (nm). The AlN layer is in contact with the substrate 40.

バッファ層６０は、ＧａＮを含んでも良い。バッファ層６０としてＧａＮを用いる場合、ＧａＮ層の厚さは、例えば、約３０ｎｍである。バッファ層６０には、窒化物半導体の混晶（例えば、ＡｌＧａＮまたはＩｎＧａＮなど）を用いても良い。   The buffer layer 60 may contain GaN. When GaN is used as the buffer layer 60, the thickness of the GaN layer is, for example, about 30 nm. The buffer layer 60 may be a nitride semiconductor mixed crystal (for example, AlGaN or InGaN).

ＡｌＮにおいては、シリコンとの化学的反応が生じにくい。基板４０にシリコン基板を用いる場合、ＡｌＮをシリコン基板と接するバッファ層６０として用いる。これにより、例えば、シリコンとガリウムとの反応によって生じるメルトバックエッチングなどが抑制される。   AlN hardly causes chemical reaction with silicon. When a silicon substrate is used as the substrate 40, AlN is used as the buffer layer 60 in contact with the silicon substrate. Thereby, for example, meltback etching caused by the reaction between silicon and gallium is suppressed.

バッファ層６０において、ＡｌＮ層は、単結晶であることが好ましい。ＡｌＮを１０００℃以上の高温でエピタキシャル成長させることで、単結晶のＡｌＮ層を形成できる。   In the buffer layer 60, the AlN layer is preferably a single crystal. A single crystal AlN layer can be formed by epitaxially growing AlN at a high temperature of 1000 ° C. or higher.

シリコンと窒化物半導体との間の熱膨張係数の差は大きい。基板４０としてシリコン基板を用いる場合、窒化物半導体との熱膨張係数差は、他の材料と比べて大きい。このため、エピタキシャル成長後に生じる基板４０の反りが大きくなり、特にクラックが生じやすい。   The difference in thermal expansion coefficient between silicon and nitride semiconductor is large. When a silicon substrate is used as the substrate 40, the difference in thermal expansion coefficient from the nitride semiconductor is larger than that of other materials. For this reason, the warp of the substrate 40 generated after epitaxial growth becomes large, and cracks are particularly likely to occur.

例えば、単結晶のＡｌＮのバッファ層６０を用いることで、エピタキシャル成長中に窒化物半導体中に応力を形成することができる。これにより、成長終了後の基板４０の反りを抑制できる。   For example, by using a single crystal AlN buffer layer 60, stress can be formed in the nitride semiconductor during epitaxial growth. Thereby, the curvature of the board | substrate 40 after completion | finish of growth can be suppressed.

バッファ層６０（ＡｌＮ層）には、引っ張り応力（歪み）が形成されていることが好ましい。ＡｌＮ層に引っ張り応力（歪み）が形成されることで、基板４０とバッファ層６０との界面での欠陥形成が抑制される。   It is preferable that tensile stress (strain) is formed in the buffer layer 60 (AlN layer). By forming tensile stress (strain) in the AlN layer, defect formation at the interface between the substrate 40 and the buffer layer 60 is suppressed.

下地層５０は、例えばＧａＮ層を含む。下地層５０は、インジウム（Ｉｎ）を含んでも良い。下地層５０がＩｎを含むことで、下地層５０と基板４０（例えばシリコン基板）との格子不整合が緩和され、転位の発生が抑制される。下地層５０がＩｎを含む場合、結晶成長中にＩｎの脱離反応が発生しやすい。Ｉｎ組成比を０．５以下とすることが好ましい。これにより、平坦性の良い下地層５０を得ることができる。   The underlayer 50 includes, for example, a GaN layer. The underlayer 50 may contain indium (In). When the underlayer 50 contains In, lattice mismatch between the underlayer 50 and the substrate 40 (for example, a silicon substrate) is alleviated, and the occurrence of dislocation is suppressed. When the underlayer 50 contains In, an In elimination reaction is likely to occur during crystal growth. The In composition ratio is preferably 0.5 or less. Thereby, the foundation layer 50 with good flatness can be obtained.

下地層５０は、基板４０の複数の凹部４５の側面（斜面４１）のそれぞれから選択的に成長される。隣接する凹部４５の側面のそれぞれから成長された複数の結晶（ＧａＮ結晶）が会合する。複数の結晶が合体する。成長を続けると、ＧａＮ結晶の上面（第１面１５ｆ）は、平坦になり、基板４０の上面４０ｕ（主面４０ａ）に対して平行になる。   The underlayer 50 is selectively grown from each of the side surfaces (slope surfaces 41) of the plurality of recesses 45 of the substrate 40. A plurality of crystals (GaN crystals) grown from the side surfaces of the adjacent recesses 45 are associated. Multiple crystals coalesce. If the growth is continued, the upper surface (first surface 15f) of the GaN crystal becomes flat and becomes parallel to the upper surface 40u (main surface 40a) of the substrate 40.

例えば、基板４０として、（１１３）面のシリコン基板を用いる場合には、窒化物半導体層１５の（１１−２２）面が、第１面１５ｆに対して平行になる。すなわち、（１１−２２）面が、基板４０の上面４０ｕ（主面４０ａ）に対して平行となる。このとき、窒化物半導体層１５のｃ軸１６と、第１面１５ｆに対して垂直な軸（Ｚ軸）と、の間の角度は、約５８度である。すなわち、窒化物半導体層１５のｃ軸１６と、第１面１５ｆと、の間の角度θ１は、約３２度である。   For example, when a (113) plane silicon substrate is used as the substrate 40, the (11-22) plane of the nitride semiconductor layer 15 is parallel to the first plane 15f. That is, the (11-22) plane is parallel to the upper surface 40u (main surface 40a) of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the axis (Z-axis) perpendicular to the first surface 15f is about 58 degrees. That is, the angle θ1 between the c-axis 16 of the nitride semiconductor layer 15 and the first surface 15f is about 32 degrees.

このように、凹凸（複数の凹部４５）が形成された基板４０を用い、凹部４５の側面上に、選択的に窒化物半導体結晶を成長させる。これにより、窒化物半導体層１５（例えば下地層５０）のｃ軸１６は、基板４０の上面４０ｕ（主面４０ａ）に対して傾斜する。   In this way, a nitride semiconductor crystal is selectively grown on the side surface of the recess 45 using the substrate 40 having the recesses and projections (the plurality of recesses 45). Thereby, the c-axis 16 of the nitride semiconductor layer 15 (for example, the foundation layer 50) is inclined with respect to the upper surface 40u (main surface 40a) of the substrate 40.

機能層１０におけるｃ軸は、下地層５０におけるｃ軸に対して、実質的に平行である。従って、機能層１０のｃ軸１６は、第２方向Ｄ２に対して傾斜する。機能層１０のｃ軸１６は、第３方向Ｄ３（上面４０ｕに対して垂直な方向）に対して傾斜する。   The c axis in the functional layer 10 is substantially parallel to the c axis in the base layer 50. Accordingly, the c-axis 16 of the functional layer 10 is inclined with respect to the second direction D2. The c-axis 16 of the functional layer 10 is inclined with respect to the third direction D3 (direction perpendicular to the upper surface 40u).

この例では、窒化物半導体装置１１０は、発光装置である。機能層１０は、例えば、第１半導体層１１と、活性層１３（例えば発光層）と、第２半導体層１２と、を含む。第２半導体層１２と基板４０との間に第１半導体層１１が配置される。第２半導体層１２は、第３方向Ｄ３において、第１半導体層１１と離間している。第２半導体層１２と第１半導体層１１との間に活性層１３が配置される。第１半導体層は第１導電形である。第２半導体層は第２導電形である。第１導電形は、例えばｎ形であり、第２導電形は、例えばｐ形である。   In this example, the nitride semiconductor device 110 is a light emitting device. The functional layer 10 includes, for example, a first semiconductor layer 11, an active layer 13 (for example, a light emitting layer), and a second semiconductor layer 12. The first semiconductor layer 11 is disposed between the second semiconductor layer 12 and the substrate 40. The second semiconductor layer 12 is separated from the first semiconductor layer 11 in the third direction D3. An active layer 13 is disposed between the second semiconductor layer 12 and the first semiconductor layer 11. The first semiconductor layer is of the first conductivity type. The second semiconductor layer is of the second conductivity type. The first conductivity type is, for example, n-type, and the second conductivity type is, for example, p-type.

活性層１３は、複数の障壁層と、複数の障壁層の間に設けられた井戸層と、を含む。障壁層には、例えばＧａＮが用いられる。井戸層には、例えば、ＩｎＧａＮ（例えば、Ｉｎ０．１５Ｇａ０．８５Ｎ）が用いられる。活性層１３は、ＭＱＷ（Multi-Quantum Well）構造、または、ＳＱＷ（Single-Quantum Well）構造を有する。機能層１０の厚さは、例えば１マイクロメートル（μｍ）以上５μｍ以下であり、例えば約３．５μｍである。機能層１０の厚さは、例えば約２μｍでも良い。 The active layer 13 includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers. For example, GaN is used for the barrier layer. For example, InGaN (for example, In 0.15 Ga 0.85 N) is used for the well layer. The active layer 13 has an MQW (Multi-Quantum Well) structure or an SQW (Single-Quantum Well) structure. The thickness of the functional layer 10 is, for example, not less than 1 micrometer (μm) and not more than 5 μm, for example, about 3.5 μm. The thickness of the functional layer 10 may be about 2 μm, for example.

この例では、基板４０の上に、第１半導体層１１、活性層１３及び第２半導体層１２がこの順で積層されている。   In this example, the first semiconductor layer 11, the active layer 13, and the second semiconductor layer 12 are stacked in this order on the substrate 40.

この明細書において、積層されている状態は、互いに接して重ねられる状態、及び、間に他の層が挿入されて重ねられる状態を含む。上に設けられる状態は、直接接して設けられる状態、及び、間に他の層が挿入されて設けられる状態を含む。   In this specification, the state of being stacked includes a state of being stacked in contact with each other and a state of being stacked with another layer interposed therebetween. The state provided above includes a state provided in direct contact and a state provided with another layer interposed therebetween.

後述するように、窒化物半導体装置１１０において、基板４０と、バッファ層６０と、下地層５０と、が除去された状態で使用される場合がある。   As will be described later, in the nitride semiconductor device 110, the substrate 40, the buffer layer 60, and the base layer 50 may be used in a state where they are removed.

例えば、機能層１０の少なくとも一部（例えば第１半導体層１１及び第２半導体層１２の少なくともいずれか）における不純物濃度は、下地層５０における不純物濃度よりも高い。   For example, the impurity concentration in at least a part of the functional layer 10 (for example, at least one of the first semiconductor layer 11 and the second semiconductor layer 12) is higher than the impurity concentration in the base layer 50.

図３（ａ）〜図３（ｃ）は、第１の実施形態に係る窒化物半導体装置の製造方法を例示する工程順模式的断面図である。
図３（ａ）に示すように、基板４０を用意する。例えば、基板４０には、例えば、（１１３）面のシリコン基板が用いられる。シリコン基板のオリエンテーションフラットの方位は、例えば、＜−１１０＞方向である。シリコン基板の上に、マスク層６４となる酸化シリコン膜６４ｆが形成されている。酸化シリコン膜６４ｆは、例えば、熱酸化膜である。酸化シリコン膜６４ｆの厚さは、例えば、約１００ナノメートル（ｎｍ）である。酸化シリコン膜６４ｆの上に、所定の形状のレジスト膜６５を形成する。レジスト膜６５の形状は、例えば、ストライプ状である。ストライプの延在方向を、基板４０の結晶方位に対して所定の角度で傾斜させる。ストライプの延在方向は、シリコンの＜２１−１＞方向から、＜１１０＞方向に、所定の角度で傾斜する。傾斜の角度は、５度以上８５度以下である。 FIG. 3A to FIG. 3C are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the nitride semiconductor device according to the first embodiment.
As shown in FIG. 3A, a substrate 40 is prepared. For example, as the substrate 40, for example, a (113) plane silicon substrate is used. The orientation of the orientation flat of the silicon substrate is, for example, the <−110> direction. A silicon oxide film 64f to be a mask layer 64 is formed on the silicon substrate. The silicon oxide film 64f is, for example, a thermal oxide film. The thickness of the silicon oxide film 64f is, for example, about 100 nanometers (nm). A resist film 65 having a predetermined shape is formed on the silicon oxide film 64f. The shape of the resist film 65 is, for example, a stripe shape. The extending direction of the stripe is inclined at a predetermined angle with respect to the crystal orientation of the substrate 40. The extending direction of the stripe is inclined at a predetermined angle from the <21-1> direction of silicon to the <110> direction. The angle of inclination is not less than 5 degrees and not more than 85 degrees.

レジスト膜６５の幅（ストライプの延在方向に対して直交する方向の長さ）は、例えば約３μｍである。レジスト膜６５の開口部の幅（複数のストライプどうしの間隔）は、例えば約７μｍである。ストライプの周期は、例えば約１０μｍである。   The width of the resist film 65 (the length in the direction orthogonal to the stripe extending direction) is, for example, about 3 μm. The width of the opening of the resist film 65 (interval between the plurality of stripes) is, for example, about 7 μm. The period of the stripe is about 10 μm, for example.

レジスト膜６５をマスクとして、開口部の酸化シリコン膜６４ｆを除去する。除去においては、例えば、バッファードフッ酸を用いたエッチングが行われる。除去の前に、Ｏ２アッシャ処理を行っても良い。親水性が向上し、エッチングの均一性が向上する。酸化シリコン膜６４ｆの一部の除去の後に、レジスト膜６５を除去する。これにより、マスク層６４が形成される。   Using the resist film 65 as a mask, the silicon oxide film 64f in the opening is removed. In the removal, for example, etching using buffered hydrofluoric acid is performed. Prior to removal, O2 ashing may be performed. Hydrophilicity is improved and etching uniformity is improved. After removing part of the silicon oxide film 64f, the resist film 65 is removed. Thereby, the mask layer 64 is formed.

図３（ｂ）に示すように、マスク層６４をマスクとして用いて、基板４０を加工する。すなわち、基板４０に複数のストライプ状の凹部４５を形成する。この加工においては、例えば、水酸化カリウム（ＫＯＨ）溶液（２５ｗｔ％、４５℃）を用い、例えば１５分間の処理が行われる。シリコンのエッチングレートの異方性により、凹部４５の側面は、Ｚ軸に対して傾斜する。すなわち、斜面４１が形成される。シリコンをＫＯＨ溶液でエッチングする場合、シリコンの（１１１）面のエッチングレートが他の結晶面に比べて遅いため、シリコンの（１１１）面が斜面４１として形成されやすい。この加工において、ドライエッチング処理を用いて斜面４１を形成しても良い。   As shown in FIG. 3B, the substrate 40 is processed using the mask layer 64 as a mask. That is, a plurality of striped recesses 45 are formed in the substrate 40. In this processing, for example, a potassium hydroxide (KOH) solution (25 wt%, 45 ° C.) is used, and for example, a treatment for 15 minutes is performed. Due to the anisotropy of the etching rate of silicon, the side surface of the recess 45 is inclined with respect to the Z axis. That is, the slope 41 is formed. When silicon is etched with a KOH solution, the (111) plane of silicon is likely to be formed as the inclined surface 41 because the etching rate of the (111) plane of silicon is slower than other crystal planes. In this processing, the slope 41 may be formed using a dry etching process.

これにより、側面が傾斜した複数の凹部４５を有する基板４０が得られる。凹部４５の側面（側壁）の一部は、シリコンの（１−１１）面となる。この側面（斜面４１）は、基板４０の上面４０ｕの（１１３）面に対して傾斜する。側面（斜面４１）と、（１１３）面との間の角度は、約５８．５度である。この斜面４１（すなわち、（１−１１）面）から窒化物結晶が成長される。側面（側壁）の一部は、（１−１１）面に限らず、（１１−１）面や（−１１−１）面などの（１１１）面と等価な結晶面（ミラー指数の包括表現で｛１１１｝面で表される結晶面）であれば良い。シリコンの（１１１）面と等価な結晶面を形成することで、窒化物結晶の結晶成長が可能となる。   Thereby, the board | substrate 40 which has the some recessed part 45 in which the side surface inclined was obtained. A part of the side surface (side wall) of the recess 45 is a (1-11) surface of silicon. The side surface (inclined surface 41) is inclined with respect to the (113) surface of the upper surface 40u of the substrate 40. The angle between the side surface (inclined surface 41) and the (113) surface is about 58.5 degrees. A nitride crystal is grown from the slope 41 (that is, the (1-11) plane). A part of the side surface (side wall) is not limited to the (1-11) plane, but is a crystal plane equivalent to the (111) plane such as the (11-1) plane or the (-11-1) plane (a comprehensive expression of the Miller index) Or a crystal plane represented by {111} plane). By forming a crystal plane equivalent to the (111) plane of silicon, nitride crystal can be grown.

図３（ｃ）に示すように、基板４０の斜面４１の上に、バッファ層６０を形成する。さらに、バッファ層６０の上に、下地層５０を形成し、下地層５０の上に、機能層１０をエピタキシャル成長させる。エピタキシャル成長の例について、以下説明する。   As shown in FIG. 3C, the buffer layer 60 is formed on the slope 41 of the substrate 40. Further, the base layer 50 is formed on the buffer layer 60, and the functional layer 10 is epitaxially grown on the base layer 50. An example of epitaxial growth will be described below.

例えば、斜面４１が形成された上記の基板４０を、有機洗浄及び酸洗浄によって処理する。この後、基板４０をＭＯＣＶＤ装置の反応室内に導入する。トリメチルアルミニウム（ＴＭＡｌ）及びアンモニア（ＮＨ３）を用い、バッファ層６０となるＡｌＮ層を形成する。バッファ層６０の厚さは、約１００ｎｍである。 For example, the substrate 40 on which the inclined surface 41 is formed is processed by organic cleaning and acid cleaning. Thereafter, the substrate 40 is introduced into the reaction chamber of the MOCVD apparatus. An AlN layer to be the buffer layer 60 is formed using trimethylaluminum (TMAl) and ammonia (NH 3 ). The thickness of the buffer layer 60 is about 100 nm.

その後、窒素及び水素を含む雰囲気にて、ＴＭＧａ及びアンモニアを用い、下地層５０の一部となるアンドープのＧａＮ層を成長させる。このときの成長温度は約１０６０℃であり、成長圧力は６００ｈＰａであり、Ｖ／III比は、３３００である。このアンドープのＧａＮ層は、凹部４５の側面（側壁）である（１−１１）面（すなわち斜面４１）から成長する。   Thereafter, an undoped GaN layer to be a part of the base layer 50 is grown using TMGa and ammonia in an atmosphere containing nitrogen and hydrogen. At this time, the growth temperature is about 1060 ° C., the growth pressure is 600 hPa, and the V / III ratio is 3300. The undoped GaN layer grows from the (1-11) plane (that is, the inclined surface 41) which is the side surface (side wall) of the recess 45.

これにより、ｃ軸１６が基板４０の上面４０ｕ（主面４０ａ）に対して垂直な方向から５８．５度傾斜したＧａＮ結晶が得られる。すなわち、ＧａＮ層のｃ軸１６と、上面４０ｕと、の間の角度θ１は、３１．５度である。   Thereby, a GaN crystal in which the c-axis 16 is inclined by 58.5 degrees from the direction perpendicular to the upper surface 40u (main surface 40a) of the substrate 40 is obtained. That is, the angle θ1 between the c-axis 16 of the GaN layer and the upper surface 40u is 31.5 degrees.

アンドープＧａＮ層の成長初期では、アンドープＧａＮ層は、ストライプ状の結晶である。成長時間を長くすることで、隣り合うストライプ状の結晶が会合する。これにより、アンドープＧａＮ層の主面（表面）は、（１１−２２）面となる。   At the initial growth stage of the undoped GaN layer, the undoped GaN layer is a stripe crystal. By increasing the growth time, adjacent stripe crystals are associated. Thereby, the main surface (surface) of the undoped GaN layer becomes the (11-22) plane.

さらに結晶成長を続け、下地層５０が形成される。この上に、第１半導体層１１、活性層１３及び第２半導体層１２を形成して、機能層１０が形成される。これにより、窒化物半導体装置１１０が得られる。   Further, the crystal growth is continued and the underlayer 50 is formed. On this, the 1st semiconductor layer 11, the active layer 13, and the 2nd semiconductor layer 12 are formed, and the functional layer 10 is formed. Thereby, the nitride semiconductor device 110 is obtained.

以下、窒化物半導体層１５に関する実験結果の例について説明する。
この実験においては、基板４０に形成される凹部４５の延在方向（第１方向Ｄ１）を変更する。すなわち、レジスト膜６５のストライプの延在方向を変更する。レジスト膜６５のストライプの延在方向と、シリコンの＜２１−１＞方向と、の角度を変更する。第１試料においては、レジスト膜６５のストライプの延在方向は、シリコンの＜２１−１＞方向に対して平行である（傾斜角度は０度）。第２試料においては、レジスト膜６５のストライプの延在方向は、シリコンの＜２１−１＞方向から、＜１１０＞方向に１３度傾斜する（傾斜角度は１３度）。第３試料においては、レジスト膜６５のストライプの延在方向は、シリコンの＜２１−１＞方向から、＜１１０＞方向に１８度傾斜する（傾斜角度は１８度）。 Hereinafter, an example of an experimental result regarding the nitride semiconductor layer 15 will be described.
In this experiment, the extending direction (first direction D1) of the recess 45 formed in the substrate 40 is changed. That is, the stripe extending direction of the resist film 65 is changed. The angle between the stripe extending direction of the resist film 65 and the <21-1> direction of silicon is changed. In the first sample, the stripe extending direction of the resist film 65 is parallel to the <21-1> direction of silicon (the tilt angle is 0 degree). In the second sample, the extending direction of the stripe of the resist film 65 is tilted 13 degrees in the <110> direction from the <21-1> direction of silicon (the tilt angle is 13 degrees). In the third sample, the stripe extending direction of the resist film 65 is inclined by 18 degrees in the <110> direction from the <21-1> direction of silicon (the inclination angle is 18 degrees).

第１〜第３試料においては、レジスト膜６５の幅は、約３μｍである。レジスト膜６５の開口部の幅は、約７μｍである。ストライプの周期は、約１０μｍである。   In the first to third samples, the width of the resist film 65 is about 3 μm. The width of the opening of the resist film 65 is about 7 μm. The period of the stripe is about 10 μm.

このような３種類の基板４０の上に、バッファ層６０としてＡｌＮ層を形成し、さらに、下地層５０のＧａＮ層を形成する。その際、ＧａＮ層の成長時間を変化させて、ＧａＮ層の成長の様子が観察される。成長時間が９０分間のときに、ＧａＮ層の厚さは、約２μｍである。   On these three types of substrates 40, an AlN layer is formed as the buffer layer 60, and a GaN layer as the underlayer 50 is further formed. At this time, the growth of the GaN layer is observed by changing the growth time of the GaN layer. When the growth time is 90 minutes, the thickness of the GaN layer is about 2 μm.

図４（ａ）〜図４（ｃ）は、窒化物半導体装置に関する実験結果を例示する電子顕微鏡写真像である。
図４（ａ）〜図４（ｃ）のそれぞれは、上記の第１試料ＳＰ１０、第２試料ＳＰ２０及び第３試料ＳＰ３０のそれぞれに対応する。これらの電子顕微鏡写真は、基板４０の上面４０ｕ（主面４０ａ）に対して垂直な方向（第３方向Ｄ３）から観察したＳＥＭ像である。これらの例では、ＧａＮ層の成長時間が３０分であり、ＧａＮ層の成長の途中の段階である。すなわち、凹部４５の複数の側面のそれぞれから成長した複数の結晶が合体する前の状態である。 FIG. 4A to FIG. 4C are electron micrograph images illustrating experimental results regarding the nitride semiconductor device.
Each of FIG. 4A to FIG. 4C corresponds to each of the first sample SP10, the second sample SP20, and the third sample SP30. These electron micrographs are SEM images observed from a direction (third direction D3) perpendicular to the upper surface 40u (main surface 40a) of the substrate 40. In these examples, the growth time of the GaN layer is 30 minutes, which is a stage in the middle of the growth of the GaN layer. That is, it is a state before a plurality of crystals grown from each of the plurality of side surfaces of the recess 45 are combined.

図４（ａ）に示すように、基板４０の凹部４５と、上面４０ｕ（マスク層６４）と、下地層５０の一部となる成長初期のＧａＮ層５１と、が観察される。このＧａＮ層５１は、凹部４５に沿ったストライプ状である。   As shown in FIG. 4A, the concave portion 45 of the substrate 40, the upper surface 40 u (mask layer 64), and the GaN layer 51 in the initial stage of growth that becomes a part of the foundation layer 50 are observed. The GaN layer 51 has a stripe shape along the recess 45.

第１試料ＳＰ１０においては、凹部４５の延在方向（第１方向Ｄ１）は、＜２１−１＞方向に沿っている。この場合、ＧａＮ層５１のｃ軸をＸ−Ｙ平面（第１面１５ｆすなわち、基板４０の上面４０ｕ）に投影した方向１６ｐは、凹部４５の延在方向（第１方向Ｄ１）に対して垂直な方向（第２方向Ｄ２）に沿う。第１試料ＳＰ１０においては、ＧａＮ層５１のｃ軸は、凹部４５の延在方向に対して垂直となる。ＧａＮ層５１の表面において、稜線５２（段差）が観察される。稜線５２は、凹部４５の延在方向（第１方向Ｄ１）に対して垂直な方向（第２方向Ｄ２）に沿う。稜線５２は、結晶表面の凹凸に由来する。この稜線５２の延在方向は、方向１６ｐに沿っている。   In the first sample SP10, the extending direction of the recess 45 (first direction D1) is along the <21-1> direction. In this case, the direction 16p in which the c-axis of the GaN layer 51 is projected onto the XY plane (first surface 15f, that is, the upper surface 40u of the substrate 40) is perpendicular to the extending direction of the recess 45 (first direction D1). Along the other direction (second direction D2). In the first sample SP10, the c-axis of the GaN layer 51 is perpendicular to the extending direction of the recess 45. On the surface of the GaN layer 51, a ridgeline 52 (step) is observed. The ridge line 52 is along a direction (second direction D2) perpendicular to the extending direction (first direction D1) of the recess 45. The ridge line 52 is derived from irregularities on the crystal surface. The extending direction of the ridge line 52 is along the direction 16p.

図４（ｂ）に示すように、第２試料ＳＰ２０（傾斜角が１３度）においては、ＧａＮ層５１のｃ軸をＸ−Ｙ平面に投影した方向１６ｐは、凹部４５の延在方向（第１方向Ｄ１）に対して垂直な方向（第２方向Ｄ２）に対して傾斜する。方向１６ｐと第２方向Ｄ２との間の角度は、傾斜角と同じであり、１３度である。稜線５２の延在方向と、第２方向Ｄ２と、の間の角度は、１３度である。   As shown in FIG. 4B, in the second sample SP20 (inclination angle of 13 degrees), the direction 16p obtained by projecting the c-axis of the GaN layer 51 onto the XY plane is the extending direction of the recess 45 (first It is inclined with respect to a direction (second direction D2) perpendicular to one direction D1). The angle between the direction 16p and the second direction D2 is the same as the tilt angle and is 13 degrees. The angle between the extending direction of the ridgeline 52 and the second direction D2 is 13 degrees.

図４（ｃ）に示すように、第３試料ＳＰ３０（傾斜角が１８度）においても、ＧａＮ層５１のｃ軸をＸ−Ｙ平面に投影した方向１６ｐは、凹部４５の延在方向（第１方向Ｄ１）に対して垂直な方向（第２方向Ｄ２）に対して傾斜する。方向１６ｐと第２方向Ｄ２との間の角度は、傾斜角と同じであり、１８度である。稜線５２の延在方向と、第２方向Ｄ２と、の間の角度は、１８度である。   As shown in FIG. 4C, in the third sample SP30 (inclination angle of 18 degrees), the direction 16p in which the c-axis of the GaN layer 51 is projected on the XY plane is the extending direction of the recess 45 (first It is inclined with respect to a direction (second direction D2) perpendicular to one direction D1). The angle between the direction 16p and the second direction D2 is the same as the tilt angle and is 18 degrees. The angle between the extending direction of the ridge line 52 and the second direction D2 is 18 degrees.

図４（ｂ）及び図４（ｃ）に示す例と同様に、例えば、主面１５ｆに対して垂直な方向（第３方向Ｄ３）から観察したＳＥＭ像において、稜線５２の延在方向と第２方向Ｄ２との間の角度が分かる。この角度により、方向１６ｐが第２方向Ｄ２に対して傾斜していることが判断できる。   Similar to the example shown in FIGS. 4B and 4C, for example, in the SEM image observed from the direction (third direction D3) perpendicular to the main surface 15f, the extension direction of the ridge line 52 and the first direction The angle between the two directions D2 is known. From this angle, it can be determined that the direction 16p is inclined with respect to the second direction D2.

図５（ａ）及び図５（ｂ）は、窒化物半導体装置に関する実験結果を例示する電子顕微鏡写真像である。
図５（ａ）及び図５（ｂ）は、以下の第４試料ＳＰ１１及び第５試料ＳＰ３１のそれぞれに対応する。これらの試料においては、レジスト膜６５の幅は、約２．５μｍである。レジスト膜６５の開口部の幅は、約２．５μｍである。ストライプの周期は、約５μｍである。すなわち、第４試料ＳＰ１１及び第５試料ＳＰ３１においては、レジスト膜６５のストライプの周期は、第１〜第３試料ＳＰ１０〜ＳＰ３０に比べて短い。 FIG. 5A and FIG. 5B are electron micrograph images illustrating experimental results regarding the nitride semiconductor device.
FIGS. 5A and 5B correspond to the following fourth sample SP11 and fifth sample SP31, respectively. In these samples, the width of the resist film 65 is about 2.5 μm. The width of the opening of the resist film 65 is about 2.5 μm. The period of the stripe is about 5 μm. That is, in the fourth sample SP11 and the fifth sample SP31, the stripe period of the resist film 65 is shorter than that of the first to third samples SP10 to SP30.

第４試料ＳＰ１１においては、レジスト膜６５のストライプの延在方向は、シリコンの＜２１−１＞方向に対して平行である（傾斜角度は０度）。第５試料ＳＰ３１においては、レジスト膜６５のストライプの延在方向は、シリコンの＜２１−１＞方向から、＜１１０＞方向に１８度傾斜する（傾斜角度は１８度）。   In the fourth sample SP11, the stripe extending direction of the resist film 65 is parallel to the <21-1> direction of silicon (the tilt angle is 0 degree). In the fifth sample SP31, the stripe extending direction of the resist film 65 is inclined by 18 degrees in the <110> direction from the <21-1> direction of silicon (the inclination angle is 18 degrees).

第４試料ＳＰ１１及び第５試料ＳＰ３１においては、ＧａＮ層５１の成長時間は、６０分であり、第１〜第３試料ＳＰ１０〜ＳＰ３０に比べて長い。   In the fourth sample SP11 and the fifth sample SP31, the growth time of the GaN layer 51 is 60 minutes, which is longer than that of the first to third samples SP10 to SP30.

図５（ａ）に示すように、第４試料ＳＰ１１においては、成長時間を６０分とすることで、隣り合うストライプ状のＧａＮ結晶どうしが会合し、ＧａＮ層５１（下地層５０）が得られる。会合後に成長されたＧａＮ層５１の厚さは、約２．５μｍである。ＧａＮ層５１の主面（表面）は、（１１−２２）面である。このＧａＮ層５１を成長させた後に室温にすると、クラックＣＲが発生する。クラックＣＲの延在方向は、凹部４５の延在方向（第１方向Ｄ１）に対して垂直である。クラックＣＲは、第２方向Ｄ２に沿って延在する。クラックＣＲは、複数のＧａＮ結晶が合体する境界に対して垂直な方向に延在する。第１方向Ｄ１に沿うクラックは、観察されない。複数のクラックＣＲの間隔（第１方向Ｄ１における間隔）は、約５００μｍである。   As shown in FIG. 5A, in the fourth sample SP11, by setting the growth time to 60 minutes, adjacent stripe-shaped GaN crystals are associated with each other, and the GaN layer 51 (underlayer 50) is obtained. . The thickness of the GaN layer 51 grown after the association is about 2.5 μm. The main surface (surface) of the GaN layer 51 is the (11-22) plane. When the GaN layer 51 is grown and then brought to room temperature, a crack CR is generated. The extending direction of the crack CR is perpendicular to the extending direction of the recess 45 (first direction D1). The crack CR extends along the second direction D2. The crack CR extends in a direction perpendicular to a boundary where a plurality of GaN crystals are combined. Cracks along the first direction D1 are not observed. The interval between the plurality of cracks CR (interval in the first direction D1) is about 500 μm.

図５（ｂ）に示すように、第５試料ＳＰ３１においても、成長時間を６０分とすることで、隣り合うストライプ状のＧａＮ結晶どうしが会合し、ＧａＮ層５１（下地層５０）が得られる。ＧａＮ層５１の主面（表面）は、（１１−２２）面である。このＧａＮ層５１を成長させた後に室温にしても、クラックＣＲは観測されない。   As shown in FIG. 5B, also in the fifth sample SP31, by setting the growth time to 60 minutes, adjacent striped GaN crystals are associated with each other, and the GaN layer 51 (underlayer 50) is obtained. . The main surface (surface) of the GaN layer 51 is the (11-22) plane. Even if the GaN layer 51 is grown and then brought to room temperature, no crack CR is observed.

このように、凹部４５の延在方向（第１方向Ｄ１）を、基板４０の結晶方位に対して所定の角度で傾斜させることで、クラックＣＲが抑制できる。この例では、凹部４５の延在方向を、基板４０の＜２−１１＞方向から傾斜させる。ＧａＮ層５１のｃ軸の方位を、基板４０の上面４０ｕ（主面４０ａ）に対して平行な面内（Ｘ−Ｙ面内）で回転できる。ｃ軸の方位を、凹部４５の延在方向に対して垂直な方向（第２方向Ｄ２）から回転することで、クラックＣＲが抑制できる。   In this way, the crack CR can be suppressed by inclining the extending direction of the recess 45 (first direction D1) at a predetermined angle with respect to the crystal orientation of the substrate 40. In this example, the extending direction of the recess 45 is inclined from the <2-11> direction of the substrate 40. The azimuth of the c-axis of the GaN layer 51 can be rotated in a plane parallel to the upper surface 40u (main surface 40a) of the substrate 40 (in the XY plane). By rotating the azimuth of the c-axis from the direction (second direction D2) perpendicular to the extending direction of the recess 45, the crack CR can be suppressed.

図６（ａ）〜図６（ｄ）は、窒化物半導体装置の特性を例示するグラフ図である。
図６（ａ）は、基板４０の凹部４５の延在方向（第１方向Ｄ１）を変えたときの、シリコン基板とＧａＮ層との熱膨張係数の差を例示している。シリコン基板の主面は、（１１３）面である。ＧａＮ層の主面は、（１１−２２）面である。横軸は、第１方向Ｄ１と、シリコンの＜２１−１＞方向と、の間の角度（傾斜角α）である。縦軸は、熱膨張係数差ΔＣである。熱膨張係数差ΔＣは、基板４０の上面４０ｕ（主面４０ａ）に対して平行な２つの方向で異なる。差ΔＣ１は、凹部４５の延在方向（第１方向Ｄ１）における熱膨張係数の差である。差ΔＣ２は、凹部４５の延在方向に対して垂直な方向（第２方向Ｄ２）における熱膨張係数の差である。傾斜角αは、方向１６ｐと第２方向Ｄ２との間の角度に対応する。 FIG. 6A to FIG. 6D are graphs illustrating characteristics of the nitride semiconductor device.
FIG. 6A illustrates the difference in thermal expansion coefficient between the silicon substrate and the GaN layer when the extending direction of the recess 45 of the substrate 40 (first direction D1) is changed. The main surface of the silicon substrate is the (113) surface. The main surface of the GaN layer is the (11-22) plane. The horizontal axis is an angle (inclination angle α) between the first direction D1 and the <21-1> direction of silicon. The vertical axis represents the thermal expansion coefficient difference ΔC. The difference in thermal expansion coefficient ΔC differs in two directions parallel to the upper surface 40u (main surface 40a) of the substrate 40. The difference ΔC1 is a difference in thermal expansion coefficient in the extending direction of the recess 45 (first direction D1). The difference ΔC2 is a difference in thermal expansion coefficient in a direction perpendicular to the extending direction of the recess 45 (second direction D2). The inclination angle α corresponds to the angle between the direction 16p and the second direction D2.

図６（ｂ）は、基板４０の凹部４５の延在方向（第１方向Ｄ１）を変えたときの、シリコン基板とＧａＮ層との熱膨張係数の差を例示している。シリコン基板の主面は、（００１）面である。ＧａＮ層の主面は、（１０−１１）面である。この場合、ｃ軸１６とＧａＮ層の主面との間の角度θ１は、約３２度である。横軸は、第１方向Ｄ１とシリコンの＜−１１０＞方向と、の間の角度（傾斜角α）である。縦軸は、熱膨張係数差ΔＣである。 FIG. 6B illustrates the difference in thermal expansion coefficient between the silicon substrate and the GaN layer when the extending direction of the recess 45 of the substrate 40 (first direction D1) is changed. The main surface of the silicon substrate is the (001) plane. The main surface of the GaN layer is a (10-11) plane. In this case, the angle θ1 between the main surface of the c-axis 16 and the GaN layer is about 32 degrees. The horizontal axis is an angle (inclination angle α) between the first direction D1 and the <−110> direction of silicon. The vertical axis represents the thermal expansion coefficient difference ΔC.

図６（ｃ）は、基板４０の凹部４５の延在方向（第１方向Ｄ１）を変えたときの、シリコン基板とＧａＮ層との熱膨張係数の差を例示している。シリコン基板の主面は、（１１０）面である。ＧａＮ層の主面は、（１１−２０）面である。この場合、ｃ軸１６とＧａＮ層の主面との間の角度θ１は、約０度である。横軸は、第１方向Ｄ１とシリコンの＜−１１２＞方向と、の間の角度（傾斜角α）である。縦軸は、熱膨張係数差ΔＣである。   FIG. 6C illustrates the difference in thermal expansion coefficient between the silicon substrate and the GaN layer when the extending direction (first direction D1) of the recess 45 of the substrate 40 is changed. The main surface of the silicon substrate is the (110) plane. The main surface of the GaN layer is the (11-20) plane. In this case, the angle θ1 between the c-axis 16 and the main surface of the GaN layer is about 0 degree. The horizontal axis is the angle (tilt angle α) between the first direction D1 and the <−112> direction of silicon. The vertical axis represents the thermal expansion coefficient difference ΔC.

図６（ｄ）は、基板４０の凹部４５の延在方向（第１方向Ｄ１）を変えたときの、シリコン基板とＧａＮ層との熱膨張係数の差を例示している。シリコン基板の主面は、（１１２）面である。ＧａＮ層の主面は（１０−１０）面である。この場合、ｃ軸１６とＧａＮ層の主面との間の角度θ１は、約０度である。横軸は、第１方向Ｄ１とシリコンの＜−１１０＞方向と、の間の角度（傾斜角α）である。縦軸は、熱膨張係数差ΔＣである。   FIG. 6D illustrates the difference in thermal expansion coefficient between the silicon substrate and the GaN layer when the extending direction of the recess 45 of the substrate 40 (first direction D1) is changed. The main surface of the silicon substrate is the (112) surface. The main surface of the GaN layer is a (10-10) plane. In this case, the angle θ1 between the c-axis 16 and the main surface of the GaN layer is about 0 degree. The horizontal axis is an angle (inclination angle α) between the first direction D1 and the <−110> direction of silicon. The vertical axis represents the thermal expansion coefficient difference ΔC.

シリコンの熱膨張係数は、例えば、３．５９×１０−６（／Ｋ）である。ＧａＮのａ軸方向の熱膨張係数は、例えば、５．５９×１０−６（／Ｋ）である。ＧａＮのｃ軸方向の熱膨張係数は、例えば、３．１７×１０−６（／Ｋ）である。傾斜角αを変えることで、第１方向Ｄ１における、ＧａＮのａ軸方向の成分及びｃ軸方向の成分の大きさが変化する。連動して、第２方向Ｄ２における、ＧａＮのａ軸方向の成分及びｃ軸方向の成分の大きさが変化する。 The thermal expansion coefficient of silicon is, for example, 3.59 × 10 −6 (/ K). The thermal expansion coefficient of GaN in the a-axis direction is, for example, 5.59 × 10 −6 (/ K). The thermal expansion coefficient in the c-axis direction of GaN is, for example, 3.17 × 10 −6 (/ K). By changing the inclination angle α, the magnitude of the component in the a-axis direction and the component in the c-axis direction of GaN in the first direction D1 changes. In conjunction with this, the magnitudes of the component in the a-axis direction and the component in the c-axis direction of GaN in the second direction D2 change.

図６（ａ）において、傾斜角αが０度の場合は、凹部４５の延在方向（第１方向Ｄ１）が、＜２１−１＞方向に沿う場合に対応する。この場合には、熱膨張係数の差ΔＣ１は、約５６％と大きい。このため、第１方向Ｄ１に対して直交する第２方向Ｄ２に沿って、クラックＣＲが生じると考えられる。   In FIG. 6A, when the inclination angle α is 0 degree, this corresponds to the case where the extending direction of the recess 45 (first direction D1) is along the <21-1> direction. In this case, the thermal expansion coefficient difference ΔC1 is as large as about 56%. For this reason, it is thought that the crack CR occurs along the second direction D2 orthogonal to the first direction D1.

傾斜角αが０度の場合において、熱膨張係数の差ΔＣ２の絶対値は、約２％と小さい。このため、第１方向Ｄ１に沿ったクラックは生じ難いと考えられる。   When the inclination angle α is 0 degree, the absolute value of the difference ΔC2 in the thermal expansion coefficient is as small as about 2%. For this reason, it is thought that the crack along the 1st direction D1 does not produce easily.

シリコンの熱膨張係数は、ＧａＮのａ軸方向の熱膨張係数と、ＧａＮのｃ軸方向の熱膨張係数と、の間である。このため、積層方向（第３方向Ｄ３）に対してｃ軸を傾斜させることで、ＧａＮのａ軸とシリコンとの間の熱膨張係数差と、ＧａＮのｃ軸とシリコンとの間の熱膨張係数差と、が互いに補償するように作用する。その結果、熱膨張係数差の総和が小さくなる。その結果、凹部４５の延在方向に対して垂直な方向には、クラックが生じ難いと考えられる。   The thermal expansion coefficient of silicon is between the thermal expansion coefficient of GaN in the a-axis direction and the thermal expansion coefficient of GaN in the c-axis direction. For this reason, by inclining the c-axis with respect to the stacking direction (third direction D3), the difference in thermal expansion coefficient between the a-axis of GaN and silicon and the thermal expansion between the c-axis of GaN and silicon. The coefficient difference acts to compensate each other. As a result, the sum of the differences in thermal expansion coefficients is reduced. As a result, it is considered that cracks hardly occur in a direction perpendicular to the extending direction of the recess 45.

図６（ａ）に示すように、傾斜角αが大きいと、差ΔＣ１は小さくなる。これは、ＧａＮのｃ軸を第１方向Ｄ１に投影した成分が大きくなるためである。傾斜角αが１８度の場合は、差ΔＣ１は、約４８％となる。すなわち、傾斜角αが０度の場合に比べて、差ΔＣ１は、１０％程度小さくなる。これにより、クラックの形成が抑制されると考えられる。   As shown in FIG. 6A, when the inclination angle α is large, the difference ΔC1 is small. This is because the component obtained by projecting the c-axis of GaN in the first direction D1 becomes large. When the inclination angle α is 18 degrees, the difference ΔC1 is about 48%. That is, the difference ΔC1 is smaller by about 10% than when the inclination angle α is 0 degree. Thereby, it is thought that formation of a crack is suppressed.

一方、傾斜角αが１８度の場合、差ΔＣ２は、増大し、約４％となる。すなわち、熱膨張係数差の異方性（差ΔＣ１と差ΔＣ２との間の差）が小さくなる。これにより、反りの異方性が抑制される。   On the other hand, when the inclination angle α is 18 degrees, the difference ΔC2 increases to about 4%. That is, the anisotropy of the difference in thermal expansion coefficient (the difference between the difference ΔC1 and the difference ΔC2) is reduced. Thereby, the anisotropy of curvature is suppressed.

図６（ｂ）〜図６（ｄ）においても、同様に、傾斜角αが大きいと、差ΔＣ１は小さくなる。一方、差ΔＣ２は増大し、熱膨張係数差の異方性（差ΔＣ１と差ΔＣ２との間の差）が小さくなる。傾斜角αを大きくすることで、第２方向Ｄ２に沿った反りやクラックＣＲを抑制できる。   Similarly, in FIGS. 6B to 6D, the difference ΔC1 decreases as the inclination angle α increases. On the other hand, the difference ΔC2 increases and the anisotropy of the difference in thermal expansion coefficient (the difference between the difference ΔC1 and the difference ΔC2) decreases. By increasing the inclination angle α, warpage and cracks CR along the second direction D2 can be suppressed.

傾斜角αは、５度以上８５度以下であることが好ましい。傾斜角αが５度よりも小さい、または８５度よりも大きい場合には、熱膨張係数差（差ΔＣ１及び差ΔＣ２）の、傾斜角αが０度のときの値からの変化が１％未満である。このため、反りやクラックの抑制の効果が不十分である。傾斜角αは、１３度以上がさらに好ましい。熱膨張係数差の異方性が小さくなり、クラックが抑制される。傾斜角αは、４５度以下がさらに好ましい。窒化物結晶がｃ軸配向成長しやすくなり、結晶性が高くなる。傾斜角αは、ｃ軸１６をＧａＮ層の主面に投影した方向と、第２方向Ｄ２と、の間の角度に対応する。   The inclination angle α is preferably 5 degrees or greater and 85 degrees or less. When the inclination angle α is smaller than 5 degrees or larger than 85 degrees, the change in thermal expansion coefficient difference (difference ΔC1 and difference ΔC2) from the value when the inclination angle α is 0 degrees is less than 1%. It is. For this reason, the effect of suppressing warpage and cracks is insufficient. The inclination angle α is more preferably 13 degrees or more. Anisotropy of the difference in thermal expansion coefficient is reduced, and cracks are suppressed. The inclination angle α is more preferably 45 degrees or less. Nitride crystals are easily grown in c-axis orientation and the crystallinity is increased. The inclination angle α corresponds to the angle between the direction in which the c-axis 16 is projected onto the main surface of the GaN layer and the second direction D2.

このように、窒化物半導体層１５のｃ軸１６のＸ−Ｙ平面に投影した方向を、第２方向Ｄ２に対して傾斜させることで、熱膨張係数差の異方性が抑制できる。これにより、基板４０の反りが抑制できる。クラックＣＲを抑制できる。   Thus, the anisotropy of the thermal expansion coefficient difference can be suppressed by inclining the direction projected on the XY plane of the c-axis 16 of the nitride semiconductor layer 15 with respect to the second direction D2. Thereby, the curvature of the board | substrate 40 can be suppressed. Crack CR can be suppressed.

実施形態において、窒化物半導体層１５のｃ軸１６は、第３方向Ｄ３（すなわち、積層方向）に対して傾斜する。これにより、窒化物半導体層１５に生じる内部電界を抑制でき、特性が向上できる。例えば、窒化物半導体層１５を用いた発光装置において、発光効率が向上できる。特性の向上とともに、反りを抑制し、クラックを抑制し、高い生産性が得られる。   In the embodiment, the c-axis 16 of the nitride semiconductor layer 15 is inclined with respect to the third direction D3 (that is, the stacking direction). Thereby, the internal electric field generated in the nitride semiconductor layer 15 can be suppressed, and the characteristics can be improved. For example, in the light emitting device using the nitride semiconductor layer 15, the light emission efficiency can be improved. Along with improved characteristics, warpage is suppressed, cracks are suppressed, and high productivity is obtained.

図７（ａ）〜図７（ｄ）は、窒化物半導体装置を例示する電子顕微鏡写真像及び模式図である。
図７（ｄ）は、上記の第３試料ＳＰ３０の基板４０を例示する模式的平面図である。図７（ａ）〜図７（ｃ）は、図７（ｄ）のＡ１−Ａ２線断面の電子顕微鏡写真像である。 FIG. 7A to FIG. 7D are an electron micrograph image and a schematic view illustrating a nitride semiconductor device.
FIG. 7D is a schematic plan view illustrating the substrate 40 of the third sample SP30. Fig.7 (a)-FIG.7 (c) are the electron micrograph images of the A1-A2 line cross section of FIG.7 (d).

図７（ｄ）に示すように、基板４０は、シリコンのウェーハであり、オリエンテーションフラット４７を有する。オリエンテーションフラット４７と、凹部４５の延在方向（第１方向Ｄ１）との間の角度βは、約１７度である。   As shown in FIG. 7D, the substrate 40 is a silicon wafer and has an orientation flat 47. The angle β between the orientation flat 47 and the extending direction of the recess 45 (first direction D1) is about 17 degrees.

図７（ａ）〜図７（ｃ）に示すように、複数の凹部４５が形成される。凹部４５は溝状である。基板４０の上面４０ｕと、側面４６ａｓの下端と、の距離ｄ１は、約２．７μｍである。基板４０の上面４０ｕと、側面４６ａｒの下端と、の距離ｄ２は、約２．２μｍである。基板４０の上面４０ｕには、マスク層６４のシリコン酸化膜が形成されている。   As shown in FIGS. 7A to 7C, a plurality of recesses 45 are formed. The recess 45 has a groove shape. The distance d1 between the upper surface 40u of the substrate 40 and the lower end of the side surface 46as is about 2.7 μm. The distance d2 between the upper surface 40u of the substrate 40 and the lower end of the side surface 46ar is about 2.2 μm. A silicon oxide film of the mask layer 64 is formed on the upper surface 40 u of the substrate 40.

実施形態において、基板４０に設けられる複数の凹部４５のそれぞれの深さは、０．３μｍ以上３μｍ以下であることが好ましい。さらに好ましくは、０．５μｍ以上０．９μｍ以下である。凹部４５の深さは、距離ｄ１である。これにより底面４６ａｔからの成長が抑制され、側面４６ａｓからの成長が支配的になりやすく、窒化物結晶の成長の選択性が向上する。   In the embodiment, the depth of each of the plurality of recesses 45 provided in the substrate 40 is preferably 0.3 μm or more and 3 μm or less. More preferably, it is 0.5 μm or more and 0.9 μm or less. The depth of the recess 45 is a distance d1. Thereby, the growth from the bottom surface 46at is suppressed, the growth from the side surface 46as is likely to be dominant, and the selectivity of the growth of the nitride crystal is improved.

複数の凹部４５のそれぞれの間の上面４０ｕの第２方向Ｄ２の長さＬ１（レジスト膜６５の幅に対応）は、約１μｍである。複数の凹部４５のそれぞれの深さ（距離ｄ２）は、上面４０ｕの第２方向Ｄ２の長さＬ１の０．３倍以上３倍以下である。これにより、側面４６ａｓからのＧａＮ層の成長が支配的になりやすく、メルトバックエッチングが抑制されやすくなる。さらに好ましくは、０．５倍以上０．９倍以下である。窒化物結晶の成長の結晶性が向上する。   The length L1 (corresponding to the width of the resist film 65) in the second direction D2 of the upper surface 40u between each of the plurality of recesses 45 is about 1 μm. Each depth (distance d2) of the plurality of recesses 45 is not less than 0.3 times and not more than 3 times the length L1 of the upper surface 40u in the second direction D2. Thereby, the growth of the GaN layer from the side surface 46as is likely to be dominant, and the meltback etching is likely to be suppressed. More preferably, it is 0.5 times or more and 0.9 times or less. The crystallinity of nitride crystal growth is improved.

図８（ａ）〜図８（ｄ）は、窒化物半導体装置を例示する電子顕微鏡写真像である。
これらの図は、第３試料ＳＰ３０の基板４０を用いて、窒化物半導体層１５（ＧａＮ層５１）を成長させた試料の電子顕微鏡写真像である。図８（ｂ）〜図８（ｄ）は、図８（ａ）に示す部分ｐ１、部分ｐ２及び部分ｐ３のそれぞれの拡大像である。 FIG. 8A to FIG. 8D are electron micrograph images illustrating a nitride semiconductor device.
These figures are electron micrograph images of a sample in which the nitride semiconductor layer 15 (GaN layer 51) is grown using the substrate 40 of the third sample SP30. FIGS. 8B to 8D are enlarged images of the part p1, the part p2, and the part p3 shown in FIG. 8A.

基板４０の凹部４５の内側の表面にバッファ層６０（ＡｌＮ層）が成長する。窒化物結晶の結晶成長において、凹部４５の内部に原料ガスが進入（気相拡散）する。これにより、凹部４５の側面４６ａｓ、側面４６ａｒ、及び、底面４６ａｔの上にＡｌＮ層が成長する。
凹部４５の深さが深くなりすぎると、原料ガスが侵入（気相拡散）せず、底面４６ａｔの上にＡｌＮ層が成長しにくくなる。この場合には、凹部４５の底面４６ａｔからメルトバックエッチングが生じやすくなる。そのため、凹部４５の深さは、ＡｌＮ層が成長する深さであることが好ましい。凹部４５の深さは、０．３μｍ以上３μｍ以下であることが好ましい。 A buffer layer 60 (AlN layer) grows on the inner surface of the recess 45 of the substrate 40. In the crystal growth of the nitride crystal, the source gas enters (gas phase diffusion) into the recess 45. Thereby, an AlN layer grows on the side surface 46as, the side surface 46ar, and the bottom surface 46at of the recess 45.
When the depth of the recess 45 becomes too deep, the source gas does not enter (gas phase diffusion), and the AlN layer is difficult to grow on the bottom surface 46at. In this case, meltback etching is likely to occur from the bottom surface 46at of the recess 45. Therefore, it is preferable that the depth of the recess 45 is a depth at which the AlN layer grows. The depth of the recess 45 is preferably 0.3 μm or more and 3 μm or less.

そして、このＡｌＮ層の上にＧａＮ層５１が成長する。図８（ａ）において、ＡｌＮ層の被覆性は良好であり、ＡｌＮ層によりシリコンが覆われる。ＧａＮ層５１と基板４０（シリコン）との間でメルトバックエッチングは、生じていない。シリコンの基板４０に接して、ＡｌＮ層を形成することが望ましい。図８（ａ）に示すように、側面４６ａｓの下端と、の距離ｄ１は、約２．８μｍである。基板４０の上面４０ｕと、側面４６ａｒの下端と、の距離ｄ２は、約２．３μｍである。複数の凹部４５のそれぞれの深さ（距離ｄ２）は、上面４０ｕの第２方向Ｄ２の長さＬ１の約３倍である。底面４６ａｔからの成長が抑制され、側面４６ａｓからの成長が支配的となる。凹部４５の深さが浅くなりすぎると、底面４６ａｔからの成長が生じ、側面４６ａｓからの成長が阻害され、結晶品質が低下する。   A GaN layer 51 is grown on the AlN layer. In FIG. 8A, the coverage of the AlN layer is good, and silicon is covered with the AlN layer. Melt back etching does not occur between the GaN layer 51 and the substrate 40 (silicon). It is desirable to form an AlN layer in contact with the silicon substrate 40. As shown in FIG. 8A, the distance d1 from the lower end of the side surface 46as is about 2.8 μm. The distance d2 between the upper surface 40u of the substrate 40 and the lower end of the side surface 46ar is about 2.3 μm. The depth (distance d2) of each of the plurality of recesses 45 is about three times the length L1 of the upper surface 40u in the second direction D2. Growth from the bottom surface 46at is suppressed, and growth from the side surface 46as becomes dominant. If the depth of the recess 45 becomes too shallow, growth from the bottom surface 46at occurs, growth from the side surface 46as is hindered, and crystal quality deteriorates.

図９（ａ）〜図９（ｊ）は、窒化物半導体装置を例示する電子顕微鏡写真像及び模式的斜視図である。
図９（ｂ）、図９（ｃ）、図９（ｅ）、図９（ｇ）、図９（ｉ）の例において、図中の点線は側面４６ａｓを示している。これら例においては、側面４６ａｓは、シリコンの｛１１１｝面に実質的に対応する。
図９（ａ）及び図９（ｂ）の例では、基板４０の上面４０ｕは、シリコンの（１１１）面である。この時、窒化物半導体層１５（例えばＧａＮ層５１）のｃ軸１６は、基板４０の上面４０ｕに対して実質的に垂直である。窒化物半導体層１５のｃ面は、上面４０ｕに対して実質的に平行である。 FIG. 9A to FIG. 9J are an electron micrograph image and a schematic perspective view illustrating a nitride semiconductor device.
In the examples of FIG. 9B, FIG. 9C, FIG. 9E, FIG. 9G, and FIG. 9I, the dotted line in the figure indicates the side surface 46as. In these examples, the side surface 46as substantially corresponds to the {111} plane of silicon.
In the example of FIGS. 9A and 9B, the upper surface 40u of the substrate 40 is a (111) surface of silicon. At this time, the c-axis 16 of the nitride semiconductor layer 15 (for example, the GaN layer 51) is substantially perpendicular to the upper surface 40u of the substrate 40. The c-plane of the nitride semiconductor layer 15 is substantially parallel to the upper surface 40u.

図９（ｃ）及び図９（ｄ）の例では、基板４０の上面４０ｕは、シリコンの（１１２）面である。この時、窒化物半導体層１５（例えばＧａＮ層５１）のｃ軸１６は、基板４０の上面４０ｕに対して平行である。窒化物半導体層１５のｍ面（（１０−１０）面）は、上面４０ｕに対して実質的に平行である。   In the examples of FIGS. 9C and 9D, the upper surface 40u of the substrate 40 is a (112) surface of silicon. At this time, the c-axis 16 of the nitride semiconductor layer 15 (for example, the GaN layer 51) is parallel to the upper surface 40u of the substrate 40. The m-plane ((10-10) plane) of the nitride semiconductor layer 15 is substantially parallel to the upper surface 40u.

図９（ｅ）及び図９（ｆ）の例では、基板４０の上面４０ｕは、シリコンの（１１３）面である。この時、窒化物半導体層１５（例えばＧａＮ層５１）のｃ軸１６は、基板４０の上面４０ｕに対して傾斜する。窒化物半導体層１５の（１１−２２）面は、上面４０ｕに対して実質的に平行である。   In the example of FIGS. 9E and 9F, the upper surface 40u of the substrate 40 is a (113) surface of silicon. At this time, the c-axis 16 of the nitride semiconductor layer 15 (for example, the GaN layer 51) is inclined with respect to the upper surface 40u of the substrate 40. The (11-22) plane of the nitride semiconductor layer 15 is substantially parallel to the upper surface 40u.

図９（ｇ）及び図９（ｈ）の例では、基板４０の上面４０ｕは、シリコンの（００１）面である。この時、窒化物半導体層１５（例えばＧａＮ層５１）のｃ軸１６は、基板４０の上面４０ｕに対して傾斜する。窒化物半導体層１５の（１０−１１）面は、上面４０ｕに対して実質的に平行である。   In the example of FIGS. 9G and 9H, the upper surface 40u of the substrate 40 is a (001) surface of silicon. At this time, the c-axis 16 of the nitride semiconductor layer 15 (for example, the GaN layer 51) is inclined with respect to the upper surface 40u of the substrate 40. The (10-11) plane of the nitride semiconductor layer 15 is substantially parallel to the upper surface 40u.

図９（ｉ）及び図９（ｊ）の例では、基板４０の上面４０ｕは、シリコンの（１１０）面である。この時、窒化物半導体層１５（例えばＧａＮ層５１）のｃ軸１６は、基板４０の上面４０ｕに対して実質的に平行である。窒化物半導体層１５のａ面（（１１−２０）面）は、上面４０ｕに対して実質的に平行である。   9 (i) and 9 (j), the upper surface 40u of the substrate 40 is a (110) surface of silicon. At this time, the c-axis 16 of the nitride semiconductor layer 15 (for example, the GaN layer 51) is substantially parallel to the upper surface 40u of the substrate 40. The a-plane ((11-20) plane) of the nitride semiconductor layer 15 is substantially parallel to the upper surface 40u.

このように、基板４０として用いるシリコン基板の面方位を変えることで、窒化物半導体層１５の上面（第１面１５ｆ）の面方位、及び、ｃ軸１６の方向が、制御できる。   Thus, by changing the plane orientation of the silicon substrate used as the substrate 40, the plane orientation of the upper surface (first surface 15f) of the nitride semiconductor layer 15 and the direction of the c-axis 16 can be controlled.

既に説明したように、例えば、（１１３）面のシリコン基板を用いる場合には、窒化物半導体層１５の（１１−２２）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕに対して垂直な軸と、の間の角度は、約５８度である。言い換えれば、ｃ軸１６と第１面１５ｆとの間の角度θ１は、約３２度である。   As already described, for example, when a (113) plane silicon substrate is used, the (11-22) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the axis perpendicular to the upper surface 40 u of the substrate 40 is about 58 degrees. In other words, the angle θ1 between the c-axis 16 and the first surface 15f is about 32 degrees.

例えば、基板４０として、（００１）面で、＜１１０＞方向に向かって約８度傾斜させたシリコン基板を用いても良い。この場合には、窒化物半導体層１５の（１０−１１）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕに対して垂直な軸と、の間の角度は、約６２度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、約２８度である。   For example, as the substrate 40, a silicon substrate inclined by about 8 degrees toward the <110> direction on the (001) plane may be used. In this case, the (10-11) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the axis perpendicular to the upper surface 40 u of the substrate 40 is about 62 degrees. The angle θ1 between the c-axis 16 and the first surface 15f is about 28 degrees.

例えば、基板４０として、（１１２）面のシリコン基板を用いても良い。この場合には、窒化物半導体層１５の（１０−１０）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕと、の間の角度は、実質的に０度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、実質的に０度である。   For example, a (112) plane silicon substrate may be used as the substrate 40. In this case, the (10-10) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the upper surface 40u of the substrate 40 is substantially 0 degree. The angle θ1 between the c-axis 16 and the first surface 15f is substantially 0 degree.

例えば、基板４０として、（１１０）面のシリコン基板を用いても良い。この場合には、窒化物半導体層１５の（１１−２０）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕと、の間の角度は、実質的に０度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、実質的に０度である。   For example, a (110) plane silicon substrate may be used as the substrate 40. In this case, the (11-20) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the upper surface 40u of the substrate 40 is substantially 0 degree. The angle θ1 between the c-axis 16 and the first surface 15f is substantially 0 degree.

実施形態において、基板４０として、サファイア基板を用いても良い。
例えば、基板４０として、ｒ面（（１−１０２）面）のサファイア基板を用いても良い。この場合には、窒化物半導体層１５の（１１−２２）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕに対して垂直な軸と、の間の角度は、約５８度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、約３２度である。 In the embodiment, a sapphire substrate may be used as the substrate 40.
For example, an r-plane ((1-102) plane) sapphire substrate may be used as the substrate 40. In this case, the (11-22) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the axis perpendicular to the upper surface 40 u of the substrate 40 is about 58 degrees. The angle θ1 between the c-axis 16 and the first surface 15f is about 32 degrees.

例えば、基板４０として、ｎ面（（１１−２３）面）のサファイア基板を用いても良い。この場合には、窒化物半導体層１５の（１０−１１）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕに対して垂直な軸と、の間の角度は、約６２度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、約２８度である。   For example, an n-plane ((11-23) plane) sapphire substrate may be used as the substrate 40. In this case, the (10-11) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the axis perpendicular to the upper surface 40 u of the substrate 40 is about 62 degrees. The angle θ1 between the c-axis 16 and the first surface 15f is about 28 degrees.

例えば、基板４０として、ａ面（（１１−２０）面））のサファイア基板を用いても良い。この場合には、窒化物半導体層１５の（１０−１０）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕと、の間の角度は、実質的に０度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、実質的に０度である。   For example, as the substrate 40, an a-plane ((11-20) plane) sapphire substrate may be used. In this case, the (10-10) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the upper surface 40u of the substrate 40 is substantially 0 degree. The angle θ1 between the c-axis 16 and the first surface 15f is substantially 0 degree.

例えば、基板４０として、ｍ面（（１０−１０）面）またはｃ面（（０００１）面）のサファイア基板を用いても良い。この場合には、窒化物半導体層１５の（１１−２０）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕと、の間の角度は、実質的に０度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、実質的に０度である。   For example, a sapphire substrate of m-plane ((10-10) plane) or c-plane ((0001) plane) may be used as the substrate 40. In this case, the (11-20) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the upper surface 40u of the substrate 40 is substantially 0 degree. The angle θ1 between the c-axis 16 and the first surface 15f is substantially 0 degree.

例えば、基板４０として、ｃ面（（０００１）面）のサファイア基板を用いても良い。この場合には、窒化物半導体層１５の（１１−２０）面が、基板４０の上面４０ｕに対して平行になる。このとき、窒化物半導体層１５のｃ軸１６と、基板４０の上面４０ｕと、の間の角度は、実質的に０度である。ｃ軸１６と第１面１５ｆとの間の角度θ１は、実質的に０度である。   For example, a c-plane ((0001) plane) sapphire substrate may be used as the substrate 40. In this case, the (11-20) plane of the nitride semiconductor layer 15 is parallel to the upper surface 40 u of the substrate 40. At this time, the angle between the c-axis 16 of the nitride semiconductor layer 15 and the upper surface 40u of the substrate 40 is substantially 0 degree. The angle θ1 between the c-axis 16 and the first surface 15f is substantially 0 degree.

基板４０の面方位によって、窒化物半導体層１５の第１面１５ｆ（主面）の結晶面を変化させることができる。   Depending on the plane orientation of the substrate 40, the crystal plane of the first surface 15 f (main surface) of the nitride semiconductor layer 15 can be changed.

例えば、実施形態において、窒化物半導体層１５の第１面１５ｆは、（１１−２２）面、（１０−１１）面、（１１−２０）面、及び、（１０−１０）面のいずれかに対して平行である。窒化物半導体層１５の表面に凹凸などが形成される場合、第１面１５ｆが、（１１−２２）面、（１０−１１）面、（１１−２０）面、及び、（１０−１０）面のいずれかに対して平行な部分を含む場合がある。   For example, in the embodiment, the first surface 15f of the nitride semiconductor layer 15 is any one of the (11-22) plane, the (10-11) plane, the (11-20) plane, and the (10-10) plane. Is parallel to. When unevenness or the like is formed on the surface of the nitride semiconductor layer 15, the first surface 15f has a (11-22) plane, a (10-11) plane, a (11-20) plane, and (10-10). It may include a portion parallel to any of the surfaces.

図１０（ａ）〜図１０（ｄ）は、第１の実施形態に係る窒化物半導体装置を例示する模式的断面図である。
これらの例においては、窒化物半導体装置は、発光装置（例えばＬＥＤ）である。
図１０（ａ）に示す窒化物半導体装置１２１においては、基板４０の上に下地層５０（例えばＧａＮ層）が設けられ、下地層５０の上に、機能層１０が設けられる。機能層１０は、第１半導体層１１、第２半導体層１２及び活性層１３に加えて、低不純物濃度層１１ｉをさらに含む。低不純物濃度層１１ｉは、第１半導体層１１と下地層５０との間に配置される。低不純物濃度層１１ｉにおける不純物濃度は、第１半導体層１１における不純物濃度よりも低い。低不純物濃度層１１ｉには、例えば、アンドープのＧａＮが用いられる。 FIG. 10A to FIG. 10D are schematic cross-sectional views illustrating the nitride semiconductor device according to the first embodiment.
In these examples, the nitride semiconductor device is a light emitting device (for example, LED).
In the nitride semiconductor device 121 shown in FIG. 10A, a base layer 50 (for example, a GaN layer) is provided on the substrate 40, and the functional layer 10 is provided on the base layer 50. The functional layer 10 further includes a low impurity concentration layer 11 i in addition to the first semiconductor layer 11, the second semiconductor layer 12, and the active layer 13. The low impurity concentration layer 11 i is disposed between the first semiconductor layer 11 and the base layer 50. The impurity concentration in the low impurity concentration layer 11 i is lower than the impurity concentration in the first semiconductor layer 11. For the low impurity concentration layer 11i, for example, undoped GaN is used.

この例では、第１半導体層１１は、第１部分１１ａと第２部分１１ｂとを含む。第２部分１１ｂは、第１面１５ｆに対して平行な面内で、第１部分１１ａと並ぶ。第２半導体層１２は、第３方向Ｄ３において、第１部分１１ａと離間する。第２半導体層１２と第１部分１１ａとの間に活性層１３が配置される。   In this example, the first semiconductor layer 11 includes a first portion 11a and a second portion 11b. The second portion 11b is aligned with the first portion 11a in a plane parallel to the first surface 15f. The second semiconductor layer 12 is separated from the first portion 11a in the third direction D3. An active layer 13 is disposed between the second semiconductor layer 12 and the first portion 11a.

第１電極１１ｅと、第２電極１２ｅと、が設けられる。第１電極１１ｅは、第１半導体層１１の第２部分１１ｂと電気的に接続される。第２電極１２ｅは、第２半導体層１２と電気的に接続される。   A first electrode 11e and a second electrode 12e are provided. The first electrode 11 e is electrically connected to the second portion 11 b of the first semiconductor layer 11. The second electrode 12e is electrically connected to the second semiconductor layer 12.

第１電極１１ｅと第２電極１２ｅとの間に電圧を印加することで、活性層１３に電流が供給され、活性層１３から光が放出される。   By applying a voltage between the first electrode 11e and the second electrode 12e, a current is supplied to the active layer 13, and light is emitted from the active layer 13.

図１０（ｂ）に示す窒化物半導体装置１２２においては、窒化物半導体層１５が形成された後に、基板４０及び下地層５０が除去されている。この例では、保持部７０が設けられている。第１電極１１ｅと保持部７０との間に、第２電極１２ｅが設けられる。第１電極１１ｅと第２電極１２ｅとの間に機能層１０が設けられる。   In the nitride semiconductor device 122 shown in FIG. 10B, the substrate 40 and the underlayer 50 are removed after the nitride semiconductor layer 15 is formed. In this example, a holding unit 70 is provided. A second electrode 12e is provided between the first electrode 11e and the holding unit 70. The functional layer 10 is provided between the first electrode 11e and the second electrode 12e.

図１０（ｃ）に示す窒化物半導体装置１２３においても、基板４０と下地層５０が除去されている。第１半導体層１１の第１部分１１ａと保持部７０との間に第２半導体層１２が配置される。第２半導体層１２と保持部７０との間に第２電極１２ｅが配置される。保持部７０は、第２電極１２ｅと電気的に接続される。第１部分１１ａと第２半導体層１２との間に活性層１３が配置される。第１半導体層１１の第２部分１１ｂと保持部７０との間に第１電極１１ｅが設けられる。第１電極１１ｅと保持部７０との間に絶縁層７５が設けられる。第１電極１１ｅは、活性層１３、第２半導体層１２、第２電極１２ｅ及び保持部７０と、電気的に絶縁される。   Also in the nitride semiconductor device 123 shown in FIG. 10C, the substrate 40 and the base layer 50 are removed. The second semiconductor layer 12 is disposed between the first portion 11 a of the first semiconductor layer 11 and the holding unit 70. The second electrode 12 e is disposed between the second semiconductor layer 12 and the holding unit 70. The holding part 70 is electrically connected to the second electrode 12e. An active layer 13 is disposed between the first portion 11 a and the second semiconductor layer 12. The first electrode 11 e is provided between the second portion 11 b of the first semiconductor layer 11 and the holding unit 70. An insulating layer 75 is provided between the first electrode 11 e and the holding unit 70. The first electrode 11e is electrically insulated from the active layer 13, the second semiconductor layer 12, the second electrode 12e, and the holding unit 70.

図１０（ｄ）に示す窒化物半導体装置１２４においても、基板４０と下地層５０が除去されている。この例では、保持部７０は、第１電極１１ｅと電気的に接続される。第２電極１２ｅと保持部７０との間に絶縁層７５が設けられる。第１電極１１ｅ及び保持部７０は、活性層１３、第２半導体層１２及び第２電極１２ｅと、電気的に絶縁される。   Also in the nitride semiconductor device 124 shown in FIG. 10D, the substrate 40 and the base layer 50 are removed. In this example, the holding unit 70 is electrically connected to the first electrode 11e. An insulating layer 75 is provided between the second electrode 12 e and the holding unit 70. The first electrode 11e and the holding unit 70 are electrically insulated from the active layer 13, the second semiconductor layer 12, and the second electrode 12e.

図１１は、第１の実施形態に係る別の窒化物半導体装置を例示する模式的断面図である。
この例の窒化物半導体装置１３１は、ＨＥＭＴ（High Electron Mobility Transistor）装置である。窒化物半導体装置１３１においては、機能層１０は、第１層８１と、第２層８２と、を含む。窒化物半導体装置１３１には、ゲート電極８５と、ソース電極８３と、ドレイン電極８４と、が設けられる。 FIG. 11 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the first embodiment.
The nitride semiconductor device 131 in this example is a HEMT (High Electron Mobility Transistor) device. In nitride semiconductor device 131, functional layer 10 includes a first layer 81 and a second layer 82. The nitride semiconductor device 131 is provided with a gate electrode 85, a source electrode 83, and a drain electrode 84.

第２層８２は、第１層８１と基板４０との間に設けられる。
第２層８２には、例えばアンドープのＡｌαＧａ１−αＮ（０≦α≦１）が用いられる。第１層８１には、例えばアンドープまたはｎ形のＡｌβＧａ１−βＮ（０≦β≦１、α＜β）が用いられる。例えば、第２層８２にはアンドープのＧａＮ層が用いられ、第１層８１にはアンドープまたはｎ形のＡｌＧａＮ層が用いられる。 The second layer 82 is provided between the first layer 81 and the substrate 40.
The second layer 82, for example, undoped Al α Ga 1-α N ( 0 ≦ α ≦ 1) is used. The first layer 81, for example, Al β Ga 1-β N ( 0 ≦ β ≦ 1, α <β) of undoped or n-type is used. For example, an undoped GaN layer is used for the second layer 82, and an undoped or n-type AlGaN layer is used for the first layer 81.

ゲート電極８５、ソース電極８３及びドレイン電極８４と、基板４０と、の間に、機能層１０が配置される。これらの電極は、Ｘ−Ｙ平面内に並ぶ。ゲート電極８５は、ソース電極８３とドレイン電極８４との間に配置される。ソース電極８３及びドレイン電極８４は、第１層８１とオーミック接触する。ゲート電極８５は、例えば、第１層８１とショットキー接触する。   The functional layer 10 is disposed between the gate electrode 85, the source electrode 83 and the drain electrode 84, and the substrate 40. These electrodes are arranged in the XY plane. The gate electrode 85 is disposed between the source electrode 83 and the drain electrode 84. The source electrode 83 and the drain electrode 84 are in ohmic contact with the first layer 81. For example, the gate electrode 85 is in Schottky contact with the first layer 81.

第１層８１の格子定数は、第２層８２の格子定数よりも小さい。これにより、第１層８１に歪みが生じる。ピエゾ効果により、第１層８１内にピエゾ分極が生じる。第２層８２のうちの第１層８１との界面付近に、２次元電子ガス８２ｇが形成される。   The lattice constant of the first layer 81 is smaller than the lattice constant of the second layer 82. As a result, distortion occurs in the first layer 81. Piezoelectric polarization occurs in the first layer 81 due to the piezoelectric effect. A two-dimensional electron gas 82 g is formed near the interface of the second layer 82 with the first layer 81.

窒化物半導体装置１３１においては、ゲート電極８５に印加する電圧を制御することで、ゲート電極８５の下の２次元電子ガス８２ｇの濃度が変化し、ソース電極８３とドレイン電極８４との間に流れる電流が制御される。   In the nitride semiconductor device 131, by controlling the voltage applied to the gate electrode 85, the concentration of the two-dimensional electron gas 82 g below the gate electrode 85 changes and flows between the source electrode 83 and the drain electrode 84. The current is controlled.

このように、この例の窒化物半導体装置１３１は、基板４０及び窒化物半導体層１５に加え、第１電極（ソース電極８３）と、第２電極（ドレイン電極８４）と、第３電極（ゲート電極８５）と、をさらに含む。これらの電極と、基板４０と、の間に窒化物半導体層１５が配置される。窒化物半導体層１５（例えば機能層１０）は、第１層８１と、第２層８２と、を含む。第１層８１と基板４０との間に第２層８２が配置される。第１層８１の格子定数は、第２層８２の格子定数よりも小さい。   Thus, the nitride semiconductor device 131 in this example includes the first electrode (source electrode 83), the second electrode (drain electrode 84), and the third electrode (gate) in addition to the substrate 40 and the nitride semiconductor layer 15. An electrode 85). A nitride semiconductor layer 15 is disposed between these electrodes and the substrate 40. The nitride semiconductor layer 15 (for example, the functional layer 10) includes a first layer 81 and a second layer 82. A second layer 82 is disposed between the first layer 81 and the substrate 40. The lattice constant of the first layer 81 is smaller than the lattice constant of the second layer 82.

窒化物半導体装置１３１においては、実施形態に係る窒化物半導体層１５を用いることで、反りが抑制され、クラックＣＲが抑制できる。   In the nitride semiconductor device 131, by using the nitride semiconductor layer 15 according to the embodiment, warpage can be suppressed and crack CR can be suppressed.

このように、実施形態に係る窒化物半導体装置は、窒化物半導体層１５を含む。この窒化物半導体層１５は、基板４０の上に形成される。この基板４０は、主面４０ａに沿って広がる。主面４０ａは、上面４０ｕと、複数の斜面４１と、を含む（図１（ｂ）参照）。複数の斜面４１は、上面４０ｕに対して傾斜する。上面４０ｕに対して平行な第１方向Ｄ１における複数の斜面４１のそれぞれの長さは、上面４０ｕに対して平行で第１方向Ｄ１に対して垂直な第２方向Ｄ２における複数の斜面４１のそれぞれの長さよりも長い。複数の斜面４１は、第２方向に並ぶ。このような、基板４０の複数の斜面４１から、窒化物半導体層１５は成長される。窒化物半導体層１５のｃ軸１６は、第２方向Ｄ２に対して傾斜している。ｃ軸１６は、上面４０ｕに対して垂直な第３方向Ｄ３と交差する。例えば、ｃ軸１６は、第３方向Ｄ３に対して傾斜する。   As described above, the nitride semiconductor device according to the embodiment includes the nitride semiconductor layer 15. The nitride semiconductor layer 15 is formed on the substrate 40. The substrate 40 extends along the main surface 40a. The main surface 40a includes an upper surface 40u and a plurality of inclined surfaces 41 (see FIG. 1B). The plurality of inclined surfaces 41 are inclined with respect to the upper surface 40u. The lengths of the plurality of inclined surfaces 41 in the first direction D1 parallel to the upper surface 40u are the lengths of the plurality of inclined surfaces 41 in the second direction D2 parallel to the upper surface 40u and perpendicular to the first direction D1. Longer than the length of. The plurality of inclined surfaces 41 are arranged in the second direction. The nitride semiconductor layer 15 is grown from the plurality of inclined surfaces 41 of the substrate 40 as described above. The c-axis 16 of the nitride semiconductor layer 15 is inclined with respect to the second direction D2. The c-axis 16 intersects the third direction D3 perpendicular to the upper surface 40u. For example, the c-axis 16 is inclined with respect to the third direction D3.

ｃ軸１６と上面４０ｕとの間の角度は、０度以上８５度以下である。ｃ軸１６を上面４０ｕに投影した方向と、第２方向Ｄ２と、の間の角度は、５度以上８５度以下である。   The angle between the c-axis 16 and the upper surface 40u is not less than 0 degrees and not more than 85 degrees. The angle between the direction in which the c-axis 16 is projected onto the upper surface 40u and the second direction D2 is not less than 5 degrees and not more than 85 degrees.

例えば、基板４０がシリコン基板の場合、基板４０の上面４０ｕは、シリコンの（１１３）面、（００１）面、（１１２）面、及び、（１１０）面のいずれかに対して平行である。   For example, when the substrate 40 is a silicon substrate, the upper surface 40u of the substrate 40 is parallel to any of the (113) plane, (001) plane, (112) plane, and (110) plane of silicon.

基板４０の面方位は厳密面に限らず、指数が入れ替わった等価面でも良い。例えば、シリコンの（１１３）面の場合、（１１−３）面や（３１１）面などでも良い。すなわち、（１１３）面と等価な面を含むミラー指数の包括表現である｛１１３｝面で表される結晶面であれば良い。   The plane orientation of the substrate 40 is not limited to a strict plane, and may be an equivalent plane in which indices are switched. For example, in the case of the (113) plane of silicon, the (11-3) plane or the (311) plane may be used. That is, any crystal plane represented by the {113} plane, which is a comprehensive expression of the Miller index including a plane equivalent to the (113) plane, may be used.

図１２は、窒化物半導体装置を例示する電子顕微鏡写真像である。
図１２には、電子線回折法などを用いて測定されたｃ軸１６を示している。図１２は、第１方向Ｄ１の方向に観察した断面ＴＥＭ像である。 FIG. 12 is an electron micrograph image illustrating a nitride semiconductor device.
FIG. 12 shows the c-axis 16 measured using an electron beam diffraction method or the like. FIG. 12 is a cross-sectional TEM image observed in the first direction D1.

図１２には、転位１８が観察されている。ｃ軸１６と、転位１８の方向と、は、ほぼ平行である。転位１８の方向は、ｃ軸１６である。例示した転位１８は、斜面４１を起点に伸びている。転位１８の方向は、操作が加わらない限り、窒化物結晶内で変化しない。斜面が見られない場合でも、転位１８の方向は、ｃ軸１６である。   In FIG. 12, dislocations 18 are observed. The c-axis 16 and the direction of the dislocation 18 are substantially parallel. The direction of the dislocation 18 is the c-axis 16. The illustrated dislocation 18 extends from the slope 41 as a starting point. The direction of the dislocation 18 does not change within the nitride crystal unless manipulation is applied. Even when no slope is seen, the direction of the dislocation 18 is the c-axis 16.

図１２に示すように、積層欠陥１９が観察されている。積層欠陥１９は、ｃ軸に対して垂直な方向に沿って延びる。したがって、積層欠陥１９は、窒化物結晶の主面（第１面１５ｆ）と交差する。積層欠陥１９は、境界１７の領域に、主に形成される。例えば、斜面が観察されない場合において、積層欠陥１９の方向及び転位１８の方向などから、ｃ軸１６及び境界１７が判断できる。例えば、積層欠陥１９が主面と交差することにより、ｃ軸１６が、上面４０ｕに対して垂直な第３方向Ｄ３と交差していることが判断できる。   As shown in FIG. 12, a stacking fault 19 is observed. The stacking fault 19 extends along a direction perpendicular to the c-axis. Therefore, the stacking fault 19 intersects the main surface (first surface 15f) of the nitride crystal. The stacking fault 19 is mainly formed in the region of the boundary 17. For example, when the slope is not observed, the c-axis 16 and the boundary 17 can be determined from the direction of the stacking fault 19 and the direction of the dislocation 18. For example, when the stacking fault 19 intersects the main surface, it can be determined that the c-axis 16 intersects the third direction D3 perpendicular to the upper surface 40u.

（第２の実施形態）
本実施形態は、窒化物半導体層の製造方法に係る。
図１３は、第２の実施形態に係る窒化物半導体層の製造方法を例示するフローチャート図である。
本製造方法においては、基板４０を用意する（ステップＳ１１０）。この基板４０は、主面４０ａを有する。主面４０ａは、上面４０ｕと、複数の斜面４１と、を含む。複数の斜面４１は、上面４０ｕに対して傾斜する。上面４０ｕに対して平行な第１方向Ｄ１における複数の斜面４１のそれぞれの長さは、上面４０ｕに対して平行で第１方向Ｄ１に対して垂直な第２方向Ｄ２における複数の斜面４１のそれぞれの長さよりも長い。複数の斜面４１は、第２方向Ｄ２に並ぶ。 (Second Embodiment)
The present embodiment relates to a method for manufacturing a nitride semiconductor layer.
FIG. 13 is a flowchart illustrating the method for manufacturing the nitride semiconductor layer according to the second embodiment.
In this manufacturing method, the substrate 40 is prepared (step S110). The substrate 40 has a main surface 40a. The main surface 40a includes an upper surface 40u and a plurality of inclined surfaces 41. The plurality of inclined surfaces 41 are inclined with respect to the upper surface 40u. The lengths of the plurality of inclined surfaces 41 in the first direction D1 parallel to the upper surface 40u are the lengths of the plurality of inclined surfaces 41 in the second direction D2 parallel to the upper surface 40u and perpendicular to the first direction D1. Longer than the length of. The plurality of inclined surfaces 41 are arranged in the second direction D2.

本製造方法においては、複数の斜面４１から、エピタキシャル成長により、窒化物半導体層１５を成長させる（ステップＳ１２０）。   In this manufacturing method, the nitride semiconductor layer 15 is grown from the plurality of inclined surfaces 41 by epitaxial growth (step S120).

窒化物半導体層１５のｃ軸１６は、第１方向Ｄ１に対して傾斜する。ｃ軸１６は、第２方向Ｄ２に対して傾斜する。ｃ軸１６は、上面４０ｕに対して垂直な第３方向Ｄ３と交差する。例えば、ｃ軸１６は、第３方向Ｄ３に対して傾斜する。
本製造方法によれば、反りが抑制でき、クラックＣＲが抑制できる。 The c-axis 16 of the nitride semiconductor layer 15 is inclined with respect to the first direction D1. The c-axis 16 is inclined with respect to the second direction D2. The c-axis 16 intersects the third direction D3 perpendicular to the upper surface 40u. For example, the c-axis 16 is inclined with respect to the third direction D3.
According to this manufacturing method, warpage can be suppressed and crack CR can be suppressed.

実施形態に係る窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法において、窒化物半導体層１５の成長方法には、例えば、有機金属気相堆積（Metal-Organic Chemical Vapor Deposition：ＭＯＣＶＤ）法、有機金属気相成長（Metal-Organic Vapor Phase Epitaxy：ＭＯＶＰＥ）法、分子線エピタキシー（Molecular Beam Epitaxy：ＭＢＥ）法、及び、ハライド気相エピタキシー（Halide Vapor Phase Epitaxy：ＨＶＰＥ）法などを用いることができる。   In the nitride semiconductor layer, nitride semiconductor device, and nitride semiconductor layer manufacturing method according to the embodiment, the nitride semiconductor layer 15 may be grown by, for example, metal-organic chemical vapor deposition (MOCVD). ) Method, Metal-Organic Vapor Phase Epitaxy (MOVPE) method, Molecular Beam Epitaxy (MBE) method, Halide Vapor Phase Epitaxy (HVPE) method, etc. be able to.

実施形態によれば、高生産性の窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法が提供できる。   According to the embodiment, a highly productive nitride semiconductor layer, a nitride semiconductor device, and a method for manufacturing the nitride semiconductor layer can be provided.

なお、本明細書において「窒化物半導体」とは、ＢｘＩｎｙＡｌｚＧａ１−ｘ−ｙ−ｚＮ（０≦ｘ≦１，０≦ｙ≦１，０≦ｚ≦１，ｘ＋ｙ＋ｚ≦１）なる化学式において組成比ｘ、ｙ及びｚをそれぞれの範囲内で変化させた全ての組成の半導体を含むものとする。またさらに、上記化学式において、Ｎ（窒素）以外のＶ族元素もさらに含むもの、導電形などの各種の物性を制御するために添加される各種の元素をさらに含むもの、及び、意図せずに含まれる各種の元素をさらに含むものも、「窒化物半導体」に含まれるものとする。 In this specification, “nitride semiconductor” means B x In y Al z Ga 1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

なお、本願明細書において、「垂直」及び「平行」は、厳密な垂直及び厳密な平行だけではなく、例えば製造工程におけるばらつきなどを含むものであり、実質的に垂直及び実質的に平行であれば良い。   In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

以上、具体例を参照しつつ、本発明の実施の形態について説明した。しかし、本発明は、これらの具体例に限定されるものではない。例えば、窒化物半導体装置に含まれる窒化物半導体層、基板、バッファ層、下地層、半導体層、活性層及び電極などの各要素の具体的な構成に関しては、当業者が公知の範囲から適宜選択することにより本発明を同様に実施し、同様の効果を得ることができる限り、本発明の範囲に包含される。   The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a specific configuration of each element such as a nitride semiconductor layer, a substrate, a buffer layer, a base layer, a semiconductor layer, an active layer, and an electrode included in the nitride semiconductor device is appropriately selected by those skilled in the art from a known range. By doing so, the present invention is included in the scope of the present invention as long as the same effects can be obtained and similar effects can be obtained.

また、各具体例のいずれか２つ以上の要素を技術的に可能な範囲で組み合わせたものも、本発明の要旨を包含する限り本発明の範囲に含まれる。   Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

その他、本発明の実施の形態として上述した窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法を基にして、当業者が適宜設計変更して実施し得る全ての窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法も、本発明の要旨を包含する限り、本発明の範囲に属する。   In addition, all nitride semiconductor layers that can be implemented by those skilled in the art by appropriately modifying the design based on the nitride semiconductor layer, the nitride semiconductor device, and the method for manufacturing the nitride semiconductor layer described above as embodiments of the present invention. The nitride semiconductor device and the method for manufacturing the nitride semiconductor layer also belong to the scope of the present invention as long as they include the gist of the present invention.

その他、本発明の思想の範疇において、当業者であれば、各種の変更例及び修正例に想到し得るものであり、それら変更例及び修正例についても本発明の範囲に属するものと了解される。   In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

１０…機能層、 １１…第１半導体層、 １１ａ…第１部分、 １１ｂ…第２部分、 １１ｅ…第１電極、 １１ｉ…低不純物濃度層、 １２…第２半導体層、 １２ｅ…第２電極、 １３…活性層、 １５…窒化物半導体層、 １５ａ、１５ｂ…第１、第２領域、 １５ｆ…第１面、 １６、１６ａ、１６ｂ…ｃ軸、 １６ｐ…方向、 １７…境界、 １８…転位、 １９…積層欠陥、 ４０…基板、 ４０ａ…主面、 ４０ｕ…上面、 ４１、４１ａ、４１ｂ…斜面、 ４５…凹部、 ４５ａ、４５ｂ…第１、第２凹部、 ４６ａｓ、４６ａｒ、４６ｂｓ、４６ｂｒ…側面、 ４６ａｔ、４６ｂｔ…底面、 ４７…オリエンテーションフラット、 ５０…下地層、 ５１…ＧａＮ層、 ５２…稜線、 ６０…バッファ層、 ６４…マスク層、 ６４ｆ…酸化シリコン膜、 ６５…レジスト膜、 ７０…保持部、 ７５…絶縁層、 ８１、８２…第１、第２層、 ８２ｇ…２次元電子ガス、 ８３…ソース電極（第１電極）、 ８４…ドレイン電極（第２電極）、 ８５…ゲート電極（第３電極）、 ΔＣ…熱膨張係数差、 ΔＣ１、ΔＣ２…差、 α…傾斜角、 β…角度、 θ１、θ２…角度、 １１０、１２１〜１２４、１３１…窒化物半導体装置、 ＣＲ…クラック、 Ｄ１〜Ｄ３…第１〜第３方向、 Ｌ１…長さ、 ＳＰ１０、ＳＰ２０、ＳＰ３０、ＳＰ１１、ＳＰ３１…第１〜第５試料、 ｄ１、ｄ２…距離、 ｐ１〜ｐ３…部分   DESCRIPTION OF SYMBOLS 10 ... Functional layer, 11 ... 1st semiconductor layer, 11a ... 1st part, 11b ... 2nd part, 11e ... 1st electrode, 11i ... Low impurity concentration layer, 12 ... 2nd semiconductor layer, 12e ... 2nd electrode, DESCRIPTION OF SYMBOLS 13 ... Active layer, 15 ... Nitride semiconductor layer, 15a, 15b ... 1st, 2nd area | region, 15f ... 1st surface, 16, 16a, 16b ... c-axis, 16p ... direction, 17 ... Boundary, 18 ... Dislocation, 19 ... Stacking fault, 40 ... Substrate, 40a ... Main surface, 40u ... Upper surface, 41, 41a, 41b ... Slope, 45 ... Recess, 45a, 45b ... First, second recess, 46as, 46ar, 46bs, 46br ... Side 46 at, 46 bt ... bottom surface, 47 ... orientation flat, 50 ... underlayer, 51 ... GaN layer, 52 ... ridge line, 60 ... buffer layer, 64 ... mask layer, 64 f ... CON film, 65 ... resist film, 70 ... holding part, 75 ... insulating layer, 81, 82 ... first and second layers, 82g ... two-dimensional electron gas, 83 ... source electrode (first electrode), 84 ... drain electrode (Second electrode), 85 ... gate electrode (third electrode), ΔC ... thermal expansion coefficient difference, ΔC1, ΔC2 ... difference, α ... inclination angle, β ... angle, θ1, θ2 ... angle, 110, 121-124, 131: nitride semiconductor device, CR: crack, D1 to D3: first to third directions, L1: length, SP10, SP20, SP30, SP11, SP31 ... first to fifth samples, d1, d2 ... distance, p1-p3 ... part

Claims (20)

第１面に沿って広がる窒化物半導体層であって、
第１領域であって、前記第１面に対して平行な第１方向における前記第１領域の長さは、前記第１面に対して平行で前記第１方向に対して垂直な第２方向における前記第１領域の長さよりも長い前記第１領域と、
前記第２方向において前記第１領域と並ぶ第２領域であって、前記第１方向における前記第２領域の長さは、前記第２方向における前記第２領域の長さよりも長い前記第２領域と、
を備え、
前記第１領域及び前記第２領域のｃ軸は、前記第２方向に対して傾斜し、
前記ｃ軸は、前記第１面に対して垂直な第３方向と交差し、
前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜した、窒化物半導体層。 A nitride semiconductor layer extending along a first surface,
The length of the first region in the first direction parallel to the first surface is a second direction parallel to the first surface and perpendicular to the first direction. The first region being longer than the length of the first region in
The second region, which is aligned with the first region in the second direction, wherein the length of the second region in the first direction is longer than the length of the second region in the second direction. When,
With
The c-axis of the first region and the second region is inclined with respect to the second direction,
The c-axis intersects a third direction perpendicular to the first surface ;
The nitride semiconductor layer , wherein the c-axis is inclined with respect to a plane including the second direction and the third direction . 前記ｃ軸と、前記第１面と、の間の角度は、０度以上８５度以下である請求項１記載の窒化物半導体層。   The nitride semiconductor layer according to claim 1, wherein an angle between the c-axis and the first surface is not less than 0 degrees and not more than 85 degrees. 前記ｃ軸を前記第１面に投影した方向と、前記第２方向と、の間の角度は、５度以上８５度以下である請求項１または２に記載の窒化物半導体層。   3. The nitride semiconductor layer according to claim 1, wherein an angle between a direction in which the c-axis is projected on the first surface and the second direction is not less than 5 degrees and not more than 85 degrees. 前記第１面は、（１１−２２）面、（１０−１１）面、（１１−２０）面、及び、（１０−１０）面のいずれかに対して平行である請求項１〜３のいずれか１つに記載の窒化物半導体層。   The first surface is parallel to any of the (11-22) plane, the (10-11) plane, the (11-20) plane, and the (10-10) plane. The nitride semiconductor layer as described in any one. 前記窒化物半導体層は、
第１導電形の第１半導体層と、
前記第３方向において前記第１半導体層と離間し第２導電形の第２半導体層と、
前記第１半導体層と前記第２半導体層との間に設けられた活性層と、
を含む請求項１〜４のいずれか１つに記載の窒化物半導体層。 The nitride semiconductor layer is
A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type spaced apart from the first semiconductor layer in the third direction;
An active layer provided between the first semiconductor layer and the second semiconductor layer;
The nitride semiconductor layer according to claim 1, comprising: 上面と、前記上面に対して傾斜する複数の斜面と、を含む主面を有する基板であって、前記上面に対して平行な第１方向における前記複数の斜面のそれぞれの長さは、前記上面に対して平行で前記第１方向に対して垂直な第２方向における前記複数の斜面のそれぞれの長さよりも長く、前記複数の斜面は前記第２方向に並ぶ、前記基板と、
前記複数の斜面から成長された窒化物半導体層と、
を備え、
前記窒化物半導体層のｃ軸は、前記第２方向に対して傾斜し、
前記ｃ軸は、前記上面に対して垂直な第３方向と交差し、
前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜した、窒化物半導体装置。 A substrate having a main surface including an upper surface and a plurality of inclined surfaces inclined with respect to the upper surface, wherein each length of the plurality of inclined surfaces in a first direction parallel to the upper surface is the upper surface Longer than each of the plurality of slopes in a second direction parallel to the first direction and perpendicular to the first direction, the plurality of slopes being aligned in the second direction; and
And the nitride semiconductor layer grown from the plurality of inclined surfaces,
With
A c-axis of the nitride semiconductor layer is inclined with respect to the second direction;
The c-axis intersects a third direction perpendicular to the top surface ;
The nitride semiconductor device , wherein the c-axis is inclined with respect to a plane including the second direction and the third direction . 前記基板の少なくとも一部が除去されている請求項６記載の窒化物半導体装置。   The nitride semiconductor device according to claim 6, wherein at least a part of the substrate is removed. 窒化物半導体層を備え、
上面と、前記上面に対して傾斜する複数の斜面と、を含む主面を有する基板であって、前記上面に対して平行な第１方向における前記複数の斜面のそれぞれの長さは、前記上面に対して平行で前記第１方向に対して垂直な第２方向における前記複数の斜面のそれぞれの長さよりも長く、前記複数の斜面は前記第２方向に並ぶ、前記基板の前記複数の斜面から、前記窒化物半導体層は成長され、
前記窒化物半導体層のｃ軸は、前記第２方向に対して傾斜し、
前記ｃ軸は、前記上面に対して垂直な第３方向と交差し、
前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜した、窒化物半導体装置。 Comprising a nitride semiconductor layer;
A substrate having a main surface including an upper surface and a plurality of inclined surfaces inclined with respect to the upper surface, wherein each length of the plurality of inclined surfaces in a first direction parallel to the upper surface is the upper surface Longer than each of the plurality of slopes in a second direction parallel to the first direction and perpendicular to the first direction, the plurality of slopes being aligned in the second direction from the plurality of slopes of the substrate The nitride semiconductor layer is grown;
A c-axis of the nitride semiconductor layer is inclined with respect to the second direction;
The c-axis intersects a third direction perpendicular to the top surface ;
The nitride semiconductor device , wherein the c-axis is inclined with respect to a plane including the second direction and the third direction . 前記ｃ軸と前記上面との間の角度は、０度以上８５度以下である請求項６〜８のいずれか１つに記載の窒化物半導体装置。   The nitride semiconductor device according to any one of claims 6 to 8, wherein an angle between the c-axis and the upper surface is not less than 0 degrees and not more than 85 degrees. 前記上面に前記ｃ軸を投影した方向と、前記第２方向と、の間の角度は、５度以上８５度以下である請求項６〜９のいずれか１つに記載の窒化物半導体装置。   10. The nitride semiconductor device according to claim 6, wherein an angle between a direction in which the c-axis is projected on the upper surface and the second direction is not less than 5 degrees and not more than 85 degrees. 前記窒化物半導体層の（１１−２２）面、（１０−１１）面、（１１−２０）面、及び、（１０−１０）面のいずれかは、前記上面に対して平行である請求項６〜１０のいずれか１つに記載の窒化物半導体装置。   The (11-22) plane, (10-11) plane, (11-20) plane, or (10-10) plane of the nitride semiconductor layer is parallel to the upper surface. The nitride semiconductor device according to any one of 6 to 10. 前記基板は、シリコン基板である請求項６〜１１のいずれか１つに記載の窒化物半導体装置。   The nitride semiconductor device according to claim 6, wherein the substrate is a silicon substrate. 前記上面は、シリコンの（１１３）面、（００１）面、（１１２）面、及び、（１１０）面のいずれかに対して平行である請求項１２記載の窒化物半導体装置。   The nitride semiconductor device according to claim 12, wherein the upper surface is parallel to any of a (113) plane, a (001) plane, a (112) plane, and a (110) plane of silicon. 前記基板は、前記第２方向に並ぶ複数の凹部を有し、
前記複数の斜面のそれぞれは、前記複数の凹部のそれぞれの側面の一部である請求項６〜１３のいずれか１つに記載の窒化物半導体装置。 The substrate has a plurality of recesses arranged in the second direction,
The nitride semiconductor device according to claim 6, wherein each of the plurality of inclined surfaces is a part of a side surface of each of the plurality of recesses. 前記基板は、前記第２方向に並ぶ複数の凹部を有し、
前記複数の凹部のそれぞれは、互いに向かい合う第１側面及び第２側面を含み、
前記複数の斜面のそれぞれは、前記複数の凹部のそれぞれの前記第１側面である請求項６〜１３のいずれか１つに記載の窒化物半導体装置。 The substrate has a plurality of recesses arranged in the second direction,
Each of the plurality of recesses includes a first side surface and a second side surface facing each other,
The nitride semiconductor device according to claim 6, wherein each of the plurality of inclined surfaces is the first side surface of each of the plurality of recesses. 前記複数の凹部のそれぞれの深さは、０．３マイクロメートル以上３マイクロメートル以下である請求項６〜１５のいずれか１つに記載の窒化物半導体装置。   The nitride semiconductor device according to any one of claims 6 to 15, wherein each of the plurality of recesses has a depth of not less than 0.3 micrometers and not more than 3 micrometers. 前期複数の凹部のそれぞれの深さは、前記複数の凹部のそれぞれの間の前記上面の前記第２方向の長さの０．３倍以上３倍以下である請求項６〜１６のいずれか１つに記載の窒化物半導体装置。   The depth of each of the plurality of recesses in the previous period is not less than 0.3 times and not more than 3 times the length in the second direction of the upper surface between each of the plurality of recesses. The nitride semiconductor device described in 1. 前記窒化物半導体層は、
第１半導体層と、
前記第１半導体層と前記基板との間に設けられた下地層と、
を含み、
前記第１半導体層における不純物濃度は、前記下地層における不純物濃度よりも高い請求項６〜１７のいずれか１つに記載の窒化物半導体装置。 The nitride semiconductor layer is
A first semiconductor layer;
An underlayer provided between the first semiconductor layer and the substrate;
Including
The nitride semiconductor device according to claim 6, wherein an impurity concentration in the first semiconductor layer is higher than an impurity concentration in the base layer. 前記上面に対して平行な面内に並ぶ第１電極と、第２電極と、第３電極と、をさらに備え、
前記第１電極、前記第２電極及び前記第３電極と、前記基板と、の間に前記窒化物半導体層が配置され、
前記窒化物半導体層は、機能層を含み、
前記機能層は、第１層と、第２層と、を含み、
前記第１層と前記基板との間に前記第２層が配置され、
前記第１層の格子定数は、前記第２層の格子定数よりも小さい請求項６〜１８のいずれか１つに記載の窒化物半導体装置。 A first electrode arranged in a plane parallel to the upper surface, a second electrode, and a third electrode;
The nitride semiconductor layer is disposed between the first electrode, the second electrode, the third electrode, and the substrate;
The nitride semiconductor layer includes a functional layer,
The functional layer includes a first layer and a second layer,
The second layer is disposed between the first layer and the substrate;
The nitride semiconductor device according to claim 6, wherein a lattice constant of the first layer is smaller than a lattice constant of the second layer. 上面と、前記上面に対して傾斜する複数の斜面と、を含む主面を有する基板であって、前記上面に対して平行な第１方向における前記複数の斜面のそれぞれの長さは、前記上面に対して平行で前記第１方向に対して垂直な第２方向における前記複数の斜面のそれぞれの長さよりも長く、前記複数の斜面は前記第２方向に並ぶ、前記基板を用意し、
前記複数の斜面からエピタキシャル成長により窒化物半導体層を成長させ、
前記窒化物半導体層のｃ軸は、前記第２方向に対して傾斜し、
前記ｃ軸は、前記上面に対して垂直な第３方向と交差し、
前記ｃ軸は、前記第２方向及び前記第３方向を含む平面に対して傾斜した、窒化物半導体層の製造方法。 A substrate having a main surface including an upper surface and a plurality of inclined surfaces inclined with respect to the upper surface, wherein each length of the plurality of inclined surfaces in a first direction parallel to the upper surface is the upper surface A substrate that is longer than each of the plurality of inclined surfaces in a second direction parallel to the first direction and perpendicular to the first direction, the plurality of inclined surfaces being arranged in the second direction;
Growing a nitride semiconductor layer by epitaxial growth from the plurality of slopes;
A c-axis of the nitride semiconductor layer is inclined with respect to the second direction;
The c-axis intersects a third direction perpendicular to the top surface ;
The method for manufacturing a nitride semiconductor layer , wherein the c-axis is inclined with respect to a plane including the second direction and the third direction .
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