JP6198566B2 - IMAGING DEVICE, IMAGING SYSTEM, IMAGING DEVICE CONTROL METHOD, PROGRAM, AND STORAGE MEDIUM - Google Patents

Description

  The present invention relates to an imaging apparatus that performs focus detection using an imaging element including focus detection pixels.

  2. Description of the Related Art Conventionally, imaging devices that perform high-speed and high-precision focus detection using an image sensor including focus detection pixels are known. Patent Document 1 discloses a configuration in which focus detection pixels and defect data are mixed in an image sensor including focus detection pixels. Specifically, each pixel of the focus detection pixel has an address, whether or not it is a defect, information on whether or not it is a pupil division direction, and whether it is an A image or a B image, and a configuration in which a degree of freedom is secured. It has become. Patent Document 2 discloses a method of thinning out and reading out signal charges from an image sensor having a predetermined pixel arrangement.

JP 2009-163229 A JP 2009-60597 A

  However, when the image sensor having the pixel arrangement disclosed in Patent Document 2 is applied to the configuration of Patent Document 1, the amount of data for each focus detection pixel stored in the ROM or RAM increases. In addition, with the increase in the number of pixels in the image sensor, a technique (N-width processing) in which a plurality of pixels (N pixels) are processed in parallel in one cycle is used. It will double.

  Therefore, the present invention provides an imaging apparatus, an imaging system, an imaging apparatus control method, a program, and a storage medium that can perform high-speed and high-precision focus detection while suppressing an increase in data amount and circuit scale.

Imaging apparatus according to one aspect of the present invention includes a storage unit for storing an image sensor for outputting a pixel signal by photoelectrically converting an optical image, the compressed information obtained by compressing the information about the focus detection image element of the image sensor, decoding means for decoding the information about the compressed the focus detection image element has, on the basis of the information decoded by said decoding means, for separating the focus detection signal obtained from the focus detection pixels of the pixel signal Signal separation means, and the focus detection pixels are repeatedly arranged in a predetermined pattern in the imaging device, and the compression information includes position information of the focus detection pixels included in the predetermined pattern, and , The number of repetitions of the predetermined pattern .

  An imaging system according to another aspect of the present invention includes a lens device including a photographing optical system and the imaging device.

Control method for an imaging apparatus as another aspect of the present invention includes the steps of outputting a pixel signal by photoelectrically converting an optical image, storage means for storing the compressed information obtained by compressing the information about the focus detection image element of the image sensor from the steps of reading and decoding the information about the compressed the focus detection image element has, on the basis of the decoded said information and separates the focus detection signal obtained from the focus detection pixels of the pixel signal step The focus detection pixels are repeatedly arranged in a predetermined pattern in the image sensor, and the compression information includes position information of the focus detection pixels included in the predetermined pattern, and the predetermined Including the number of times the pattern is repeated .

  A program according to another aspect of the present invention is configured to cause a computer to execute a method for controlling the imaging apparatus.

  A storage medium according to another aspect of the present invention stores the program.

  Other objects and features of the present invention are illustrated in the following examples.

  According to the present invention, there are provided an imaging device, an imaging system, an imaging device control method, a program, and a storage medium capable of high-speed and high-precision focus detection while suppressing an increase in data amount and circuit scale.

It is a block diagram of the imaging device in each embodiment. It is a block diagram of the focus detection pixel contained in the image pick-up element in each Example. It is an arrangement view of focus detection pixels included in the image sensor in each embodiment. It is explanatory drawing of the pixel information and compression information in each Example. It is explanatory drawing of the compression method in Example 1. FIG. In Example 1, it is explanatory drawing of the compression method when a defective pixel is contained. 3 is a circuit diagram of a decoder in Embodiment 1. FIG. FIG. 10 is an explanatory diagram of a shift register according to a third embodiment. It is a circuit diagram of the defective pixel position interpretation circuit in each embodiment. 6 is a circuit diagram of a decoder in Embodiment 2. FIG. It is explanatory drawing of the compression method in Example 2. FIG. It is explanatory drawing of the compression method in Example 3. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, with reference to FIG. 1, the circuit configuration of the imaging apparatus according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram of an imaging apparatus 100 in the present embodiment.

  In FIG. 1, reference numeral 101 denotes a lens unit (imaging optical system). In the present embodiment, the lens unit 101 is configured integrally with the imaging apparatus main body, but is not limited thereto. The present embodiment can also be applied to an imaging system including an imaging apparatus body and a lens unit (lens apparatus) that can be attached to and detached from the imaging apparatus body.

  Reference numeral 102 denotes an image sensor. The image sensor 102 includes focus detection pixels in at least some of the plurality of pixels, photoelectrically converts a subject image (optical image) obtained via the lens unit 101, and outputs a pixel signal. Details of the structure of the image sensor 102 will be described later. Reference numeral 109 denotes an A / D conversion circuit. The A / D conversion circuit 109 converts the pixel signal (analog image signal) output from the image sensor 102 into a digital image signal.

  Reference numeral 103 denotes a pixel information ROM (storage means). The pixel information ROM 103 stores information relating to the focus detection pixels and defective pixels of the image sensor 102 in a compressed state. That is, the pixel information ROM 103 stores pixel information such as positions and types of focus detection pixels and defective pixels among a plurality of pixels included in the image sensor 102. The pixel information ROM 103 can also store information relating to dummy pixels in a compressed state. In this case, a focus detection pixel separation circuit 104 and a defective pixel interpolation circuit 105, which will be described later, are configured to ignore signals input from the dummy pixels.

  Reference numeral 110 denotes a decoder (decoding means). The decoder 110 decodes (decodes) the compressed pixel information. That is, the decoder 110 decodes information related to the compressed focus detection pixel and defective pixel. Reference numeral 111 denotes a defective pixel position interpretation circuit (position determination means). The defective pixel position interpretation circuit 111 interprets pixel information such as the position and type of defective pixels and focus detection pixels. In particular, the defective pixel position interpretation circuit 111 determines the position of the defective pixel using the information decoded by the decoder 110. A focus detection pixel separation circuit 104 described later separates focus detection signals based on the determination result by the defective pixel position interpretation circuit 111. A defective pixel interpolation circuit 105 described later interpolates a pixel signal corresponding to the defective pixel based on the determination result by the defective pixel position interpretation circuit 111.

  Reference numeral 104 denotes a focus detection pixel separation circuit (signal separation means). The focus detection pixel separation circuit 104 separates the focus detection signal obtained from the focus detection pixel among the pixel signals based on the information decoded by the decoder 110. That is, the focus detection pixel separation circuit 104 extracts (extracts) and separates the signal obtained from the focus detection pixel from the signal (digital image signal) from the A / D conversion circuit 109.

  Reference numeral 105 denotes a defective pixel interpolation circuit (signal interpolation means). The defective pixel interpolation circuit 105 interpolates the pixel signal corresponding to the defective pixel based on the information decoded by the decoder 110. That is, the defective pixel interpolation circuit 105 interpolates defective pixels (signals corresponding to defective pixels) of the image sensor 102. Reference numeral 106 denotes a development processing circuit (signal processing means). The development processing circuit 106 generates a color video signal based on an output signal (image signal) from the image sensor 102. That is, the development processing circuit 106 generates an image using the pixel signal obtained from the image sensor 102 and the pixel signal corresponding to the defective pixel interpolated by the defective pixel interpolation circuit 105.

  Reference numeral 108 denotes a focus detection circuit (focus detection means). The focus detection circuit 108 calculates the defocus amount based on the output signal from the focus detection pixel (the focus detection signal obtained from the focus detection pixel separation circuit 104). Reference numeral 107 denotes a control microcomputer (control means) that controls the entire system. The control microcomputer 107 controls the lens unit 101 (performs focus control) according to the focus detection result (defocus amount) of the focus detection circuit 108.

  Next, the configuration of focus detection pixels included in the image sensor 102 will be described with reference to FIG. FIG. 2 is a configuration diagram of focus detection pixels included in the image sensor 102. 2A is a top view of the focus detection pixel, FIG. 2B is a cross-sectional view of the focus detection pixel, and FIG. 2C is a top view of another focus detection pixel.

  As shown in FIGS. 2A to 2C, the regions 203 and 204 are light receiving regions formed by the openings of the light shielding plates 207 and 208, respectively. The light flux obtained through the lens unit 101 is transmitted through the microlenses 205 and 206 to the light receiving element 201 (first focus detection pixel for A image) and the light receiving element 202 (second focus detection for B image). Incident on the pixel). Light beams that have passed through different pupil regions of the lens unit 101 (imaging optical system) are incident on the light receiving elements 201 and 202 (focus detection pixels) by the micro lenses 205 and 206, respectively. With such a configuration, the pupil of the lens unit 101 (photographing optical system) is divided symmetrically left and right. The state shown in FIG. 2A is called a horizontal eye because the pupil is divided in the horizontal direction, and the state shown in FIG. 2C is called a vertical eye because the pupil is divided in the vertical direction.

  Next, the arrangement of focus detection pixels included in the image sensor 102 will be described with reference to FIG. FIG. 3 is a layout diagram of focus detection pixels included in the image sensor 102. As shown in FIG. 3A, a plurality of focus detection pixels are repeatedly arranged in the region 311 (inside the broken line portion) of the image sensor 102. Numerical values (32, 24, 8,...) Displayed in FIG. 3A are distances from one focus detection pixel to the next focus detection pixel. In addition, the numerical value and period displayed on Fig.3 (a) are examples, and a present Example is not limited to this.

  FIG. 3B is a detailed example in which one set of focus detection pixels is repeatedly arranged. The image sensor 102 of this embodiment employs an R, G, B Bayer array. Reference numeral 301 denotes a horizontal A image pixel AF_AW, 302 a horizontal B image pixel AF_BW, 303 a vertical A image pixel AF_AH, and 304 a vertical B image pixel AF_BH. In this embodiment, the focus detection pixels are replaced with the G pixels. The A image pixel 301 (AF_AW) is 24 pixels after the A image pixel 301 (AF_AW), the pixel 301 (AF_AW) is 8 pixels later, the pixel 303 (AF_AH) is 16 pixels later, and the next set of A Image pixels are arranged. Such a pixel arrangement is repeated in the region 311.

  Next, pixel information stored in the pixel information ROM 103 will be described with reference to FIG. FIG. 4 is an explanatory diagram of pixel information and compression information. As shown in FIG. 4A, the image information includes an ID 401, an operand 402, and position information 403, and is stored in the pixel information ROM 103. The types of pixel information include focus detection pixel information 404, defective pixel information 405, and dummy pixel information 406. The pixel information ROM 103 includes compression information 407 (dictionary reference command). In this embodiment, pixel information and compression information are 22 bits.

  ID 401 indicates whether the pixel is a focus detection pixel, a defective pixel, or a dummy pixel (pixel information) or compression information, and is composed of 2 bits. The focus detection ID indicates that the pixel is a focus detection pixel. The defective pixel ID indicates that the pixel is a defective pixel. The defective pixel includes a defect whose gain is to be corrected, a defect which is to be interpolated from surrounding pixels, and a defect whose offset is to be corrected. The dummy ID indicates that the pixel is a dummy pixel. The dummy pixel is not processed as a defective pixel. Details of the dummy pixel will be described later.

  Regarding the pixel information (404 to 406), the operand 402 differs depending on the ID 401 and is composed of 4 bits. The position information 403 stores position information in common and is composed of 16 bits. The pixel position information 403 is not stored as XY coordinates, but is stored as a relative pixel distance from the previous defective pixel to the next defective pixel. By storing it as a relative distance between pixels, it is possible to express with a small number of bits. For example, to express a sensor of 4000 × 3000 pixels by the XY coordinate position, 12 bits + 12 bits and 24 bits are required. If the relative distance from the previous time is 16 bits, it is possible to efficiently store about one defective pixel in 64 kilopixels on average. When the relative distance is 16 bits and the next defective pixel exists at a distance exceeding 64 kilopixels, the distance is compensated using dummy pixel information 406 (dummy ID). In the case of the dummy pixel information 406, neither the defective pixel nor the focus detection pixel is processed.

  The compression information is information for compressing repeatedly detected focus detection pixel information 404 or defective pixel information 405. The compression information is composed of a compression ID of 2 bits, LENGTH of 10 bits, and COUNT of 10 bits. Details of these will be described later.

  As shown in FIGS. 4B and 4C, numbers are assigned to the ID 401 and the operand 402 so that the types of pixel information (404 to 406) and compression ID (compression information 407) can be distinguished and decoded. It has become. The number of bits in this embodiment is merely an example, and the present invention is not limited to these.

  Next, a method of compressing the pixel information (404 to 406) with the compression information 407 (compression ID) will be described with reference to FIGS. As shown in FIG. 3, as an example, it is assumed that the focus detection pixels are a set of four pixels and are repeated 100 times in one line.

  First, consider the case where there are no defective pixels and the focus detection pixels are repeated under the above conditions. FIG. 5 is an explanatory diagram of the compression method in this embodiment. As shown in FIG. 5A, all IDs 401 indicate focus detection IDs, and operands 402 all indicate aperture IDs. The aperture ID is shown in the order of the A image of the horizontal eye, the A image of the vertical eye, the A image of the horizontal eye, and the A image of the vertical eye. The position information 403 indicates the numerical value of the distance shown in FIG. The head position information (= 4100 pixels) is the distance from the upper left pixel of the image (meaning that it is the first focus detection pixel), or the last focus detection pixel, defective pixel, Or the distance from a dummy pixel is shown.

  When FIG. 5A is compressed, it can be expressed as shown in FIG. Following the second set of pixel information, a compression ID indicating compression information 407, LENGTH indicating the number of pixel information included in the set, and COUNT indicating how many times the set is repeated are specified. Since one set is composed of four pixels, LENGTH = 4 and the second set of pixel information is used 98 times from the third set to the 100th set, so COUNT = 98.

  Next, consider a case where there is one defective pixel in the middle of repeating the focus detection pixel. FIG. 6 is an explanatory diagram of a compression method when defective pixels are included. As shown in FIG. 6A, if a defective pixel ID enters between the focus detection ID and the focus detection ID of the 31st set, that one set cannot be compressed. Therefore, as shown in FIG. 6B, the first 28 sets are compressed and the latter 68 sets are compressed.

  Next, the circuit configuration of the decoder 110 will be described with reference to FIG. FIG. 7 is a circuit diagram of the decoder 110. When the pixel of the image sensor 102 is a focus detection pixel or a defective pixel, the decoder 110 reads pixel information or compression information from the pixel information ROM 103. When the ID 401 is a compression ID, DEC_EN = 1. On the other hand, when the ID 401 is not a compression ID, that is, when the ID 401 is a focus detection ID, a defective pixel ID, or a dummy ID, DEC_EN = 0. The ID 401 stored at the top in the pixel information ROM 103 is always one of a focus detection ID, a defective pixel ID, or a dummy ID. For this reason, pixel information is written in an SRAM (not shown) in the decoder 110.

  When DEC_EN = 0, WRITE_EN = 1. Thereby, the pixel information including the ID 401, the operand 402, and the position information 403 read from the pixel information ROM 103 is stored in the shift register 704 in the decoder 110. In this embodiment, as shown in FIGS. 5 and 6, since LENGTH = 4, the data is stored in the four FFs 705 to 708 (flip-flops) in the shift register 704 of FIG. Since it is actually a shift register, pixel information is input from the FF 705, and when the next pixel information is input, the pixel information is shifted toward the FF 706. Finally, the first pixel information is stored in FF 708, the second pixel information is stored in FF 707, the third pixel information is stored in FF 706, and the fourth pixel information is stored in FF 705.

  When DEC_EN = 1 when the compression information is input, the value of COUNT included in the compression information is loaded as the initial value of the counter 701, and the value of LENGTH is loaded as the initial value of the counter 702. The counter 701 and the counter 702 are counted down in a cycle in which the pixel is a focus detection pixel or a defective pixel.

  The count value of the counter 702 having an initial value of (LEGNTH-1) is set as SEL, and the FFs 705 to 708 in the shift register 704 are selected according to the value of SEL. When SEL is 3, FF 708 is selected, when it is 2, FF 707 is selected, when it is 1, FF 706 is selected, and when it is 0, FF 705 is selected. The counter 702 is a down counter, and after SEL = 0, the counter 702 is reset to 3 and the FF 708 is selected.

  The pixel information selected by SEL is output to the selector 703. REPLACE_EN = 1 until the counter 701 loaded with the value of COUNT becomes zero. Then, the pixel information read from the shift register 704 in the selector 703 is output to the defective pixel position interpretation circuit 111. When the value of the counter 701 becomes 0, REPLACE_EN = 0, and the pixel information stored next to the compression information is read from the pixel information ROM 103.

  Next, the defective pixel position interpretation circuit 111 will be described with reference to FIG. FIG. 9 is a circuit diagram of the defective pixel position interpretation circuit 111. Pixel information output from the decoder 110 is loaded into the pixel ID circuit 901, the operand circuit 902, and the pixel position down counter 903, respectively. Pixel ID circuit 901 loads ID 401, operand circuit 902 loads operand 402, and pixel position down counter 903 loads position information 403.

  The pixel position down counter 903 loaded with the position information 403 counts down every time a pixel (pixel signal) passes. Until the pixel position down counter 903 becomes 0, the NOT gate 904 generates a BUSY signal and suppresses transfer of the next data. When the pixel position down counter 903 finishes counting, the output of the NOT gate 904 becomes 1, the BUSY signal is released, and the next pixel information is loaded. On the other hand, the ID 401 loaded in the pixel ID circuit 901 is held during that time, and the ID detection circuit 906 determines whether the ID 401 is a type to be processed.

  The AND gate 907 ANDs the determination result and the timing output of the pixel position down counter 903 and outputs a defect flag. The defect to be processed is designated by the ID designation register 905. The setting of the ID designation register 905 can be changed by the control microcomputer 107. In the case of the focus detection ID and the defective pixel ID, they are detected by the ID detection circuit 906, and a defect flag is output. On the other hand, since the dummy ID is ignored by the ID detection circuit 906, the defect flag is not output.

  A circuit similar to the ID designation register 905 in the defective pixel position interpretation circuit 111 is provided in both the defective pixel interpolation circuit 105 and the focus detection pixel separation circuit 104, and the setting contents of the ID designation register are different from each other. In the ID designation register in the focus detection pixel separation circuit 104, only the focus detection ID is registered. On the other hand, in the ID designation register 905 of the defective pixel interpolation circuit 105, the focus detection ID is registered as a defective pixel in addition to the defective pixel ID. With such a setting, the focus detection pixel can be interpolated as a defective pixel and the focus detection pixel can be separated.

  The dummy ID is not registered in the ID designation register in either the defective pixel interpolation circuit 105 or the focus detection pixel separation circuit 104. For this reason, although it counts down, there is no detection output. For the focus detection pixel separation circuit 104, a defective pixel is also treated as a dummy ID. In this manner, by skipping pixel information whose contents to be processed are not determined, an infrared pixel arrangement can be configured discretely, for example. Therefore, even when a processing circuit is added, it is possible to expand the focus detection pixel separation circuit 104 and the defective pixel interpolation circuit 105 without changing by adding an infrared pixel separation circuit.

  In the focus detection pixel separation circuit 104 in FIG. 1, an A image and a B image are output separately from the aperture ID specified by the operand 402 and input to the focus detection circuit 108. The focus detection circuit 108 calculates the defocus amount based on the image shift amount between the A image and the B image. Note that the details of the focus detection circuit 108 are not the essence of the present invention, and thus the description thereof is omitted. Further, the details of the defective pixel interpolation method are not the essence of the present invention, and the description thereof will be omitted. In this embodiment, when the focus detection pixel has a defect, it can be dealt with by increasing the ID 401 by one type. The defective pixel information 405 can also be compressed using the compression information 407.

  As described above, in the present embodiment, the pixel information ROM 103 preferably stores the position information regarding the focus detection pixel and the defective pixel (and the dummy pixel as necessary) and the compression information for compressing the position information. I remember it. The compression information includes the number of pixels included in the repetitive pattern of the position information of the focus detection pixel and the defective pixel (and the position information of the dummy pixel as necessary) and the number of the repetitive pattern.

  Next, a second embodiment of the present invention will be described. In the present embodiment, a case will be described in which the input from the image sensor 102 is N pixels per cycle, and N double width processing in which N pixels are processed in parallel by a circuit. In the present embodiment, the case of N = 2 will be described. However, the present invention is not limited to this, and can be applied to a case of N ≧ 3.

  FIG. 10 is a circuit diagram of the decoder 1010 in the present embodiment. 10, the same elements as those of the first embodiment described with reference to FIG. 7 are denoted by the same reference numerals. In this embodiment, since double width processing is performed (N = 2), two signals (image signals) output from the A / D conversion circuit 109 are output per cycle.

  Next, pixel information and compression information stored in the pixel information ROM 103 will be described with reference to FIG. FIG. 11 is an explanatory diagram of a compression method in the present embodiment. If only the focus detection pixel information 404 with LENGTH = 3 is arranged as shown in FIG. 11A, the double width processing is performed, so that one pixel is left. Therefore, when the pixel information is arranged in the pixel information ROM 103 and when compression is performed, the arrangement alignment is adjusted to double width. As shown in FIG. 11B, the dummy pixel information 406 is inserted into the fourth to match the double width alignment. Since the dummy ID is ignored in the subsequent circuit, the position information of the dummy pixel information 406 may be set somewhere between the previous pixel information and the next pixel information. LENGTH of the compression information 407 is (the number of sets of pixel information including dummy pixel information) / (N-fold width). Therefore, in the case of FIG. 11B, LENGTH = 4 / double width = 2. For COUNT, as in the first embodiment, COUNT = (98 repetitions of one set).

  Hereinafter, as illustrated in FIG. 11B, the order of the pixel information is referred to as an odd-numbered pixel and an even-numbered pixel. Since the set of repeated pixel information is double-width aligned, the compression information 407 is always an odd-numbered pixel.

  In FIG. 10, out of the double width, pixel information or compression information 407 connected from the pixel information ROM 103 to the selector 703 is an odd pixel, and pixel information connected to the selector 1003 is an even pixel. The decoder 1010 performs decoding with reference to the compression information 407 of the odd-numbered pixels.

  In the shift register 704 of this embodiment, odd-numbered pixel information is stored in FF 705 and FF 707, and even-numbered pixel information is stored in FF 706 and FF 708. The pixel information of the first cycle is stored in FF707 and FF708, and the pixel information of the second cycle is stored in FF705 and FF706. The FF 706 stores dummy pixel information.

  When the compression information 407 is input, the value of (LENGTH = 2-1) is loaded as an initial value into the counter 702 as in the first embodiment, and the shift register 704 selects any of FF705 to FF708 according to SEL as the counter value. Select whether to output pixel information. When SEL = 1, the shift register 704 reads out the pixel information of the FF 707, and the selector 703 outputs this pixel information. At the same time, the shift register 704 reads out the pixel information of the FF 708, and the selector 1003 outputs this pixel information. On the other hand, when SEL = 0, the shift register 704 reads out the pixel information of the FF 705, and the selector 703 outputs this pixel information. At the same time, the shift register 704 reads the dummy pixel information 406 of the FF 706, and the selector 1003 outputs the dummy pixel information 406.

  In FIG. 10, a defective pixel position interpretation circuit 1011 has a counter for odd pixels and a counter (not shown) for even pixels. The details of the defective pixel position interpretation circuit 1011 are not the essence of the present invention, and thus the description thereof is omitted. As described above, even in the case of the N-fold width, by inserting the dummy pixel information 406, it is possible to use a circuit similar to the single-width described in the first embodiment.

  As described above, in this embodiment, the decoder 110 reads N defective pixels, focus detection pixels, and compression information from the pixel information ROM 103 per cycle (N ≧ 2). The compression information is set (encoded) so as to have a cycle that is a multiple of N.

  As described above, in this embodiment, the decoder 110 reads out the pixels (focus detection pixels and defective pixels) included in the repetitive pattern from the pixel information ROM 103 by N (N ≧ 2) per cycle. The compression information is set so that the number of pixels included in one repetitive pattern is a multiple of N. Preferably, the compression information includes information on dummy pixels so that the number of pixels included in the repetitive pattern is a multiple of N.

  Next, Embodiment 3 of the present invention will be described. In the present embodiment, a case will be described in which N-fold width processing is performed, and the compression information 407 includes ADDRESESS indicating the address of the FF in the shift register 704. In the present embodiment, the case of N = 2 will be described. However, the present invention is not limited to this, and can be applied to a case of N ≧ 3.

  The pixel information and compression information 407 stored in the pixel information ROM 103 will be described with reference to FIG. FIG. 12 is an explanatory diagram of a compression method in the present embodiment. As shown in FIG. 12A, focus detection pixel information 404 with LENGTH = 3 is arranged, and a defective pixel ID is inserted between the focus detection ID and the focus detection ID of the 31st set. Then, as shown in FIG. 12B, a dummy ID is inserted so as to achieve double-width alignment as in the second embodiment. Since the 2nd to 30th sets in FIG. 12A are repetitions of the same pattern, compression information is inserted following the 2nd set. In the 31st group, since the defective pixel ID is inserted, the compression is not performed, and the compression ID for compressing the 32nd group to the 100th group is inserted after the 31st group.

  Here, the operation of the shift register 704 in this embodiment will be described with reference to FIG. FIG. 8 is an explanatory diagram of the shift register 704. FIG. 8A shows that the pixel information of the second set is stored in order from FF 705 to FF 708. The method of reading from the shift register 704 up to the 30th set is the same as in the second embodiment.

  The address (ADDRESS) of the compression information of the 3rd to 30th sets in FIG. Starting from ADDRESS = 1, (LENGTH = 2) × (double width) = 4 pixels are read out COUNT = 28 times. Next, the pixel information of the 31st set is stored in the shift register 704, but the already stored 2nd set of pixel information is shifted to the FFs 709 to 712 shown in FIG. 8B. The 31st set of pixel information is stored in FF705 to FF708. Next, since the 32nd to 100th sets have the same pattern as the second set, ADDRESS of the compression information indicates 3. Starting from ADDRESS = 3, (LENGTH = 2) × (double width) = 4 pixels are read out COUNT = 69 times. Thus, even if the repeated pattern is divided at an arbitrary place, a remote reference destination can be specified, and a further compression effect can be obtained.

  As described above, in this embodiment, the compression information includes the number of pixels included in the repetitive pattern of the position information of the focus detection pixel and the defective pixel (and the position information of the dummy pixel as necessary) and the number of repetitive patterns. Including. The compression information includes an address related to position information of the defective pixel or focus detection pixel at the head of the repetitive pattern.

[Other Embodiments]
The present invention is also realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and the computer (or CPU, MPU, etc.) of the system or apparatus reads the program. To be executed. In this case, a computer-executable program describing the procedure of the imaging apparatus control method and a storage medium storing the program constitute the present invention.

  According to each embodiment, by compressing the amount of data for each focus detection pixel and defective pixel, it is possible to obtain the effects of reducing the memory usage and simplifying the circuit. Further, by using dummy pixel information in order to match the number of repeated sets of pixel information with an alignment that is a multiple of N, N pixels can be processed in one cycle. Therefore, according to each embodiment, there are provided an imaging device, an imaging system, an imaging device control method, a program, and a storage medium capable of high-speed and high-precision focus detection while suppressing an increase in data amount and circuit scale To do.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

DESCRIPTION OF SYMBOLS 100 Imaging device 102 Imaging element 103 Image information ROM
104 focus detection pixel separation circuit 105 defective pixel interpolation circuit 110 decoder

Claims (15)

An image sensor that photoelectrically converts an optical image and outputs a pixel signal;
Storage means for storing the compressed information obtained by compressing the information about the focus detection image element of the image sensor,
Decoding means for decoding the information about the compressed the focus detection image element has,
Signal separation means for separating a focus detection signal obtained from the focus detection pixel among the pixel signals based on the information decoded by the decoding means ;
The focus detection pixels are repeatedly arranged in a predetermined pattern in the image sensor,
The imaging apparatus , wherein the compression information includes position information of the focus detection pixels included in the predetermined pattern and the number of repetitions of the predetermined pattern . The imaging apparatus according to claim 1, wherein the compression information further includes a number of information indicating positions of the focus detection pixels included in the predetermined pattern. The compression information further includes position information of dummy pixels included in the predetermined pattern,
The imaging apparatus according to claim 2, wherein the information indicating the position of the focus detection pixel included in the predetermined pattern includes position information of the focus detection pixel and position information of the dummy pixel. The imaging apparatus according to claim 1, wherein the compression information further includes position information of defective pixels. The imaging apparatus according to claim 4, wherein the compression information includes an address related to position information of the defective pixel or the focus detection pixel at the head of the predetermined pattern. The imaging apparatus according to claim 4, wherein the compression information includes the number of repetitions of the predetermined pattern in a range not including the defective pixel. Position determining means for determining the position of the focus detection pixel and the defective pixel using the information decoded by the decoding means ;
Signal interpolation means for interpolating pixel signals corresponding to the focus detection pixels and the defective pixels based on the determination result by the position determination means;
The imaging apparatus according to any one of claims 4 Optimum 6 to feature to further have a. It said decoding means, from the storage unit, one by N per 1-cycle the focus detection image element included in the predetermined pattern (N ≧ 2) read,
The imaging apparatus according to claim 3 , wherein the compression information is set so that the number of pixels included in the predetermined pattern is a multiple of N. Wherein the compression information, as the number of the pixels included in the repeating pattern is a multiple of N, the imaging apparatus according to claim 8, characterized in that it contains the position information of the dummy pixels. Focus detection means for calculating a defocus amount based on the focus detection signal obtained from the signal separation means;
The imaging apparatus according to any one of claims 1 to 9, further comprising a control means for performing focus control in accordance with the defocus amount.   11. The imaging apparatus according to claim 1, wherein the focus detection pixel outputs the focus detection signal based on light beams that have passed through different pupil regions of the photographing optical system. A lens device equipped with a photographing optical system;
An imaging system comprising: the imaging device according to claim 1. Photoelectrically converting the optical image and outputting a pixel signal;
From a storage means for storing the compressed information obtained by compressing the information about the focus detection image element of the image pickup device, a step of reading and decoding the information about the compressed the focus detection image element has,
Separating the focus detection signal obtained from the focus detection pixel among the pixel signals based on the decoded information ,
The focus detection pixels are repeatedly arranged in a predetermined pattern in the image sensor,
The method for controlling an imaging apparatus, wherein the compression information includes position information of the focus detection pixels included in the predetermined pattern and the number of repetitions of the predetermined pattern .   A program configured to cause a computer to execute the control method of the imaging apparatus according to claim 13.   A storage medium storing the program according to claim 14.