JP6191530B2 - Bus communication system and master communication device - Google Patents

Description

  The present invention relates to a bus communication system in which a master communication device and a slave communication device are connected via a single bus (data transmission path), and the bus is pulled up by a pull-up resistor. It relates to the master communication apparatus.

  Conventionally, there is provided a bus communication system in which a master communication device and a slave communication device are connected via a single bus (data transmission path), and the bus is pulled up by a pull-up resistor (for example, Patent Document 1).

Japanese Patent Laid-Open No. 60-117843

  In this type of bus communication system, when the slave communication device transmits a data signal superimposed on the synchronization signal transmitted from the master communication device, both the synchronization signal from the master communication device and the data signal from the slave communication device are A section that becomes a low level occurs. That is, the output waveform from the master communication device and the output waveform from the slave communication device overlap, and a waveform collision occurs. When a waveform collision occurs, when the synchronization signal from the master communication device is switched from low level to high level (when rising), the current that was previously drawn to the master communication device side will flow to the slave communication device side all at once. . As a result, there is a problem in that noise may be superimposed on the data signal transmitted from the slave communication device to the master communication device.

  The present invention has been made in view of the circumstances described above, and an object of the present invention is to provide a bus communication system and a master that can reduce the possibility of noise overlapping with a data signal transmitted from the slave communication device to the master communication device. It is to provide a communication device.

  According to the first aspect of the present invention, the single bus connecting the master communication device and the slave communication device is pulled up by the pull-up resistor. In the master communication device, the master driver circuit intermittently transmits the synchronization signal at a predetermined transmission cycle. In the slave communication device, when the synchronization signal is received by the slave side receiver circuit, the synchronization circuit generates a synchronization timing from the synchronization signal, and the slave side driver circuit transmits the data signal superimposed on the synchronization signal following the synchronization timing. To do. In the master communication device, the master side driver circuit receives the data signal by the master side receiver circuit.

  The phenomenon in which the current drawn to the master communication device side, which is the subject of the present invention, flows all at once to the slave communication device side is that a waveform collision occurs when the slave communication device transmits a data signal (bit string) at a low level. This occurs every time the synchronization signal is switched from the low level to the high level while the data signal is being transmitted at the low level. In response to such a problem, the comparison circuit compares the waveform of the synchronization signal transmitted from the master side driver circuit with the waveform of the signal on the bus, and determines whether or not the two waveforms match. When the comparison circuit determines that the two waveforms do not match, the transmission control circuit suppresses transmission of the synchronization signal from the master side driver circuit (stops or thins out transmission). By suppressing the transmission of the synchronization signal from the master side driver circuit in this way, the occurrence of waveform collision can be suppressed, and the synchronization signal is changed from the low level to the high level while the slave communication device is transmitting the data signal at the low level. The frequency of switching can be suppressed. As a result, it is possible to suppress the frequency of occurrence of a phenomenon in which the current drawn to the master communication device side flows to the slave communication device side at once, and to reduce the possibility of noise being superimposed on the data signal.

Functional block diagram showing a first embodiment of the present invention Timing chart (1) Timing chart (2) Timing chart (part 3) Timing chart (4) Functional block diagram showing a second embodiment of the present invention Timing chart (4)

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The bus communication system 1 is configured by connecting a master communication device 2 and a plurality of slave communication devices 3 via a single bus 4. A pull-up resistor 5 and a diode 6 are connected in series between the bus 4 and the power supply voltage (Vdd). That is, the bus 4 is connected to the power supply voltage side by the pull-up resistor 5 so that a high level or low level voltage is applied to the master communication device 2 and the slave communication device 3. If an intermediate voltage between the high level and the low level is applied to the master communication device 2 or the slave communication device 3, the internal state may become unstable or malfunction. Further, when a voltage lower than the low level or a voltage higher than the high level is applied to the master communication device 2 or the slave communication device 3, there is a possibility that a current outside the design flows to cause a circuit breakdown or the like. In this configuration, since the bus 4 is connected to the power supply voltage side by the pull-up resistor 5, it is possible to avoid such a possible malfunction and stabilize the operation of the entire system. . The master communication device 2 and the plurality of slave communication devices 3 are, for example, integrated circuits (ICs).

  The master communication device 2 includes a logic circuit 7, a driver circuit 8 (master side drive circuit), and a receiver circuit 9 (master side receiver circuit). The logic circuit 7 includes a data transmission circuit 7a, a data reception circuit 7b, a data comparison circuit 7c (comparison circuit), and a data transmission control circuit 7d (transmission control circuit). The data transmission circuit 7a generates transmission data (bit string), and outputs the generated transmission data to the data comparison circuit 7c and the data transmission control circuit 7d. The data transmission circuit 7a may output transmission data input from the outside to the data comparison circuit 7c and the data transmission control circuit 7d as they are. When the data reception circuit 7b inputs the reception data by a signal (signal on the bus 4) input from the receiver circuit 9 (A2), the data reception circuit 7b outputs the input reception data to the data comparison circuit 7c. When the data comparison circuit 7c receives the transmission data from the data transmission circuit 7a and receives the reception data from the data reception circuit 7b, the data comparison circuit 7c compares the input transmission data with the reception data, and a control command corresponding to the comparison result. Is output to the data transmission control circuit 7d. The data transmission control circuit 7d controls (allows or prohibits) the output (A1) of the transmission data input from the data transmission circuit 7a to the driver circuit 8 based on the control command input from the data comparison circuit 7c.

  The driver circuit 8 has a drain terminal or a collector terminal connected to the bus 4 and is an open drain or open collector output circuit. In the master communication device 2, the logic circuit 7 itself may be replaced with a microcomputer or the like.

  The slave communication device 3 includes a logic circuit 10, a receiver circuit 11 (slave side receiver circuit), and a driver circuit 12 (slave side driver circuit). The logic circuit 10 includes a falling edge detection circuit 10a, a synchronization circuit 10b, a data transmission circuit 10c, and a data transmission control circuit 10d. When the falling edge detection circuit 10a detects the falling edge of the signal (the signal on the bus 4) input from the receiver circuit 11 (B2, X2), it outputs the detection of the falling edge to the synchronization circuit 10b. When receiving the falling edge detection from the falling edge detection circuit 10a, the synchronization circuit 10b establishes synchronization at the timing of the falling edge and outputs a synchronization command to the data transmission control circuit 10d. The data transmission circuit 10c generates transmission data (bit string) and outputs the generated transmission data to the data transmission control circuit 10d. Note that, similarly to the data transmission circuit 7a of the master communication device 2, the data transmission circuit 10 may output transmission data input from the outside to the data transmission control circuit 10d as it is. The data transmission control circuit 10d controls the output (B1, X1) of the transmission data input from the data transmission circuit 10c to the driver circuit 12 based on the synchronization command input from the synchronization circuit 10b.

  The driver circuit 12 has a drain terminal or a collector terminal connected to the bus 4 and is an open drain or open collector output circuit. In the slave communication device 3, the logic circuit 10 itself may be replaced by a microcomputer or the like.

Next, the operation of the above configuration will be described with reference to FIGS.
As shown in FIG. 5, it is assumed that the master communication device 2 intermittently transmits a synchronization signal from the driver circuit 8 at a predetermined transmission cycle (t1, t3, t7, t9, t13, and t17 in FIG. 5). At this time, the master communication device 2 follows the transmission of the synchronization signal, the signal on the bus 4 is switched from the high level to the low level, and a current (bus current) flows on the master communication device 2 side on the bus 4. The slave communication device 3 detects the switching of the signal on the bus 4 from the high level to the low level, and receives the synchronization signal transmitted from the master communication device 2 by the receiver circuit 11. When receiving the synchronization signal by the receiver circuit 11, the slave communication device 3 detects the falling edge of the received synchronization signal by the falling edge detection circuit 10a, and establishes synchronization by the synchronization circuit 10b at the timing of the falling edge. Then, the synchronization timing is generated. The slave communication device 3 follows the synchronization timing, and superimposes the data signal on the synchronization signal and transmits it from the driver circuit 12 (t4, t10, t14 in FIG. 5).

  In this case, in the configuration in which the slave communication device 3 transmits the data signal superimposed on the synchronization signal, the output waveform from the master communication device 2 and the output waveform from the slave communication device 3 overlap, and a waveform collision occurs (FIG. 5). Middle t4 to t5, t10 to t11, t14 to t15). When a waveform collision occurs, when the synchronization signal from the master communication device 2 is switched from a low level to a high level (rising up), the current that has been drawn to the master communication device 2 side until then is immediately transferred to the slave communication device 3 side. Flows (maximum current change occurs). As a result, there is a possibility that noise is superimposed on the data signal transmitted from the slave communication device 3 to the master communication device 2. That is, as shown in FIG. 5, if the master communication device 2 continues to transmit the synchronization signal intermittently at a predetermined transmission cycle, a phenomenon in which the maximum current change occurs frequently occurs. The possibility of noise increases.

  In consideration of this point, in the present invention, in the master communication device 2, the data comparison circuit 7c compares the transmission data input from the data transmission circuit 7a with the reception data input from the data reception circuit 7b, so that the driver The waveform of the synchronization signal transmitted from the circuit 8 is compared with the waveform of the signal on the bus 4. When the data comparison circuit 7c detects that the waveform of the synchronization signal transmitted from the driver circuit 8 is different from the waveform of the signal on the bus 4, the data comparison circuit 7c outputs a control command indicating output stop of the transmission data to the data transmission control circuit 7d. To do. When the data transmission control circuit 7d receives a control command indicating stop of transmission data output from the data comparison circuit 7c, the data transmission control circuit 7d stops output of the transmission data to the driver circuit 8 and stops transmission of the synchronization signal from the driver circuit 8. (Suppress transmission).

  That is, as shown in FIG. 2, when the master communication device 2 detects that the waveform of the synchronization signal transmitted from the driver circuit 8 is different from the waveform of the signal on the bus 4 at the timing t5 in FIG. Thereafter, for example, by resetting the driver circuit 8 or fixing the input of the driver circuit 8 to a high level to fix the output of the driver circuit 8 to a high level, the synchronization signal is transmitted from the driver circuit 8. Stop. Stopping the transmission of the synchronization signal means continuously performing control that does not transmit the synchronization signal at the original transmission timing of the synchronization signal. Specifically, the master communication device 2 transmits the synchronization signal from the driver circuit 8 at the timing t3 in FIG. 2, but stops transmitting the synchronization signal at the timings t7, t9, and t13 in FIG. As a result, when the slave communication device 3 transmits a data signal (bit string), it is only necessary to cause a waveform collision at the beginning (first time) of the data signal, and the transmission of the data signal is completed thereafter. Waveform collision does not occur until As a result, when the slave communication device 3 transmits a data signal, if the data signal to be transmitted in one transmission is M bytes, and N bits of them are at a low level, there is a possibility that noise will overlap the data signal. Compared to the conventional configuration (configuration of FIG. 5), it is possible to reduce to 1 / N. In the slave communication device 3, the operation of the synchronization circuit 10 b may be continued or stopped during the period in which the master communication device 2 stops transmitting the synchronization signal.

  In addition, as shown in FIG. 2, if the slave communication device 3 transmits the data signal at the timing when the synchronization signal is originally transmitted during the period in which the master communication device 2 stops transmitting the synchronization signal. Thus, synchronization with other slave communication devices 3 can be ensured. Further, if it is not necessary to ensure synchronization with other slave communication devices 3 or if synchronization with low accuracy is sufficient (if synchronization with high accuracy is not required), as shown in FIG. The slave communication device 3 may transmit the data signal while keeping the signal constant.

  Further, as shown in FIG. 4, after detecting that the waveform of the synchronization signal transmitted from the driver circuit 8 is different from the waveform of the signal on the bus 4, the master communication device 2 performs synchronization from the driver circuit 8. The signal transmission may be thinned out without stopping (t29, t35, t41 in FIG. 4). To thin out the transmission of the synchronization signal is to intermittently perform control that does not transmit the synchronization signal at the transmission timing of the original synchronization signal. Even with such a configuration, it is possible to reduce the possibility of noise being superimposed on the data signal as compared with the conventional configuration. Further, in this case, since it is only thinned out without stopping the transmission of the synchronization signal, it is possible to ensure synchronization with other slave communication devices 3. Note that the master communication device 2 may thin out the transmission of the synchronization signal at any rate.

  Further, when the data length is stored in the transmission frame of the data signal transmitted by the slave communication device 3, the master communication device 2 reads the data length from the signal waveform on the bus 4 and detects the end of transmission. Thereafter, the stop or thinning of the transmission of the synchronization signal is canceled, and the transmission of the synchronization signal may be resumed (t17 in FIG. 2). When the data length is not stored in the transmission frame of the data signal transmitted by the slave communication device 3, the master communication device 2 detects the synchronization signal after detecting the end of reception of the data signal from the slave communication device 3. It suffices to cancel the transmission stop or thinning and restart the transmission of the synchronization signal.

  As described above, according to the first embodiment, when the master communication device 2 compares the waveform of the synchronization signal transmitted by itself with the waveform of the signal on the bus 4 and determines that the two waveforms match. The transmission of simultaneous signals was suppressed. Thereby, the occurrence of waveform collision can be suppressed, and the frequency at which the synchronization signal is switched from the low level to the high level while the slave communication device 3 is transmitting the data signal at the low level can be suppressed. As a result, it is possible to suppress the frequency of occurrence of a phenomenon in which the current drawn to the master communication device 2 side flows to the slave communication device 3 side at once, and to reduce the possibility of noise being superimposed on the data signal. it can. In this case, if the transmission of the synchronization signal is stopped by suppressing the transmission of the synchronization signal, only the waveform collision occurs at the beginning (first time) of the data signal. Can be completely suppressed. In addition, if the transmission of the synchronization signal is thinned out to suppress the transmission of the synchronization signal, the possibility of noise overlapping with the data signal can be reduced, and synchronization with other slave communication devices 3 can be ensured. It becomes possible to do.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In addition, description is abbreviate | omitted about the same part as above-mentioned 1st Embodiment, and a different part is demonstrated. In the second embodiment, the slave communication device 22 includes a voltage reading circuit 23 in addition to the logic circuit 10, the receiver circuit 11, and the driver circuit 12. The voltage reading circuit 23 reads the voltage of the signal on the bus 4 and outputs the read voltage to the driver circuit 12. The driver circuit 12 accelerates / decelerates the voltage change of the data signal based on the voltage input from the voltage reading circuit 23. That is, the slave communication device 22 accelerates or decelerates the voltage change of the data signal transmitted from the driver circuit 12 based on the voltage of the signal on the bus 4, thereby converting the data signal into a rectangular wave (square wave). Transmit with a waveform with a gentler voltage change. In this case, since the noise easily overlaps the edge portion of the edge, it is possible to make it difficult for the noise to overlap the data signal by slowing the voltage change.

  As described above, according to the second embodiment, in the slave communication device 3, the voltage change of the data signal is accelerated / decelerated. As a result, the possibility of noise overlapping with the data signal can be further reduced.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be modified or expanded as follows.
In the second embodiment, a configuration in which a current reading circuit that reads the current of a signal flowing on the bus 4 may be provided instead of the voltage reading circuit 23. The slave communication device 22 may be provided with a voltage reading circuit 23 and a current reading circuit, and the master communication device 2 may be provided with a voltage reading circuit and a current reading circuit so as to accelerate and decelerate the voltage change of the synchronization signal. . If comprised in this way, in addition to reducing the possibility that noise will overlap with a data signal, the possibility that noise will overlap with a synchronizing signal can also be reduced.

  In the drawing, 1 and 21 are bus communication systems, 2 is a master communication device, 3 and 22 are slave communication devices, 4 is a bus, 7c is a data comparison circuit (comparison circuit), and 7d is a data transmission control circuit (transmission control circuit). , 8 is a driver circuit (master side driver circuit), 9 is a receiver circuit (master side receiver circuit), 10b is a synchronization circuit, 11 is a receiver circuit (slave side receiver circuit), 12 is a driver circuit (slave side driver circuit), Reference numeral 23 denotes a voltage reading circuit.

Claims (9)

A single bus (4) connecting the master communication device (2) and the slave communication device (3, 22) is pulled up by a pull-up resistor (5), and the master communication device sends a synchronization signal to a predetermined signal. A slave-side receiver that includes a master-side driver circuit (8) that intermittently transmits data at a transmission cycle and a master-side receiver circuit (9) that receives a data signal, wherein the slave communication device receives the synchronization signal. A circuit (11), a synchronization circuit (10b) for generating a synchronization timing from the synchronization signal, a slave side driver circuit (12) for transmitting the data signal following the synchronization timing and overlapping the synchronization signal, In a bus communication system (1, 21) comprising:
A comparison circuit (7c) that compares the waveform of the synchronization signal transmitted from the master side driver circuit with the waveform of the signal on the bus to determine whether or not the two waveforms match;
A transmission control circuit (7d) that suppresses transmission of the synchronization signal from the master driver circuit when the comparison circuit determines that the waveforms of the two do not match; Bus communication system. The bus communication system according to claim 1,
The synchronization circuit continues to operate even during a period in which the transmission control circuit suppresses transmission of the synchronization signal,
The bus-side communication system, wherein the slave-side driver circuit transmits the data signal at the predetermined transmission period in a period in which the master-side driver circuit suppresses transmission of the synchronization signal. The bus communication system according to claim 1,
The bus communication system, wherein the synchronization circuit stops operating in a period in which the transmission control circuit suppresses transmission of the synchronization signal. In the bus communication system according to any one of claims 1 to 3,
The bus control system, wherein the transmission control circuit stops transmission of the synchronization signal from the master side driver circuit as suppressing transmission of the synchronization signal. In the bus communication system according to any one of claims 1 to 3,
The bus communication system, wherein the transmission control circuit thins out the transmission of the synchronization signal from the master side driver circuit as suppressing the transmission of the synchronization signal. The bus communication system according to any one of claims 1 to 5,
The transmission control circuit cancels the suppression of the transmission of the synchronization signal when the transmission end of the data signal from the slave side driver circuit is specified after the transmission of the synchronization signal is suppressed. Bus communication system. The bus communication system according to claim 6,
The transmission control circuit reads the data length of the data signal transmitted from the slave side driver circuit, and specifies the end of reception of the data signal of the read data length, thereby the data from the slave side driver circuit. A bus communication system characterized by identifying the end of signal transmission. The bus communication system according to any one of claims 1 to 7,
A voltage reading circuit (23) for reading the voltage of the signal on the bus;
The bus-side communication system, wherein the slave side driver circuit accelerates or decelerates the voltage change of the data signal based on the voltage of the signal on the bus read by the voltage reading circuit. A single bus (4) connected to the slave communication device (3, 22) is pulled up by a pull-up resistor (5), and the slave communication device generates a synchronization timing from the synchronization signal and outputs a data signal. A master side driver circuit (8) used in a bus communication system (1, 21) that transmits the synchronization signal following the synchronization timing, and transmits the synchronization signal intermittently at a predetermined transmission cycle. In a master communication device (2) comprising a master side receiver circuit (9) for receiving the data signal,
A comparison circuit (7c) that compares the waveform of the synchronization signal transmitted from the master side driver circuit with the waveform of the signal on the bus to determine whether or not the two waveforms match;
A transmission control circuit (7d) that suppresses transmission of the synchronization signal from the master side driver circuit when the comparison circuit determines that the waveforms of the two do not match; Master communication device.

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