DE102018110252A1 - Transceiver, system with transceivers and signal - Google Patents

Abstract

A transceiver is provided, comprising: a transmitter adapted to
to provide at a output a first signal according to a physical communication protocol, and
providing at the output a second signal comprising at least one cryptographic datum, the first and the second signal being superimposed as an overlay signal at the output, and the overlay signal satisfying the physical communication protocol. Appropriate transceivers with receivers, systems and signals are also provided.

Description

TECHNICAL AREA

The present application relates to transceivers, systems with such transceivers, corresponding signals and corresponding methods.

BACKGROUND

Many devices contain a variety of components that communicate with each other to exchange data. An example of such devices are vehicles in which a plurality of control units, such as microcontrollers, communicate with each other to control various vehicle functions. In addition, sensors in vehicles detect physical quantities and communicate with the aforementioned control units to communicate the measured quantities. Examples of such control units in vehicles include engine controls, transmission controls, anti-theft control units, and the like. Examples of sensors include cameras, speed sensors, radar sensors, temperature sensors, and the like.

The communication between the various components can be wireless or wired, with wired communication being used in many applications. In vehicles, the CAN (controller area network) bus is often used ISO 11898 standardized. Other bus systems, such as the FlexRay bus ( ISO 17458-1 to ISO 17458-4 ) or LIN bus (future ISO 17987-1) can be used.

In such devices, it may happen that a communication device intends to participate in the communication between the components. For example, an external communication device may be connected to a CAN bus of a vehicle to manipulate the vehicle, for example, to adjust a mileage of a speedometer or to override theft protection measures of the vehicle. Therefore, it is desirable to be able to detect such communication devices attempting unauthorized intervention.

SHORT VERSION

There are provided transceivers and a signal as defined in the independent claims. The dependent claims define further embodiments as well as a system with such transceivers.

• einen Transmitter, der dazu ausgebildet ist,
  • - an einem Ausgang ein erstes Signal gemäß eines physikalischen Kommunikationsprotokolls bereitzustellen, und
  • - an dem Ausgang ein zweites Signal bereitzustellen, das mindestens ein kryptographisches Datum umfasst, wobei das erste und das zweite Signal als ein Überlagerungssignal an dem Ausgang einander überlagert sind, und wobei das Überlagerungssignal das physikalische Kommunikationsprotokoll erfüllt.

According to one embodiment, a transceiver is provided, comprising:

• a transmitter designed to
  • to provide at a output a first signal according to a physical communication protocol, and
  • providing at the output a second signal comprising at least one cryptographic datum, the first and the second signal being superimposed as an overlay signal at the output, and the overlay signal satisfying the physical communication protocol.

• einen Receiver, der dazu ausgebildet ist,
  • - ein Empfangssignal, welches eine Überlagerung eines ersten Signals gemäß einem physikalischen Kommunikationsprotokoll mit einem zweiten Signal, das ein kryptographisches Datum umfasst, ist, zu empfangen,
  • - das Empfangssignal gemäß dem physikalischen Kommunikationsprotokoll zu verarbeiten, um in dem ersten Signal übertragene Informationen zu gewinnen, und
  • - aus dem Empfangssignal das kryptographische Datum zu gewinnen.

According to another embodiment, there is provided a transceiver comprising:

• a receiver that is designed to
  • a receive signal which is a superposition of a first signal according to a physical communication protocol with a second signal comprising a cryptographic datum,
  • to process the received signal according to the physical communication protocol to obtain information transmitted in the first signal, and
  • - From the received signal to win the cryptographic date.

• - einem erstes Signal gemäß eines physikalischen Kommunikationsprotokolls, und
• -einem zweites Signal, das mindestens ein kryptographisches Datum umfasst,

wobei das Signal das physikalische Kommunikationsprotokoll erfüllt.According to another embodiment, a signal is provided comprising an overlay of:

• - a first signal according to a physical communication protocol, and
• a second signal comprising at least one cryptographic datum,

wherein the signal meets the physical communication protocol.

list of figures

• 1 is a block diagram of a system according to some embodiments.
• 2 is a flowchart of a method according to some embodiments.
• 3 shows a system according to some embodiments.
• 4 shows a communication circuit with a transceiver according to some embodiments.
• 5 shows a driver circuit for generating various signal levels, which may be used in some embodiments.
• 6-9 show examples of signals according to some embodiments.
• 10 shows a part of a transmitter for a CAN bus.
• 11 shows curves for the circuit of the 10 with variation of different parameters.
• 12 shows curves for the circuit of the 10 with variation of different parameters.
• 13 shows a communication circuit for transceivers according to some embodiments.
• 14 shows curves to illustrate some embodiments.
• 15 shows a communication circuit according to some embodiments.
• 16 shows a communication circuit for transceivers according to some embodiments.
• 17 shows a communication circuit for transceivers according to some embodiments.
• 18 shows a communication circuit for transceivers according to some embodiments.
• 19 shows a communication circuit for transceivers according to some embodiments.
• 20 shows a communication circuit for transceivers according to some embodiments.
• 21 shows curves to illustrate some embodiments.
• 22 and 23 show diagrams to illustrate the influence of electromagnetic interference.
• 24 shows a system according to some embodiments.
• 25 shows a flowchart for illustrating a method according to some embodiments.
• 27-36 show communication circuits for transceivers according to some embodiments.
• 37 FIG. 12 shows a physical communication protocol and a logic protocol layer according to some embodiments. FIG.

DETAILED DESCRIPTION

In the following, various embodiments will be described in detail. It should be understood that these embodiments are for illustration only and are not to be construed as limiting. Thus, a description of an embodiment having a plurality of features (e.g., components, properties, acts, etc.) should not be construed as requiring all of these features to implement the particular embodiment. Rather, some features may be replaced by alternative features or omitted. In addition to the features explicitly illustrated, additional features, such as features used in conventional communication circuits, may also be provided.

Features of various embodiments may be combined with each other unless otherwise specified. Variations and modifications, which for one of the embodiments are also applicable to other embodiments and are therefore not described repeatedly.

In the following, various embodiments of communication circuits and arrangements of such communication circuits will be explained in detail. Although the communication circuits will be described in part with reference to certain communication media, particularly certain bus systems such as a CAN bus, the illustrated techniques are also applicable to other communication media, for example, wired communication media, wireless communication media, or optical communication media such as optical fibers. The use of specific examples is therefore merely illustrative.

In the description, reference is made in part to a physical communication protocol of the communication and a logic protocol layer of the communication. The physical communication protocol defines functions corresponding to the physical layer of the OSI layer model and defines how data to be transmitted, eg a bit stream, is converted into physical signals on a transmission medium. The logic protocol layer is superior to the physical communication protocol and, for example, relates to higher layers of the OSI model or even layers above the OSI model (applications) and can in particular relate to which data is transmitted, including encoding or encryption of the data. This is in 37 with a physical communication protocol 370 and a parent logic protocol layer 371 illustrated.

1 is a schematic representation of a system 10 according to some embodiments with a first communication circuit 11 which serves as a transmitter in the example shown, ie as a transmitter, and a second communication circuit 12 , which serves as a receiver, ie receiver in the example shown. The system 10 may be part of a device such as a vehicle, and the communication circuits 11 . 12 may be arranged in components of this device to allow communication of the components with each other.

The communication circuit 11 sends via a communication medium 13 Signals to the communication circuit 12 , The communication medium 13 may be a wireless communication medium, a wired communication medium or even an optical communication medium. In the case of a wired communication medium may be, in particular, a bus system such as a CAN bus, a FlexRay bus or a LIN bus, but is not limited thereto.

While in 1 the communication circuit 11 as a transmitter and the communication circuit 12 is shown as a receiver, the communication circuit 11 also additional circuit parts for receiving signals and / or the communication circuit 12 additionally comprise circuit parts for transmitting signals in order to enable bidirectional communication, so that the communication circuits 11 . 12 both are designed as transceivers (transceivers).

Communication via the communication medium 13 takes place according to a physical communication protocol. Such physical communication protocols are defined for different types of communication and define, as explained above, in particular, how an information to be sent (payload data, control data and the like) is to be converted into physical signals (on a communication medium or wirelessly). For example, voltage levels are defined for the CAN bus and similar bus systems which define two different states corresponding to a logical 1 and a logic 0, and signals are sent as a sequence of such voltage levels. However, other types of signals are possible, such as frequency modulated signals, ac signals, quadrature amplitude (QAM) modulated signals, and the like.

For this purpose, a signal generating circuit receives 15 an information to be sent, eg user data or control data to be sent, and generates a first signal s1 according to the physical communication protocol. The information to be transmitted can be obtained as a logic signal from a logic protocol layer arranged above the physical communication protocol in accordance with a logic protocol. This first signal s1 As explained, for example, it may have two or more different voltage or current levels to convert the information into the signal. This signal generation can be done in any conventional manner for the particular physical communication protocol.

In addition, by means of a modulation circuit 16 the first signal s1 with a second signal s2 which is a cryptographic date 14 covers, superimposed. A cryptographic date is included in particular, a code or other date that authenticates one over the communication medium 13 transmitted signal as coming from an authorized communication user (ie, communication users who are allowed to communicate with each other). For example, the cryptographic date may be a predetermined bit sequence that is only known or determinable by authorized communication users. An unauthorized communication participant, eg a communication device, unauthorized with the communication medium 13 On the other hand, as explained in the introduction, the cryptographic date is not known, for example because no corresponding key is provided to it. The cryptographic date can be generated using conventional cryptographic techniques, eg, based on a cryptographic key that the transmitter 11 from a parent instance, as will be explained later. The term "cryptographic" is thus not to be understood in the strict sense as encryption, but in the broader sense as an element indicative that contributes to the system 10 resistant to manipulation. The cryptographic date can in particular a security code of the transmitter 11 represent which the transmitter 11 identified as the source of a transmitted signal and thus allows authentication.

In the modulation circuit 16 becomes the second signal s2 with the cryptographic date at the physical level to that of the signal generating circuit 15 generated first signal s1 modulated, eg by modifying signal levels of the first signal s1 so as to form a beat signal s. This differs from approaches in which information to be sent is encrypted, which corresponds to encryption on a logical protocol layer. However, as will be explained later, such encryption or other coding may be additionally performed on the logic protocol layer.

In some embodiments, the communication protocol defines tolerances for levels to use. For example, the communication protocol may specify that a level corresponding to a logical 1 must be within a first voltage range and / or that a level corresponding to a logical 0 must be within a second voltage range, each validly recognized as 1 or 0 to become. In embodiments, the modulation circuit then modulates the first signal by being superimposed with the second such that the levels of the signal remain within the specified ranges. Even with other types of communication protocols, amplitudes of the second signal s2 be so small that the beat signal s meets the physical communication protocol, that is, that the beat signal s is processable according to the physical communication protocol to the information of the first signal s1 regain. This may ensure backward compatibility in some embodiments, ie, receivers that are not as later for the receiving circuit 12 discussed, can receive the signal correctly. Examples of such superpositions of signals will be explained in more detail later.

It should also be noted that the signal generation circuit 15 and the modulation circuit 16 Although illustrated for illustrative purposes as blocks connected in series, as explained later, the modulation and the signal generation can also take place simultaneously. The arrangement shown thus serves only to illustrate the various functions.

The thus modulated overlay signal s is then transmitted via the communication medium 13 to the communication circuit 12 Posted. The communication circuit 12 includes a signal receiving circuit 17 showing the information which is generated by the signal generating circuit 15 in the first signal s1 was implemented, recovers. In addition, the communication circuit 12 a code reception circuit 18 on, which in the by the modulation circuit 16 modulated second signal s2 retrieves the contained cryptographic date. If the cryptographic date retrieved in this way does not match an expected cryptographic date (eg, one in the communication circuit 12 stored cryptographic date or a cryptographic date derived from a provided key), measures can be taken. For example, the received signal and the information derived therefrom may be discarded, a corresponding signal may be generated to inform other components of the unauthenticated signal, and / or a user may be informed. In this way, unauthorized access attempts may be detected in some embodiments, and countermeasures may be taken.

The signal receiving circuit 17 can be configured in a conventional manner for the respective physical communication protocol. Examples of the code receiving circuit 18 and in particular, calibration possibilities for the code reception circuit 18 will be explained later. It should be noted that the communication circuit 12 can also process received signals, which are only the first signal contain or in which the second signal is not processable because of disturbances, for example. In this case, for example, only the signal receiving circuit 17 processed.

2 FIG. 10 is a flow chart illustrating methods according to some embodiments. FIG. To avoid repetition, the procedure of the 2 with reference to the 1 explained. The procedure of 2 However, it is also independent of the device 1 usable.

at 20 an information to be sent is converted into a first signal. As already for the signal generation circuit 15 This can be done on the basis of a physical communication protocol, so that a signal is generated which has levels that can represent a logical 1 and a logical 0, or otherwise transmits the information to be transmitted.

at 21 the transmit signal is modulated in accordance with a second signal comprising a cryptographic datum, as for the modulation circuit 16 in 1 described. The cryptographic date can be generated based on a key. Thus, a heterodyne signal is generated which complies with the physical communication protocol as described above. As for the signal generation circuit 15 and the modulation circuit 16 of the 1 must also described the implementation at 20 and modulating at 21 not take place one after the other, but can also be carried out simultaneously.

Receiver side is then at 22 the information is retrieved from the beat signal as for the signal receiving circuit 17 described, and at 23 the cryptographic data is retrieved from the beat signal, as for the code receiving circuit 18 of the 1 described. Also gaining the information 22 and gaining the cryptographic date 23 do not have to like in 2 shown sequentially, but can also be done simultaneously or in a different order. Meets that 23 If the cryptographic date obtained does not match an expected cryptographic date, appropriate action can be taken, as already described with reference to 1 explained.

The 3 shows a communication circuit arrangement according to some embodiments, in which as a communication medium, a CAN bus 36 is used. In the embodiment of the 3 serves a communication circuit 30 . 35 as a transmitter, and a communication circuit 31 . 37 as receiver. The reference number 30 refers to a transmitting node, a transceiver 35 supplied with data to be sent and a security code. The transceiver 35 can also serve to receive data, what in 3 is not explicitly shown. The sending node 30 can be implemented by means of a microcontroller.

Data to be sent will be sent to a send buffer 33 of the transmitting node 30 written in a conventional way. These data to be sent are transmitted by a transmission circuit 34 converted into a bit sequence to be sent, ie a sequence of logical ones and zeros, since then as a signal Tx to the transceiver 35 is sent.

A security code generator 32 receives a key and generates a security code as a cryptographic date based on this key. The key can be received by a key management device, which is specially protected, in particular by a hardware security module (HSM), as will be explained in more detail later.

The security code generator 32 further receives information about the data to be transmitted and a position of so-called dominant transmission bits, and generates the security code in the illustrated example of the CAN protocol so that the security code is modulated only to dominant bits of a data part of the transmission. Also in other physical communication protocols, certain levels may be selected to which the second signal is modulated with the cryptographic date.

Dominant bits are bits in which a bus is like the CAN bus 36 is actively driven to a level while being passively pulled to a different level by resistors in so-called recessive bits. In CAN transmission, bits representing a logical 0 are dominant bits, and bits representing a logical 1 are recessive bits. For other communication standards, this may be different and, for example, all bits may be actively driven. "Only one data part" refers to the fact that the transmission takes place in CAN and other communication protocols in so-called frames, which have a so-called header followed by the data part for payload data. In some embodiments, the security code is modulated only to this data part. This can be advantageous in the CAN protocol because multiple transmitters can simultaneously transmit on the CAN bus during the header. In other embodiments, in particular other physical communication protocols, header bits for modulation with the security code can also be used.

The transceiver 35 then modulates the amplitudes of the dominant bits according to the security code, which in this embodiment corresponds to the superposition of the second signal. By knowing the data and the bit positions, the security code generator can generate the security code in such a way that bit changes of the security code (from 0 to 1 or from 1 to 0) only occur with dominant bits. An example of this will be explained later. Here, the second signal is thus a pulse-shaped signal with two states corresponding to 0 and 1. In other embodiments, other types of second signals, such as alternating current signals such as QAM modulated signals, can be used, as long as a cryptographic date is transferable.

On the receiver side, a CAN transceiver decodes 37 the security code from the sent signal and provides a receive circuit 38 a receiving node 31 In addition, a reception signal based on the received levels according to the CAN communication protocol ready. The receiving circuit 38 takes place from the signal Rx receive data received in a receive buffer 39 get saved.

The recovered security code, the position of received bits, and the received data become a verification circuit 310 provided. The verification circuit 310 receives the key based on which the security code generator 32 has generated the security code. Based on the key, the receive data, and the receive bit position, the verification circuitry may 310 determine an expected security code according to the same rules, according to which the security code generator 32 has determined the security code from the key, the transmission data and the transmission bit position. Examples of this will be explained. This expected security code is then compared to the received security code. If they match, authentication succeeds and the received data can be used. In the event of a mismatch, the authentication failed and, as already described with reference to the 1 explained actions are taken.

An example of the structure of CAN transceivers according to embodiments, for example, the CAN transceivers 35 . 37 of the 3 , are now with reference to the 4 and 5 explained.

4 shows a CAN transceiver 41 according to an embodiment, which with a microcontroller 40 communicated. The microcontroller 40 can in particular the for the transmitting node 30 of the 3 and / or the receiving node 31 of the 3 take over explained functions, in particular a second signal and a cryptographic date, such as a security code, and provide a first signal to be transmitted.

In 4 are transmission data to be sent as the first signal with Tx, received data received from a received signal with Rx, the second signal to be sent security code with sc_send and the received security code with sc_empf.

The first send data to be sent Tx which determine the first signal, and the security code to be sent as the second signal are sent to a transmitter 42 of the transceiver 41 transmitted. This generates on CAN lines CANH, CANL, a corresponding overlay signal according to the CAN communication protocol, which is modulated by the security code. The lines CANH, CANL, are as specified by the above-mentioned CAN standards with a resistor 45 about 60 Ohm connected. For recessive bits, the potential of the CANH, CANL lines is similar across the resistor 45 each other, so that there is substantially no potential difference between the lines. For dominant bits, the lines CANH, CANL from the transmitter 42 actively driven to a voltage difference.

Examples of the implementation of the transmitter 42 this will be explained later in more detail. To receive the lines are CANH, CANL with a receiver 43 connected, which is the first signal s1 recovers. In addition, the lines with a monitoring circuit 44 connected, which recovers the security code from the differential voltage between the voltages on the lines CANH, CANL. For this purpose, the differential voltage can be compared in particular with a threshold value, as will be explained in more detail later.

The 5 shows a part of a transmitter, in particular a driver as an example of a possible implementation of the transmitter 42 of the 5 , Generally, in the dominant phase, the CANH line is connected through a resistor to a positive voltage (eg, VDD, VCC, or other supply voltage Vs), and the CANL line is connected through a resistor of a smaller voltage (e.g., VSS, ground, or the like). connected. This connection can be done step by step over several resistors. The 5 shows a corresponding circuit for the line CANH. A corresponding circuit can also be provided for the line CANL.

The driver of 5 includes a parallel connection 50 a variety of resistances 55 . 53 . 51 , each with an associated switch 56 . 54 . 52 is connected in series. The switches can be implemented by means of transistors. A first connection of the resistors 55 . 53 51 is connected to a supply voltage Vs, and a respective second terminal is connected to a first terminal of the respective associated switch. Second connections of the switches 56 . 54 . 52 are over a diode 57 connected to the CANH line. The number of three resistors and three associated switches is to be understood as an example, and there may be provided any number of resistors, each with associated switches.

For a recessive bit, all switches are 56 . 54 . 52 opened, and over the resistance 45 of the 4 a voltage difference between CANH and CANl is compensated. In a dominant bit, the switches 56 . 54 . 52 successively closed, so that the voltage level on the line CANH ultimately by the supply voltage vs the value of the resistors 55 . 53 . 51 , the value of the resistance 45 and the value of corresponding resistors of a corresponding circuit connected to the CANL line.

At the transmission circuit 42 of the 4 determines the security code, how many switches in a dominant bit, eg a change of Tx in 4 from 1 to 0, be closed. For example, part of the switch 56 . 54 . 52 , eg all switches except the switch 52 , always closed in the dominant case. Another part of the switch, such as the switch 52 , is controlled in the dominant case depending on the security code. In this way, for example, by closing the switch 56 . 54 the level for a dominant bit of the CAN transmission is generated, and by selectively closing the switch 52 the security code is modulated. The resistance 51 is dimensioned in this example so that by opening and closing the switch 52 the voltage level on the CANH line does not leave a dominant level voltage range specified by the communication protocol, in this case the CAN protocol. This may ensure backward compatibility in some embodiments. In other embodiments, more than one switch may be used to modulate the security code to the signal.

For further illustration shows the 6 Examples of signals of the embodiment of 4 , It should be noted that these and other forms of signal presented in this application are illustrative only and the exact waveforms are used depending on the implementation, information to be transmitted and selected security code or other cryptographic data, communication protocols used, and external circumstances how to change temperature.

With 60 are the transmission data Tx in 4 referred to, ie that of the microcontroller 40 in the transceiver 41 received data to be sent, which determine the first signal. The data represents a sequence of logical ones and zeros.

With 61 is the security code to send, which determines the second signal. With 62 is a finally transmitted to the CAN bus overlay signal is shown, wherein the difference between the voltages on the lines CANH, CANL, also referred to as Vdiff, is shown. With a logical 1 of the transmission data 60 there is a recessive state of the bus, ie the CANH, CANL lines are not actively driven, and via the resistor 45 the potential of the cables CANH, CANL is equal to each other. The overlay signal 62 which reflects the difference voltage Vdiff is thus at or near 0. At a logic 0 (low level) of the signal 60 The lines CANH, CANL are each connected via resistors with voltages, as with reference to 5 explained, so that there is a difference voltage. During these dominant phases becomes the security code 61 modulated as a second signal. As with the overlay signal 62 can be seen, is the tension during the dominant phases V diff a bit higher, at a level 65 if the signal 61 is at logic 1 (high level), and slightly lower at a level 66 if the security code 61 is at logic 0 (low level). This can as with reference to the 5 explained by selectively closing the switch as the switch 52 be achieved.

With 63 are the ones out of the signal 62 recovered receive data Rx designated. This corresponds to the signal 60 with a delay that depends on a choice of sampling times. With 64 is the recovered security code. This also corresponds with a delay to the sent security code 61 , For this to be possible, signal changes are briefly explained above of the security code 61 chosen to be during dominant phases, for example as in 6 shown to coincide with the onset of dominant phases, as already explained with reference to the 3 explains a security code generator receives information about the data to be sent. An edge change of the signal 61 during a recessive phase, however, would not be immediately in the signal 62 but possibly only at the next dominant bit, resulting in a change in the signal 64 compared to the signal 61 would lead.

It should be noted that depending on the data to be sent, relatively many recessive bits can be sent successively. Depending on the physical communication protocol used, however, a certain number of dominant phases is ensured so that the security code or, in general, a second signal which includes a cryptographic date can be modulated.

As explained above, the choice of sampling times (and possibly also other effects such as signal propagation times) results in a delay between the transmission data Tx which are to be sent and the received received data Rx , This will now be with reference to the 7 and 8th explained in more detail. The 7 and 8th In this case, in particular, the retrieval of the security code and the selection of sampling instants for this purpose, ie the selection of times at which the voltage difference Vdiff is evaluated to obtain the security code.

The 7 shows as history 70 the transmission data Tx , as a superposition signal 71 the voltage Vdiff, as a course 72 the reception data Rx and as a course 73 the recovered security code. In this example, the voltage becomes V diff with respect to the security code at the falling edge of the signal Rx evaluated. In other words, once a falling edge of the signal Rx and thus a transition to a dominant phase is detected, the voltage difference Vdiff evaluated to recover a value for the security code. This can be done by comparing the voltage difference V diff with a threshold value between the two possible signal levels in the dominant case (compare the two in 6 shown level 65 . 66 , as threshold then a voltage between these levels is selected), as will be explained later. In this case, the recovered security code 73 to the reception data 72 synchronous with respect to edge changes. For this it is necessary that at this time the overlay signal 71 for scanning to recover the security code is "valid", ie has reached its steady state value. This is the case, for example, if the loop delay is less than the duration of one bit at the highest bit rate (for example, 5 megabits per second) 200 Nanoseconds), otherwise the bit status could have changed again.

An alternative is in 8th shown. The 8th shows transmission data Tx , a beat signal 81 as a voltage difference V diff on the bus, reception data Rx and a recovered security code 83 , Here, the sampling of the differential voltage takes place V diff a predetermined time dt after the falling edge of transmission data 80 , where the time dt is less than the time duration of one bit at the highest occurring bit rate. This ensures that the bit has not changed again at the sampling time. In this case, the recovered security code 83 with regard to edge change, not synchronous with the received data 82 ,

These sampling times are to be understood as examples only, and sampling times may generally be chosen in which the signal has taken the signal levels to be sampled to the extent that the different levels of the modulated security code are distinguishable.

In some implementations, such as some communications protocols, it may be desirable for signals to behave consistently with respect to the history of rising and falling edges. By overlaying the second signal, eg modulating the security code, it may happen in some implementations that this is not guaranteed. By way of illustration, in 9 transmit data Tx representing a bit string to be transmitted. A curve 91 shows a case for the transmitted beat signal when a logical high level of the security code is modulated. A dashed curve 92 shows the case of the beat signal in which a logic low level of the security code is modulated, in the example of the curves 91 . 92 Switch be closed successively, as with reference to the 5 explained. As can be seen, the rising edges in both cases are identical until the respective signal level is reached. However, the falling edges can be offset in time. If a certain sampling threshold for sampling the signal 91 respectively. 92 This can be done as if through curves 93 . 94 indicated to different reception data Rx lead, whose flanks are slightly offset from each other. This can be detrimental in some high bit rate applications.

In such a case, the switching to a higher level for a logical 1 of the security code may be staggered as in a lower part of the security code 9 is shown. Here again are transmission data Tx shown, and a course 96 shows a delayed version of the transmission data 95 , In this case, the generation of the beat signal takes place 97 without the modulated security code based on the delayed signal 96 , The end of the Aufmodulation of the security code, however, takes place with the rising edge of the signal 95 such that the security code is modulated at a distance from the edges of the signal, as by the signal 97 shown. In other words, a superimposition of the second signal according to the security code takes place here after no change in level of the first signal has occurred for a specific time and no level change of the first signal will take place for a specific time. A threshold voltage 98 , based on the signal change of the received signal is thus always crossed at the same time regardless of the modulated security code. The rising edge of the transmission data 95 can also be used to scan the security code (see the notes to the 7 and 8th regarding the scanning of the security code).

By modulating the security code as in the overlay signal 97 the loop delay is slightly increased since the delayed transmit data 96 are used as the basis for the generation of the signal, however, the behavior regarding rising and falling edges in some embodiments remains independent of the modulated security code.

As already explained above, the security code can be recovered by comparing the received signal in the case of a CAN bus, the differential voltage, with a threshold value (eg threshold voltage). This threshold is expediently between the two possible levels of the security code, for example between the levels 65 and 66 of the 6 , These two levels are relatively close together in some embodiments, for example, to ensure that both levels are within a tolerance range for a corresponding signal level of the signal according to the communication protocol, as explained. Additionally, in some implementations, the levels may vary depending on circumstances such as temperature, supply voltage, component manufacturing tolerances, and the like, which in some embodiments may make it difficult to properly select the threshold voltage. This will now be with reference to the 10 and 11 is explained using the example of a CAN bus, and then various calibration options are explained below, which make it possible to determine a suitable threshold voltage in implementations in which such variations occur.

wobei Rload der Widerstandswert des Widerstandswert 100 und Ud die Diodenspannung der Dioden 102, 103 in Durchlassrichtung ist. 10 schematically shows a driver of a transmitter for a CAN bus in the dominant state. The 10 shows the two already discussed lines CANH, CANL a CAN bus, which via a load resistor 100 according to the load resistance 45 of the 4 are connected. The load resistance 100 indicates a value of CAN bus 60 Ohm, where tolerances in a range of about 50 Ohm up 75 Ohm are allowed. The CANH line is via a resistor 101 with a resistance value RH and a diode 102 connected to a positive supply voltage VCC, and the line CANL is via a diode 103 and a resistance 104 connected to ground with a resistance value RL. The resistance 101 corresponds to, for example, those resistors 55 . 53 . 51 of the 5 , whose switches are closed in the dominant state, so is an equivalent circuit diagram for the parallel switches and resistors 5 in the dominant state, and the diode 102 corresponds to the diode 57 of the 5 , The diode 103 and the resistance 104 correspond to corresponding components between CANL and ground. The differential voltage Vdiff between CANH and CANL is calculated as: $$\text{V diff}=\left(\text{VCC}-2\text{Ud}\right)*\text{Rload}/\left(\text{RH}+\text{RL}+\text{Rload}\right).$$

where Rload is the resistance value of the resistance value 100 and Ud the diode voltage of the diodes 102 . 103 in the forward direction.

RH and RL vary between the two levels used in the displayed security code. To give a numerical example, RH = RL = 20 ohms for the one level of the security code and RH = RL = 15 ohms for the other level. With example values VCC = 5 volts, Rload = 60 ohms and Ud = 0.7 volts then results with the above formal Vdiff, low = 2.16 volts and Vdiff, high = 2.4 volts for the two possible levels with which the security code is modulated. The voltage difference between these two levels is therefore slightly above 200 mV in this example.

As apparent from the above equation, the voltage Vdiff depends on the supply voltage VCC and the load resistance 100 from. In addition, the quantities in the equation, for example the diode voltage Ud, also depend on the temperature. The dependence on the supply voltage and on Rload is in the 11 shown schematically. The 12 also illustrates a dependence on temperature.

In the 11 show curves 110 - 115 the voltage Vdiff according to the above equation across the load resistor Rload. Rload varies between 50 and 75 Ohm, which may correspond to a permitted variation range for CAN buses, for example. In 12 the voltage Vdiff is plotted against the temperature.

The curves 110 - 115 show the voltage Vdiff for various supply voltages and for a high level (corresponding to the above Vdiff, high) and a low level (corresponding to the above Vdiff, low) for the example values for RH, RL of 15 respectively. 20 Ohms as explained above. In particular, the curve shows 110 Vdiff, high for VCC = 5.25 volts, the curve 1111 Vdiff, high for VCC = 5, the curve 112 Vdiff, low for VCC = 5.25 volts, the curve 113 Vdiff, high for VCC = 4.75 volts, the curve 114 Vdiff, low for VCC = 5 volts and the curve 115 Vdiff, low for VCC = 4.75 volts. In 12 shows the curve 120 Vdiff, high for VCC = 5 volts and Rload = 75 ohms, the curve 121 Vdiff, high for VCC = 5 volts and Rload = 60 ohms, the curve 122 Vdiff, low for VCC = 5 volts and Rload = 75 ohms, the curve 123 Vdiff, high for VCC = 5 volts and Rload = 50 ohms, the curve 124 Vdiff, low for VCC = 5 volts and Rload = 60 ohms and the curve 125 Vdiff, low for VCC = 5 volts and Rload = 50 ohms.

The external load resistance 100 is not known a priori and can vary as explained. The supply voltage may also vary, for example between 4.75 volts and 5.25 volts as in 11 specified. Like from the 11 and 12 As can be seen, in such implementations where such variations may occur, not a single threshold (ie, a threshold voltage in this case) can be established, with which a distinction can be made between Vdiff, high, and Vdiff, low for all occurring load resistances, voltages, and temperatures. For example, at a threshold of 2.30 volts as in 4 seen at a resistor Rload over 60 Ohms and a supply voltage of 5.75 volts both Vdiff, high (curve 110 ) as well as Vdiff, low (curve 112 ) above this threshold, so that a distinction would not be possible. The same applies to other possible thresholds.

Therefore, in some embodiments in which such variations may occur, a calibration is performed for which various possibilities are discussed below. On the other hand, in embodiments in which such variations do not occur or to a small extent, a single threshold can be selected and the calibration can be omitted.

The 13 shows a circuit used for such a calibration according to some embodiments. In the embodiment of the 13 will be a replica of the in 10 shown driver to obtain a reference voltage Vref. A replica of a circuit part is a circuit which generally contains components corresponding to the circuit part, which components may be scaled with respect to the circuit part (for example, a surface reduced by a scaling factor, a resistor increased by a scaling factor, and the like). The replica in the embodiment of 13 includes a resistor 131 according to the resistance 101 , a diode 132 according to the diode 102 , a diode 133 according to the diode 103 and a resistance 134 according to the resistance 104 , As in 13 indicated are the resistances 133 . 134 concerning the resistances 101 . 104 scaled by a factor n, in particular by a factor n higher, which limits a current flow through the replica. The diodes 132 . 133 wise compared with the diodes 102 . 103 an area reduced by the scaling factor n, which reduces a footprint for the replica and reduces the power consumption. For typical values, n> 30 may be used to keep a current draw of the replica below 1 mA. Significantly higher values of n would further reduce power consumption but, depending on the implementation, could match the replica to the in 10 deteriorate. For the resistors 131 . 134 In this case, an intermediate value between the values n * RH and n * RL can be used for the high and low levels of the security code. About the resistance 130 then drops a voltage that is used as a reference voltage in some Embodiments is used. Variations in the supply voltage VCC and the temperature have the same effect on the voltage Vdiff and on the reference voltage Vref obtained by the simulation with such a circuit, so that the influence of fluctuating reference voltages and temperatures can be compensated thereby.

However, this does not yet cause variations in the resistance Rload of the resistor 100 balanced. Because the resistance 100 In many implementations, an external resistor is often not known a priori.

In embodiments in which such variations of a load resistance occur, which influence the levels of the modulated second signal, for example on the basis of the discussed security code (in this case the voltage Vdiff), additionally the resistor 130 that the resistance 100 emulates, be adjustable and calibrated to a value RL_RF = n * Rload, where n is again the scaling. Ways in which such a calibration can be made will be explained later. The result of such a calibration is in 14 shown. In 14 shows a curve 140 the voltage Vdiff, high for a supply voltage of 5 volts and a load resistor Rload of 55 Ohm above the temperature, and a curve 142 shows the voltage Vdiff, low for the supply voltage and the load resistance of 55 Ohm. A curve 141 shows a reference voltage Vref over the temperature, which with a resistance 130 was obtained, its resistance value RL RF on 55 Ohm * n was set. The resistors 131 . 134 in each case n * 17 ohms, ie a value between the above-mentioned example values of 20 Ohm and 15 Ohm for low and high levels of security code.

Similar results are obtained for other values of Rload. Thus, by calibrating the resistance value RL RF in some embodiments, a reference voltage may be generated which may be used as a threshold voltage to distinguish the two levels.

15 FIG. 12 shows a calibration circuit according to some embodiments, with which such calibration of a replicated resistor for determining a suitable threshold voltage (reference voltage) as a threshold value can take place. The 15 comprises the part of the driver of the transmitter with the reference numerals 100 - 104 , which already with reference to the 10 has been described. As already explained, the resistors 101 . 104 each two different values (eg 15 Ohm and 20 Ohms), and these are in 15 With R1 and R2 designated. R1 corresponds to the resistance value for the low level ( 20 Ohm in the above example) and R2 for the high level ( 15 Ohm in the above example), ie R2 < R1 ,

The circuit of 15 includes two replicas of this driver. A first replica includes a resistor 153 , according to the resistance 101 , a diode 154 according to the diode 102 , an adjustable resistor 155 according to the resistance 100 , a diode 156 according to the diode 103 and a resistance 157 corresponding to the diode 104 , The diodes 154 . 156 are with respect to the diodes 102 . 103 scaled by a factor of n (for example, by n small area) and the resistance values of the resistors 153 . 157 are n * R2, ie are with respect to the resistance value of the resistors 101 . 104 scaled to the high level of the security code.

A second replica includes a resistor 158 according to the resistance 101 , a diode 159 according to the diode 102 , an adjustable resistor 1510 according to the load resistance 100 , a diode 1511 according to the diode 103 and a resistance 1512 according to the resistance 104 , The diodes 159 . 1511 are again with respect to the diodes 102 . 103 For example, scaled by the factor n have an n-times smaller area. The resistors 158 . 1512 are with respect to the resistance value R1 scaled by n, ie, in terms of the resistance value for the low level.

A calibration circuit 152 measures the differential voltage Vdiff at the resistor 100 , For calibration, for example, at the beginning of a CAN telegram or during a calibration phase, the transmission circuit initially the resistance R1 for the resistances 101 . 104 adjust and then the resistance R2 or the other way around.

In addition, the calibration circuit measures 152 the voltage drop across the resistor 155 , in 15 referred to as Vref2, and the voltage drop across the resistor 1510 , in 15 denoted as Vref1, where the resistors 155 . 1510 are set to the same resistance value.

During the calibration phase, the calibration circuit stops 152 during the phase in which the resistors 101 . 104 on R1 are set, the resistance 1510 and the resistance 155 such that Vref1 = Vdiff holds. Because the resistors 158 and 1512 equal to nx R1 are, after this setting, that the value of the resistors 1510 . 155 equals nx Rload is. In this way, so are the resistors 155 and 1510 the resistance Rload of the resistor adjusted so that the reference voltages Vref1 . Vref2 the two possible values of the signal V diff for high and low levels of security code. From the values Vref1 . Vref2 Then, a threshold value Vref for retrieving the security code can be determined by setting Vref to a value between Vref1 and Vref2 is set.

In the embodiment of 16 is in addition to the two replicas of 15 a third replica comprising a resistor 160 according to the resistance 101 , a diode 161 according to the diode 102 , an adjustable resistor 162 according to the load resistance 100 , a diode 163 according to the diode 103 and a resistance 164 according to the resistance 104 provided. The resistance 160 and the resistance 164 are with respect to a resistance with a resistance value between R1 and R2 is scaled by a factor of n. As in the numerical example, when R1 = 20 ohms and R2 = 15 ohms, a resistance value of the resistors 160 and 164 for example n * 17 ohms or n times another value between R1 and R2 be. The diodes 161 and 163 are compared with the diodes 102 and 103 also scaled by the factor n, for example, have an area n times smaller.

In this case, the resistors 155 . 1510 and 162 set simultaneously as explained above, for example so that Vref1 = Vdiff in a phase in which the resistors 101 . 104 on R1 are, applies. By choosing the resistors 160 . 164 then falls to the resistance 162 a reference voltage Vref, which is between Vdiff, high and Vdiff, low and thus can be used as a threshold for obtaining the security code from the received signal.

Another possibility for determining a voltage Vref, which can serve as a threshold, is in 17 shown. Compared with the 15 are in the embodiment of 17 additional resistances 170 . 171 . 172 . 173 provided as in 17 shown with the resistors 1510 . 155 are interconnected. In some embodiments, all resistors 170 - 173 an equal resistance value R on. Between a first node, which is between the resistors 170 . 171 lies and a second node, which is between the resistors 172 . 173 is then a voltage Vref which can serve as a threshold can be tapped. Assign all resistances 170-173 has an equal resistance, Vref = (Vref1 + Vref2) / 2. By changing the resistance values 170-173 this can be changed, for example, Vref closer Vref1 or closer to Vref2 be pushed. In embodiments, the resistors 170-173 higher resistance values than the resistors 153 . 157 . 158 and 1512 , In some embodiments, this may reduce an error in determining the reference voltage Vref.

In some embodiments, interference may occur on communication lines such as bus lines, in the case of a CAN bus lines CANH, CANL. Examples of such disturbances include high-frequency interference (RF interference), which may be caused for example by electromagnetic interference (EMI).

If such disturbances occur during the calibration operations described, they can corrupt the result of the calibration. To avoid this, measures can be taken in some embodiments. For example, in the embodiment of the 16 an additional voltage monitoring 1513 optionally provided, which monitors the voltage on the bus lines CANH, CANL and verifies that they are within a permitted range. For example, for a CAN bus, the allowable range may be between 1 and 4 volts. Other communication media may have other permitted ranges.

A calibration, ie a setting of the resistors 1510 . 155 to match the measured voltage V diff , is only valid if the voltages on the buses on the CANH, CANL lines are in the permitted range. If they are outside the permitted range, the calibration is invalid and must be repeated.

In another embodiment, which in the 18 is shown, the resistors 1510 and 155 be set independently of two calibration circuits. Accordingly, compared with the 15 in the 18 the calibration circuit 152 by a first calibration circuit 180 for adjusting the resistance 155 and a second calibration circuit 181 for setting the resistance 1510 replaced. The calibrations can be offset in time. A comparison circuit 182 compares the calibration results. With a correct calibration, those should be for the resistors 155 and 1510 set resistance values are at least approximately the same. If they differ by more than a predetermined threshold, in some embodiments, the setting of the resistors 155 . 1510 discarded and the calibration is repeated. These measures to ensure a successful calibration, which may also be referred to as validation of the calibration, with reference to the 16 and 18 have been explained are also applicable to other embodiments, for example, the embodiment of 17 ,

In some embodiments, the calibration discussed above is performed only in some phases of a communication. For example, in a CAN bus, there are phases of communication such as an arbitration phase to begin communication, which many transmitters may be in a dominant state. Calibration at such a time could in some cases falsify the result of the calibration. Therefore, in some embodiments, calibration is performed only outside such an arbitration phase.

In some embodiments, the calibration may be activated by a separate signal from a microcontroller or other controller. An example of this is in 19 shown. The embodiment of 19 is a modification of the embodiment of 4 , and like components bear the same reference numerals and will not be explained again.

In addition to the in 4 Components shown may be the microcontroller 40 through an arrow 190 displayed with a calibration_en signal activate and deactivate the calibration. So can the microcontroller 40 eg disable the calibration during the above-mentioned arbitration phase.

Various possibilities have been explained above, such as variable external resistance such as load resistance 100 a calibration can be performed to obtain a reference voltage Vref as a threshold.

In other embodiments, a difference between voltage levels for the security code may be chosen such that a same reference voltage can be used in a total allowed range of load resistances that need not be calibrated. This can be viewed as a calibration of the driver on the transmitter side. A corresponding embodiment is in 20 shown.

The 20 again shows the described part of the transmission circuit with the reference numerals 100-104 , In addition, a replica is provided in which a resistor 201 the resistance 101 , a diode 202 the diode 102 , a resistance 200 the resistance 100 , a diode 203 the diode 103 and a resistance 204 the resistance 104 equivalent. The diodes 202 and 203 are with respect to the diodes 102 and 103 scaled by a scaling factor n, for example, have an area n times smaller. The resistance 200 is with respect to a mean resistance value of the load resistance 100 scaled by the factor n. In the case of a CAN bus, the resistance 200 For example, have a resistance of n * 60 ohms. The resistors 201 and 204 are relative to a mean value of the resistors 101 . 104 scaled by the scaling factor n. As already explained, the resistors 101 . 104 to generate two levels to modulate the security code take two different values, and the resistors 201 . 204 are scaled with respect to an intermediate value.

To give a numerical example, in the embodiment of the 20 the resistances 101 . 104 either on 10 Ohm for a high level or up 20 Ohms for a low level, which corresponds to a difference of approximately 500 mV between the levels for the numerical examples already used above. The resistors 201 . 204 may then have a value of n * 15 ohms, or n * another value of between 10 Ohm and 20 Ohms, for example n * 14 ohms. The voltage drop across the resistor 200 is then used as a reference voltage to recover the security code. In such embodiments, there is no calibration of the resistor 200 necessary. In some embodiments, however, the area requirement is because of the greater difference between the two values of the resistors 101 . 104 higher. In addition, the difference between the levels can not be arbitrarily set high depending on the communication protocol used when the above-explained backward compatibility in which the levels are kept in specified ranges should be obtained.

The 20 shows simulation results for a circuit as described with reference to FIG 20 explained. The 20 shows in particular voltages Vdiff, high and Vdiff, low above the temperature in degrees Celsius for different load resistors Rload and a constant supply voltage VCC = 5 volts. A curve 210 shows Vdiff, high for Rload = 75 ohm, a curve 211 shows Vdiff, high for Rload = 50 ohm, a curve 213 shows Vdiff, low for Rload = 75 ohms and a curve 214 shows Vdiff, low for Rload = 50 ohms. A curve 212 shows the reference voltage at the resistor 200 of the 20 for a resistance value of n * 60 ohms. As can be seen, for the whole range of Rload from 50 Ohm up 75 Ohm by means of the reference voltage 212 according to the curve 212 between Vdiff, high and Vdiff, low can be distinguished.

Thus, an embodiment without the above-described calibration is possible, for example, as with reference to 20 explains the possible resistance values for the resistors 101 . 104 be chosen so that the distance between Vdiff, high and Vdiff, low is sufficiently large.

As explained above, in general, the difference between Vdiff, low and Vdiff, high is relatively small, for example, about 200 mV or about 500 mV in the above examples. This signal can be influenced by electromagnetic interference. In order to improve electromagnetic compatibility (EMC), in some embodiments, measures may be taken to at least reduce the effects of electromagnetic interference on the signal. This will now be with reference to the 22 and 23 explained. The 22 and 23 each show an equivalent circuit diagram for an output stage of a CAN bus with lines CANH, CANL under the influence of electromagnetic interference.

As well in 22 as well as in 23 is with the reference numeral 220 the output resistance (according to the resistance 100 in previous figures), about 60 Ohms, designated. Each line CANH, CANL is with a resistor 221 . 222 which is about 120 ohms in the illustrated example. In addition, there is a capacity 223 respectively. 224 provided with a capacity value of 4.7 nanofarrad. The resistors 221 . 222 and the capacities 223 . 224 represent a coupling network via which faults are coupled into the bus lines CANH, CANL.

In case of 22 and 23 becomes an electromagnetic interference by a source of interference 226 , with AC voltage source 228 and resistance 227 represented via the coupling network ( 221 - 224 ) is coupled into the CANH, CANL lines. In the event of such a disturbance, Vdiff is provided by a short-circuit current which corresponds to a maximum possible current flow, since in this case a current limitation occurs on the CANH-coupled side or the CANL-coupled side of a driver. This driver is in 22 through a power source 229 and in the case of 23 through a power source 230 represents. At high voltages (eg due to disturbances) drivers with current limitation behave like a current source. The power sources 229 respectively. 230 Thus, they also represent the short circuit current in the case of 22 to a positive voltage, like VCC, and in the case of 23 flows to ground. Such a current limit can be achieved, for example, by a maximum current flow of a switch implemented by one or more transistors, such as the switch 56 . 54 . 52 of the 5 occur.

In both cases, the short-circuit current flows in the same way over both lines CANH, CANL, as indicated by arrows 2210 . 2211 in the 22 and 23 indicated.

The resulting differential voltage Vdiff in this case is Vdiff = Rload * ishort / 2, where ishort is the short-circuit current.

By a suitable choice of the current limitation of this short-circuit current can be achieved that even with electromagnetic interference, the voltage Vdiff remains substantially unchanged. Specifically, the short circuit current can be set to be twice the current flowing in the normal state (i.e., current flowing in the dominant state). Such current limiting can be achieved in any conventional manner, for example by means of a current mirror.

As explained above (in the case without electromagnetic interference) Vdiff = (VCC-2Ud) * Rload / (RH + RL + Rload).

With the above-mentioned condition that the short-circuit current is twice the current flowing under normal conditions, one obtains $$\text{ishort}=2*\left(\text{VCC}-2\text{Ud}\right)/\left(\text{RH}+\text{RL}+\text{Rload}\right),$$

und somit gleich dem obigen Wert von Vdiff ohne den Einfluss elektromagnetischer Störungen. Somit kann durch die oben beschriebene Begrenzung des Kurzschlussstromes der Einfluss von elektromagnetischen Störungen auf die Differenzspannungen Vdiff bei manchen Ausführungsbeispielen zumindest verringert, wenn nicht beseitigt werden. Dabei kann der Strombegrenzungswert ishort entsprechend der Änderung von RH und RL für die verschiedenen Pegel des zweiten Signals jeweils geändert werden. Es kann bei anderen Ausführungsbeispielen auch ein Mittelwert für ishort für die verschiedenen Werte von RH, RL gebildet werden. Thus, the voltage Vdiff, en under the influence of an electromagnetic interference $$\text{V diff}\text{, en}=\text{* Ishort Rload}/2=\text{Rload *}\left(\text{VCC}-2\text{Ud}\right)\left(\text{RH}+\text{RL}+\text{Rload}\right)$$

and thus equal to the above value of Vdiff without the influence of electromagnetic interference. Thus, the limitation of the short circuit current described above can at least reduce, if not eliminate, the influence of electromagnetic interference on the differential voltages Vdiff in some embodiments. At this time, the current limit value can be changed according to the change of RH and RL for the different levels of the second signal, respectively. In other embodiments, an average value for ishort may also be formed for the various values of RH, RL.

In the above, many embodiments have been discussed in which a first signal having a cryptographic datum is physically modulated onto a signal. In addition to this security code, coding may also be done in a logical protocol layer, i. the information to be sent is encrypted on the basis of a (secret) key, which may be identical to or different from a key used to generate the cryptographic date. As explained below, this can provide redundancy with concurrent diversity (different security methods, encryption on the Logical Log Layer, and superimposition of the second signal with the cryptographic date). Such encryption by means of keys can be implemented in various forms in a conventional manner.

The 24 shows a corresponding communication circuit arrangement according to an embodiment with a first communication circuit 241 serving as a transmitter and a second communication circuit 242 , which serves as a receiver. The embodiment of 24 is based on the embodiment of the 1 , and corresponding elements bear the same reference numerals. In particular, the modulation of a second signal having a cryptographic datum takes place on a physical level, as with reference to FIGS 1 described here, all here with reference to the 1-23 described variants and implementation options are applicable.

Therefore, only the differences between the communication circuitry will be described below 240 and the communication circuitry 10 of the 1 explained.

In the communication circuit 241 becomes an information to be transmitted of a signal generation and coding circuit 245 fed. The signal generation and encoding circuit encrypts the information based on a key on a logical protocol layer operating in accordance with a logic protocol. On the basis of the thus encrypted information, a transmission signal is then generated, as for the generation of a signal by the signal generation circuit 15 of the 1 described, with the difference that now the encrypted information is used as a basis. This signal is then in the modulation circuit 16 as described the second signal with the cryptographic date 14 modulated and the signal is transmitted via the communication medium 13 transfer.

In the communication circuit 242 is firstly by the already described code receiving circuit 18 in the modulation circuit 16 recovered modulated security code. On the other hand, in a signal receiving and decoding circuit 247 on the one hand retrieved the encrypted information from the received signal and then decrypted the encrypted information in a logic protocol layer. For this purpose, the signal receiving and decoding circuit of the key used for encryption or a decryption key corresponding thereto are provided.

This encryption and decryption can be done in any conventional manner.

Corresponds to that by the code receiving circuit 18 obtained cryptographic date not the expected security code, can be taken as described measures. These measures can correspond to the measures already described. In addition, when the decryption in the signal receiving and decoding circuit 247 is correct, even a warning is issued, or no action can be taken if authentication by the successful decryption alone on the logical protocol layer is acceptable. Thus, redundancy is provided in this way with two different security mechanisms (encryption on the logical protocol layer and modulation of a second signal with cryptographic date on the physical layer) with simultaneous diversity (two different measures).

In the 25 a corresponding method according to some embodiments is shown. The procedure of 25 can in the communication circuitry 240 of the 24 and is described with reference to it to avoid repetition, but may also be independent of the communication circuitry 240 be used.

As already for the procedure of 2 have executed the steps of the 25 not necessarily be performed in the order shown, and in particular, various operations can also be performed simultaneously.

at 250 an information is encrypted, for example on the basis of a key, as for the signal generation and coding circuit 215 described. at 251 We convert the encrypted information into a first signal, in particular based on a physical communication protocol, such as the discussed CAN protocol or another communication protocol.

at 252 the first signal is superimposed by a second signal with a cryptographic date. The cryptographic date can be one of a same key that is used to encrypt 250 was used, derived date, or another cryptographic date.

The overlay signal thus generated is sent to a receiver, and at 253 the encrypted information is retrieved from the broadcasting original. at 254 the encrypted information is then decrypted. at 255 In addition, the cryptographic date is retrieved from the beat signal. Depending on whether the decryption at 254 and / or the cryptographic date at 255 The information may be considered to be authenticated, ie sent by an authorized recipient, as previously described.

The functionalities described can be implemented in various ways. In particular, some of the functionalities, for example the provision of the security code adapted to the data to be sent, can be provided in a microcontroller, as for the microcontroller 40 of the 19 described then the corresponding information to a CAN transceiver as the CAN transceiver 41 of the 19 gives and receives from this. Details of such implementation options will now be described with reference to FIGS 26-36 explained.

The 26 shows a block diagram of a microcontroller 260 according to an embodiment.

The microcontroller 260 may for example be a control unit (MCU, microcontrol unit) of a vehicle, such as a motor control, transmission control or other control unit. In a vehicle, a plurality of such control units are often installed.

In addition to the functions of the microcontroller shown explicitly below 260 and also described below microcontroller can further conventional functions in the microcontroller 260 be implemented.

The microcontroller 260 has a Hardware Security Module (MSM) 261 on, in which keys (keys) are stored, which can serve as a cryptographic date in the above-described methods and apparatus, or from which such a cryptographic date, such as the security code described, can be generated. The hardware security module 261 is protected from access and interference, such as particle interference, electromagnetic radiation, and the like, by additional measures known per se. It is also better against attacks and accesses than the rest of the microcontroller 260 protected. Software of the hardware security module 261 may run in separate memory areas, for example, and algorithms may be page channel resistant.

The microcontroller 260 also contains one or more circuitry called SPAD (safe physical anomaly detection) 263A-263D implementing the described techniques. In particular, each SPAD 263A-263D (collectively referred to as SPAD 263 designated) provide a aufzumodulierenden security code for a transceiver such as a CAN transceiver, as with reference to the 4 has been explained. The number of four SPADs 263 in 26 this is just an example and you can choose any number of SPADs you need.

The SPADs 263 receive control and data information via an internal bus 262 of the microcontroller. For example, the data and information to be transmitted with respect to a position of transmit and receive bits as described with reference to FIGS 3 be provided explained. In addition, the SPADs get 263 Keys from the hardware security module 261 , This can either be done via the control and data bus 262 or also via a separate connection as indicated by dashed lines. These keys may then be used as a cryptographic date in the techniques described above, or a cryptographic date, such as the security code discussed, may be generated from the keys according to a predetermined algorithm.

The SPADs can each be assigned to communication interfaces. This is schematically in the 27 shown. Here includes a microcontroller 270 SPAD 273A -274D and the hardware security module 261 of the 27 , The SPADs 273A-unit 273D are summarized below as SPADs 273 denotes the number of four SPADs 273 again, only as a non-limiting example. Each of the SPADs 273 is a respective communication interface 274A . 274B . 274C respectively. 274C (in summary as communication interfaces 274 assigned) assigned. The communication interfaces 274 For example, they may be coupled to CAN transceivers as described or coupled to transceivers for other types of buses, but are not limited thereto.

In the embodiment of the 27 is every SPAD 273 a respective communication interface 274 assigned. In other embodiments, an SPAD may be associated with multiple communication interfaces. A corresponding embodiment is as a microcontroller 280 in 28 shown. The 28 shows a microcontroller 280 with the hardware security module already described 261 and the internal bus 262 , With the bus are communication interfaces 262A - 262C , summarizing as communication interfaces 282 designated arranged. The communication interfaces 282 can be seen as submodules of a single communication interface, which is a single SPAD 281 assigned. The SPAD 281 performs the described techniques for all communication interfaces 282A-282C out. The number of three communication interfaces shown 282 in 28 is just another example. Thus, the show 27 and 28 in that SPADs can be assigned communication interfaces in various ways. Also mixed forms between 27 and 28 are possible in which some SPAD are assigned to multiple communication interfaces and other SPADs are assigned to only one communication interface.

The 29 shows a block diagram of a SPAD 290 as he is known as SPAD in the 26 . 27 and 28 is usable.

The SPAD 290 includes a module 291 for key exchange with a hardware security module such as the described hardware security module 261 of the 26-28 , Based on a received key represents a module 293 provide a security code for modulating on a physical level signal as described. A module 294 receives a security code obtained from a received signal and carries in a module 292 authentication based on a received key indicating an expected security code as described. The authentication at 292 can be redundant. For example, an encoding of the transmitted information on a logic protocol layer can also be described as described, or the verification of the received security code can be carried out redundantly in a plurality of circuit parts. Depending on the success of the authentication, a signal indicating successful or failed authentication may then be issued, and if authentication fails, action may be taken as described.

As already explained above, a multiplicity of microcontrollers can be arranged in a device such as a vehicle. In some embodiments, information about successful or failed authentications can be collected from multiple microcontrollers, and action can then be taken based on that collection. This is in 30 shown schematically.

30 shows a variety of microcontrollers 300A . 300B . 300C Again, the number of three microcontrollers is to be understood as an example only, each of which includes a SPAD as described above for authentication and which are connected to a communication medium, such as a common bus. Each of the microcontrollers 300 performs authentication measurements on the bus (eg the described checks of a received cryptographic date) and reports information about the authentications (eg about failed authentications) to an aggregation unit 301 , The aggregation unit 301 evaluates the received information and causes further action. For example, if only one MCU can not authenticate a signal, some may Embodiments still no action to be taken, as this could for example also be based on a transmission error. If several microcontrollers receive messages that can not be authenticated, this can be considered, for example, as an intrusion attempt, and a measure can be taken as described. This also provides redundancy in the detection of illicitly coupled communication devices and thus can help meet security requirements.

A SPAD can receive signals from a transmission medium such as the transmission medium 13 of the 1 received in different ways. This will now be with reference to the 31 - 35 explained in more detail.

In the 31 are a SPAD 312 and an associated communication interface 311 in a microcontroller 310 arranged. Further elements as already described above may be present in the microcontroller, in particular a hardware security module and further communication interfaces and / or further SPADs. The communication interface 311 is with a transceiver 313 , which implements a physical layer of communication, connected, for example with a CAN transceiver as described. The transceiver 313 then communicates via a physical medium 315 , for example a CAN bus.

In the arrangement of 31 receives the SPAD 312 directly signals from the physical medium 315 via a protective circuit connected in between 314 For example, to recover the security code. The protection circuit 314 may include conventional protective elements such as electrostatic discharge (ESD) protection elements, overcurrent protection devices or overvoltage protection elements. The embodiment of 31 can use a conventional transceiver, but requires an additional protection circuit 314 ,

Another arrangement is in the 32 shown. Here again is a communication interface 321 and a SPAD 322 in a microcontroller 322 arranged. The communication interface 321 communicates with a transceiver 322 who in the case of 32 a little more detailed with a driver circuit 327 , a transmitter 326 , a receiver 325 and a protection circuit 324 is shown. In contrast to 31 SPAD uses the protection circuit here 324 of the transceiver 323 with, ie it receives from the protection circuit 324 filtered signals. The embodiment of 32 requires no additional protection circuit, but requires a suitably designed transceiver 323 from the protection circuit 324 sends the signal directly to the SPAD.

Another arrangement is in 33 shown. A microcontroller 330 contains a communication interface 331 and a SPAD 332 , The communication interface 331 is with a transceiver 334 connected, which like the transceiver of 32 a driver circuit 335 , a transmitter 336 , a receiver 337 and a protection circuit 338 contains. From the protection circuit 338 become signals of a measuring circuit 339 fed, which can recover, for example, the security code and the recovered security code via an interface 3310 to a corresponding interface 333 in the microcontroller 330 and from there to the SPAD 332 sends. Here is the recovery so - as well as in 4 shown - in the transceiver.

The embodiment of 33 requires a more complex transceiver 334 with the measuring circuit 339 , but on the other hand allows for more precise measurements.

In another embodiment, which is in 34 shown can be a measurement unit 349 according to the measuring unit 339 outside a transceiver 344 and outside a microcontroller 340 together with an interface 3410 be arranged, for example, in a separate block to directly on the medium 315 Perform measurements. The transceiver 344 contains a driver circuit 345 , a transmitter 346 , a receiver 347 and a protection circuit 348 , The microcontroller 340 contains a SPAD 342 , a communication interface 341 and an interface 343 , Here is an additional unit with the measuring unit 349 and the interface 3410 necessary, which possibly requires its own protection circuit. Otherwise, the operation is as in the embodiment of 33 ,

The 31-34 show that different divisions and implementations of the discussed functionalities are possible.

The functionalities of a SPAD can also be provided centrally in a switched network. The 35 shows such a network with a switch 352 which different Communication participant, in the example of 35 a first microcontroller 350 with a first transceiver 351 , a second microcontroller 3511 with a second transceiver 359 and a third microcontroller 3512 with a third transceiver 3510 optionally with each other. For this the switch points 352 transceiver 353 . 358 and 357 on, as shown with the transceivers 351 . 359 and 3510 to communicate. Furthermore, the switch has 352 via a processor unit 355 with a SPAD 356 with which of the microcontrollers 350 . 3511 . 3512 over the respective transceivers 351 . 359 . 3510 transmitted signals must be authenticated. In this case, not every microcontroller must have a SPAD, but authentication (checking the modulated cryptographic date and / or additional encryption on the logic protocol layer) can be checked centrally in the switch.

Even with a transceiver that services multiple channels, for example, multiple channels on one or more CAN buses, the provision and verification of a security code can be done for all channels in a single unit. An example is in 36 shown schematically.

In the embodiment of the 36 set send / receive node 361A . 361B . 361C a transmission signal TX for a respective assigned CAN bus 362A . 362B or 362C ready and receive a corresponding received signal RX. In this regard, the function corresponds to the CAN node 361A . 361B . 361C the elements 33 . 34 . 39 and 38 of the 3 ,

The provision of a security code is provided in a time-division multiplexed manner based on a time control by a time multiplexer, as indicated by an arrow 356 indicated the security code for a multichannel transceiver 364 provides and controls which CAN bus 362A . 362B . 362C each served. The knots 361A . 361B . 361D provide as also with reference to 3 described data and bit positions to the time multiplexer 360 so that it can create a suitable security code for modulating on dominant bits of the respective CAN bus. The transceiver 364 then modulates the security code basically as already described to the signals on the respective CAN bus, with the difference that it is done in a time-division multiplexing alternately for the CAN buses. In this way, in some embodiments, an implementation for a plurality of CAN buses with comparatively few components can be realized.

Thus, as can be seen from the figures described above, there are a variety of different ways to implement the techniques described. Thus, the application of the described techniques is not limited to a specific type of implementation.

The following examples define at least some of the embodiments.

• einen Transmitter, der dazu ausgebildet ist,
  • - an einem Ausgang ein erstes Signal gemäß eines physikalischen Kommunikationsprotokolls bereitzustellen, und
  • - an dem Ausgang ein zweites Signal bereitzustellen, das mindestens ein kryptographisches Datum umfasst, wobei das erste und das zweite Signal als ein Überlagerungssignal an dem Ausgang einander überlagert sind, und wobei das Überlagerungssignal das physikalische Kommunikationsprotokoll erfüllt.

Example 1. Transceiver comprising:

• a transmitter designed to
  • to provide at a output a first signal according to a physical communication protocol, and
  • providing at the output a second signal comprising at least one cryptographic datum, the first and the second signal being superimposed as an overlay signal at the output, and the overlay signal satisfying the physical communication protocol.

Example 2. Transceiver according to Example 1,
wherein the second signal is a pulse-shaped signal or an AC-shaped signal.

Example 3. A transceiver according to any one of Examples 1 to 2, wherein the second signal is superimposed on the first signal only at one of at least two levels of the first signal according to the physical communication protocol.

Example 4. A transceiver according to one of the examples 1 to 3, wherein the second signal is superimposed if no level change of the first signal took place for a certain time or no level change of the first signal will take place for a certain time.

Example 5. A transceiver according to any one of Examples 1 to 4, wherein a logic protocol layer overlying the physical communication protocol provides a logic signal and the logic signal is used to generate the first signal.

Example 6. The transceiver of Example 5, wherein the logic protocol layer is configured to encrypt data to be sent to provide the logic signal.

Example 7. A transceiver according to any one of the preceding examples, wherein the cryptographic date is a security code of the transceiver.

Example 8. A transceiver according to any one of the preceding examples, wherein the transceiver is provided with a key for generating the cryptographic date.

Example 9. A transceiver according to Example 8, wherein the key is provided by a trans-parent key instance.

Example 10. The transceiver of any of the preceding examples, wherein the transmitter comprises a driver circuit configured to provide the heterodyne signal, and wherein the transmitter is configured to calibrate the driver circuit.

Example 11. The transceiver of Example 10, wherein the driver circuit comprises a first series connection of a first switch and a first resistor coupled between a supply voltage and the output, the first switch being responsive to the first signal, and the driver circuit a second series circuit of a second switch and a second resistor which is coupled between the supply voltage and the output, wherein the second switch in response to the cryptographic date is controlled.

• einen Receiver, der dazu ausgebildet ist,
  • - ein Empfangssignal, welches eine Überlagerung eines ersten Signals gemäß einem physikalischen Kommunikationsprotokoll mit einem zweiten Signal, das ein kryptographisches Datum umfasst, ist, zu empfangen,
  • - das Empfangssignal gemäß dem physikalischen Kommunikationsprotokoll zu verarbeiten, um in dem ersten Signal übertragene Informationen zu gewinnen, und
  • - aus dem Empfangssignal das kryptographische Datum zu gewinnen.

Example 12. Transceiver comprising:

• a receiver that is designed to
  • a receive signal which is a superposition of a first signal according to a physical communication protocol with a second signal comprising a cryptographic datum,
  • to process the received signal according to the physical communication protocol to obtain information transmitted in the first signal, and
  • - From the received signal to win the cryptographic date.

Example 13. The transceiver of Example 12, wherein the second signal is a pulsed signal or an AC signal.

Example 14. Transceiver according to one of Examples 12 or 13,
wherein the receiver is configured to obtain the cryptographic date from the superposition of the second signal over the first signal only at one of at least two levels of the first signal according to the physical communication protocol.

Example 15. A transceiver according to any one of Examples 1 to 3, wherein the receiver is adapted to obtain the cryptographic date from the superposition of the second signal over the first signal if no level change of the first signal has occurred for a certain time or for a certain time no level change of the first signal will occur.

Example 16. A transceiver according to any one of Examples 12 to 15, wherein the information obtained from the first signal is provided to a logic protocol layer that is the parent of the physical communication protocol as a logic signal.

Example 17. The transceiver of Example 16, wherein the logic protocol layer is configured to extract data sent from the logic signal by decryption.

Example 18. The transceiver of any preceding example, wherein the cryptographic datum is a security code of another transceiver from which the receive signal is received, and wherein the transceiver is configured to compare the cryptographic datum to an expected cryptographic datum to the further transceiver to authenticate.

Example 19. The transceiver of Example 18, wherein the transceiver is provided with a key to generate the expected cryptographic date.

Example 20. A transceiver according to example 19, wherein the key is provided by a trans-parent key instance.

Example 21. The transceiver of any one of Examples 12-20, wherein the receiver comprises a receive circuit configured to acquire the cryptographic datum, and wherein the receiver is configured to calibrate the receive circuit.

Example 22. The transceiver of Example 21, wherein calibrating comprises determining a reference voltage to obtain the cryptographic date.

Example 23. A transceiver according to example 22, wherein the communication circuit comprises a calibration circuit configured to determine the reference voltage in dependence on a supply voltage and / or a temperature.

Example 24. The transceiver of Example 23, wherein the calibration circuit comprises a scaled replica of at least a portion of a transmit path to transmit the receive signal, the calibration circuit configured to determine the reference voltage based on a voltage drop across a portion of the replica.

Example 25. The transceiver of Example 24, wherein the portion of the replica includes a resistor that simulates a resistor coupled to at least one transmission line over which the receive signal is receivable.

Example 26. A transceiver according to example 24 or 25, wherein the portion of the replica is adjustable, the calibration circuit being arranged to adjust the portion of the replica to match a corresponding portion of the transmit path.

Example 27. The transceiver of Example 26, wherein the calibration circuit is configured to adjust the portion of the replica based on variations of the at least two signal levels during a calibration phase.

Example 28. A transceiver according to Example 26 or 28, wherein the calibration circuit is arranged to validate the adjustment of the part of the replica.

Example 29. A transceiver according to any one of Examples 12-28, wherein the receiver is arranged to process only the received signal in accordance with the physical communication protocol to obtain information transmitted in the first signal when the received signal does not include a second signal and / or the cryptographic signal Date can not be obtained from the received signal.

• einen ersten Transceiver nach einem der Beispiele 1-11, und
• einen mit dem ersten Transceiver über ein Kommunikationsmedium gekoppelten zweiten Transceiver nach einem der Beispiele 12-29.

Example 30. System comprising:

• a first transceiver according to any of Examples 1-11, and
• a second transceiver coupled to the first transceiver via a communication medium according to any one of Examples 12-29.

Example 31. The system of Example 30, wherein the first transceiver and / or the second transceiver is part of a control unit of a vehicle.

• - einem erstes Signal gemäß eines physikalischen Kommunikationsprotokolls, und
• -einem zweites Signal, das mindestens ein kryptographisches Datum umfasst,

wobei das Signal das physikalische Kommunikationsprotokoll erfüllt.Example 32. Signal comprising an overlay of:

• a first signal according to a physical communication protocol, and
• a second signal comprising at least one cryptographic datum,

wherein the signal meets the physical communication protocol.

Example 33. Signal according to example 32,
wherein the second signal is a pulse-shaped signal or an AC-shaped signal.

Example 34. The signal of any one of Examples 32 or 33, wherein the second signal is superimposed on the first signal only on one of at least two levels of the first signal according to the physical communication protocol.

Example 35. A signal according to any of Examples 32 and 33, wherein the second signal is superimposed on the first signal if no level change of the first signal occurred for a certain time or if no level change of the first signal occurs for a certain time.

Example 36. The signal of any one of Examples 32 to 35, wherein the first signal comprises logically encrypted data.

While specific embodiments have been illustrated and described in this specification, persons of ordinary skill in the art will recognize that a variety of alternative and / or equivalent implementations as substitution for the specific embodiments shown and described in this specification are without departing from the scope of FIG Deviation can be chosen according to the invention. It is the intention that this application covers any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents of the claims.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• ISO 11898 [0003]
• ISO 17458-1 [0003]
• ISO 17458-4 [0003]

Claims (30)

Transceiver (41) comprising: a transmitter (42) adapted to to provide at a output a first signal (s1) according to a physical communication protocol, and providing at the output a second signal (s2) comprising at least one cryptographic datum (14), the first (s1) and second (s2) signals being superimposed as an overlay signal (s) at the output, and wherein the overlay signal meets the physical communication protocol. Transceiver (41) after Claim 1 wherein the second signal (s2) is a pulse-shaped signal or an AC-shaped signal. Transceiver after one of Claims 1 to 2 wherein the second signal (s2) is superimposed on the first signal (s1) only on one of at least two levels of the first signal according to the physical communication protocol. Transceiver after one of Claims 1 to 3 , wherein the second signal (s2) is superimposed if no level change of the first signal (s1) took place for a certain time or no level change of the first signal (s1) will take place for a certain time. Transceiver after one of Claims 1 to 4 wherein a logic protocol layer overlying the physical communication protocol provides a logic signal, and the logic signal is used to generate the first signal (s1). Transceiver after Claim 5 wherein the logic protocol layer is configured to encrypt data to be transmitted to provide the logic signal. A transceiver according to any one of the preceding claims, wherein the cryptographic datum (14) is a security code of the transceiver. A transceiver according to any one of the preceding claims, wherein the transceiver is provided with a key for generating the cryptographic date (14). Transceiver after Claim 8 in which the key is provided by a key instance (261) which is superordinate to the transceiver (41). A transceiver according to any one of the preceding claims, wherein the transmitter (42) comprises a driver circuit (50) arranged to provide the heterodyne signal, and wherein the transmitter (42) is arranged to calibrate the driver circuit. Transceiver after Claim 10 wherein the driver circuit (50) comprises a first series connection of a first switch (56, 54) and a first resistor (55, 53) coupled between a supply voltage and the output, the first switch (56, 54) in Dependent on the first signal (s1) is controllable, and the driver circuit has a second series connection of a second switch (52) and a second resistor (51) which is coupled between the supply voltage and the output, wherein the second switch (52) depending on the cryptographic date is controllable. Transceiver (41) comprising: a receiver (43) adapted to a receive signal (s) which is a superposition of a first signal according to a physical communication protocol with a second signal comprising a cryptographic datum (14), to process the received signal according to the physical communication protocol to obtain information transmitted in the first signal, and - From the received signal to win the cryptographic date. Transceiver after Claim 12 , wherein the second signal is a pulse-shaped signal or an AC-shaped signal. Transceiver after one of Claims 12 or 13 wherein the receiver (43) is adapted to obtain the cryptographic datum from the superposition of the second signal over the first signal only at one of at least two levels of the first signal according to the physical communication protocol. Transceiver after one of Claims 1 to 3 wherein the receiver (43) is adapted to gain the cryptographic date from the superposition of the second signal over the first signal, if no level change of the first signal took place for a certain time or if no level change of the first signal takes place for a certain time. Transceiver (41) after one of Claims 12 to 15 wherein the information obtained from the first signal is provided as a logic signal to a logic protocol layer that is the parent of the physical communication protocol. Transceiver (41) after Claim 16 wherein the logic protocol layer is configured to extract data sent from the logic signal by decryption. The transceiver (41) of any one of the preceding claims, wherein the cryptographic datum is a security code of another transceiver from which the receive signal is received, and wherein the transceiver (41) is arranged to compare the cryptographic datum to an expected cryptographic datum to authenticate the other transceiver. Transceiver (41) after Claim 18 wherein the transceiver (41) is provided with a key for generating the expected cryptographic date. Transceiver (41) after Claim 19 in which the key is provided by a key instance (261) which is superordinate to the transceiver (41). Transceiver (41) after one of Claims 12 - 20 wherein the receiver (43) comprises a receiving circuit (44) arranged to acquire the cryptographic data, and wherein the receiver (43) is arranged to calibrate the receiving circuit. Transceiver after Claim 21 wherein calibrating comprises determining a reference voltage to obtain the cryptographic date. Transceiver (41) after one of Claims 12 - 21 wherein the receiver (43) is arranged to process only the received signal according to the physical communication protocol in order to obtain information transmitted in the first signal when the received signal does not contain a second signal and / or the cryptographic data can not be obtained from the received signal. A system (10) comprising: a first transceiver according to any one of Claims 1 - 11 , and a second transceiver coupled to the first transceiver via a communication medium (13) according to any one of Claims 12 - 23 , System after Claim 24 wherein the first transceiver and / or the second transceiver is part of a control unit of a vehicle. Signal comprising an overlay of: a first signal (s1) according to a physical communication protocol, and a second signal (s2) comprising at least one cryptographic datum, the signal fulfilling the physical communication protocol. Signal after Claim 26 wherein the second signal (s2) is a pulse-shaped signal or an AC-shaped signal. Signal after one of Claims 26 or 27 wherein the second signal (s2) is superimposed on the first signal (s1) only on one of at least two levels of the first signal (s1) according to the physical communication protocol. Signal after one of Claims 26 to 28 , wherein the second signal (s2) is superimposed on the first signal (s1) if no level change of the first signal (s1) occurred for a certain time or if no level change of the first signal (s1) will take place for a certain time. Signal after one of Claims 26 to 29 wherein the first signal (s1) comprises logically encrypted data.

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