JP6185589B2 - Semiconductor device and data concealing method in semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device including two nonvolatile memory cells that hold complementary data.

Conventionally, a technique for improving the confidentiality of stored data is known.
For example, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2008-204507 (Patent Document 1) uses a scramble information generated by a random number generation unit to perform a scramble process on write data and then writes to a data storage unit Is described. Since the scramble information is stored in the SRAM, which is a volatile memory, the scramble information is erased when the power is turned off so that the scramble information is erased even when the stored data remains in the data storage portion when the semiconductor device is turned off. The stored data cannot be read correctly. Thereby, the confidentiality of stored data can be improved.

  Japanese Patent Application Laid-Open No. 2010-277484 (Patent Document 2) also describes a non-volatile storage device that performs descrambling after writing data is written and scrambled.

JP 2008-204507 A JP 2010-277484 A

  By the way, in the twin cell composed of two cells holding complementary data, the threshold voltages of the two cells are both reduced by erasing the twin cell data. At this time, it is assumed that the difference between the threshold voltages of the two cells in the write state before erasing the twin cell data may remain after erasing the twin cell data. Therefore, even though the twin cell data is erased, the write state before erasing the twin cell data is read, which may cause a security problem.

  However, the method described in Patent Document 1 has a problem in that stored data in the data storage unit is not read when the power is turned off.

  In addition, in the method described in Patent Document 2, by storing a scrambled write data, a written flag that is a different bit pattern for each writing unit, and an error correction code, a power cutoff during writing, etc. The purpose is to detect anomalies, and the above-mentioned security problems cannot be solved.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

According to the semiconductor device of one embodiment of the present invention, the scramble unit scrambles data to be written to the twin cell in the first storage unit using the scramble data. The writing unit writes the scrambled write data into the twin cells in the first storage unit. The writing unit writes the scrambled data into the memory cell in the second storage unit. Descrambling unit uses the scrubber down table data read from the second storage unit, the data read from the first storage unit to process descramble.

  According to one embodiment of the present invention, it is possible to avoid reading the write state before erasing the twin cell data.

It is a figure showing the structure of the semiconductor device of 1st Embodiment. 3 is a flowchart showing a procedure for erasing twin cell data from a memory array in the semiconductor device of the first embodiment. It is a figure showing the structure of the microcomputer of 2nd Embodiment. It is a figure showing the structure of a flash memory module. (A) is a figure showing the example of the bias voltage given to a split gate type flash memory element. (B) is a figure showing the example of the bias voltage given to the stacked gate type flash memory element using a hot carrier write system. (C) is a figure showing the example of the bias voltage given to the stacked gate type | mold flash memory element using an FN tunnel write system. (A) is a diagram showing a state in which twin cell data stores “0”. (B) is a diagram showing a state in which twin cell data stores “1”. (C) is a diagram showing an initialized state of twin cell data. (A) is a diagram showing a sequence for erasing twin cell data “0”. (B) is a diagram showing a sequence for erasing twin cell data “1”. It is a figure showing the detailed circuit structure of the reading system of the twin cell data of 2nd Embodiment, a writing system, and an erasing system. It is a figure showing the main components which are concerned with writing and reading of the twin cell data in the semiconductor device of 3rd Embodiment. It is a figure showing the structure of the expansion part engaged in writing and reading of the twin cell data in the semiconductor device of 4th Embodiment. It is a figure showing the main components engaged in writing and reading of the twin cell data in the semiconductor device of 5th Embodiment. (A) is a diagram showing a state in which a single cell stores single cell data “0”. (B) is a diagram showing a state in which a single cell stores single cell data “1”. It is a figure showing the main components engaged in writing and reading of the twin cell data in the semiconductor device of 6th Embodiment. (A) is a diagram showing a state in which three single cells store single cell data “0”. (B) is a diagram showing a state in which three single cells store single cell data “1”. FIG. 4 is a diagram illustrating a sense amplifier included in a read column selection circuit & sense amplifier. It is a figure showing the structure of the normal part and expansion part of 7th Embodiment. It is a figure showing the structure of the normal part of the modification of 7th Embodiment, and an expansion part. It is a figure showing 1 erase block structure of the memory array of 8th Embodiment. It is a figure showing the activation timing of the several source line in 8th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment.

The semiconductor device 500 includes a first storage unit 502, a second storage unit 503, a scramble unit 501, a write unit 509, a write unit 511, and a descramble unit 504.
The first storage unit 502 includes a twin cell 505. The twin cell 505 includes a memory cell 506 and a memory cell 507. The memory cell 506 and the memory cell 507 can be electrically rewritten. The twin cell 505 stores 1-bit data in a complementary manner depending on the difference in threshold voltage between the memory cell 506 and the memory cell 507.

The second memory portion 503 includes an electrically rewritable memory cell 510.
When the data in the twin cell 505 in the first memory unit 502 is erased, the data in the memory cell 510 in the second memory unit 503 is also erased.

  The scramble unit 501 scrambles data to be written in the twin cell 505 of the first storage unit 502 using the scramble data.

  The writing unit 509 writes the scrambled write data to the twin cell 505 in the first storage unit 502.

  The writing unit 511 writes scrambled data to the memory cell 510 in the second storage unit 503.

  The descrambling unit 504 performs descrambling processing on the data read from the first storage unit 502 using the scramble data read from the second storage unit 503.

  FIG. 2 is a flowchart showing a procedure of a write process and a read process of write data to the first storage unit in the semiconductor device of the first embodiment.

First, the semiconductor device receives a write request signal (step S101).
The scramble unit 501 scrambles the data to be written to the twin cell 505 of the first storage unit 502 using the scramble data (step S102).

  Next, the writing unit 509 writes the scrambled write data to the twin cell 505 in the first storage unit 502 (step S103).

  Next, the writing unit 511 writes scrambled data to the memory cell 510 in the second storage unit 503 (step S104).

Next, the semiconductor device receives a read request signal (step S105).
Next, the descrambling unit 504 performs descrambling processing on the data read from the first storage unit 502 using the scramble data read from the second storage unit 503 (step S106).

  As described above, according to the present embodiment, even if write data after scramble processing is erased, write data is prevented from being restored unless both the write data after scramble processing and the scramble data are read. be able to.

[Second Embodiment]
The semiconductor device of this embodiment is a microcomputer.
(Microcomputer)
FIG. 3 is a diagram illustrating the configuration of the microcomputer 1 according to the second embodiment.

  A microcomputer (MCU) 1 shown in FIG. 3 is formed on one semiconductor chip such as single crystal silicon by, for example, a complementary MOS integrated circuit manufacturing technique.

  The microcomputer 1 has a high-speed bus HBUS and a peripheral bus PBUS, although not particularly limited. The high-speed bus HBUS and the peripheral bus PBUS are not particularly limited, but each have a data bus, an address bus, and a control bus. By providing two buses, it is possible to reduce the load on the bus and to guarantee a high-speed access operation compared to the case where all circuits are commonly connected to the common bus.

  The high-speed bus HBUS includes a central processing unit (CPU) 2, a direct memory access controller (DMAC) 3, a bus interface control between the high-speed bus HBUS and the peripheral bus PBUS, or a bus that includes an instruction control unit and an execution unit to execute instructions. A bus interface circuit (BIF) 4 that performs bridge control is connected.

  Further, a random access memory (RAM) 5 used for a work area of the central processing unit 2 and a flash memory module (FMDL) 6 as a nonvolatile memory module for storing data and programs are connected to the high-speed bus HBUS. Is done.

  The peripheral bus PBUS controls a flash sequencer (FSQC) 7 that performs command access control to the flash memory module (FMDL) 6, external input / output ports (PRT) 8 and 9, timer (TMR) 10, and microcomputer 1. A clock pulse generator (CPG) 11 for generating an internal clock CLK is connected.

  Further, the microcomputer 1 includes a clock terminal to which an oscillator is connected to XTAL / EXTAL or an external clock is supplied, an external hardware standby terminal STB for instructing a standby state, an external reset terminal RES for instructing a reset, an external power supply A terminal Vcc and an external ground terminal Vss are provided.

  Here, the flash sequencer 7 as a logic circuit and the flash memory module 6 having an array configuration are designed using different CAD tools, and are therefore shown as separate circuit blocks for convenience. Configure flash memory. The flash memory module 6 is connected to the high-speed bus HBUS via a read-only high-speed access port (HACSP). The CPU 2 or the DMAC 3 can read-access the flash memory module 6 from the high-speed bus HBUS via the high-speed access port. The CPU 2 or the DMAC 3 issues a command to the flash sequencer 7 via the peripheral bus PBUS via the bus interface 4 when performing write and initialization access to the flash memory module 6. As a result, the flash sequencer 7 initializes the flash memory module and controls the write operation from the peripheral bus PBUS through the low-speed access port (LACSP).

(Flash memory module)
FIG. 4 is a diagram showing the configuration of the flash memory module 6.

  The flash memory module 6 stores 1-bit information using two nonvolatile memory cells. That is, the memory array (MARY) 19 includes a plurality of two rewritable nonvolatile memory cells MCP and MCN as 1-bit twin cells. FIG. 4 representatively shows only one pair. In this specification, the memory cell MCP is called a positive cell, and the memory cell MCN is called a negative cell.

  The volatile memory cells MCP and MCN are, for example, split gate type flash memory devices exemplified in FIG. This memory element has a control gate CG and a memory gate MG disposed on a channel formation region between the source / drain regions via a gate insulating film. A charge trap region (SiN) such as silicon nitride is disposed between the memory gate MG and the gate insulating film. The source or drain region on the selection gate side is connected to the bit line BL, and the source or drain region on the memory gate MG side is connected to the source line SL.

  In order to lower the threshold voltage Vth of the memory cell, BL = Hi-Z (high impedance state), CG = Open, MG = -10V, SL = 6, WELL = 0V, and between the well region (WELL) and the memory gate MG Electrons are extracted from the charge trap region (SiN) to the well region (WELL) by the high electric field. This processing unit is a plurality of memory cells sharing the memory gate MG.

  To raise the threshold voltage Vth of the memory cell, BL = 0V, CG = 0.9V, MG = 10V, SL = 6, WELL = 0V, and a write current is supplied from the source line SL to the bit line BL, thereby controlling the control gate. Hot electrons generated at the boundary between the CG and the memory gate MG are injected into the charge trap region (SiN). Since the electron injection is determined by whether or not a bit line current is passed, this process is controlled in units of bits.

  Reading is performed with BL = 1.5V, CG = 1.5V, MG = 0V, SL = 0V, and WELL = 0V. If the threshold voltage Vth of the memory cell is low, the memory cell is turned on, and if the threshold voltage Vth is high, the memory cell is turned off.

  The memory device is not limited to the split gate type flash memory device, and may be a stacked gate type flash memory device illustrated in FIGS. 5B and 5C. This memory element is configured by stacking a floating gate FG and a control gate WL via a gate insulating film on a channel formation region between a source / drain region. In FIG. 5B, the threshold voltage Vth is increased by the hot carrier writing method, and the threshold voltage Vth is decreased by the emission of electrons to the well region WELL. In FIG. 5C, the threshold voltage Vth is increased by the FN tunnel writing method, and the threshold voltage Vth is decreased by the emission of electrons to the bit line BL.

  Voltages applied to the memory gate MG, control gate CG, source lines SL, WELL, and bit line BL described above are generated and supplied by the power supply circuit (VPG) 31 under the control of the flash sequencer 7.

  In the following description, it is assumed that the memory element is a split gate flash memory element.

  Information storage by one twin cell composed of the nonvolatile memory cells MCP and MCN is performed by storing complementary data in the nonvolatile memory cells MCP and MCN.

  That is, each of the memory cells MCP and MCN has cell data “1” (low threshold voltage state; state in which the threshold voltage is smaller than the erase verify level) or cell data “0” (high threshold voltage state; the threshold voltage is in the erase verify state). State above the level).

  As shown in FIG. 6A, the twin cell data “0” is a state in which the positive cell MCP holds the cell data “0” and the negative cell MCN holds the cell data “1”. As shown in FIG. 6B, the twin cell data “1” is a state in which the positive cell MCP holds the cell data “1” and the negative cell MCN holds the cell data “0”. As shown in FIG. 6C, the state in which the positive cell MCP and the negative cell MCN of the twin cell both hold the cell data “1” is an initialized state, and the twin cell data becomes indefinite. The initialized state is also called a blank erase state.

  Switching from the state of twin cell data “0” and the state of twin cell data “1” to the initialized state is called erasing of the twin cell data. Further, changing from the initialized state to the twin cell data “1” holding state or the twin cell data “0” holding state is called normal writing.

  When erasing twin cell data, the cell data of both the positive cell MCP and the negative cell MCN is temporarily set to “0” (referred to as pre-write), and then the erase pulse is applied to both cell data. Processing to set “1” is performed. In pre-write, for both the positive cell MCP and the negative cell MCN, the applied voltage is made smaller than that during normal writing, or the writing pulse is weakened by shortening the period during which the writing pulse is applied. To do. In the pre-write, the increase amount of the threshold voltage of the memory cell having the smaller threshold voltage is smaller than the increase amount of the threshold voltage Vth during normal writing. The purpose of performing the pre-write is to reduce variations in erasing stress between the positive cell MCP and the negative cell MCN and to suppress deterioration of the retention characteristics. In order to prevent the stress due to prewrite from becoming greater than the stress due to normal write, a voltage smaller than the voltage during general normal write (increase Vth) shown in FIG. 5 is applied during prewrite.

FIG. 7A shows a sequence for erasing twin cell data “0”.
As shown in FIG. 7A, when the erase of the twin cell data “0” is executed, both cells are initialized by the prewrite, but before the erase, Since the threshold voltage Vth of the positive cell MCP is larger than the threshold voltage Vth of the negative cell MCN, there is a possibility that this relationship is maintained even after erasing. When reading is performed in a state in which this relationship is maintained, the threshold voltage Vth between the positive cell MCP and the negative cell MCN is different regardless of the initialized state. Data “0” equal to “0” may be read.

FIG. 7B shows a sequence for erasing twin cell data “1”.
As shown in FIG. 7B, when the erasure of the twin cell data “1” is executed, both cells are initialized by the pre-write, but before the erasure, Since the threshold voltage Vth of the negative cell MCN is larger than the threshold voltage Vth of the positive cell MCP, there is a possibility that this relationship is maintained even after erasing. When reading is performed in the immediately preceding twin cell data state, the threshold voltage Vth between the positive cell MCP and the negative cell MCN is different regardless of the initialized state. Data “1” equal to “1” may be read.

  Even if the data is erased in this way, if it is not an undefined value that does not determine the data each time it is read, but data with the same probability as the previous twin cell data can be read with a high probability, this may cause a security problem. There is. The embodiment of the present invention aims to solve such a possible problem.

  In the twin-cell memory cells MCP and MCN typically shown in FIG. 4, the memory gate MG is connected to a common memory gate selection line MGL, and the control gate CG is connected to a common word line WL. Actually, a large number of twin cells are arranged in a matrix and connected to the corresponding memory gate selection line MGL and word line WL in an array unit in the row direction. Memory cells MCP and MCN are connected to bit lines BLP and BLN in units of columns.

  The word line WL is selected by the first row decoder (RDEC1) 24. The memory gate selection line MGL is selected by the second row decoder (RDEC2) 25. The selection operation by the first row decoder 24 and the second row decoder 25 follows the address information supplied to the HACSP in the read access, and follows the address information supplied to the LACSP in the data write operation and the initialization operation.

  The write column selection circuit 51 selects a write column according to the decoding result of the column decoder (CDEC) 30, and writes write data sent from the input / output circuit (IOBUF) 29 interfaced to the data bus (PBUS_D) of the peripheral bus PBUS. Output to the scramble unit 35. The selection operation of the column decoder 30 follows address information supplied to the LACSP.

  The scramble unit 35 scrambles the write data sent from the write column selection circuit 51 and sends the scrambled write data to the write latch unit 36.

  The write latch unit 36 latches the scrambled write data and allows a write current to flow through either of the bit lines BLP and BLN of the selected write column, thereby causing the memory cell MCP of the selected write column to , MCN is written (that is, the threshold voltage Vth is increased).

  The verify unit 33 determines that the threshold voltage Vth of the memory cells MCP and MCN is at the write verify level according to the voltages of the bit lines BLP and BLN of the selected write column and the scrambled write data held in the write latch unit 36. To verify if it is greater than. The write verify result is supplied to the flash sequencer 7 through the peripheral data bus PBUS_D.

  The verify unit 33 executes erase verify. In the erase verify, it is verified whether or not the threshold voltage Vth of both the memory cells MCP and MCN constituting each twin cell in the erase target area is lower than the erase verify level. The erase verify result is supplied to the flash sequencer 7 through the peripheral data bus PBUS_D.

  The bit line BLP connected to the memory cell MCP and the bit line BLN connected to the memory cell MCN are connected to the column selection & amplification unit 37.

  The column selection & amplification unit 37 selects a read column. The column selection & amplification unit 37 reads the twin cell data of the memory cells MCP and MCN of the selected read column by amplifying the voltage difference between the bit lines BLP and BLN of the selected read column.

  The descrambling unit 38 descrambles the read twin cell data output from the column selection & amplification unit 37 and outputs the data to the data bus HBUS_D of the high-speed bus HBUS via the output buffer (OBUF) 26.

  The power supply circuit (VPG) 31 generates various operation voltages necessary for reading, writing, and initialization. The timing generator (TMG) 32 generates an internal control signal that defines internal operation timing according to an access strobe signal supplied from the CPU 2 or the like to the HACSP, an access command supplied from the FSQC 7 to the LACSP, or the like.

  The control unit of the flash memory includes a flash sequencer (FSQC) 7 and a timing generator (TMG) 32.

  FIG. 8 is a diagram illustrating main components involved in writing and reading twin cell data in the semiconductor device of the second embodiment.

  As shown in FIG. 8, the semiconductor device of the second embodiment includes a normal unit 100 and an expansion unit 101.

  The normal unit 100 includes a write column selection circuit 51, scramblers 61_1 to 61_N, inverters IVN_1 to IVN_N, write latch circuits 62P_1 to 62P_N, 62N_1 to 62N_N, a normal mat NMAT1, a read column selection circuit & sense amplifier 64. And descramblers 65_1 to 65_N.

  The expansion unit 101 includes a scramble data generation circuit 52, inverters IVE_1 to IVE_N, write latch circuits 63P_1 to 63P_N, 63N_1 to 63N_N, an expansion mat EMAT1, and a read column selection circuit & sense amplifier 66.

  The scramblers 61_1 to 61_N constitute the scrambler 35 in FIG. The descramblers 65_1 to 65_N constitute the descramble unit 38 of FIG. The write latch circuits 62P_1 to 62P_N, 62N_1 to 62N_N, 63P_1 to 63P_N, and 63N_1 to 63N_N constitute the write latch unit 36 of FIG. The read column selection circuit & sense amplifiers 64 and 66 constitute the column selection & amplification unit 37 of FIG.

  The scramble data generation circuit 52 generates N-bit scramble data S1 to SN. Each bit Si is sent to the write latch circuit 63P_i and also sent to the write latch circuit 63N_i via the inverter IVE_i.

  The scramble data generation circuit 52 outputs the same scramble data (S1 to SN) for the write data having the same row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25. , Scrambled data (S1 to SN) that are different from each other are output for write data that is selected in different rows.

  The scramble data generation circuit 52 outputs the scramble data (S1 to SN) to the write latch circuits 63P_1 to 63P_N and 63N_1 to 63N_N when the generated scramble data (S1 to SN) is not yet written in EMAT1. .

  The regular mat NMAT1 includes a plurality of twin cells MTC (i, j). However, i represents a column and is 1 to N. j represents a line and is 1 to L. Twin cell MTC (i, j) includes positive cell MCP (i, j) and negative cell MCN (i, j). Positive cell MCP (i, j) is connected to bit line BLNP_i. Negative cell MCN (i, j) is connected to bit line BLNN_i.

  The expansion mat EMAT1 includes a plurality of twin cells ETC (i, j). However, i represents a column and is 1 to N. j represents a line and is 1 to L. The twin cell ETC (i, j) includes a positive cell EMCP (i, j) and a negative cell EMCN (i, j). The positive cell EMCP (i, j) is connected to the bit line BLEP_i. The negative cell EMCN (i, j) is connected to the bit line BLEN_i.

  When the twin cell data of the twin cell MTC (i, j) (i = 1 to N, j = 1 to L) of the normal mat NMAT1 is erased, the twin cell ETC (i, j) (i = 1 to 1) of the expansion mat EMAT1 N, j = 1 to L) twin cell data is also erased.

  The write column selection circuit 51 selects a column in which data is written from the first column to the Nth column of the normal mat NMAT1. When the selected column is j, the write column selection circuit 51 outputs 1-bit write data sent from the input / output circuit (IOBUF) 29 to the scrambler 61_j corresponding to the selected column j.

  The scrambler 61_i (i = 1 to N) receives 1 bit Si of the N bits of scrambled data S1 to SN from the scramble data generation circuit 52. The scrambler 61_i scrambles the 1-bit write data with Si when the 1-bit write data D is sent from the write column selection circuit 51. The scrambled write data DSi are sent to the write latch circuit 62P_i and also sent to the write latch circuit 62N_i via the inverter IVN_i.

  Scramble processing means reversibly converting write data using scramble data. The descrambling process means obtaining original write data by converting the scrambled data using the scrambled data.

  In an example of the scramble processing method, exclusive OR of write data and scramble data is obtained by scramble processing, and original write data is obtained by exclusive OR of scrambled data and scramble data by descrambling processing. Here, all of the scramble processing methods by the N scramblers 61_i (i = 1 to N) may be the same, all may be different, or different from the same. It may be mixed.

  The write latch circuit 62P_i (i = 1 to N) grounds the bit line BLNP_i while the write pulse WPLS is activated when the scrambled write data DSi sent from the scrambler 61_i is “0”. By connecting to the voltage Vss, a write current flows through the bit line BLNP_i. As a result, the threshold voltage Vth of the memory cell MCP (i, k) in the selected row k increases, and cell data “0” is written.

  When the scrambled write data DSi sent from the scrambler 61_i is “1”, the write latch circuit 62P_i (i = 1 to N) connects the bit line BLNP_i to the power supply voltage VDD. A write current is prevented from flowing through BLNP_i. As a result, the threshold voltage Vth of the memory cell MCP (i, k) in the selected row k does not change.

  When the inverted data / DSi of the scrambled write data sent from the inverter IVN_i is “0”, the write latch circuit 62N_i (i = 1 to N) has the bit line during the period when the write pulse WPLS is activated. By connecting BLNN_i to the ground voltage Vss, a write current flows through the bit line BLNN_i. As a result, the threshold voltage Vth of the memory cell MCN (i, k) in the selected row k increases, and cell data “0” is written.

  The write latch circuit 62N_i (i = 1 to N) connects the bit line BLNN_i to the power supply voltage VDD when the inverted data / DSi of the scrambled write data sent from the inverter IVN_i is “1”. The write current is prevented from flowing through the bit line BLNN_i. As a result, the threshold voltage Vth of the memory cell MCN (i, k) in the selected row k does not change.

  The read column selection circuit & sense amplifier 64 selects a column from which data is read from the first column to the Nth column of the normal mat NMAT1. When the selected column is j, the read column selection circuit & sense amplifier 64 amplifies the difference between the voltage of the bit line BLNP_j and the voltage of the bit line BLNN_j, reads the scrambled twin cell data, and Output to the tumbler 65_j. When the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 is k rows, the scrambled write data RDSj of the twin cell MTC (j, k) is read out. After the scrambled write data DSj is written in the twin cell MTC (j, k), when the data in the twin cell MTC (j, k) is not erased, the read data RDSj becomes equal to DSj. On the other hand, when data is read from twin cell MTC (j, k) after data in twin cell MTC (j, k) is erased, read data RDSj should be originally an indefinite value. May be equal to DSj as described with reference to FIG.

  Write latch circuit 63P_i (i = 1 to N) receives 1 bit Si of N bits of scrambled data S1 to SN from scramble data generation circuit 52. When Si is “0”, the write latch circuit 63P_i causes the write current to flow through the bit line BLEP_i by connecting the bit line BLEP_i to the ground voltage Vss while the write pulse WPLS is activated. . As a result, the threshold voltage Vth of the memory cell EMCP (i, k) in the selected row k increases, and cell data “0” is written.

  The write latch circuit 63P_i (i = 1 to N) prevents the write current from flowing through the bit line BLEP_i by connecting the bit line BLEP_i to the power supply voltage VDD when Si is “1”. As a result, the threshold voltage Vth of the memory cell EMCP (i, k) in the selected row k does not change.

  Write latch circuit 63N_i (i = 1 to N) receives inverted value / Si of 1-bit Si among N-bit scrambled data S1 to SN sent from inverter IVE_i. When / Si is “0”, the write latch circuit 63N_i connects the bit line BLEN_i to the ground voltage Vss while the write pulse WPLS is activated so that the write current flows through the bit line BLEN_i. To do. As a result, the threshold voltage Vth of the memory cell EMCN (i, k) in the selected row k increases, and the cell data “0” is written.

  The write latch circuit 63N_i (i = 1 to N) prevents the write current from flowing through the bit line BLEN_i by connecting the bit line BLNN_i to the power supply voltage VDD when / Si is “1”. As a result, the threshold voltage Vth of the memory cell EMCN (i, k) in the selected row k does not change.

  The read column selection circuit & sense amplifier 66 selects a column from which data is read out of the first column to the Nth column of the expansion mat EMAT1. When the selected column is j, the read column selection circuit & sense amplifier 66 amplifies the difference between the voltage of the bit line BLEP_j and the voltage of the bit line BLEN_j, reads the scrambled data, and reads the scrambled data into the disk Output to the tumbler 65_j. When the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 is k rows, the scrambled data RSj of the twin cell ETC (j, k) is output. After the scrambled data Sj is written in the twin cell ETC (j, k), when the data of the twin cell ETC (j, k) is not erased, the read twin cell data RSj becomes equal to Sj. On the other hand, when data is read from the twin cell ETC (j, k) after the data in the twin cell ETC (j, k) is erased, the read data RSj should originally be an indefinite value. May be equal to Sj as described with reference to FIG.

  The descrambler 65_i (i = 1 to N) outputs the 1-bit scrambled twin cell data RDSi output from the read column selection circuit & sense amplifier 64 and the 1 output from the read column selection circuit & sense amplifier 66. The descrambling process is performed using the bit scrambled data RSi, and the result is output to the output buffer (OBUF) 26.

Here, all of the descrambling methods by N descramblers 65_i (i = 1 to N) may be the same, all may be different, or different from the same. May be mixed. However, methods of descramble processing by the descrambler 65_i (i = 1~N) is based on the converted write data DSi with scrubber down table data Si in the corresponding scrambler 61_i using the same scramble data Si Must be able to be restored to the write data D.

  As described above, according to the present embodiment, when the scrambled write data is written to the regular mat and is not erased, the scrambled write data and the scrambled data are correctly read out. The write data can be normally restored by the descrambling process.

  When the scrambled write data is written to the regular mat and erased, the scrambled data is also erased from the expansion mat. Even in this state, there is a possibility that both the scrambled write data before erasure and the scrambled data before erasure may be read, but since the probability is low, the probability that the write data is restored by the descrambling process is increased. Can be lowered.

[Modification of Second Embodiment]
In the second embodiment, the bit selected by the write column selection circuit 51 and the twin cells in the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 are scrambled by 1 bit. The write data is written, but the present invention is not limited to this. 1-bit scrambled write data is input to all the columns of the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 when N-bit write data is input from the outside. May be written.

In the second embodiment, the scrambler 61_i and the descrambler 65_i use the 1-bit data Si to scramble and descramble the write data. However, the present invention is not limited to this. The scrambler 61_i and the descrambler 65_i may scramble and descramble the write data using a plurality of bits of the N-bit scramble data (S1 to SN).
[Third Embodiment]
FIG. 9 is a diagram illustrating main components involved in writing and reading twin cell data in the semiconductor device of the third embodiment.

  The semiconductor device of FIG. 9 is different from the semiconductor device of the second embodiment of FIG. 8 as follows. 8 includes N scramblers 61_1 to 61_N and N descramblers 65_1 to 65_N, whereas the regular part 200 of the semiconductor device in FIG. The scrambler 71 and one descrambler 75 are provided.

  The scrambler 71 receives N-bit scramble data S <b> 1 to SN from the scramble data generation circuit 52. When the column selected by the write column selection circuit 51 is i and 1-bit write data D is sent from the write column selection circuit 51, the scrambler 71 scrambles the 1-bit write data with Si. The scrambled write data DSi are sent to the write latch circuit 62P_i and also sent to the write latch circuit 62N_i via the inverter IVN_i.

  The descrambler 75 uses the 1-bit scrambled twin cell data RDSi output from the read column selection circuit & sense amplifier 64 and the 1-bit scramble data RSi output from the read column selection circuit & sense amplifier 66. The descrambling process is then performed and output to the output buffer (OBUF) 26. Here, the method of the descrambling process by the descrambler 75 cannot restore the write data DSi converted by using the scramble data Si in the scrambler 71 to the original write data D by using the same scramble data Si. must not.

  As described above, according to the present embodiment, the scramble process and the descramble process for N columns of write data are performed by one scrambler 71 and one descrambler 75, so that the circuit scale is reduced. It can be made smaller than in the second embodiment.

[Modification of Third Embodiment]
In the third embodiment, similarly to the modification of the second embodiment, N-bit write data is input from the outside and is selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25. 1-bit scrambled write data may be written in each of all the columns in the row.

The scrambler 71 and the descrambler 75 may scramble and descramble the write data using a plurality of bits of the N-bit scramble data (S1 to SN).
[Fourth Embodiment]
FIG. 10 is a diagram illustrating a configuration of an extension unit involved in writing and reading of twin cell data in the semiconductor device of the fourth embodiment. Since the normal part is the same as that of the second embodiment, the description will not be repeated.

  The extension unit 301 is different from the extension unit 101 of the semiconductor device according to the second embodiment shown in FIG.

8 includes 2N write latch circuits 63P_1 to 63P_N and 63N_1 to 6 3 N_N, whereas the expansion unit 301 illustrated in FIG. 10 includes 6N write latch circuits 73P1_1 to 73P1_N and 73P2_1. 73P2_N, 73P3_1 to 73P3_N, 73N1_1 to 73N1_N, 73N2_1 to 73N2_N, 73N3_1 to 73N3_N.

  The expansion mat EMAT1 of the expansion unit 101 in FIG. 8 includes N × L twin cells ETC (i, j) (where i is 1 to N, j = 1 to L), whereas the expansion mat EMAT1 in FIG. The expansion mat EMAT2 of the unit 301 includes 3N × L twin cells ETC (s, i, j) (where s = 1 to 3, i = 1 to N, j = 1 to L).

  The twin cell ETC (s, i, j) includes a positive cell EMCP (s, i, j) and a negative cell EMCN (s, i, j). The positive cell EMCP (s, i, j) is connected to the bit line BLEPs_i. The negative cell EMCN (s, i, j) is connected to the bit line BLENs_i.

  The scramble data generation circuit 52 generates N-bit scramble data S1 to SN. Each bit Si is sent to the write latch circuits 73P1_i, 73P2_i, 73P3_i, and is also sent to the write latch circuits 73N1_i, 73N2_i, 73N3_i via the inverter IVE_i.

  Write latch circuits 73P1_i, 73P2_i, 73P3_i receive 1-bit Si of N-bit scrambled data S1 to SN from scramble data generation circuit 52. When the Si is “0”, the write latch circuits 73P1_i, 73P2_i, and 73P3_i connect the bit lines BLEP1_i, BLEP2_i, and BLEP3_i to the ground voltage Vss during the period when the write pulse WPLS is activated. , BLEP2_i, BLEP3_i so that a write current flows. As a result, the threshold voltage Vth of the memory cells EMCP (1, i, k), EMCP (2, i, k), and EMCP (3, i, k) in the selected row k increases, and the cell data “0”. Is written.

  When Si is “1”, the write latch circuits 73P1_i, 73P2_i, and 73P3_i connect the bit lines BLEP1_i, BLEP2_i, and BLEP3_i to the power supply voltage VDD so that no write current flows through the bit lines BLEP1_i, BLEP2_i, and BLEP3_i. Like that. As a result, the threshold voltage Vth of the memory cells EMCP (1, i, k), EMCP (2, i, k), and EMCP (3, i, k) in the selected row k does not change.

  Write latch circuits 73N1_i, 73N2_i, and 73N3_i receive 1-bit inverted value / Si of N-bit scrambled data S1 to SN from inverter IVE_i. When / Si is “0”, the write latch circuits 73N1_i, 73N2_i, and 73N3_i connect the bit lines BLEN1_i, BLEN2_i, and BLEN3_i to the ground voltage Vss while the write pulse WNLS is activated. A write current is caused to flow through BLEN1_i, BLEN2_i, and BLEN3_i. As a result, the threshold voltage Vth of the memory cells EMCN (1, i, k), EMCN (2, i, k), EMCN (3, i, k) of the selected row k increases, and the cell data “0” Is written.

  When / Si is “1”, the write latch circuits 73N1_i, 73N2_i, and 73N3_i connect the bit lines BLEN1_i, BLEN2_i, and BLEN3_i to the power supply voltage VDD, whereby a write current flows through the bit lines BLEN1_i, BLEN2_i, and BLEN3_i. Do not. As a result, the threshold voltage Vth of the memory cells EMCN (1, i, k), EMCN (2, i, k), EMCN (3, i, k) in the selected row k does not change.

Read column selection circuit and a sense amplifier 7 6 selects the reading sequence data of the first column to the N-th column of the extension mat EMAT2. Read column selection circuit and a sense amplifier 7 6, when the selected column is j amplifies the difference between the voltage and the voltage of the bit line BLEN1_j bit line BLEP1_j, reads the scrambled data Te is output to the determination circuit 77 . Read column selection circuit and a sense amplifier 7 6, when the selected column is j amplifies the difference between the voltage and the voltage of the bit line BLEN2_j bit line BLEP2_j, reads the scrambled data Te is output to the determination circuit 77 . Read column selection circuit and a sense amplifier 7 6, when the selected column is j amplifies the difference between the voltage and the voltage of the bit line BLEN3_j bit line BLEP3_j, reads the scrambled data Te is output to the determination circuit 77 .

  When the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 is k rows, the first scrambled data RSj1, twin cell ETC ( 2, j, k) second scrambled data RSj2 and third cell ETC (3, j, k) third scrambled data RSj3 are read out.

  After the scrambled data Sj is written in the twin cell ETC (1, j, k), ETC (2, j, k), ETC (3, j, k), the twin cell ETC (1, j, k), ETC ( 2, j, k) and ETC (3, j, k) are not erased, the read data RSj1, RSj2, and RSj3 are equal to Sj. On the other hand, after the data of the twin cells ETC (1, j, k), ETC (2, j, k), ETC (3, j, k) are erased, the twin cells ETC (1, j, k), ETC (2 , J, k), when data is read from ETC (3, j, k), the read data RSj1, RSj2, and RSj3 should originally be indefinite values, but FIG. 7 is used. As described above, it may be equal to Sj.

  When the values of the first scramble data RSi1, the second scramble data RSi2, and the third scramble data RSi3 are all the same, the determination circuit 77 outputs the same value as the read scramble data RSi.

  The determination circuit 77 is “0” when two of the first scrambled data RSi1, the second scrambled data RSi2, and the third scrambled data RSi3 are “1” and the rest are “0”. Is output as scrambled data RSi. The determination circuit 77 is “1” when two of the first scrambled data RSi1, the second scrambled data RSi2, and the third scrambled data RSi3 are “0” and the rest are “1”. Is output as scrambled data RSi.

  As described above, according to the present embodiment, the scrambled data is written to the three twin cells of the expansion mat, and the scrambled data is determined based on the data values read from the three twin cells at the time of reading. The probability that the previous scrambled data is read can be reduced.

[Fifth Embodiment]
FIG. 11 is a diagram illustrating main components involved in writing and reading twin cell data in the semiconductor device of the fifth embodiment.

  The semiconductor device of FIG. 11 is different from the semiconductor device of the second embodiment of FIG. 8 as follows. The semiconductor device in FIG. 8 includes 2N write latch circuits 63P_1 to 63P_N and 63N_1 to 63N_N, whereas the extension unit 401 in FIG. 11 includes N write latch circuits 83_1 to 83_N.

  Further, the expansion mat EMAT1 of the expansion unit 101 of FIG. 8 includes N × L twin cells ETC (i, j) (where i is 1 to N, j = 1 to L), whereas FIG. The expansion mat EMAT3 of the expansion unit 401 includes N × L single cells EMC (i, j) (where i = 1 to N, j = 1 to L). The single cell EMC (i, j) is connected to the bit line BLE_i.

  As shown in FIG. 12A, the single cell data “0” is a state in which the memory cell MC holds the cell data “0” (high threshold voltage state; the threshold voltage is equal to or higher than the erase verify level). As shown in FIG. 12B, the single cell data “1” is a state in which the memory cell MC holds the cell data “1” (low threshold voltage state; the threshold voltage is smaller than the erase verify level). .

  The scramble data generation circuit 52 generates N-bit scramble data S1 to SN. Each bit Si is sent to the write latch circuit 83_i.

  Write latch circuit 83 — i (i = 1 to N) receives 1 bit Si of N bits of scrambled data S 1 to SN from scramble data generation circuit 52. When Si is “0”, the write latch circuit 83_i connects the bit line BLE_i to the ground voltage Vss during a period in which the write pulse WPLS is activated so that a write current flows through the bit line BLE_i. . As a result, the threshold voltage Vth of the single cell EMC (i, k) in the selected row k increases, and the cell data “0” is written. When Si is “1”, the write latch circuit 83 — i prevents the write current from flowing through the bit line BLE_i by connecting the bit line BLE_i to the power supply voltage VDD. As a result, the threshold voltage Vth of the single cell EMC (i, k) in the selected row k does not change.

The read column selection circuit & sense amplifier 86 selects a column from which data is read out of the first column to the Nth column of the expansion mat EMAT3. One input terminal of the sense amplifier of the read column select circuit & sense amplifier 8 6, when the selected column is j is connected to the bit line BLE_j, the other input terminal is connected to a constant current source circuit. This sense amplifier amplifies the voltage difference between the two input terminals, reads the scrambled data, and outputs it to the descrambler 65_j.

  When the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 is k rows, the scrambled data RSj of the single cell EMC (j, k) is output. After the scrambled data Sj is written to the single cell EMC (j, k), when the data of the single cell EMC (j, k) is not erased, the read data RSj becomes equal to Sj. On the other hand, when data is read from single cell EMC (j, k) after data in single cell EMC (j, k) is erased, read data RSj has a fixed value “1”. .

  As described above, according to the present embodiment, when the scrambled write data is written to the regular mat and is not erased, the scrambled write data and the scrambled data are correctly read out. The write data can be normally restored by the descrambling process.

  When the scrambled write data is written to the regular mat and erased, the scrambled data is also erased from the expansion mat. In this state, the scrambled write data before erasure may be read out, but the scrambled data before erasure is not read out (fixed value “1” is read out). It is possible to prevent the write data from being restored by the processing.

[Sixth Embodiment]
FIG. 13 is a diagram illustrating main components involved in writing and reading of twin cell data in the semiconductor device of the sixth embodiment.

The semiconductor device of FIG. 13 is different from the semiconductor device of the second embodiment of FIG. 8 as follows. 8 includes 2N write latch circuits 63P_1 to 63P_N and 63N_1 to 6 3 N_N, whereas the extension unit 501 in FIG. 13 includes 3N write latch circuits 93_1_1 to 93_1_N, 93_2_1 to 93_2_N, 93_3_1 to 93_3_N.

  Further, the expansion mat EMAT1 of the expansion unit 101 of FIG. 8 includes N × L twin cells ETC (i, j) (where i is 1 to N, j = 1 to L), whereas FIG. The expansion mat EMAT4 of the expansion unit 501 includes 3N × L single cells EMC (s, i, j) (where s = 1 to 3, i = 1 to N, j = 1 to L). The single cell EMC (s, i, j) is connected to the bit line BLEs_i.

  The scramble data generation circuit 52 generates N-bit scramble data S1 to SN. Each bit Si is sent to the write latch circuits 93_1_i, 93_2_i, and 93_3_i.

  Write latch circuits 93_1_i, 93_2_i, and 93_3_i receive 1-bit Si from N-bit scrambled data S1 to SN from scramble data generation circuit 52. When Si is “0”, the write latch circuits 93_1_i, 93_2_i, and 93_3_i connect the bit lines BLE1_i, BLE2_i, and BLE3_i to the ground voltage Vss during the period when the write pulse WPLS is activated. , BLE2_i, BLE3_i so that a write current flows. As a result, the threshold voltage Vth of the memory cells EMC (1, i, k), EMC (2, i, k), and EMC (3, i, k) in the selected row k increases, and the cell data “0”. Is written.

  When Si is “1”, the write latch circuits 93_1_i, 93_2_i, and 93_3_i connect the bit lines BLE1_i, BLE2_i, and BLE3_i to the power supply voltage VDD so that no write current flows through the bit lines BLE1_i, BLE2_i, and BLE3_i. Like that. As a result, the threshold voltage Vth of the memory cell EMC (1, i, k), EMC (2, i, k), EMC (3, i, k) in the selected row k does not change.

  As shown in FIG. 14A, when Si to be stored is “0”, memory cells EMC (1, i, k), EMC (2, i, k), EMC (3, i, k) Is a state in which the cell data “0” (high threshold voltage state; state in which the threshold voltage is equal to or higher than the erase verify level) is held. As shown in FIG. 14B, when Si to be stored is “1”, the memory cells EMC (1, i, k), EMC (2, i, k), EMC (3, i, k) Is a state in which the cell data “1” (low threshold voltage state; state in which the threshold voltage is smaller than the erase verify level) is held.

  The read column selection circuit & sense amplifier 96 selects a column from which data is read out of the first column to the Nth column of the expansion mat EMAT4.

  FIG. 15 is a diagram showing sense amplifier 97 of read column selection circuit & sense amplifier 96. When the selected column is j, one input terminal of the sense amplifier 97 is connected to the bit lines BLE1_j, BLE2_j, and BLE3_j, and the other input terminal is connected to the constant current source circuit 98. The sense amplifier 97 amplifies the voltage difference between the two input terminals, reads the scrambled data, and outputs the scrambled data to the descrambler 65_j.

  In this embodiment, even when the data retention characteristic of any one of the three memory cells is poor and the threshold voltage is lowered, the total value of the currents from the three memory cells and the constant current source circuit 98 Since the sum of currents is compared, a read margin can be ensured. Therefore, the constant current output from the constant current source circuit 98 is set to a value that considers the read margin.

  When the row selected by the first row decoder (RDEC1) 24 and the second row decoder (RDEC2) 25 is k rows, single cells EMC (1, j, k), EMC (2, j, k), The scramble data RSj of EMC (3, j, k) is output. After the scrambled data Sj is written to the single cells EMC (1, j, k), EMC (2, j, k), and EMC (3, j, k), the single cells EMC (1, j, k), When the data of EMC (2, j, k) and EMC (3, j, k) is not erased, the read data RSj is equal to Sj. On the other hand, after the data of the single cells EMC (1, j, k), EMC (2, jk), and EMC (3, j, k) are erased, the single cells EMC (1, j, k), EMC (2 , J, k), EMC (3, j, k), the read data RSj has a fixed value “1”.

  As described above, according to the present embodiment, when the scrambled write data is written to the regular mat and is not erased, the scrambled write data and the scrambled data are correctly read out. The write data can be normally restored by the descrambling process. At this time, the holding power of the scrambled data in the expansion mat can be enhanced as compared with the fifth embodiment.

  When the scrambled write data is written to the regular mat and erased, the scrambled data is also erased from the expansion mat. In this state, the scrambled write data before erasure may be read out, but the scrambled data before erasure is not read out (fixed value “1” is read out). It is possible to prevent the write data from being restored by the processing.

[Seventh Embodiment]
FIG. 16 is a diagram illustrating the configuration of the normal part and the extension part of the seventh embodiment.

As shown in FIG. 16, the semiconductor device of the present embodiment includes M number regular portion 100 of the second embodiment of FIG. 8 (normal portion 100_1~100_ M).

  That is, the N-bit scramble data S1 to SN generated by the scramble data generation circuit 52 of the extension unit 101 is sent to the scramblers 61_1 to 61_N of the M normal units 100_1 to 100_M. The read N-bit scrambled data RS1 to RSN output from the read column selection circuit & sense amplifier 66 of the extension unit 101 are sent to the descramblers 65_1 to 65_N of the M normal units 100_1 to 100_M.

  Here, the normal part 100_i corresponds to the data input pin DIi among the M data input pins DI1 to DIM, and corresponds to the data output pin DOi among the M data output pins DO1 to DOM.

  M normal parts 100_1 to 100_M execute simultaneous writing of M-bit write data from M data input pins DI1 to DIM, M normal parts 100_1 to 100_M execute simultaneous reading, and M M-bit data read from the data output pins DO1 to DOM is output.

  As described above, in this embodiment, N-bit scrambled data is applied to N × M columns of write data in the normal part, so that the area of the expansion mat can be made smaller than in the second embodiment. Can do.

[Modification of the seventh embodiment]
FIG. 17 is a diagram illustrating configurations of a normal part and an extension part according to a modification of the seventh embodiment.

  As shown in FIG. 17, the semiconductor device of this modification includes M normal parts 200 of the third embodiment in FIG. 9 (normal parts 200_1 to 200_M).

  That is, the N-bit scramble data S1 to SN generated by the scramble data generation circuit 52 of the extension unit 101 is sent to the scramblers 71 of M normal units 200_1 to 200_M. The read N-bit scrambled data RS1 to RSN output from the read column selection circuit & sense amplifier 66 of the extension unit 101 are sent to the descrambler 75 of M normal parts 200_1 to 200_M.

  Here, as in the seventh embodiment, the normal part 200_i corresponds to the data input pin DIi in the M data input pins DI1 to DIM, and the data output in the M data output pins DO1 to DOM. Corresponds to pin DOi.

  M normal parts 200_1 to 200_M execute simultaneous writing of M-bit write data from M data input pins DI1 to DIM, and M normal parts 200_1 to 200_M execute simultaneous reading, M-bit data read from the data output pins DO1 to DOM is output.

  As described above, in this modification, the N-bit scrambled data is applied to the N × M columns of write data of the normal part, so that the expansion mat area can be made smaller than in the third embodiment. it can.

[Eighth Embodiment]
FIG. 18 is a diagram showing a 1-erasure block configuration of the memory array according to the eighth embodiment.

  One erase block consists of a regular mat and an extended mat. The regular mat of one erase block is divided into small blocks NMAT <0> to NMAT <31>. The extension mat of one erase block is divided into small blocks EMAT <0> to EMAT <31>.

  The small block NMAT <i> of the regular mat and the small block EMAT <i> of the expansion mat are arranged adjacent to each other. As an example, the scrambled data stored in the small block EMAT <i> of the extended mat may be used for the scramble process and the descramble process of the write data to the small block NMAT <i> of the regular mat. Alternatively, a part of the scrambled data stored in the small block EMAT <i> of the extended mat is used for the scramble process and the descramble process of the write data to the small block NMAT <i> of the regular mat, One or more regular mat small blocks EMAT <j> (j ≠ i) may be used for scramble processing and descramble processing of write data.

  The memory cells of the small block NMAT <i> of the normal mat and the small block EMAT <i> of the expansion mat are connected to the common source line SL <i>, and these memory cells are erased at the same timing. The

  As shown in FIG. 19, first, the source line SL <0> is activated, and first, the memory cells of the small block NMAT <0> of the normal mat and the small block EMAT <0> of the expansion mat are erased. .

  Next, the source line SL <1> is activated, and the memory cells of the small block NMAT <1> of the normal mat and the small block EMAT <1> of the expansion mat are erased.

  Finally, the source line SL <31> is activated, and the memory cells of the normal mat small block NMAT <31> and the extended mat small block EMAT <31> are erased.

  As described above, according to the present embodiment, the expansion mats are physically distributed and disposed, and therefore, only when a specific time-division erasure occurs when the expansion mats are physically concentrated. It is possible to avoid the problem that the number of bits increases or the extension mat needs to be erased by time division.

  The present invention is not limited to the embodiment described above, and includes, for example, the following modifications.

(1) Switching control In the semiconductor device according to the embodiment of the present invention, the write data is scrambled at the time of writing, and the read data is descrambled at the time of reading. It is not limited.

  For example, a semiconductor device has both a normal write and read function and a write and descramble function with the scramble process, and can switch which function is executed. Good.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1 microcomputer (MCU), 2 central processing unit (CPU), 3 direct memory access controller (DMAC), 4 bus interface circuit (BIF), 5 random access memory (RAM), 6 flash memory module (FMDL), 7 flash Sequencer (FSQC), 8, 9 External I / O port (PRT), 10 Timer (TMR), 11 Clock pulse generator (CPG), 19 Memory array (MARY), 24 First row decoder (RDEC1), 25 Second row Decoder (RDEC2), 29 Input / output circuit (IOBUF), 30 column decoder (CDEC), 31 power supply circuit (VPG), 32, timing generator (TMG), 33 verify unit, 34 write column selection unit, 35,501 scramble unit , 36 writing , 37 column selection & amplification unit, 38,504 descrambling unit, 51 write column selection circuit, 52 scramble data generation circuit, 61_1 to 61_N, 71 scrambler, 62P_1 to 62P_N, 62N_1 to 62N_N, 63P_1 to 63P_N, 63N_1 ~63N_ N, 73P1_1~73P1_N, 73P2_1~73P2_N, 73P3_1~73P3_N , 73N1_1~73N1_N, 73N2_1~73N2_N, 73N3_1~73N3_N, 83_1~83_N, 93_1_1~93_1_N, 93_2_1~93_2_N, 93_3_1~93_3_N write latch circuit, 64 and 66 Read column selection circuit & sense amplifier, 65_1 to 65_N, 75 descrambler, 97 sense amplifier, 98 constant current source circuit 100, 100_1 to 100_M, 200, 200_1 to 200_M Normal part, 101, 301, 401, 501 Expansion part, NMAT1, NMAT <0> to NMAT <31> Normal mat, EMAT1, EMAT2, EMAT3, EMAT4, EMAT <0> ~ EMAT <31> expansion mat, 500 semiconductor device, 502 first storage unit, 503 second storage unit, 506, 507, 510, MCP (i, j), MCN (i, j), EMCP (i, j), EMCN (i, j), EMC (i, j), EMC (s, i, j), EMCP (s, i, j), EMCN (s, i, j) Memory cell, 505, MTC ( i, j), ETC (i, j), ETC (s, i, j) Twin cell 509, 511 Writing unit, BLNP_1 to BLNP_N, BLNN_1 to BLNN N, BLEP_1~BLEP_N, BLEN_1~BLEN_N, BLE_1~BLE_N bit lines, IVN_1~IVN_N, IVE_1~IVE_N inverter, PBUS_D peripheral data bus, DI0～DIM data input pin, DO0～DOM data output pin.

Claims (18)

A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A second memory portion including electrically rewritable memory cells;
A scramble unit that scrambles data to be written to the twin cell in the first storage unit using scramble data;
A first writing unit for writing the scrambled write data to the twin cells in the first storage unit;
A second writing unit for writing the scrambled data into the memory cell in the second storage unit;
A descrambling unit that descrambles the data read from the first storage unit using the scrambled data read from the second storage unit;
The second storage unit is formed of a single memory cell comprises a single cell storing one bit of the scrambling data, the semiconductor device. A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A second memory portion including electrically rewritable memory cells;
A scramble unit that scrambles data to be written to the twin cell in the first storage unit using scramble data;
A first writing unit for writing the scrambled write data to the twin cells in the first storage unit;
A second writing unit for writing the scrambled data into the memory cell in the second storage unit;
A descrambling unit that descrambles the data read from the first storage unit using the scrambled data read from the second storage unit;
The second storage unit is composed of one memory cell, and includes a plurality of single cells that store one bit of the scrambled data, and the plurality of single cells store one bit of scrambled data in an overlapping manner,
It connected one input terminal simultaneously to a plurality of bit lines connected to the plurality of single cells, comprising a sense amplifier the other input terminal is connected to the constant current source circuit, the semiconductor device. A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A second memory portion including electrically rewritable memory cells;
A scramble unit that scrambles data to be written to the twin cell in the first storage unit using scramble data;
A first writing unit for writing the scrambled write data to the twin cells in the first storage unit;
A second writing unit for writing the scrambled data into the memory cell in the second storage unit;
A descrambling unit that descrambles the data read from the first storage unit using the scrambled data read from the second storage unit;
The second storage unit is composed of two memory cells, and includes a plurality of twin cells that store one bit of scrambled data. The plurality of twin cells store one bit of scrambled data in an overlapping manner,
When the 1-bit values read from the plurality of twin cells are all the same, the same value is sent to the descramble unit, and the 1-bit values read from the plurality of twin cells are different from the others. In some cases , the semiconductor device includes a determination circuit that sends a less frequent value to the descramble unit. A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A second memory portion including electrically rewritable memory cells;
A scramble unit that scrambles data to be written to the twin cell in the first storage unit using scramble data;
A first writing unit for writing the scrambled write data to the twin cells in the first storage unit;
A second writing unit for writing the scrambled data into the memory cell in the second storage unit;
A descrambling unit that descrambles the data read from the first storage unit using the scrambled data read from the second storage unit;
The first storage unit and the second storage unit are each divided into the same number of small blocks,
It said first small block and a set of small blocks of the second storage unit of the storage unit is erased at the same timing, the semiconductor device. A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A second memory portion including electrically rewritable memory cells;
A scramble unit that scrambles data to be written to the twin cell in the first storage unit using scramble data;
A first writing unit for writing the scrambled write data to the twin cells in the first storage unit;
A second writing unit for writing the scrambled data into the memory cell in the second storage unit;
A descrambling unit that descrambles the data read from the first storage unit using the scrambled data read from the second storage unit;
Wherein when the data of the first storage unit is erased, the data of the second storage unit is also erased, the semiconductor device. The scramble unit is
A plurality of scramblers provided for each column of the first storage unit;
The scrambler scrambles 1-bit write data for twin cells in a corresponding column using the scramble data,
The descrambling part is
A plurality of descramblers provided for each column of the first storage unit;
6. The descrambler according to claim 1, wherein the descrambler performs descrambling processing on 1-bit data read from a twin cell in a corresponding column using scrambled data read from the second storage unit. 7. Semiconductor device. The scrambled data is composed of a plurality of bits,
The scrambler scrambles 1-bit write data for twin cells in a corresponding column using one bit corresponding to the column among a plurality of bits constituting the scramble data,
7. The semiconductor according to claim 6, wherein the descrambler performs descrambling processing on 1-bit data read from a twin cell in a corresponding column using 1 bit corresponding to the column among a plurality of bits constituting the scrambled data. apparatus. The scramble unit is
Including a scrambler provided in common to the plurality of columns of the first storage unit,
The scrambler scrambles 1-bit write data for the twin cell using the scramble data,
The descrambling part is
A descrambler provided in common for the plurality of columns of the first storage unit;
6. The semiconductor device according to claim 1, wherein the descrambler performs descrambling processing on 1-bit data read from the twin cell using scrambled data read from the second storage unit. 7. . The scrambled data is composed of a plurality of bits,
The scrambler scrambles 1-bit write data for a twin cell using 1 bit corresponding to the column of the twin cells among a plurality of bits constituting the scramble data,
9. The semiconductor device according to claim 8, wherein the descrambler performs descrambling processing on 1-bit data read from the twin cell by using 1 bit corresponding to a column of the twin cells among a plurality of bits constituting the scrambled data. . Multiple sets of data input pins and data output pins;
Each set of data input pins and data output pins includes the scrambler and the descrambler,
9. The semiconductor device according to claim 8, wherein the plurality of scramblers perform scramble processing using the same scramble data, and the plurality of descramblers perform descrambling processing using the same scramble data. A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A second storage unit including an electrically rewritable memory cell and configured to erase data in the memory cell when data in the twin cell is erased;
The first data is scrambled using scrambled data to generate second data, the second data is written into the twin cell in the first storage unit, and the memory in the second storage unit Means for writing the scrambled data into a cell;
A semiconductor device comprising: a descrambling unit that descrambles the second data read from the first storage unit using the scrambled data read from the second storage unit. The semiconductor device according to claim 11 , wherein the second storage unit includes a twin cell that includes two memory cells and stores one bit of the scrambled data. The semiconductor device according to claim 11 , wherein the second storage unit includes a single cell that includes one memory cell and stores one bit of the scrambled data. The second storage unit is composed of one memory cell, and includes a plurality of single cells that store one bit of the scrambled data, and the plurality of single cells store one bit of scrambled data in an overlapping manner,
12. The semiconductor device according to claim 11 , further comprising a sense amplifier having one input terminal connected simultaneously to a plurality of bit lines connected to the plurality of single cells and the other input terminal connected to a constant current source circuit. The second storage unit is composed of two memory cells, and includes a plurality of twin cells that store one bit of scrambled data. The plurality of twin cells store one bit of scrambled data in an overlapping manner,
When the 1-bit values read from the plurality of twin cells are all the same, the same value is sent to the descramble unit, and the 1-bit values read from the plurality of twin cells are different from the others. The semiconductor device according to claim 11 , further comprising a determination circuit that sends a less frequent value to the descramble unit. The first storage unit and the second storage unit are each divided into the same number of small blocks,
The semiconductor device according to claim 11 , wherein a set of the small block of the first storage unit and the set of the small block of the second storage unit are erased at the same timing. 12. The semiconductor device according to claim 11 , wherein when the data in the first storage unit is erased, the data in the second storage unit is also erased. A first storage unit including a twin cell that is electrically rewritable and stores 1-bit data complementarily according to a difference in threshold voltage;
A method for concealing data in a semiconductor device, comprising: a second storage unit including an electrically rewritable memory cell and configured to erase data in the memory cell when data in the twin cell is erased Because
Receiving a write request signal;
After receiving the write request signal, scramble the first data using scrambled data to generate second data;
Writing the second data into the twin cell in the first storage unit;
Writing the scrambled data into the memory cells in the second storage unit;
Receiving a read request signal; and
A step of descrambling the second data read from the first storage unit using the scrambled data read from the second storage unit after receiving the read request signal. A data concealment method in a semiconductor device.

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