JP6172231B2 - Power converter - Google Patents

Description

  The present invention relates to a power converter that converts a DC voltage into an AC voltage, and more particularly, to a reduction in loss of a single-phase three-level power converter.

  A three-level inverter method has been proposed for an inverter device that converts DC power into AC power from the viewpoint of reducing waveform distortion (for example, Patent Document 1 and Patent Document 2). Hereinafter, as a conventional example of a single-phase three-level inverter, the configuration and operation of circuits disclosed in Patent Document 1 and Patent Document 2 will be described with reference to FIGS.

  FIG. 9 is a circuit configuration diagram of a single-phase three-level inverter disclosed in Patent Document 1. In the single-phase three-level inverter, the control unit 6a controls the on / off state of the switch elements constituting the inverter circuit 3a, converts the DC voltage 2E of the power source 1 into a single-phase AC voltage, and converts this single-phase AC voltage to This is supplied to the load 5.

  In FIG. 9, a capacitor C1 and a capacitor C2 are connected in series at both ends of the power source 1. Capacitor C1 and capacitor C2 constitute a first DC power source and a second DC power source. When the voltage of the power source 1 is 2E, the voltages of the capacitor C1 and the capacitor C2 are E, respectively. A voltage detector 2 is connected to both ends of the power source 1, and the voltage detector 2 detects the voltage 2E of the power source 1.

  Next, the series circuit which connected the switch elements 1u-4u in series is connected to the both ends of the series circuit which consists of the capacitor | condenser C1 and the capacitor | condenser C2. Diodes 1x to 4x are connected in antiparallel to the switch elements 1u to 4u constituting the series circuit, respectively. Also, diodes 5x and 6x are connected in series between the connection point of the switch elements 1u and 2u and the connection point of the switch elements 3u and 4u. Further, the connection point between the diodes 5x and 6x is connected to the connection point between the capacitors C1 and C2.

  Further, a series circuit in which switch elements 1v to 4v are connected in series is connected to both ends of a series circuit composed of the capacitor C1 and the capacitor C2. Diodes 1y to 4y are connected in antiparallel to the switch elements 1v to 4v constituting the series circuit, respectively. Diodes 5y and 6y are connected in series between the connection point of the switch elements 1v and 2v and the connection point of the switch elements 3v and 4v. Further, the connection point between the diodes 5y and 6y is connected to the connection point between the capacitors C1 and C2.

  Here, the switch elements 1u to 4u and the diodes 1x to 6x constitute a first half bridge. The switch elements 1v to 4v and the diodes 1y to 6y constitute a second half bridge. Further, the first half bridge and the second half bridge constitute an inverter circuit 3a.

  A connection point between the switch elements 2u and 3u is a U terminal, and a connection point between the switch elements 2v and 3v is a V terminal. The U terminal and the V terminal are AC output terminals of the inverter circuit 3a. A voltage detector 4 and a load 5 are connected in parallel between the U terminal and the V terminal.

  Next, the control unit 6a outputs gate signals of the switch elements 1u to 4u and 1v to 4v. Therefore, the control unit 6a includes an output voltage command unit 61, a control calculation unit 62, and a first PWM control unit 63a.

Below, operation | movement of the control part 6a is demonstrated. First, the output voltage command means 61 outputs a command value of a voltage to be applied to the load by the inverter circuit 3a.
The control calculation means 62 performs AVR calculation with a PI controller or the like so that the AC output voltage detected by the voltage detector 4 matches the output voltage command output by the output voltage command means 61. Further, the control calculation means 62 calculates the modulation signal for PWM control by dividing the result of the AVR calculation by the DC input voltage detected by the voltage detector 2.

  The first PWM control unit 63a compares the carrier signal generated internally with the modulation signal output from the control calculation unit 62, and generates gate signals of the switch elements 1u to 4u and 1v to 4v. This gate signal is output to the inverter circuit 3a.

The switch elements 1u to 4u and 1v to 4v are on / off controlled by the gate signal. As a result, a desired AC voltage is output between the U and V terminals of the inverter circuit 3a.
FIG. 10 is a diagram showing an example of an output voltage waveform generated between the U and V terminals of the inverter circuit 3a shown in FIG. Since the single-phase three-level inverter generally operates at a carrier frequency of about 10 kHz, the output voltage has a waveform closer to a sine wave.

  Table 1 is a table showing voltages output between the U and V terminals of the inverter circuit 3a corresponding to the combinations of the on / off states of the switch elements 1u to 4u and 1v to 4v. By repeating the modes 1 to 8 shown in Table 1, the voltage having the waveform shown in FIG. 10 is output between the U and V terminals of the inverter circuit 3a. As shown in FIG. 10 and Table 1, the output voltage of the inverter circuit 3a has five levels of 0, E, 2E, -E, and -2E.

FIG. 11 is a circuit configuration diagram of a single-phase three-level inverter disclosed in Patent Document 2. In the single-phase three-level inverter of FIG. 11, the control unit 6b controls the on / off state of the switch elements constituting the inverter circuit 3b to convert the DC voltage 2E of the power source 1 into a single-phase AC voltage. An alternating voltage is supplied to the load 5.

  The first DC power source and the second DC power source including the power source 1 and the capacitors C1 and C2 are the same as those in the conventional example shown in FIG. A voltage detector 2 is connected to both ends of the power source 1 to detect the voltage 2E of the power source 1.

  Next, the switch elements 1u and 4u are connected in series to both ends of the series circuit composed of the capacitor C1 and the capacitor C2, and the connection between the connection point and the connection point between the capacitors C1 and C2 is reversed. A circuit in which switching elements 2u and 3u having a withstand voltage are connected in antiparallel is connected. Diodes 1x and 4x are connected in antiparallel to the switch elements 1u and 4u, respectively.

  Further, switching elements 1v and 4v are connected in series to both ends of the series circuit composed of the capacitor C1 and the capacitor C2, and a reverse breakdown voltage is connected between the connection point and the connection point between the capacitors C1 and C2. Is connected to a circuit in which switch elements 2v and 3v having the above are connected in antiparallel. Diodes 1y and 4y are connected in antiparallel to the switch elements 1v and 4v, respectively.

  Here, the switch elements 1u to 4u and the diodes 1x and 4x constitute a first half bridge. Switch elements 1v to 4v and diodes 1y and 4y constitute a second half bridge. Further, the first half bridge and the second half bridge constitute an inverter circuit 3b.

  A connection point between the switch elements 1u and 4u is a U terminal, and a connection point between the switch elements 1v and 4v is a V terminal. The U terminal and the V terminal are AC output terminals of the inverter circuit 3b. A voltage detector 4 and a load 5 are connected in parallel between the U terminal and the V terminal.

  Next, the control unit 6b outputs gate signals of the switch elements 1u to 4u and 1v to 4v. Therefore, the control unit 6b includes an output voltage command unit 61, a control calculation unit 62, and a first PWM control unit 63b.

Below, operation | movement of the control part 6b is demonstrated. Of the control unit 6b, the output voltage command means 61 and the control calculation means 62 are the same as the single-phase three-level inverter shown in FIG.
The first PWM control unit 63b compares the carrier signal generated internally and the modulation signal output from the control calculation unit 62, and generates gate signals of the switch elements 1u to 4u and 1v to 4v. The on / off states of the switch elements 1u to 4u and 1v to 4v are controlled by this gate signal, and a desired alternating voltage is output between the U and V terminals of the inverter circuit 3b.

  Table 2 is a table showing the voltage output between the U and V terminals of the inverter circuit 3b corresponding to the combination of the on / off states of the switch elements 1u to 4u and 1v to 4v constituting the inverter circuit 3b. By repeating the modes 1 to 8 shown in Table 2, a voltage having the same waveform as the waveform shown in FIG. 10 is output between the U and V terminals of the inverter circuit 3b. As shown in FIG. 10 and Table 2, the output voltage of the inverter circuit 3b shown in FIG. 11 also has five levels of 0, E, 2E, -E, and -2E.

JP 2008-178284 A JP 2007-28860 A

  However, in the above-described conventional example, the single-phase three-level inverter performs a switching operation with a full bridge regardless of the level of the AC output voltage. That is, as shown in Table 1 and Table 2, all switch elements (1u to 4u, 1v to 4v) constituting the first half bridge and the second half bridge repeat the on / off state. Therefore, conduction loss and switching loss occur in all switch elements, and conduction loss and reverse recovery loss occur in all diodes.

  Accordingly, the present invention has been made to solve the above-described problems. In general, a single-phase three-level inverter that performs a full-bridge operation has a fundamental wave amplitude of an AC output voltage of the first DC power source and the second DC power source. When the voltage is lower than the voltage E of the direct-current power supply, it is intended to reduce the loss generated in the inverter circuit by operating with a half bridge.

  The power conversion device of the present invention includes a power converter composed of a first half bridge and a second half bridge connected to a three-level power source, and either the first half bridge or the second half bridge. The half bridge outputs either the high potential, intermediate potential, or low potential of the three-level power supply, and the other half bridge outputs the intermediate potential of the three-level power supply. It is characterized by having a half-bridge operation mode for outputting.

  In addition, the power conversion device further outputs either a high potential, an intermediate potential, or a low potential of the three-level power source from both the first half bridge and the second half bridge, so that the output terminals of both bridges are connected. A full-bridge operation mode for outputting an alternating voltage can be provided.

  When the power converter has a half-bridge operation mode and a full-bridge operation mode, the power converter has the half-bridge when the amplitude value of the AC output voltage command is smaller than a half voltage value of the three-level power source. It operates in the operation mode and operates in the full bridge operation mode when the amplitude value of the AC output voltage command is larger than the 1/2 voltage value of the three-level power supply.

  According to the present invention, a desired AC output voltage can be obtained by causing the three-level power converter to perform a half-bridge operation. In this case, the number of switch elements that perform the switching operation can be halved compared to the case of performing the full bridge operation. Thereby, the loss which arises in a power converter circuit can be reduced.

  In particular, the above-described effects can be effectively exhibited in a three-level power conversion device used in applications where the output voltage is variably controlled between 0 V and the rated voltage or where the DC input voltage varies greatly.

The circuit block diagram of the power converter device which concerns on the 1st Embodiment of this invention. The output voltage waveform of the 3 level inverter which concerns on 1st Embodiment. The figure explaining operation | movement of the mode 1 in 1st Embodiment. The figure explaining operation | movement of the mode 3 in 1st Embodiment. The circuit block diagram of the power converter device which concerns on 2nd Embodiment concerning this invention. The figure explaining operation | movement of mode 1 in 2nd Embodiment. The figure explaining operation | movement of the mode 3 in 2nd Embodiment. The block diagram which shows other embodiment of the control part which concerns on this invention. The circuit block diagram which shows an example of the conventional power converter device. The figure which shows the output voltage waveform of the conventional power converter device. The circuit block diagram which shows another example of the conventional power converter device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. In FIG. 1 to FIG. 8, elements common to the constituent elements shown in FIG. 9 and FIG. 11, which are examples of embodiments of the conventional power conversion device, are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a circuit diagram showing a configuration of a single-phase three-level inverter according to the first embodiment of the present invention. The first embodiment is characterized in that, in the conventional single-phase three-level inverter shown in FIG. 9, the control unit 6a is the control unit 6a ', and other components are the same.

  Hereinafter, the configuration and operation of the control unit 6a 'will be described. Like the control unit 6a, the control unit 6a ′ includes an output voltage command unit 61, a control calculation unit 62, and a first PWM control unit 63a, and further includes a second PWM control unit 64a and a gate signal selection unit 65. And.

  Here, like the conventional single-phase three-level inverter shown in FIG. 9, the first PWM control unit 63a receives the modulation signal output from the control calculation means 62 and inputs the switching elements 1u to 1u constituting the inverter circuit 3a. A gate signal for on / off control of 4u, 1v to 4v with a full bridge is generated.

The second PWM control unit 64a receives the modulation signal output from the control calculation means 62 as input, and controls the switching elements 1u to 4u and 1v to 4v constituting the inverter circuit 3a to be turned on / off by a half bridge. Generate a gate signal.

  The gate signal selection unit 65 selects either the output signal of the first PWM control unit 63a or the output signal of the second PWM control unit 64a, and outputs the selected signal as the gate signal of the inverter circuit 3a.

  When determining which of the output signal of the first PWM control unit 63a and the output signal of the second PWM control unit 64a is to be selected, the voltage of the power source 1 detected by the voltage detector 2 and the output voltage command means 61 The output voltage command to be output is referred to.

  For example, when the amplitude of the fundamental wave of the AC output voltage is higher than the voltage E of the first DC power supply and the second DC power supply, the gate signal selection unit 65 selects the first PWM control unit. The output of 63a is output as a gate signal. On the other hand, when the amplitude of the fundamental wave of the AC output voltage is lower than the voltage E of the first DC power supply and the second DC power supply, the output of the second PWM control unit 64a is output as a gate signal.

  The inverter circuit 3a operates as a full bridge when the output of the first PWM control unit 63a is output as a gate signal from the gate signal selection unit 65, and the output of the second PWM control unit 64a is output as a gate signal. It operates with a half bridge.

  FIG. 2 is a diagram showing an example of an output voltage waveform generated between the U and V terminals when the inverter circuit 3a shown in FIG. 1 performs a half-bridge operation. Table 3 shows an example of output voltages corresponding to combinations of on / off states of the switch elements 1u to 4u and 1v to 4v when the inverter circuit 3a performs a half bridge operation in the first half bridge. As shown in FIG. 2 and Table 3, the voltage output between the U and V terminals of the inverter circuit 3a has three levels of 0, E, and -E.

FIG. 3 is a diagram for explaining the operation of mode 1 shown in FIG. 2 and Table 3 in the half-bridge operation of inverter circuit 3a shown in FIG. Mode 1 is a mode in which the voltage between the U and V terminals of the inverter circuit 3a is E.

  As shown in Table 3, the switch elements 1v and 4v of the second half bridge are always in the off state, and the switch elements 2v and 3v are always in the on state. Therefore, when the switch elements 1u and 2u of the first half bridge are simultaneously turned on (3u and 4u are turned off), the voltage E of the first DC power supply (capacitor C1) is changed from the capacitor C1 to the switch elements 1u and 2u. The voltage is applied to the load 5 through the path of the load 5 → the switch element 3v → the diode 6y → the capacitor C1 (FIG. 3).

FIG. 4 shows the half-bridge operation of the inverter circuit 3a shown in FIG.
It is a figure explaining operation | movement of the mode 3 shown in FIG. Mode 3 is a mode in which the voltage between the U and V terminals of the inverter circuit 3a is -E.

  As shown in Table 3, the switch elements 1v and 4v of the second half bridge are always in the off state, and the switch elements 2v and 3v are always in the on state. Therefore, when the switch elements 3u and 4u of the first half bridge are simultaneously turned on (1u and 2u are turned off), the voltage E of the second DC power supply (capacitor C2) is changed from the capacitor C2 to the diode 5y to the switch element. It is applied to the load 5 through the path 2v → load 5 → switch elements 3u, 4u → capacitor C2 (FIG. 4).

  In mode 2 and mode 4, the switch elements 2u, 3u, 2v, 3v of the first half bridge and the second half bridge are turned on, and the switch elements 1u, 4u, 1v, 4v are turned off. . Therefore, the voltage between the U and V terminals of the inverter circuit 3a is 0V.

  In this way, the control unit 6a 'can output an AC voltage between the U and V terminals by causing the inverter circuit 3a to perform a half-bridge operation based on the PWM-modulated gate signal.

  From the above, when the inverter circuit 3a is operated in a half-bridge by the first half bridge, in the second half bridge, conduction loss occurs only in the switch elements 2v and 3v, and no conduction loss occurs in the switch elements 1v and 4v. . Further, no switching loss occurs in any of the switch elements 1v to 4v constituting the second half bridge.

  Therefore, the loss of the inverter circuit 3a can be reduced as compared with the case where the first half bridge and the second half bridge are operated in a full bridge. As a result, the efficiency of the inverter circuit 3a can be improved.

  FIG. 5 is a circuit diagram showing a configuration of a single-phase three-level inverter according to the second embodiment of the present invention. The second embodiment is characterized in that, in the conventional single-phase three-level inverter shown in FIG. 11, the control unit 6b is a control unit 6b ', and other components are the same.

  Hereinafter, the configuration and operation of the control unit 6b 'will be described. Like the control unit 6b, the control unit 6b ′ includes an output voltage command unit 61, a control calculation unit 62, and a first PWM control unit 63b, and further includes a second PWM control unit 64b and a gate signal selection unit 65. And.

  Here, like the conventional single-phase three-level inverter shown in FIG. 11, the first PWM control unit 63b receives the modulation signal output from the control arithmetic means 62 as an input, and switches elements 1u to 1u constituting the inverter circuit 3b. A gate signal for on / off control of 4u, 1v to 4v with a full bridge is generated.

  Further, the second PWM control unit 64b receives the modulation signal output from the control calculation means 62 as input, and performs on / off control of the switch elements 1u to 4u and 1v to 4v constituting the inverter circuit 3b with a half bridge. Generate a gate signal.

  The gate signal selection unit 65 selects either the output signal of the first PWM control unit 63b or the output signal of the second PWM control unit 64b, and outputs the selected signal as the gate signal of the inverter circuit 3b.

  When determining which of the output signal of the first PWM control unit 63b and the output signal of the second PWM control unit 64b is to be selected, the voltage of the power source 1 detected by the voltage detector 2 and the output voltage command means 61 are The output voltage command to be output is referred to.

  For example, the gate signal selection unit 65 uses the output of the first PWM control unit 63b as a gate signal when the amplitude of the fundamental wave of the AC output voltage is higher than the voltage E of the first DC power supply and the second DC power supply. Output. On the other hand, when the amplitude of the fundamental wave of the AC output voltage is lower than the voltage E of the first DC power supply and the second DC power supply, the gate signal selection unit 65 uses the output of the second PWM control unit 64b as a gate signal. Output.

  The inverter circuit 3b operates as a full bridge when the output of the first PWM control unit 63b is output as a gate signal from the gate signal selection unit 65, and the output of the second PWM control unit 64b is output as a gate signal. It operates with a half bridge.

  When the inverter circuit 3b operates as a half bridge, the waveform of the output voltage generated between the U and V terminals is the same as in FIG. Table 4 shows an example of output voltages corresponding to combinations of on / off states of the switch elements 1u to 4u and 1v to 4v when the inverter circuit 3b performs a half bridge operation in the first half bridge. As shown in FIG. 2 and Table 4, the voltage output between the U and V terminals of the inverter circuit 3b has three levels of 0, E, and -E.

FIG. 6 is a diagram for explaining the operation of mode 1 shown in FIG. 2 and Table 4 in the half-bridge operation of inverter circuit 3b shown in FIG. Mode 1 is a mode in which the voltage between the U and V terminals of the inverter circuit 3b is E.

  As shown in Table 4, the switch elements 1v and 4v of the second half bridge are always in the off state, and the switch elements 2v and 3v are always in the on state. Therefore, when the switch element 1u of the first half bridge is turned on (4u is turned off), the voltage E of the first DC power supply is changed from the capacitor C1 → the switch element 1u → the load 5 → the switch element 3v → the capacitor C1. In the path, it is applied to the load 5 (FIG. 6).

  FIG. 7 is a diagram for explaining the operation of mode 3 shown in FIG. 2 and Table 4 in the half-bridge operation of inverter circuit 3b shown in FIG. Mode 3 is a mode in which the voltage between the U and V terminals of the inverter circuit 3b is -E.

  As shown in Table 4, the switch elements 1v and 4v of the second half bridge are always in the off state, and the switch elements 2v and 3v are always in the on state. Therefore, when the switch element 4u of the first half bridge is turned on (1u is turned off), the voltage E of the second DC power source is changed from the capacitor C2 → the switch element 2v → the load 5 → the switch element 4u → the capacitor C2. In the path, it is applied to the load 5 (FIG. 7).

  In mode 2 and mode 4, the switch elements 2u, 3u, 2v, 3v of the first half bridge and the second half bridge are turned on, and the switch elements 1u, 4u, 1v, 4v are turned off. . Therefore, the voltage between the U and V terminals of the inverter circuit 3b is 0V.

  Thus, the control unit 6b 'can output an AC voltage between the U and V terminals by causing the inverter circuit 3a to perform a half-bridge operation based on the PWM-modulated gate signal.

  As described above, when the inverter circuit 3b is operated in the half bridge by the first half bridge, the conduction loss is generated only in the switch elements 2v and 3v in the second half bridge, and the conduction loss is not generated in the switch elements 1v and 4v. . Further, no switching loss occurs in any of the switch elements 1v to 4v constituting the second half bridge.

  Therefore, the loss of the inverter circuit 3b can be reduced as compared with the case where the inverter circuit 3b is operated as a full bridge by the first half bridge and the second half bridge. As a result, the efficiency of the inverter circuit 3b can be improved.

  In FIG. 5, even if each of the switch elements 2u, 3u, 2v, and 3v is replaced with a circuit in which the switch element and the diode are connected in series, the inverter circuit 3b can be operated as a half bridge, resulting in a loss. Can be reduced.

  Further, in FIG. 5, a circuit in which the switch elements 2u and 3u are connected in antiparallel and a circuit in which the switch elements 2v and 3v are connected in antiparallel are reversed from a circuit in which the switch elements and diodes are connected in antiparallel. Even if it replaces with the circuit connected in series, the inverter circuit 3b can be operated by a half bridge, and a loss can be reduced.

  In the first and second embodiments, a desired output voltage is obtained between the U and V terminals of the inverter circuits 3a and 3b by causing the inverter circuit to perform a half bridge operation with the first half bridge. Although the case of obtaining is described as an example, the loss of the inverter circuits 3a and 3b can be similarly reduced by causing the inverter circuit to perform a half-bridge operation with the second half-bridge.

  As a more preferred embodiment, when the inverter circuits 3a and 3b are operated as a half bridge, the first half bridge and the second half bridge are alternately operated as a half bridge every half cycle of the AC output voltage, for example. It is possible. As a third embodiment for enabling such an operation, FIG. 9 shows a configuration of the control unit 6c. The control unit 6c will be described by taking the first embodiment as an example. The control unit 6c is characterized in that a bridge switching means 66 is further provided in the configuration of the control unit 6a 'in FIG.

  The bridge switching unit 66 outputs a signal for designating a bridge for performing a half-bridge operation based on the output voltage command output from the output voltage command unit 61. For example, the bridge switching means 66 outputs a signal designating the first half bridge when the polarity of the output voltage command is positive, and a signal designating the second half bridge when the polarity of the output voltage command is negative. Is output.

  The second PWM control unit 64a outputs a gate signal for causing either the first half bridge or the second half bridge to perform a half bridge operation based on the bridge designation signal output by the bridge switching unit 66.

  Specifically, when the bridge designation signal designates the first half bridge, the second PWM control unit 64a includes the switch elements 1u to 4u corresponding to the mode 1 to the mode 4 shown in Table 3. The gate signals corresponding to the on / off states of 1v to 4v are output as the gate signals of the first half bridge and the second half bridge.

  On the other hand, when the bridge designation signal designates the second half bridge, the second PWM control unit 64a switches the switch elements 1u to 4u and 1v to 4v corresponding to the modes 1 to 4 shown in Table 3. The gate signals corresponding to the on / off states of the first half bridge and the second half bridge are output by switching the gate signals.

  By switching the operation of the first half bridge and the second half bridge in this manner, the switching elements and diodes of the first half bridge and the second half bridge are evenly lossed, and the heat between the bridges Responsibility can be averaged.

As a result, the cooling design of the first half bridge and the second half bridge can be shared, and the cost can be reduced by sharing the cooling member.
Note that the control unit 6c can also be applied to the second embodiment, and the same effects as described above can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Power supply, 2 ... Voltage detector, 3a, 3b ... Inverter circuit, 4 ... Voltage detector, 5 ... Load, 6a, 6b, 6c, 6a ', 6b' ... Control unit 61 ... Output voltage command means 62 ... Control calculation means 63a, 63b ... first PWM control unit 64a, 64b ... second PWM control unit 65 ... Gate signal selection unit, 66... Bridge switching unit, 1u, 2u, 3u, 4u, 1v, 2v, 3v, 4v ... Switch element, 1x, 2x, 3x, 4x, 1y, 2y, 3y, 4y ... Diodes, C1, C2 ... Capacitors

Claims (9)

Comprising a first half-bridge connected to the three-level power supply and a three-level power converter and a second half bridge,
The three-level power converter, the first half-bridge or a high potential of one of the half-bridge the three-level power supply of the second half bridge, intermediate potential, and outputs one of the low potential, A power converter having a half-bridge operation mode in which an alternating voltage is output between the output terminals of both bridges when the other half-bridge outputs an intermediate potential of the three-level power source. The power conversion device according to claim 1,
The three-level power converter when operating in the half bridge operation mode, the high potential of the three-level power supply, intermediate potential, a bridge for outputting a bridge for outputting one of a low potential intermediate the potential of the three-level power supply And the power conversion device characterized by being switched alternately. The power conversion device according to claim 1 or 2,
The three-level power converter is further the first half-bridge or a high potential of both of the second half bridge the three-level power supply, intermediate potential, by outputting any one of a low potential, both bridges A power converter having a full-bridge operation mode for outputting an alternating voltage between output terminals. The power conversion device according to claim 3,
The three-level power converter operates in the half-bridge operation mode when the amplitude value of the AC output voltage command is smaller than a half voltage value of the three-level power source, and the amplitude value of the AC output voltage command is The power conversion device operates in the full-bridge operation mode when the voltage is larger than a half voltage value of the three-level power source. The power conversion device according to any one of claims 1 to 4, wherein:
The previous SL first half bridge and the second half bridge,
First, second, third and fourth switch elements connected in series;
First, second, third and fourth diodes connected in antiparallel to the first, second, third and fourth switch elements, respectively;
A fifth diode connected between the connection point between the intermediate potential point of the three-level power source and the first switching element and the second switching element,
A sixth diode connected between the connection point between the intermediate potential point of the three-level power supply and the third switching element and the fourth switching element,
A power conversion device comprising: The power conversion device according to any one of claims 1 to 4, wherein:
The previous SL first half bridge and the second half bridge,
A first switch element and a fourth switch element connected in series;
A first diode and a fourth diode connected in antiparallel, respectively to said first switching element and the fourth switching element,
A bidirectional switch circuit connected between the connection point between the intermediate potential point of the three-level power source and the first switching element and the fourth switching element,
A power conversion device comprising: The power conversion device according to claim 6,
The bidirectional switch circuit is configured by connecting a second switch element and a third switch element in antiparallel, and a power conversion device. The power conversion device according to claim 6,
In the bidirectional switch circuit, a circuit in which a second diode is connected in series to a second switch element and a circuit in which a third diode is connected in series to a third switch element are connected in antiparallel. It is comprised, The power converter device characterized by the above-mentioned. The power conversion device according to claim 6,
In the bidirectional switch circuit, a second switch element and a third switch element are connected in anti-series, and a second diode is connected in anti-parallel to the second switch element. A power converter comprising a switch element and a third diode connected in antiparallel.