JP6171490B2 - Manufacturing method of mask for EUV exposure - Google Patents
Manufacturing method of mask for EUV exposure Download PDFInfo
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- JP6171490B2 JP6171490B2 JP2013072948A JP2013072948A JP6171490B2 JP 6171490 B2 JP6171490 B2 JP 6171490B2 JP 2013072948 A JP2013072948 A JP 2013072948A JP 2013072948 A JP2013072948 A JP 2013072948A JP 6171490 B2 JP6171490 B2 JP 6171490B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 2
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 13
- 239000011651 chromium Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 239000000126 substance Substances 0.000 description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 6
- 229910052804 chromium Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 239000002585 base Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000001659 ion-beam spectroscopy Methods 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910021642 ultra pure water Inorganic materials 0.000 description 2
- 239000012498 ultrapure water Substances 0.000 description 2
- NPNMHHNXCILFEF-UHFFFAOYSA-N [F].[Sn]=O Chemical compound [F].[Sn]=O NPNMHHNXCILFEF-UHFFFAOYSA-N 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- CXOWYMLTGOFURZ-UHFFFAOYSA-N azanylidynechromium Chemical compound [Cr]#N CXOWYMLTGOFURZ-UHFFFAOYSA-N 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000985 reflectance spectrum Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
本発明は、半導体製造技術に関し、特に極端紫外線（ＥＵＶ：Ｅｘｔｒｅｍｅ Ｕｌｔｒａ Ｖｉｏｌｅｔ）を使用したリソグラフィで使用するＥＵＶマスクの製造方法に関する。 The present invention relates to a semiconductor manufacturing technique, and more particularly to a method of manufacturing an EUV mask used in lithography using extreme ultraviolet (EUV).
半導体デバイスの製造プロセスにおいては、半導体デバイスの微細化に伴い、フォトリソグラフィ技術の微細化に対する要求が高まっている。既に、リソグラフィの露光も従来の波長が１９３ｎｍのＡｒＦエキシマレーザー光を用いた露光から、波長が１３．５ｎｍのＥＵＶ（Ｅｘｔｒｅｍｅ Ｕｌｔｒａ Ｖｉｏｌｅｔ：極端紫外線）領域の光を用いた露光に置き換わりつつある。 In the manufacturing process of semiconductor devices, with the miniaturization of semiconductor devices, there is an increasing demand for miniaturization of photolithography technology. Already, lithography exposure has been replaced by exposure using light in the EUV (Extreme Ultra Violet) region with a wavelength of 13.5 nm, instead of conventional exposure using ArF excimer laser light with a wavelength of 193 nm.
ＥＵＶ露光用のマスク（ＥＵＶマスク）は、ＥＵＶ領域の光に対してほとんどの物質が高い光吸収性をもつため、従来の透過型のマスクとは異なり、反射型のマスクである（例えば、特許文献１参照）。特許文献１には、ガラス基板上にモリブデン（Ｍｏ）層及びシリコン（Ｓｉ）層を交互に積層して多層膜からなる光反射膜を形成し、その上にタンタル（Ｔａ）を主成分とする光吸収体によりパターンを形成する技術が開示されている。 A mask for EUV exposure (EUV mask) is a reflection type mask unlike conventional transmission type masks because most substances have high light absorption with respect to light in the EUV region (for example, patents). Reference 1). In Patent Document 1, a molybdenum (Mo) layer and a silicon (Si) layer are alternately laminated on a glass substrate to form a light reflecting film composed of a multilayer film, and tantalum (Ta) is the main component thereon. A technique for forming a pattern with a light absorber is disclosed.
また、ＥＵＶ光は前記の通り光の透過を利用する屈折光学系が使用できないことから、露光機の光学系も反射型となる。このため、透過型のビームスプリッターを利用した偏向が不可能である。従って、反射型マスクでは、マスクへの入射光と反射光が同軸上に設計できない欠点がある。このため、ＥＵＶマスクは、６度程度光軸を傾けてマスクへ入射した光の反射光を半導体基板に導く手法が採用されている。この手法では、光軸を傾斜することから、マスクパターンに対する光の入射方向に依存して半導体基板上でマスクの配線パターンがマスクパターンとは異なる線幅となる射影効果と呼ばれる問題がある。 Further, as described above, since an EUV light cannot use a refractive optical system that utilizes the transmission of light, the optical system of the exposure machine is also a reflection type. For this reason, deflection using a transmissive beam splitter is impossible. Therefore, the reflective mask has a drawback that the incident light to the mask and the reflected light cannot be designed on the same axis. For this reason, the EUV mask employs a technique in which the reflected light of the light incident on the mask is guided to the semiconductor substrate by tilting the optical axis by about 6 degrees. In this method, since the optical axis is inclined, there is a problem called a projection effect in which the wiring pattern of the mask on the semiconductor substrate has a line width different from that of the mask pattern depending on the incident direction of light with respect to the mask pattern.
そこで、この射影効果を抑制ないし軽減するためにマスクパターンを形成している吸収膜の膜厚を薄膜化する提案がなされているが、この手法では、ＥＵＶ光を吸収するのに必要な光の減衰量が不足するため、半導体基板への反射光が増加し、半導体基板上に塗布されたレジスト膜を感光させてしまう問題が発生する。また、半導体基板では、チップを多面付で露光するために、隣接するチップにおいてはその境界領域において多重露光が発生する。さらに、ＥＵＶ光源は１３．５ｎｍにその放射スペクトルのピークを有するが、アウトオブバンド（Ｏｕｔ ｏｆ Ｂａｎｄ）と呼ばれる１３．５ｎｍ帯以外の真空紫外線から近赤外線領域の光も放射することが知られている。このアウトオブバンドは本来不必要なものであり、これは半導体ウェハ基板に塗布されたレジストを感光することから、フィルターなどで除去すべき不要な光である。 Therefore, in order to suppress or reduce this projection effect, a proposal has been made to reduce the film thickness of the absorption film forming the mask pattern. However, in this method, light necessary for absorbing EUV light is proposed. Since the amount of attenuation is insufficient, the reflected light to the semiconductor substrate increases, causing a problem of exposing the resist film applied on the semiconductor substrate. Further, in the semiconductor substrate, in order to expose the chips with multiple surfaces, multiple exposure occurs in the boundary region between adjacent chips. Furthermore, although the EUV light source has a peak of its emission spectrum at 13.5 nm, it is known to emit light in the near infrared region from vacuum ultraviolet rays other than the 13.5 nm band called out-of-band. Yes. This out-of-band is unnecessary in nature, and is unnecessary light that should be removed by a filter or the like because the resist applied to the semiconductor wafer substrate is exposed.
また、タンタル（Ｔａ）を用いた光吸収膜は真空紫外線から遠紫外線（Ｄｅｅｐ Ｕｌｔｒａ Ｖｉｏｌｅｔ）領域、近赤外線領域の光も反射することから、上述の通り、隣接したチップの境界領域近傍の半導体配線部分において無視できない光量が積算され、配線パターンの寸法に影響を与える問題が発生する。
この問題に対して、チップ境界の反射光を低減するためにＥＵＶ光の反射に寄与する多層反射膜をパターンを形成する吸収層に引き続きエッチングなどの手段で除去し、母材の石英表面を露出させるマスク構造の提案もある（例えば、特許文献２参照）。しかしながら、アウトオブバンド光は母材の石英を透過してＥＵＶマスクのパターン側とは反対面に形成された窒化クロム（ＣｒＮ）などの裏面導電膜にて反射し、再度石英を透過して半導体基板側に放射し半導体基板に塗布されたレジストを感光する問題が残っている。
Further, since the light absorption film using tantalum (Ta) reflects light in the vacuum ultraviolet to deep ultraviolet (Deep Ultra Violet) region and the near infrared region, as described above, the semiconductor wiring in the vicinity of the boundary region of adjacent chips is used. The amount of light that cannot be ignored in the portion is integrated, causing a problem that affects the dimensions of the wiring pattern.
To reduce the reflected light at the chip boundary, the multilayer reflective film that contributes to the EUV light reflection is removed by means such as etching after the absorbing layer that forms the pattern to expose the quartz surface of the base material. There is also a proposal of a mask structure to be made (see, for example, Patent Document 2). However, the out-of-band light is transmitted through the base material quartz and reflected by the back conductive film such as chromium nitride (CrN) formed on the opposite surface of the EUV mask pattern side, and is transmitted through the quartz again to form the semiconductor. There remains a problem of exposing the resist radiated to the substrate side and applied to the semiconductor substrate.
本発明は、上記課題を解決するためになされたもので、その目的とするところは、射影効果が発生せず、半導体基板で多重露光されるチップの境界領域に相応するマスク領域において、ＥＵＶおよび紫外線領域から近赤外線の反射を低減した構造を有する反射型マスクを提供する事にある。 The present invention has been made to solve the above-described problems. The object of the present invention is to produce EUV and UV in a mask region corresponding to a boundary region of a chip that is not subjected to a projection effect and is subjected to multiple exposure on a semiconductor substrate. An object of the present invention is to provide a reflective mask having a structure in which near-infrared reflection is reduced from the ultraviolet region.
本発明は、かかる課題に鑑みなされたもので、請求項１に記載の発明は、
基板の一方の面上に、ＥＵＶ光を反射する多層反射膜を備えたＥＵＶ露光用マスクの製造方法であって、
基板の一方の面に犠牲膜を形成し、他方の面に透明導電膜を形成してブランクを用意する工程と、ブランクの犠牲膜にレジストを塗布し、所定の回路パターンを描画、現像を行い、犠牲膜をエッチングする工程と、エッチングした犠牲膜をマスクとして基板をエッチングして多層反射膜埋め込み溝を作製する工程と、多層反射膜埋め込み溝にＥＵＶ露光のための多層反射膜を積層する工程と、犠牲膜上に積層された多層反射膜、および犠牲膜を剥離する工程と、を含む事を特徴とするＥＵＶ露光用マスクの製造方法としたものである。
This invention is made | formed in view of this subject, The invention of Claim 1 is
An EUV exposure mask manufacturing method comprising a multilayer reflective film that reflects EUV light on one surface of a substrate,
A sacrificial film is formed on one side of the substrate, a transparent conductive film is formed on the other side, and a blank is prepared. A resist is applied to the blank sacrificial film, and a predetermined circuit pattern is drawn and developed. Etching the sacrificial film, etching the substrate using the etched sacrificial film as a mask, forming a multilayer reflective film embedded groove, and laminating a multilayer reflective film for EUV exposure in the multilayer reflective film embedded groove And a multilayer reflective film laminated on the sacrificial film, and a step of peeling the sacrificial film.
請求項２に記載の発明は、
犠牲膜は、基板とのエッチング選択比が確保できる材料で形成され、透明導電膜は、単
層構造もしくは積層構造で、インジウムと錫の酸化物であるＩＴＯ、酸化錫（ＳｎＯ２）にアンチモン（Ｓｂ）を添加したＡＴＯ、酸化錫（ＳｎＯ２）にフッ素（Ｆ）を添加したＦＴＯ、酸化亜鉛（ＺｎＯ）にアルミナ（Ａｌ２Ｏ３）を添加したＡＺＯ、酸化亜鉛（ＺｎＯ）に酸化ガリウム（Ｇａ２Ｏ３）を添加したＧＺＯの、いずれかを含む材料で形成されることを特徴とする請求項１に記載のＥＵＶ露光用マスクの製造方法としたものである。
The invention described in claim 2
The sacrificial film is formed of a material that can ensure an etching selectivity with respect to the substrate, and the transparent conductive film has a single-layer structure or a stacked structure, which is ITO, which is an oxide of indium and tin, tin oxide (SnO 2 ), antimony ( ATO with Sb) added, FTO with tin (SnO 2 ) added with fluorine (F), AZO with zinc oxide (ZnO) added with alumina (Al 2 O 3 ), and zinc oxide (ZnO) with gallium oxide ( 2. The method for producing an EUV exposure mask according to claim 1 , wherein the mask is formed of a material containing any one of GZO added with Ga 2 O 3 ).
本発明によれば、射影効果の影響を抑制する事で、ウェハ露光パターンの位置ずれや歪みを低減させる事が可能となると共に、露光パターン以外の領域からのＥＵＶおよびＤＵＶの反射を抑制する事を特徴とするＥＵＶ用反射型マスクの製造方法を提供する。 According to the present invention, it is possible to reduce the positional deviation and distortion of the wafer exposure pattern by suppressing the influence of the projection effect, and to suppress the reflection of EUV and DUV from regions other than the exposure pattern. The manufacturing method of the reflective mask for EUV characterized by these is provided.
以下、図面を参照しつつ、本発明の実施形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
本発明では、膜として記載しているが、膜を層としても良い。 In the present invention, the film is described as a film, but the film may be a layer.
先ず、本発明の第1の実施の形態例について図１および図２を参照して説明する。図1は反射型マスク用ブランクス１０の断面図であり、図２は反射型マスク１００であって、図２（ａ）はそのマスク１００の平面図、図２（ｂ）はそのマスク１００の断面図である。 First, a first embodiment of the present invention will be described with reference to FIG. 1 and FIG. 1 is a cross-sectional view of a reflective mask blank 10, FIG. 2 is a reflective mask 100, FIG. 2A is a plan view of the mask 100, and FIG. 2B is a cross-section of the mask 100. FIG.
図２（ａ）、（ｂ）に示すように、回路パターンＡは多層反射膜１２が基板１１に埋め込まれた構造をしており、回路パターンＡを有する面と反対の面は透明な裏面導電膜１３を有する。 As shown in FIGS. 2A and 2B, the circuit pattern A has a structure in which the multilayer reflective film 12 is embedded in the substrate 11, and the surface opposite to the surface having the circuit pattern A is a transparent back surface conductive. A film 13 is provided.
次に本マスクの製造方法を図３乃至図６に示す。ここで、図３は工程Ｓ１〜Ｓ１４のステップを示し、図４乃至図６は各工程Ｓ１〜Ｓ１４での加工状態の断面図を示す。 Next, the manufacturing method of this mask is shown in FIGS. Here, FIG. 3 shows the steps of steps S1 to S14, and FIGS. 4 to 6 show cross-sectional views of the processed states in steps S1 to S14.
まず反射型マスク用ブランクス１０を用意する（図３、図４の「開始」工程）。露光するＥＵＶ光の波長は、例えば１３．５ｎｍである。基板１１は石英基板であり、６インチ角で厚さは６．３５ｍｍとする。反射型マスク１００の回路パターンＡを形成する面に犠牲膜１４を形成する。犠牲膜１４には基板１１とのエッチング選択比が十分に確保できる材料を選択する必要がある。ここでは例として、クロム（Ｃｒ）をイオンビームスパッタリング装置で５から１００ｎｍの厚みで形成する。また、回路パターンＡを形成する面と反対の面上に透明な裏面導電膜１３として酸化インジウム（ＩＴＯ）をマグネトロンスパッタにより１００ｎｍ積層して形成する。
First, the
なお、犠牲膜は、クロムのように、基板とのエッチング選択比が確保できる材料で形成する。また透明導電膜は、単層構造もしくは積層構造で、インジウムと錫の酸化物であるＩＴＯ、酸化錫（ＳｎＯ２）にアンチモン（Ｓｂ）を添加したＡＴＯ、酸化錫（ＳｎＯ２）にフッ素（Ｆ）を添加したＦＴＯ、酸化亜鉛（ＺｎＯ）にアルミナ（Ａｌ２Ｏ３）を添加したＡＺＯ、酸化亜鉛（ＺｎＯ）に酸化ガリウム（Ｇａ２Ｏ３）を添加したＧＺＯの、いずれかを含む材料で形成するとよい。 Note that the sacrificial film is formed of a material that can ensure an etching selectivity with the substrate, such as chromium. The transparent conductive film, a single-layer structure or a stacked structure, ITO is indium tin oxide, ATO added with antimony (Sb) to tin oxide (SnO 2), fluorine tin oxide (SnO 2) (F ) Added with FTO, zinc oxide (ZnO) with alumina (Al 2 O 3 ) added, zinc oxide (ZnO) with gallium oxide (Ga 2 O 3 ) added with ZZO It is good to form.
次に回路パターンＡとなる多層反射膜を埋め込むための多層反射膜埋め込み溝のガイドを犠牲膜１４に形成する。つまり、電子線に反応を示す化学増幅系や非化学増幅系レジスト２１を犠牲膜１４上に塗布（工程Ｓ１、以下同様に図３乃至図６に記した工程を表す）し、所定の回路パターンＡを電子線描画装置により描画する（Ｓ２）。その後アルカリ溶
液などで現像（Ｓ３）を行い、これにより形成したレジスト２１のパターンをマスクにしてフッ素系ガスや塩素系ガスを用いたガスプラズマにより犠牲膜１４をエッチング（Ｓ４）する。ここでは犠牲膜１４はクロム（Ｃｒ）であるため、塩素系プラズマによりエッチングを行い、不要なレジスト２１のパターンを酸素プラズマによる灰化や硫酸やオゾン水などの酸化薬液による分解ないし有機溶剤などで溶解除去（Ｓ５）する。その後必要に応じて、酸・アルカリ系薬品やオゾンガスや水素ガスなどを溶解した超純水や有機アルカリ系薬品、界面活性剤などによる洗浄処理（Ｓ６）と、遠心力を利用したスピン乾燥（Ｓ７）を行う。
Next, a guide for the multilayer reflective film embedding groove for embedding the multilayer reflective film to be the circuit pattern A is formed in the sacrificial film 14. That is, a chemical amplification system or non-chemical amplification system resist 21 that reacts with an electron beam is applied on the sacrificial film 14 (step S1, hereinafter, the steps described in FIGS. 3 to 6), and a predetermined circuit pattern is formed. A is drawn by an electron beam drawing apparatus (S2). Thereafter, development (S3) is performed with an alkaline solution or the like, and the sacrificial film 14 is etched (S4) by gas plasma using a fluorine-based gas or a chlorine-based gas using the pattern of the resist 21 formed thereby as a mask. Here, since the sacrificial film 14 is chromium (Cr), etching is performed with chlorine-based plasma, and an unnecessary resist 21 pattern is decomposed by ashing with oxygen plasma, decomposition with an oxidizing chemical such as sulfuric acid or ozone water, or an organic solvent. Dissolve and remove (S5). Thereafter, if necessary, cleaning with acid / alkaline chemicals, ultrapure water in which ozone gas or hydrogen gas is dissolved, organic alkaline chemicals, surfactants, etc. (S6), and spin drying using centrifugal force (S7) )I do.
以上の工程により回路パターンＡが犠牲膜に形成され、新たなマスクとなる。 Through the above steps, the circuit pattern A is formed on the sacrificial film and becomes a new mask.
次に回路パターンＡに多層反射膜１２を埋め込む方法を例示する。まず回路パターンＡを、犠牲膜１４をエッチングマスクとして基板１１をエッチングして多層反射膜埋め込み溝を作成（Ｓ８）する。ここで、多層反射膜埋め込み溝の深さは、埋め込む多層反射膜１２の厚みと等しくなるようにエッチングを行う。エッチング後に、埋め込み溝の内部に多層反射膜が適切に付着・積層される様に、ＳＣ−１洗浄，加熱乾燥など適宜方法にて洗浄、乾燥を行う（Ｓ９、１０）。次にＥＵＶ露光のための多層反射膜１２を作製する。モリブデン（Ｍｏ）を４．２ｎｍ、珪素（Ｓｉ）を２．８ｎｍを交互にイオンビームスパッタリング装置で交互に４０対、合計８０対を最上層が珪素（Ｓｉ）となるように積層する（Ｓ１１）。次に犠牲膜１４上に積層された多層反射膜１２、および犠牲膜１４をＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）装置により表面研磨することで剥離（Ｓ１２）する。その後必要に応じて、酸・アルカリ系薬品やオゾンガスや水素ガスなどを溶解した超純水や有機アルカリ系薬品、界面活性剤などによる洗浄処理（Ｓ１３）と、遠心力を利用したスピン乾燥（Ｓ１４）を行う。 Next, a method of embedding the multilayer reflective film 12 in the circuit pattern A is exemplified. First, the substrate 11 is etched using the circuit pattern A and the sacrificial film 14 as an etching mask to form a multilayer reflective film embedded groove (S8). Here, etching is performed so that the depth of the multilayer reflective film embedding groove is equal to the thickness of the multilayer reflective film 12 to be embedded. After the etching, cleaning and drying are performed by an appropriate method such as SC-1 cleaning or heat drying so that the multilayer reflective film is appropriately attached and laminated inside the buried trench (S9, 10). Next, the multilayer reflective film 12 for EUV exposure is produced. Molybdenum (Mo) of 4.2 nm and silicon (Si) of 2.8 nm are alternately laminated by an ion beam sputtering apparatus so that a total of 80 pairs are formed so that the uppermost layer is silicon (Si) (S11). . Next, the multilayer reflective film 12 laminated on the sacrificial film 14 and the sacrificial film 14 are peeled off (S12) by surface polishing using a CMP (Chemical Mechanical Polishing) apparatus. Thereafter, if necessary, cleaning treatment with acid / alkali chemical, ozone gas, hydrogen gas, etc., ultrapure water, organic alkaline chemical, surfactant, etc. (S13), and spin drying using centrifugal force (S14) )I do.
以上の工程により反射型マスク１００が完成する。 The reflective mask 100 is completed through the above steps.
本マスク構造においては、多層反射膜１２を埋め込んだ回路パターンＡ以外の領域は基板１１が最表面となった状態になっている。通常のＥＵＶ露光用マスクにおいては、裏面導電膜１３としてクロム（Ｃｒ）が使用されるのが一般的である。この場合、ＥＵＶ光は基板１１により吸収されるが、アウトオブバンド光に関しては、基板１１を一旦透過して裏面導電膜１３から反射して再度戻ってくる成分を除去できない。そこで、本発明においては、裏面導電膜材料として透明導電膜を使用する。 In this mask structure, the region other than the circuit pattern A in which the multilayer reflective film 12 is embedded is in a state where the substrate 11 is the outermost surface. In a normal EUV exposure mask, chromium (Cr) is generally used as the back surface conductive film 13. In this case, EUV light is absorbed by the substrate 11, but regarding the out-of-band light, the component that once passes through the substrate 11, reflects from the back surface conductive film 13, and returns again cannot be removed. Therefore, in the present invention, a transparent conductive film is used as the back surface conductive film material.
図７に従来の裏面導電膜材料の一例としてクロム（Ｃｒ）と本発明にかかるＩＴＯによる反射率スペクトルを示す。反射光とは主面側から入射し、基板１１を透過して裏面導電膜１３を反射して再度基板１１を透過して主面から射出した光である。測定には反射率計を用いた。測定の結果、波長２５０ｎｍから８５０ｎｍの範囲において、従来のクロム（Ｃｒ）に対して本発明のＩＴＯは平均で反射率は４２．１％から１３．５％に低減した。またＩＴＯのシート抵抗は９０オーム／□であった。 FIG. 7 shows a reflectance spectrum of chromium (Cr) as an example of a conventional back surface conductive film material and ITO according to the present invention. The reflected light is light incident from the main surface side, transmitted through the substrate 11, reflected from the back surface conductive film 13, transmitted through the substrate 11 again, and emitted from the main surface. A reflectometer was used for the measurement. As a result of the measurement, the average reflectance of the ITO of the present invention was reduced from 42.1% to 13.5% with respect to the conventional chromium (Cr) in the wavelength range of 250 nm to 850 nm. The sheet resistance of ITO was 90 ohm / □.
本発明により作製されるマスクは、以上のような構成であるので、従来のＥＵＶマスクのような吸収膜を有さない事により吸収膜による射影効果が発生しないため、ウェハ露光による露光パターンの位置ずれや歪みといった問題を低減する。さらに、裏面導電膜の導電性を確保しつつ多層反射膜以外の領域から生じるアウトオブバンド光がウェハ基板側に導かれず、ウェハ基板上に塗布されたレジストの感光を避ける事が可能となった。 Since the mask manufactured according to the present invention has the above-described configuration, the projection effect by the absorption film does not occur due to the absence of the absorption film as in the conventional EUV mask. Reduce problems such as misalignment and distortion. Furthermore, out-of-band light generated from a region other than the multilayer reflective film is not guided to the wafer substrate side while ensuring the conductivity of the back surface conductive film, and it is possible to avoid the resist of the resist applied on the wafer substrate. .
本発明は前記実施形態そのままに限定されるものでなく、本発明の趣旨を逸脱しない限り、変形して具体化できる。また、明細書に示される事項の適宜の組み合わせによって種々の発明を想定できるものである。 The present invention is not limited to the above-described embodiment as it is, and can be modified and embodied without departing from the gist of the present invention. Various inventions can be envisaged by appropriately combining the matters shown in the specification.
１０ 反射型マスク用ブランクス
１１ 基板
１２ 多層反射膜
１３ 裏面導電膜
１４ 犠牲膜
２１ レジスト（パターン）
１００ 反射型マスクブランク
DESCRIPTION OF
100 reflective mask blank
Claims (2)
基板の一方の面に犠牲膜を形成し、他方の面に透明導電膜を形成してブランクを用意する工程と、ブランクの犠牲膜にレジストを塗布し、所定の回路パターンを描画、現像を行い、犠牲膜をエッチングする工程と、エッチングした犠牲膜をマスクとして基板をエッチングして多層反射膜埋め込み溝を作製する工程と、多層反射膜埋め込み溝にＥＵＶ露光のための多層反射膜を積層する工程と、犠牲膜上に積層された多層反射膜、および犠牲膜を剥離する工程と、を含む事を特徴とするＥＵＶ露光用マスクの製造方法。 An EUV exposure mask manufacturing method comprising a multilayer reflective film that reflects EUV light on one surface of a substrate,
A sacrificial film is formed on one side of the substrate, a transparent conductive film is formed on the other side, and a blank is prepared. A resist is applied to the blank sacrificial film, and a predetermined circuit pattern is drawn and developed. Etching the sacrificial film, etching the substrate using the etched sacrificial film as a mask, forming a multilayer reflective film embedded groove, and laminating a multilayer reflective film for EUV exposure in the multilayer reflective film embedded groove And a multilayer reflective film stacked on the sacrificial film, and a step of peeling the sacrificial film.
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| SG11201906153SA (en) | 2017-01-17 | 2019-08-27 | Hoya Corp | Reflective mask blank, reflective mask, method of manufacturing same, and method of manufacturing semiconductor device |
| US11340524B2 (en) * | 2019-04-01 | 2022-05-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Photomask, method of fabricating a photomask, and method of fabricating a semiconductor structure using a photomask |
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