JP6162822B2 - 非対称メモリスタ - Google Patents
非対称メモリスタ Download PDFInfo
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- JP6162822B2 JP6162822B2 JP2015551996A JP2015551996A JP6162822B2 JP 6162822 B2 JP6162822 B2 JP 6162822B2 JP 2015551996 A JP2015551996 A JP 2015551996A JP 2015551996 A JP2015551996 A JP 2015551996A JP 6162822 B2 JP6162822 B2 JP 6162822B2
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of switching materials after formation, e.g. doping
- H10N70/043—Modification of switching materials after formation, e.g. doping by implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/52—Structure characterized by the electrode material, shape, etc.
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- Computational Linguistics (AREA)
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Description
分布を得るように構成されている。
(例えば、第1の電極102に隣接する領域などの、メモリスタ層106の第1の領域内の)を示し、第2の矢印110は、
(例えば、第2の電極104に隣接する領域などの、第1の領域とは異なるメモリスタ層106の第2の領域内の)を示し、それは
とは異なっていることに留意されたい。
分布を得るために、第1の電極102の領域は、第2の電極104の領域より少なくとも1.5(または2、3、5、10、20、50、もしくは100)倍大きくすることができる。
Claims (8)
- 第1の電極(102)、第2の電極(104)、及び前記第1の電極(102)と前記第2の電極(104)との間に配置されたメモリスタ層(106)を備え、前記メモリスタ層(106)における非対称な電流密度の分布を得るように構成されているメモリスタ(100)と、
電界効果トランジスタ(302)と、を備え、
前記メモリスタ(100)は前記電界効果トランジスタ(302)のゲート(304)に接続されており、
前記メモリスタ層(106)は、前記メモリスタ層(106)の前記非対称電流密度分布を得るために、非対称ドーピング濃度分布または非対称トラップ密度分布を含み、
前記電流密度は前記メモリスタ層(106)内の等電位線(112)に沿って変化し、または前記メモリスタ層(106)内の前記電流密度は、前記第1の電極(102)から前記第2の電極(104)までの電流経路(116)に沿って非対称である、人工トリパータイトシナプス(300)。 - 前記メモリスタ層(106)の導電性の断面積(114)は、前記第1の電極(102)から前記第2の電極(104)までの電流経路(116)に沿って変化する請求項1に記載の人工トリパータイトシナプス(300)。
- 前記第1の電極(102)の領域は、前記メモリスタ層(106)の前記非対称な電流密度の分布を得るために、前記第2の電極(104)の領域より少なくとも1.5倍大きい請求項1又は2に記載の人工トリパータイトシナプス(300)。
- 前記第1の電極(102)に接触する前記メモリスタ層(106)の領域は、前記メモリスタ層(106)の前記非対称な電流密度の分布を得るために、前記第2の電極(104)に接触する前記メモリスタ層(106)の領域より少なくとも1.5倍大きい請求項1から3のいずれか1項に記載の人工トリパータイトシナプス(300)。
- 前記メモリスタ層(106)はTiO2を含む請求項1から4のいずれか1項に記載の人工トリパータイトシナプス(300)。
- 前記第1の電極(102)および/または前記第2の電極(104)はTiを含む請求項1から5のいずれか1項に記載の人工トリパータイトシナプス(300)。
- 請求項1から6のいずれか1項に記載の人工トリパータイトシナプス(300)を備えたニューラルネットワーク(118)。
- 第1のニューロン(120)と、
第2のニューロン(122)と、をさらに備え、
前記人工トリパータイトシナプス(300)は前記第1のニューロン(120)と前記第2のニューロン(122)との間に直列に接続されている請求項7に記載のニューラルネットワーク(118)。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2013/050598 WO2014108215A1 (en) | 2013-01-14 | 2013-01-14 | Asymmetrical memristor |
Publications (2)
Publication Number | Publication Date |
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JP2016510501A JP2016510501A (ja) | 2016-04-07 |
JP6162822B2 true JP6162822B2 (ja) | 2017-07-12 |
Family
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Family Applications (1)
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JP2015551996A Active JP6162822B2 (ja) | 2013-01-14 | 2013-01-14 | 非対称メモリスタ |
Country Status (5)
Country | Link |
---|---|
US (1) | US9704093B2 (ja) |
EP (1) | EP2943958B1 (ja) |
JP (1) | JP6162822B2 (ja) |
HK (1) | HK1216801A1 (ja) |
WO (1) | WO2014108215A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11320588B1 (en) * | 2012-04-16 | 2022-05-03 | Mohammad A. Mazed | Super system on chip |
US9755146B2 (en) | 2015-09-10 | 2017-09-05 | ARM, Ltd. | Asymmetric correlated electron switch operation |
US9824753B2 (en) * | 2015-10-21 | 2017-11-21 | Technische Universiteit Delft | Computing device for “big data” applications using memristors |
WO2018094717A1 (zh) * | 2016-11-28 | 2018-05-31 | 华为技术有限公司 | 基于脉冲神经网络的信号处理方法和装置 |
US11276820B2 (en) | 2017-10-19 | 2022-03-15 | Ryukoku University | Memristor and neural network using same |
CN110546778A (zh) * | 2018-03-16 | 2019-12-06 | 深圳市汇顶科技股份有限公司 | 忆阻器的制造方法、忆阻器和阻变式随机存取存储器rram |
US10586922B1 (en) | 2018-08-21 | 2020-03-10 | International Business Machines Corporation | Symmetric tunable PCM resistor for artificial intelligence circuits |
CN109460818A (zh) * | 2018-09-25 | 2019-03-12 | 电子科技大学 | 一种基于忆阻桥和阵列的多层神经网络设计方法 |
CN110110840B (zh) * | 2019-04-22 | 2020-11-27 | 中国地质大学(武汉) | 一种基于忆阻神经网络的联想记忆情感识别电路 |
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US6927074B2 (en) * | 2003-05-21 | 2005-08-09 | Sharp Laboratories Of America, Inc. | Asymmetric memory cell |
US20090206375A1 (en) * | 2008-02-19 | 2009-08-20 | Saha Samar K | Reduced Leakage Current Field-Effect Transistor Having Asymmetric Doping And Fabrication Method Therefor |
WO2009113993A1 (en) * | 2008-03-14 | 2009-09-17 | Hewlett-Packard Development Company, L.P. | Neuromorphic circuit |
US7846807B2 (en) * | 2008-06-19 | 2010-12-07 | Hermes-Epitek Corp. | Method for forming memristor material and electrode structure with memristance |
US8097870B2 (en) * | 2008-11-05 | 2012-01-17 | Seagate Technology Llc | Memory cell with alignment structure |
CN102265397B (zh) * | 2008-12-23 | 2014-10-29 | 惠普开发有限公司 | 忆阻设备以及制造和使用所述忆阻设备的方法 |
WO2010085225A1 (en) * | 2009-01-26 | 2010-07-29 | Hewlett-Packard Development Company, L.P. | Controlled placement of dopants in memristor active regions |
WO2010151247A1 (en) * | 2009-06-22 | 2010-12-29 | Hewlett-Packard Development Company, L.P. | Memristive adaptive resonance networks |
US9171613B2 (en) * | 2009-07-28 | 2015-10-27 | Hewlett-Packard Development Company, L.P. | Memristors with asymmetric electrodes |
US8275728B2 (en) * | 2009-11-05 | 2012-09-25 | The United States Of America As Represented By The Secretary Of The Air Force | Neuromorphic computer |
US8120071B2 (en) * | 2010-01-11 | 2012-02-21 | Hewlett-Packard Development Company, L.P. | Memfet ram |
US8111494B2 (en) * | 2010-01-28 | 2012-02-07 | Hewlett-Packard Development Company, L.P. | Memristor-protection integrated circuit and method for protection of a memristor during switching |
DE102010000565A1 (de) | 2010-02-26 | 2011-09-01 | Technische Universität Ilmenau | Hybrides dreidimensionales Sensorarray, insbesondere zur Vermessung elektrogener Zellanordnungen, sowie Messanordnung |
US8433665B2 (en) * | 2010-07-07 | 2013-04-30 | Qualcomm Incorporated | Methods and systems for three-memristor synapse with STDP and dopamine signaling |
US8274813B2 (en) * | 2010-07-16 | 2012-09-25 | Hewlett-Packard Development Company, L.P. | Memristive negative differential resistance device |
FR2977350B1 (fr) * | 2011-06-30 | 2013-07-19 | Commissariat Energie Atomique | Reseau de neurones artificiels a base de dispositifs memristifs complementaires |
WO2013015768A1 (en) * | 2011-07-22 | 2013-01-31 | Hewlett-Packard Development Company, L.P. | Circuit and method for reading a resistive switching device in an array |
WO2013015803A1 (en) * | 2011-07-27 | 2013-01-31 | Hewlett-Packard Development Company, L.P. | Method and system for reducing write-buffer capacities within memristor-based data-storage devices |
KR102157265B1 (ko) * | 2012-10-19 | 2020-09-17 | 조지아 테크 리서치 코오포레이션 | 탄소 나노튜브들의 정렬된 어레이들 상에 형성된 다중층 코팅들 |
-
2013
- 2013-01-14 EP EP13701230.8A patent/EP2943958B1/en active Active
- 2013-01-14 JP JP2015551996A patent/JP6162822B2/ja active Active
- 2013-01-14 WO PCT/EP2013/050598 patent/WO2014108215A1/en active Application Filing
-
2015
- 2015-07-14 US US14/799,488 patent/US9704093B2/en active Active
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2016
- 2016-04-21 HK HK16104596.2A patent/HK1216801A1/zh unknown
Also Published As
Publication number | Publication date |
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JP2016510501A (ja) | 2016-04-07 |
EP2943958B1 (en) | 2019-05-22 |
US9704093B2 (en) | 2017-07-11 |
EP2943958A1 (en) | 2015-11-18 |
HK1216801A1 (zh) | 2016-12-02 |
US20160019453A1 (en) | 2016-01-21 |
WO2014108215A1 (en) | 2014-07-17 |
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