JP6160318B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, a method of manufacturing a semiconductor device in which a semiconductor layer is deposited on the substrate.

  For example, a semiconductor layer may be formed on a substrate, and the semiconductor layer may be an optical waveguide. In such a case, the semiconductor layer has an elongated structure. In an optical waveguide, the film thickness may be modulated to collect or disperse the light. For example, Patent Document 1 discloses that an undercut shadow mask is used to form a semiconductor layer whose thickness is modulated on a substrate. The semiconductor layer is used as an optical waveguide.

Japanese Patent Laid-Open No. 10-135563

  In the method of Patent Document 1, the film thickness is modulated in the width direction of the semiconductor layer serving as a waveguide. However, it is difficult to form a semiconductor layer whose film thickness is modulated in the longitudinal direction of the waveguide with high film quality and accuracy.

  The present invention has been made in view of the above problems, and an object of the present invention is to form a semiconductor layer whose film thickness is modulated in the longitudinal direction with good film quality and size.

  The present invention includes a step of forming a first layer and a second layer in order from the bottom on a substrate including a first region, a second region, a third region, and a fourth region, and the first layer and the second layer. A step of forming a mask after the step of forming a semiconductor layer, and a step of forming a semiconductor layer in the first region and the fourth region on the substrate using the mask. The forming step includes a step of removing the first layer by leaving the second layer in the first region, the width of which is modulated from one end to the other end in the longitudinal direction, and a lateral direction of the first region. The step of leaving the first layer and the second layer in the second region provided on both sides and separated from the first region, and the third region connecting the first region and the second region In the step, the second layer is left and the first layer is removed. And removing the first layer and the second layer in the fourth region other than the third region between the first region and the second region. It is a manufacturing method of an apparatus. According to the present invention, a semiconductor layer whose film thickness is modulated in the longitudinal direction can be formed with high film quality and dimensional accuracy.

  In the above configuration, the step of forming the mask includes the step of removing the second layer in the fourth region so that the second layer in the first region, the second region, and the third region remains. Removing the first layer of the first region, the third region, and the fourth region using the second layer remaining in the first region, the second region, and the third region as a mask, and It can be set as the structure containing.

  The said structure WHEREIN: The said 1st layer and the said 2nd layer can be set as the structure which is a semiconductor.

  The said structure WHEREIN: The space | interval of the said 1st area | region and the said 2nd area | region can be set as the structure which is 18 micrometers or more and 100 micrometers or less.

  The said structure WHEREIN: The film thickness of a said 2nd layer can be set as the structure which is 3 micrometers or more and 8 micrometers or less.

  The said structure WHEREIN: The said 3rd area | region can be set as the structure formed symmetrically with respect to the longitudinal axis of the said 1st area | region.

  In the above structure, the first layer is made of GaInAs, and the step of forming the mask is performed after the step of removing the second layer and before the step of removing the first layer. The method may include a step of forming an insulating film on the second layer.

  The said structure WHEREIN: The said 2nd layer of the said 1st area | region can be set as the structure thinner than the said 2nd layer of the said 3rd area | region.

  The present invention includes a substrate, and a semiconductor layer including a buffer layer, a core layer, and a cap layer that are sequentially formed on the substrate from the lower side, and the semiconductor layer extends from one end to the other end in the longitudinal direction. The semiconductor device is characterized in that the film thickness is modulated, and the film thickness in the short direction of the semiconductor layer is thinner at the center than at the end.

  The present invention includes a substrate, and a semiconductor layer including a buffer layer, a core layer including AlGaInAs or AlInAs, and a cap layer, which are sequentially formed on the substrate from the lower side. The semiconductor device is characterized in that the film thickness is modulated from one end to the other end.

  According to the present invention, a semiconductor layer whose film thickness is modulated in the longitudinal direction can be formed with high film quality and accuracy.

FIG. 1A is a plan view showing a semiconductor layer on a substrate, and FIG. 1B is a cross-sectional view taken along line AA of FIG. FIG. 2 is a cross-sectional view when the semiconductor layer in Comparative Example 1 is formed. FIG. 3 is a cross-sectional view when a semiconductor layer is formed in Comparative Example 2. FIG. 4 is a cross-sectional view when the semiconductor layer in Comparative Example 3 is formed. FIG. 5A is a plan view when the semiconductor layer is formed in Example 1, and FIG. 5B is a diagram showing the thickness T1 of the semiconductor layer with respect to the position X along DD. FIG. 6A to FIG. 6C are an AA sectional view, a BB sectional view, and a CC sectional view, respectively, of FIG. 5A. FIG. 7 is a cross-sectional view showing a semiconductor layer formed on a substrate. FIG. 8 is a diagram showing the normalized film thickness with respect to the width W0 of the shield in Comparative Example 1. FIG. 9A and FIG. 9B are schematic views showing surface photographs of Comparative Example 1 and Example 1. FIG. FIG. 10 is a plan view of the mask. FIG. 11 is a diagram illustrating the normalized film thickness with respect to the width W1 of the shield in the first embodiment. FIG. 12 is a diagram showing the presence or absence of a cross hatch with respect to the width of the shield and the interval between the supports. FIGS. 13A to 13C are diagrams showing the presence or absence of sagging of the shield with respect to the width and length of the beam. FIG. 14A is a plan view of an example of the mask, and FIG. 14B is a diagram showing the thickness of the semiconductor layer with respect to x. FIG. 15A is a plan view of another example of the mask, and FIG. 15B is a diagram showing the thickness of the semiconductor layer with respect to x. FIG. 16 is a block diagram of a system in which the semiconductor device according to the second embodiment is used. FIG. 17A to FIG. 17C are views (No. 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 18A to FIG. 18C are views (No. 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 19A to FIG. 19C are views (No. 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 20A to FIG. 20C are views (No. 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 21A to FIG. 21C are views (No. 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 22A to FIG. 22C are views (No. 6) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 23A to FIG. 23C are views (No. 7) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 24A to FIG. 24C are views (No. 8) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 25A to FIG. 21E are views (No. 9) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 26A to FIG. 26C are views (No. 10) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 27A to 27C are views (No. 11) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 28A to FIG. 28C are views (No. 12) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 29A to FIG. 29C are views (No. 13) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 30A to 30C are views (No. 14) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 31A to FIG. 31D are views (No. 15) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 32A to FIG. 32C are views (No. 16) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 33A to 33C are cross-sectional views when the semiconductor layer of Example 3 is formed. FIG. 34 is a plan view of the mask after etching the first layer. FIG. 35 is a plan view of the mask after etching the first layer. FIG. 36A to FIG. 36G are cross-sectional views illustrating the mask manufacturing method according to the fourth embodiment. FIG. 37A and FIG. 37B are views (No. 1) illustrating the mask manufacturing method according to the fourth embodiment. FIG. 38A and FIG. 38B are views (No. 2) illustrating the mask manufacturing method according to the fourth embodiment. FIG. 39 is a plan view showing the relationship between the second layer and the insulating film. FIG. 40A to FIG. 40E are views (No. 1) showing the manufacturing method of the fifth embodiment. FIG. 41A to FIG. 41E are views (No. 2) showing the manufacturing method of the fifth embodiment.

  FIG. 1A is a plan view showing a semiconductor layer on a substrate, and FIG. 1B is a cross-sectional view taken along line AA of FIG. A direction (longitudinal direction) in which the semiconductor layer 12 extends is defined as an X direction, a width direction (short direction) is defined as a Y direction, and a normal line of the substrate 10 is defined as a Z direction. The same applies to the following drawings.

  With reference to FIGS. 1A and 1B, a semiconductor layer 12 is formed on a substrate 10. The semiconductor layer 12 has an elongated shape. The thickness of the semiconductor layer 12 is modulated in the X direction. For example, the semiconductor layer 12 becomes thicker in the + X direction.

A comparative example for modulating the film thickness will be described. FIG. 2 is a cross-sectional view when the semiconductor layer in Comparative Example 1 is formed. A mask 80 composed of a first layer 82 and a second layer 84 is provided on the substrate 10. An opening 81 is formed in the first layer 82. In the second layer 84, an opening 83 having a width W0 is formed. The opening 81 of the first layer 82 is wider than the opening 83 of the second layer 84. Thereby, the second layer 84 on the opening 81 has a bowl shape. The semiconductor layer 12 is formed on the substrate 10 using the mask 80. As a film forming method, for example, MOVPE (Metal
Organic Vapor Phase Epitaxy) method is used. AlGaInAs will be described as an example of the semiconductor layer 12.

  When the semiconductor layer 12 is formed, a film 86 having the same composition as the semiconductor layer 12 is formed on the mask 80. A film 86 to be deposited on the width W 0 of the opening 83 is formed on the substrate 10 in the opening 81. If the semiconductor layer 12 is formed linearly from the opening 83, the semiconductor layer 12 has a cross-sectional shape like the virtual film 70. However, the source gas diffuses in the ± Y direction as indicated by arrows 72 and 74. For this reason, the semiconductor layer 12 is thinner than the virtual film 70. For example, the film thickness of the semiconductor layer 12 can be modulated by modulating the width W0.

  However, the diffusion rate of the group III raw material is higher for Al and Ga than for In. Arrows 72 correspond to Al and Ga source gases, and arrows 74 correspond to In source gases. Therefore, the composition of the semiconductor layer 12 differs from the target at both ends of the semiconductor layer 12 in the Y direction. Thereby, a cross hatch may occur in the semiconductor layer 12. Thus, in Comparative Example 1, the film quality cannot be made uniform.

  For example, trimethylaluminum (TMA) or triethylaluminum (TEA) can be used as the Al source gas. For example, trimethylgallium (TMG) or triethylgallium (TEG) can be used as the Ga source gas. As the In source gas, for example, trimethylindium (TMI) or triethylindium (TEI) can be used.

  FIG. 3 is a cross-sectional view when a semiconductor layer is formed in Comparative Example 2. A mask 80 is disposed apart from the substrate 10. The distance between the mask 80 and the substrate 10 is, for example, 50 μm or more. Since the source gas flows under the mask 80 as indicated by arrows 72 and 74, the semiconductor layer 12 can be formed on the substrate 10 under the mask 80. The film thickness of the semiconductor layer 12 under the mask 80 is smaller than that of the virtual film 70. By modulating the width of the mask 80 in the X direction, the film thickness of the semiconductor layer 12 can be modulated in the X direction. Further, since the source gas is supplied from both sides of the mask 80, the film quality becomes uniform as compared with the first comparative example.

  However, in order to modulate the film thickness in the longitudinal direction of the semiconductor layer 12, the width of the mask 80 in the X direction is increased and the distance between the mask 80 and the substrate 10 is increased. This deteriorates the accuracy of film thickness modulation.

  FIG. 4 is a cross-sectional view when the semiconductor layer in Comparative Example 3 is formed. A plurality of slits 88 are formed in the mask 80. The slit width W9 becomes narrower in the −X direction. The slit 88 is not formed on the −X side from the position 89. Under the mask 80 between the slits 88, the source gas is supplied from the slits 88 on both sides, and the semiconductor layer 12 is formed. By modulating the width W9 of the slit 88 in the X direction, the film thickness of the semiconductor layer 12 can be modulated. For example, the film thickness can be reduced as it goes in the -X direction.

  However, on the −X side from the position 89, the source gas is supplied only from one direction as indicated by arrows 72 and 74. As a result, the film quality of the semiconductor layer 12 varies due to the diffusion rate of the source gas.

  As in Comparative Examples 1 to 3, it is difficult to accurately form the semiconductor layer 12 whose film thickness is modulated in the longitudinal direction with good film quality (for example, without forming a cross hatch).

  FIG. 5A is a plan view when the semiconductor layer of Example 1 is formed, and FIG. 5B is a diagram showing the thickness T1 of the semiconductor layer with respect to the position X along DD. FIG. 6A to FIG. 6C are an AA sectional view, a BB sectional view, and a CC sectional view, respectively, of FIG. 5A. With reference to FIG. 5A to FIG. 6C, the mask 80 has a first layer 14 formed on the substrate 10 and a second layer 16 formed on the first layer 14. .

  The first region 50 extending in the X direction has a width W1 modulated in the short direction. The width W1 is substantially constant in the −X direction from the position X0. The width W1 is uniformly reduced in the + X direction from the position X0. A second region 52 is provided on both sides of the first region 50 in the width direction (± Y direction). The third region 54 connects the first region 50 and the second region 52. The second layer 16 in the first region 50 becomes the shield 60. The first layer 14 and the second layer 16 in the second region 52 serve as a support body 62 that supports the shield body 60 on the substrate 10. The second layer 16 in the third region 54 becomes a beam 64 that fixes the shield 60 to the support 62. The third region 54 has a shape that is long in the Y direction. The length L3 in the X direction of the third region 54 is sufficiently smaller than the width W1 of the first region 50 so that the source gas sufficiently wraps under the second layer 16 in the third region 54. The fourth region 56 is a region other than the third region 54 between the first region 50 and the second region 52.

  The mask 80 is formed in the first region 50, the second region 52, and the third region 54. In the fourth region 56, the first layer 14 and the second layer 16 are removed, and the mask 80 is not formed. In the first region 50 and the third region 54, the first layer 14 is removed, and the second layer 16 remains. In the second region 52, the first layer 14 and the second layer 16 remain. On the fourth region 56 side of the second region 52, the second layer 16 is side-etched from the first layer 14, and the first layer 14 has a bowl shape.

With reference to FIG. 6A, the semiconductor layer 12 is formed on the substrate 10. The method for forming the semiconductor layer 12 is, for example, the MOVPE method. The semiconductor layer 12 is, for example, AlGaInAs. Since the source gas diffuses under the shield 60 (region 76), the semiconductor layer 12 having a small film thickness T1 is formed on the substrate 10 under the shield 60. In the second region 52 (support 62), under the bowl-shaped second layer 16 (region 78), the source gas diffuses from one direction in the + Y direction or the −Y direction. The composition ratio becomes non-uniform due to the difference in diffusion rate between the source gas and Ga and Al source gas, and cross hatching is likely to occur. On the other hand, in the region 76, the source gas diffuses from two directions of the ± Y direction as indicated by arrows 72 and 74. For this reason, even if the diffusion rates of the In source gas (arrow 74) and the Ga and Al source gases (arrow 72) are different, the film quality of the semiconductor layer 12 is easily formed. Therefore, it becomes difficult to form a cross hatch.

  6B, since the width W1 of the first region 50 is smaller than that in FIG. 6A, the film thickness T1 is larger than that in FIG. 6A. Since the length L3 in the X direction of the third region 54 (beam 64) is sufficiently small, the influence of the beam 64 on the film thickness of the semiconductor layer 12 is small. Referring to FIG. 6C, since the width W1 of the first region 50 is smaller than that in FIG. 6B, the film thickness T1 is larger than that in FIG. 6B.

  Referring to FIG. 5B, the film thickness T1 with respect to the position X is a constant film thickness on the −X side from the position X0. On the + X side with respect to the position X, the film thickness increases as going to X.

The semiconductor layer 12 was formed using the mask 80 of Comparative Example 1.
The material film thickness of each layer of the mask 80 is as follows.
First layer 82: Al _0.52 In _0.48 As, film thickness H0
Second layer 84: InP, film thickness 1 μm

FIG. 7 is a cross-sectional view of the semiconductor layer 12 formed on a flat substrate. The semiconductor layer 12 was formed by sequentially forming a buffer layer 12a, a core layer 12b, and a cap layer 12c on the substrate 10. The material and film thickness of each layer are as follows.
Buffer layer 12a: InP, film thickness: 20nm
Core layer 12b: AlGaInAsMQW (Multi Quantum Well) layer, film thickness: 400 nm
Cap layer 12c: InP, film thickness: 400nm

  FIG. 8 is a diagram illustrating the normalized film thickness of the core layer 12b with respect to the width W0 of the shield in Comparative Example 1. When the film thickness of the core layer 12b of the semiconductor layer 12 formed on the flat substrate 10 is To and the film thickness of the core layer 12b of the semiconductor layer 12 in the opening 83 is T0, the normalized film thickness is T0 / To. It was. A mask 80 having a film thickness H0 of the first layer 14 of 1.67 μm and 4.75 μm was used. Referring to FIG. 8, as the width W0 becomes smaller, the normalized film thickness becomes smaller. The normalized film thickness is smaller as the film thickness H0 of the first layer 82 is larger. After removing the mask 80, the presence or absence of cross hatching on the surface of the semiconductor layer 12 was observed using an optical microscope. When the normalized film thickness was smaller than 0.85, a cross hatch was observed in the semiconductor layer 12 regardless of H0.

  FIG. 9A and FIG. 9B are schematic views showing surface photographs of Comparative Example 1 and Example 1. FIG. 9A and 9B are schematic diagrams of photographs in which the semiconductor layer 12 is formed using the mask 80, and the surfaces of the substrate 10 and the semiconductor layer 12 after the mask 80 is removed are observed using an optical microscope. It is. 9A is an example in which a cross hatch is observed in Comparative Example 1, and FIG. 9B is an example in which no cross hatch is observed in Example 1. FIG. As shown in FIG. 9A, the cross hatch 30 is observed on the surface of the semiconductor layer 12.

The following is the film thickness ratio with respect to the width of the first region 50 (shielding body 60) in order to obtain the optimum value of the modulation (relationship between x and W1) of the first region 50 (shielding body 60) W1 of the first embodiment. The experimental results when the width of the first region 50 is made constant are shown.
The experimental conditions are as follows.
The semiconductor layer 12 was formed using the mask 80 of Example 1.
The material film thickness of each layer of the mask 80 is as follows.
First layer 14: Al _0.52 In _0.48 As, film thickness: 1.67 μm
Second layer 16: InP, film thickness: 6 μm
The structure of the semiconductor layer 12 is the same as that of Comparative Example 1.
The method for forming the mask 80 is the same as in Example 2 described later.

  FIG. 10 is a plan view of the mask. With reference to FIG. 10, the width W <b> 1 of the first region 50 (the shield 60) is constant. The width of the third region 54 (beam 64) in the Y direction is W3, the length in the X direction is L3, and the pitch of the third region 54 in the X direction is L4. The interval between the second regions 52 (supports 62) in the Y direction is W5. W5 = 2 × W3 + W1.

  FIG. 11 is a diagram illustrating the normalized film thickness of the core layer 12b with respect to the width W1 of the shield when the interval W5 of the support 62 is 140 μm in Example 1. The method for calculating the normalized film thickness is the same as in FIG. Referring to FIG. 11, the normalized film thickness increases as the width W1 decreases.

  FIG. 12 is a diagram showing the presence or absence of a cross hatch with respect to the width W1 of the shield 60 and the interval W5 of the support 62. As shown in FIG. Referring to FIG. 12, after removing mask 80, the presence or absence of cross hatching on the surface of semiconductor layer 12 was observed using an optical microscope. “◯” indicates that no cross hatch is observed, and “X” indicates that a cross hatch is observed. When W5 = 50 μm, cross hatching was observed at W1 = 15 μm and 20 μm. A cross hatch was not observed except under these conditions. When W5 = 50 μm and W1 = 15 μm, W3 = 17.5 μm. When W5 = 50 μm and W1 = 20 μm, W3 = 15 μm. Under other conditions, W3 is 19 μm or more.

  As described above, when the width W3 in the Y direction of the beam 64 (corresponding to the interval between the first region 50 and the second region 52 (corresponding to the interval between the shield 60 and the support 62)) becomes small, the semiconductor layer 12 A cross hatch is formed. Therefore, it is preferable that the width W3 is large so that a cross hatch is not formed in the semiconductor layer 12. In the case of FIG. 12, the width W3 is preferably 18 μm or more. In order to provide a margin, the width W3 is more preferably 20 μm or more, and further preferably 30 μm or more.

  FIG. 13A to FIG. 13C are diagrams showing the presence or absence of sagging of the shield with respect to the beam width W3 and length L3. With reference to FIG. 13A, the pitch L4 in the X direction of the beam 64 was set to 50 μm, and the sag of the shield 60 was observed with respect to the width W3 in the Y direction and the length L3 in the X direction. The width W1 in the Y direction of the shield 60 is a width necessary for realizing a normalized film thickness of 0.2 or less of the core layer 12b. “◯” indicates no sagging, and “x” indicates sagging. When the length L3 of the beam 64 is 1 μm, 1.5 μm and 2 μm, the beam 64 becomes “x” when the width W3 of the beam 64 is 62 μm or more, 73 μm or more and 91 μm or more, respectively.

  With reference to FIG. 13B, the pitch L4 in the X direction of the beams 64 was set to 150 μm, and the sag of the shield 60 was observed with respect to the width W3 in the Y direction and the length L3 in the X direction. The width W1 of the shield 60 in the Y direction is 15 μm. When the length L3 of the beam 64 is 1 μm, 1.5 μm and 2 μm, the width W3 of the beam 64 is 42 μm or more, 50 μm or more and 62 μm or more. "

  FIG. 13C shows the result of conversion when the width W1 of the beam 64 in FIG. 13A is 10 μm (the width necessary to realize the normalized film thickness 0.33 of the core layer 12b). . Referring to FIG. 13C, when the length L3 of the beam 64 is 1 μm, 1.5 μm and 2 μm, the beam 64 becomes “x” when the width W3 of the beam 64 is 93 μm or more, 110 μm or more and 137 μm or more, respectively.

  The shield 60 is supported on the support 62 by a beam 64. Therefore, when the width W1 of the shield 60 increases, the length L3 of the beam 64 decreases, or the width W3 of the beam 64 increases, the shield 60 hangs down due to gravity or the like. When the pitch L4 of the beams 64 is increased, the shield 60 is likely to hang down as shown in FIG. However, when the pitch L4 of the beams 64 is increased, the influence of the beams 64 on the film thickness modulation of the semiconductor layer 12 is reduced. Thereby, it is preferable that the pitch L4 is increased. Further, when the width W3 of the beam 64 is increased, the shield 60 is likely to hang down. Therefore, it is not preferable to make the width W3 of the beam 64 too large. Therefore, the width W3 is preferably 100 μm or less. The width W3 is more preferably 80 μm or less, and further preferably 60 μm or less.

  When the second layer 16 is thinned, the shield 60 is likely to hang down and the width W3 of the beam 64 cannot be increased. Thereby, as shown in FIG. 12, the semiconductor layer 12 is likely to be cross-hatched. If the width W1 of the shield 60 is reduced, drooping is less likely to occur as shown in FIGS. 13 (a) to 13 (c). However, the range in which the thickness of the semiconductor layer 12 can be modulated becomes narrow. Therefore, the film thickness of the second layer 16 is preferably 3 μm or more, and more preferably 4 μm or more. When the second layer 16 is thick, the etching of the second layer 16 becomes difficult. Therefore, the film thickness of the second layer 16 is preferably 8 μm or less, and more preferably 7 μm or less.

  Further, a plurality of beams 64 (third region 54) are provided on one side of the shield 60 (first region 50). Thereby, the sagging of the shield 60 can be suppressed.

  Next, an example of film thickness modulation of the semiconductor layer 12 will be described.

  FIG. 14A is a plan view of an example of the mask, and FIG. 14B is a diagram showing the film thickness of the semiconductor layer 12 immediately below the center line of the shield 60. Referring to FIG. 14A, in the X direction, the mask 80 is provided between X1 and X2. On the −X side from the position X0, the width W1 in the Y direction of the shield 60 (first region 50) is constant. On the + X side from the position X0, the width W1 in the Y direction of the shield 60 is uniformly reduced. The width of the shield 60 at the position X2 is WH. The width in the Y direction of the support body 62 (second region 52) is WA, the width in the Y direction of the shield body 60 on the −X side from X0 is WC, and the fourth region 56 (between the shield body 60 and the support body 62). ) In the Y direction is WB. The distance between X1 and X2 is LG, and the distance between X0 and X2 is LF. The length LE of the beam 64 in the X direction and the pitch of the beam 64 in the X direction are LD.

The position X2 is 0, and the −X direction from the position X2 is x. When the width W1 (x) of the first region 50 changes linearly with respect to x, W1 (x) is expressed by the following formula.
W1 (x) = WH + (WC−WH) × x / LF
Referring to FIG. 14B, the film thickness of the semiconductor layer 12 decreases exponentially when x is from 0 to X2-X0. When x is X2−X0 or more, the film thickness is constant.

FIG. 15A is a plan view of another example of the mask, and FIG. 15B is a diagram showing the thickness of the semiconductor layer with respect to x. Referring to FIG. 15A, the width W1 (x) of the first region 50 varies exponentially with respect to x as in the following equation.
W1 (x) = WH × exp (X / LF × Log (WC / WH))
Referring to FIG. 15B, the film thickness of the semiconductor layer 12 decreases linearly when x is from 0 to X2-X0.

  As shown in FIGS. 14A to 15B, the film thickness of the semiconductor layer 12 is adjusted in the X direction by modulating the width W1 (x) of the shield 60 (first region 50) in the X direction. It can be modulated arbitrarily.

  For example, WA = 40 μm, WB = 27.5 μm, WC = 15 μm, LD = 150 μm, LE = 1 μm, LF = 200 μm, LG = 301 μm, and WH = 1 μm. The WA may be set so that when the first layer 14 is etched, the minimum width in the Y direction of the first layer 14 is 3 μm or more (1/2 of the film thickness of the second layer 16 of the mask 80). preferable. In order to reduce the composition distribution of the semiconductor layer 12 by vapor phase diffusion of the source gas, WB is preferably 20 μm or more, and more preferably 30 μm or more. LD is preferably 30 μm or more, and more preferably 50 μm or more. In order to reduce the composition distribution of the semiconductor layer 12 by the third region 54, LE is preferably 3 μm or less, and more preferably 2 μm or less. LE / LD ≦ 0.1 is preferable, and LE / LD ≦ 0.05 is more preferable.

  According to the first embodiment, the semiconductor layer 12 is grown on the substrate 10 using the mask 80. Thereby, the film thickness can be modulated in the longitudinal direction of the shield 60 as shown in FIG. Further, the film quality of the semiconductor layer 12 can be made uniform. Further, a second layer 16 is formed on the first layer 14 to form a mask 80. This facilitates control of the film thickness.

  The third region 54 is formed symmetrically with respect to the longitudinal axis of the first region 50. Thereby, the semiconductor layer 12 can be formed symmetrically with respect to the longitudinal axis.

  As shown in FIGS. 6A to 6C, the semiconductor layer 12 manufactured according to Example 1 has a thinner central portion than the end portion in the lateral direction. The amount of depression at the center in the width direction of the semiconductor layer 12 is larger when the thickness T1 of the semiconductor layer 12 is smaller.

  Further, as the semiconductor layer 12, an InP buffer layer 12a formed on the substrate 10, a core layer 12b containing AlGaInAs or AlInAs formed on the buffer layer 12a, and an InP cap layer 12c formed on the core layer 12b. And have. Thus, the semiconductor layer 12 containing AlGaInAs or AlInAs has been difficult to modulate the film thickness so far, but according to the first embodiment, the film thickness can be easily modulated.

As Example 1, the following materials can also be used, for example.
Top layer of substrate 10: InP
First layer 14: AlInAs, GaInAs, or AlGaInAs
Second layer 16: InP
Buffer layer 12a: InP
Core layer 12b: InGaAsPMQW layer Cap layer 12c: InP
Etching solution for the first layer 14: sulfuric acid: hydrogen peroxide solution: water = 1: 1: 1

The following materials can also be used.
Top layer of substrate 10: InGaAsP
First layer 14: InP
Second layer 16: InGaAsP or GaInAs
Buffer layer 12a: InP or InGaAsP
Core layer 12b: InGaAsPMQW layer Cap layer 12c: InGaAsP
Etching solution for first layer 14: hydrochloric acid: water = 1: 1

Furthermore, the following materials can also be used.
Top layer of substrate 10: GaInAsP
First layer 14: InP
Second layer 16: InGaAsP
Buffer layer 12a: InP or InGaAsP
Core layer 12b: AlGaInAsMQW layer Cap layer 12c: AlGaInAs or InGaAsP
Etching solution for the first layer: hydrochloric acid: water = 1: 1

  If the diffusion rates of elements differ during the formation of the semiconductor layer 12, the composition of the semiconductor layer 12 is difficult to be uniform. Therefore, when the semiconductor layer 12 includes In and Al, or when In and Ga are included, it is effective to use the first embodiment. For example, in Example 1, AlGaInAs may include AlInAs or GaInAs. The configuration of the semiconductor layer 12 is not limited to the above. For example, when the semiconductor layer 12 includes a plurality of elements, the diffusion rates of the elements may be different when the semiconductor layer 12 is formed. Therefore, it is effective to use Example 1. The first layer 14, the second layer 16, the buffer layer 12a, the core layer 12b, and the cap layer 12c are preferably a combination of materials that are epitaxially grown.

  The etchant for the first layer 14 is preferably a solution in which the first layer 14 is etched and the outermost surface of the substrate 10 and the second layer 16 are not easily etched. For example, when the outermost surface of the substrate 10 and the first layer 14 contain InP and the second layer 16 contains As, the sulfuric acid-based solution containing hydrogen peroxide or the hydrochloric acid-based solution containing hydrogen peroxide as the etching solution for the first layer 14 Can be used. When the outermost surface of the substrate 10 and the first layer 14 contain As and the second layer 16 is InP, a hydrochloric acid-based solution or bromine-based solution not containing hydrogen peroxide is used as the etching solution for the first layer 14. Can do.

  An example of a spot size converter will be described as a semiconductor device in which the first embodiment is used. FIG. 16 is a block diagram of a system in which the semiconductor device according to the second embodiment is used. Referring to FIG. 16, spot size converters 91 and 92, Mach-Zehnder modulator 93, waveguides 94 and 95, and wiring 102 are formed on a substrate 90. The spot size converter 91 is irradiated with a laser beam 98 from the tip sphere fiber 96. The spot size converter 91 converts the spot size of the laser beam 98 into the size of the waveguide 95. The Mach-Zehnder modulator 93 modulates the optical signal propagated through the waveguide 94 using the electrical signal 103 propagated through the wiring 102 and outputs the modulated signal to the waveguide 95. The spot size converter 92 converts the spot size of the modulated light 99 into the size of the front-end fiber 97. Thus, the spot size converters 91 and 92 have a function of converting the spot size of the optical signal.

  FIG. 17A to FIG. 32C are diagrams illustrating a method for manufacturing the semiconductor device (spot size converter) according to the second embodiment. FIGS. 17A to 32A and 25D are plan views, and FIGS. 17B to 32B are AA in FIGS. 17A to 32A, respectively. Cross-sectional views, FIGS. 17 (c) to 31 (c) are cross-sectional views taken along the line BB of FIGS. 17 (a) to 31 (a), respectively. FIGS. 25 (e), 31 (d), and 32 (c) are CC cross-sectional views of FIGS. 25 (a), 31 (a), and 32 (a), respectively.

Referring to FIGS. 17A to 17C, the substrate 10 is prepared by forming an n-type InP clad layer on the InP substrate. Hereinafter, the InP substrate and the n-type InP clad layer are shown as the substrate 10. The n-type InP cladding layer is grown using the MOVPE method. The growth pressure is 1 × 10 ⁴ Pa and the growth temperatures are 650 ° C. and 600 ° C., respectively. The film thickness of the n-type InP cladding layer is 2 μm. The main surface of the substrate 10 is the (100) plane, and the −X direction is the [011] direction.

Referring to FIGS. 18A to 18C, an AlInAs layer is formed as the first layer 14 and an InP layer is formed as the second layer 16 on the substrate 10. The first layer 14 and the second layer 16 are formed using the MOVPE method. The growth pressure is 1 × 10 ⁴ Pa and the growth temperature is 650 ° C. The film thicknesses of the first layer 14 and the second layer 16 are 1.6 μm and 6 μm, respectively. The first layer 14 is preferably Al _0.52 In _0.48 As lattice-matched with the InP layer.

  Referring to FIGS. 19A to 19C, an insulating film 18 is formed on the second layer 16. The insulating film 18 is a silicon nitride film and is formed using a sputtering method. The film thickness of the insulating film 18 is 0.6 μm. The insulating film 18 may be a silicon oxide film.

  Referring to FIGS. 20A to 20C, the insulating film 18 is patterned using an exposure technique and an etching method. The insulating film 18 is formed in the first region 50, the second region 52, and the third region 54 and is removed from the fourth region 56. The fourth region 56 becomes the opening 19 of the insulating film 18, and the surface of the second layer 16 is exposed in the opening 19. On the −X side from the position X0, the width of the first region 50 is constant. On the + X side from the position X0, the width of the first region 50 becomes smaller in the X direction.

  Referring to FIGS. 21A to 21C, the second layer 16 is dry-etched using the insulating film 18 as a mask. By controlling the etching time from the etching rate obtained in advance, dry etching is performed until the first layer 14 is exposed at a desired opening. The etching is not a problem unless it reaches the substrate 10, but is preferably a dry etching amount that leaves 1 μm or more of the first layer 14 so as not to damage the substrate 10. As a result, an opening 19 is formed in the second layer 16, and the first layer 14 is exposed in the opening 19.

  Referring to FIGS. 22A to 22C, the insulating film 18 is removed. A hydrofluoric acid solution is used to remove the insulating film 18. Then, it is washed with water and dried.

  Referring to FIGS. 23A to 23C, the first layer 14 in the first region 50, the third region 54, and the fourth region 56 is etched using the second layer 16 as a mask. As an etching solution, a 1: 1: 1 solution of sulfuric acid: hydrogen peroxide: water is used. This etching solution hardly etches InP and etches AlInAs. As a result, an opening 19 is formed in the first layer 14, and the surface of the substrate 10 is exposed in the opening 19. The first layer 14 in the first region 50 and the third region 54 is removed, and the cavity 20 is formed under the second layer 16 in the first region 50. The first layer 14 is removed at the end of the second region 52, and the void 21 is formed. Then, it is washed with water and dried. As described above, the mask 80 is formed from the first layer 14 and the second layer 16. The second layer 16 in the first region 50 becomes the shield 60. The first layer 14 and the second layer 16 in the second region 52 serve as the support body 62. The second layer 16 in the third region 54 becomes the beam 64.

With reference to FIG. 24A to FIG. 24C, the semiconductor layer 12 is formed on the substrate 10 using the mask 80. The semiconductor layer 12 is grown using the MOVPE method. The growth pressure is 1 × 10 ⁴ Pa, and the growth temperatures are 650 ° C. and 530 ° C. For the semiconductor layer 12, an InP buffer layer having a growth temperature of 650 ° C. and a thickness of 20 nm and an AlGaInAsMQW layer having a thickness of 400 nm are formed in this order from the substrate 10 side. Subsequently, an undoped InP cladding layer having a growth temperature of 530 ° C. and a thickness of 400 nm is formed on the MQW layer. A semiconductor film 86 is formed on the upper, lower and side surfaces of the mask 80.

  Referring to FIGS. 25A to 25E, the first layer 14 in the second region 52 is etched to form a film formed on the upper surface, the lower surface, and the side surface of the second layer 16 and the second layer 16. Lift off 86. As the etchant, a 1: 1: 1 solution of sulfuric acid: hydrogen peroxide: water is used. Since this etching solution hardly etches InP, the semiconductor layer 12 and the substrate 10 are hardly etched.

  In FIG. 25A, the broken line indicates one of the contour lines of the film thickness of the semiconductor layer 12. In FIG. 25D, the solid line indicates the contour line of the film thickness of the semiconductor layer 12. A recess is formed in the semiconductor layer 12 formed in the first region 50. In the CC (center line of the first region 50) line between X0 and X2 in the recess, the semiconductor layer 12 becomes thicker as X increases.

  Referring to FIGS. 26A to 26C, an insulating film 22 is formed on the substrate 10 and the semiconductor layer 12. The insulating film 22 is a silicon nitride film and is formed using a sputtering method. The film thickness of the insulating film 22 is 0.2 μm. The insulating film 22 may be a silicon oxide film. The insulating film 22 is patterned using an exposure technique and an etching method. The insulating film 22 is removed in the first region 50. On the −X side from the position X0, the width of the opening formed in the insulating film 22 is substantially constant. On the X side from the position X0, the width of the opening formed in the insulating film 22 increases as it goes in the X direction. The insulating film 22 is not formed on the X side from the position X2. The change point of the opening of the insulating film 22 may be other than the positions X0 and X2. The width of the opening of the insulating film 22 does not have to coincide with the first region 50.

Referring to FIGS. 27A to 27C, the semiconductor layer 24 is formed using the insulating film 22 as a mask. The semiconductor layer 24 is grown using the MOVPE method. The growth pressure is 1 × 10 ⁴ Pa, and the growth temperatures are 600 ° C. and 530 ° C. As the semiconductor layer 24, a growth temperature is 600 ° C., and an undoped InP cladding layer having a thickness of 100 nm, a p-type InP cladding layer having a thickness of 800 nm, and a p-type InGaAsP layer having a thickness of 100 nm in this order from the semiconductor layer 12 side. Form a layer. A p-type GaInAs contact layer is grown on the intermediate layer at a growth temperature of 530.degree. The InGaAsP intermediate layer is a layer that lattice-matches with InP and the composition gradually changes from InP to GaInAs. The p-type GaInAs contact layer is In _0.53 Ga _0.47 As.

  The film thickness of the semiconductor layer 24 depends on the opening width W8 in the Y direction of the mask of the insulating film 22. When the opening width W8 is large, the semiconductor layer 24 becomes thin, and when the opening width W8 is small, the semiconductor layer 24 becomes thick.

  Referring to FIGS. 28A to 28C, the insulating film 22 is removed. A hydrofluoric acid solution is used to remove the insulating film 22. Then, it is washed with water and dried.

  Referring to FIGS. 29A to 29C, an insulating film 26 is formed on the substrate 10 and the semiconductor layers 12 and 24. The insulating film 26 is a silicon nitride film and is formed using a sputtering method. The film thickness of the insulating film 26 is 0.6 μm. The insulating film 26 may be a silicon oxide film. The insulating film 26 is patterned using an exposure technique and an etching method. The insulating film 26 is divided into three parts: a central part in the Y direction of the first region 50, a + Y side portion with respect to the first region 50, and a −Y side portion with respect to the first region 50. The central portion overlapping the first region 50 is narrower than the first region 50. The width of the insulating film 26 is constant on the −X side from the position X0 and on the X side from the position X2. Between the positions X0 and X2, the width of the insulating film 26 decreases as it goes in the X direction. The distance between the + Y side portion and the -Y side portion is constant.

  Referring to FIGS. 30A to 30C, the semiconductor layers 12 and 24 and the substrate 10 are dry-etched using the insulating film 26 as a mask. For dry etching, a chlorine-based gas is used. Thereby, a recess 28 is formed in the substrate 10 and the semiconductor layer 12, and a protrusion 29 including the semiconductor layer 12 and the semiconductor layer 24 is formed between the recesses 28. Due to the influence of the semiconductor layer 24, a step 27 is formed on the substrate 10 in the recess 28.

  Referring to FIGS. 31A to 31D, the insulating film 26 is removed. A hydrofluoric acid solution is used to remove the insulating film 26. Then, it is washed with water and dried. Between the vicinity of the position X1 and X0, the width and height of the convex portion 29 are substantially constant. As shown in FIG. 31A, between the positions X0 and X2, the width of the convex portion 29 becomes smaller as it goes in the + X direction. As shown in FIG. 31D, the film thickness of the semiconductor layer 12 in the convex portion 29 increases in the + X direction between the positions X0 and X2. The film thickness of the semiconductor layer 24 in the convex portion 29 decreases as it goes in the + X direction.

    32A to 32C, the substrate 10 is cleaved at AA. Thus, the spot size converter 35 is formed. In the convex portion 29 of the spot size converter 35, the width of the semiconductor layer 12 in the Y direction decreases as it goes in the + X direction. As a result, the light incident in the + X direction from the −X direction has a smaller spot size as it goes in the + X direction. The thickness of the semiconductor layer 12 increases as it goes in the + X direction. The film thickness of the core layer 12b is also increased. As a result, the light incident in the −X direction gathers from the cladding layer to the core layer as it goes in the + X direction, and the spot size is reduced. In this way, light incident in the + X direction from the −X direction is converted so that the spot size becomes small. On the other hand, light incident in the −X direction from the + X direction is converted so as to increase the spot size.

  According to the second embodiment, as shown in FIGS. 18A to 18C, the first layer 14 is formed on the substrate 10 and the second layer 16 is formed on the first layer 14. As shown in FIG. 21A to FIG. 23C, the second layer 16 is left in the first region 50 and the third region 54, the first layer 14 is removed, and the first layer 14 in the second region 52 is removed. The second layer 16 is left, and the first layer 14 and the second layer 16 are removed in the fourth region 56. Thereby, the mask 80 is formed. As shown in FIGS. 24A to 24C, the semiconductor layer 12 is formed in the first region 50 and the fourth region 56 on the substrate 10 using the mask 80. Thereby, as in the first embodiment, the film thickness can be modulated in the longitudinal direction of the mask 80. Further, the film quality of the semiconductor layer 12 can be made uniform. Furthermore, the film thickness can be easily controlled.

  The mask 80 is formed as follows. As shown in FIGS. 21A to 21C, the second layer 16 in the fourth region 56 is removed so that the second layer 16 in the first region 50, the second region 52, and the third region 54 remains. To do. As shown in FIG. 23A to FIG. 23C, the first region 50, the third region 54, and the first region 50 are masked using the second layer 16 remaining in the first region 50, the second region 52, and the third region 54 as a mask. The first layer 14 in the four regions 56 is removed. Thereby, the mask 80 can be easily created.

  33A to 33C are cross-sectional views when the semiconductor layer of Example 3 is formed. FIG. 33A to FIG. 33C show the first region 50 and the fourth region 56. The second layer 16 is formed of an insulating film. For example, the insulating film is a silicon oxide film or a silicon nitride film. A broken line and a hatched area in the semiconductor layer 12 indicate the semiconductor layer 12 in the case of Example 1 in which the second layer 16 is a semiconductor. The solid line of the semiconductor layer 12 indicates the semiconductor layer 12 of Example 3.

  In Example 1, as shown in FIGS. 6A to 6C, semiconductor films 86 are formed on and under the second layer 16. This is because the second layer 16 is made of a semiconductor. On the other hand, when the second layer 16 is an insulating film, the film 86 is not formed above and below the second layer 16 as shown in FIGS. 33 (a) to 33 (c). Therefore, the semiconductor corresponding to the film 86 is formed as the semiconductor layer 12. Therefore, the semiconductor layer 12 is thicker than in the first embodiment. For this reason, in Example 3, in order to obtain the same film thickness of the semiconductor layer 12 as in Example 1, the width W1 is made larger. This tends to make the film quality non-uniform.

  As in the third embodiment, the second layer 16 may be an insulating film. However, in order to make the film quality of the semiconductor layer 12 more uniform, the second layer 16 is preferably made of a semiconductor as in the first embodiment. More preferably, each semiconductor has an epitaxially grown composition. In order to form a semiconductor as the second layer 16, the first layer 14 is preferably a semiconductor. When the second layer 16 is an insulating film, the first layer 14 can be a semiconductor. In this case, the composition may not be epitaxially grown as long as it is a semiconductor that can be selectively etched with respect to the insulating film and the substrate 10.

  The substrate 10 is InP whose main surface is (001), the first layer 14 is GaInAs, the second layer 16 is InP, and a mask 80 is formed using an etching solution containing hydrogen peroxide for etching the second layer 16.

  FIG. 34 is a plan view of the mask after etching the first layer. Referring to FIG. 34, when the first layer 14 is etched using the second layer 16 as a mask, the first layer 14 is largely side-etched in the [100] direction. When the side etching amount L00 in the [110] direction is 14.3 μm, the side etching amount L01 in the [100] direction is 69.7 μm. As a result, a part 68 of the second layer 16 comes into contact with the substrate 10.

  FIG. 35 is a plan view of the mask after etching the first layer. Referring to FIG. 35, the first layer 14 was side-etched using the circular second layer 16. The amount of side etching in the [100] direction is larger than the [110] direction. Thus, it can be seen that the etching rate in the [100] direction is faster than that in the [110] direction.

  FIG. 36A to FIG. 36G are cross-sectional views illustrating the mask manufacturing method according to the fourth embodiment. The right side of the center line is a cross-sectional view in the [110] direction, and the left side is a cross-sectional view in the “100” direction. FIG. 37A and FIG. 38A are plan views showing a method for manufacturing a mask according to the fourth embodiment. FIGS. 37 (b) and 38 (b) are cross-sectional views taken along the line AA in FIGS. 37 (a) and 38 (a).

  Referring to FIG. 36A, a GaInAs layer is formed as the first layer 14 on the (001) InP substrate 10. An InP layer is formed as the second layer 16 on the first layer 14. An insulating film 18 is formed on the second layer 16. Referring to FIG. 36B, the insulating film 18 is patterned. Referring to FIGS. 37 (a) and 37 (b), the insulating film 18 is a rectangle whose sides are the [110] direction and a direction equivalent to [110]. The direction of the vertex is the [100] direction.

  Referring to FIG. 36C, the second layer 16 is removed using the insulating film 18 as a mask. Referring to FIG. 36D, the insulating film 18 is removed. Referring to FIG. 36E, the insulating film 32 is formed.

  Referring to FIGS. 38A and 38B, an insulating film 32 is formed so as to cover the apex of the second layer 16. The [110] direction passing through the side of the second layer 16 is defined as a direction 33b and the [100] direction passing through the apex is defined as a direction 33a. Referring to FIG. 36F, the first layer 14 is etched using a sulfuric acid etching solution with the insulating film 32 and the second layer 16 as a mask. The amount of side etching in the direction 33a is larger than that in the direction 33b. Referring to FIG. 36G, the insulating film 32 is removed.

  Since the apex in the [100] direction is covered with the insulating film 32, the side etching of the first layer 14 in the [100] direction is suppressed.

  FIG. 39 is a plan view showing the relationship between the second layer and the insulating film. Referring to FIG. 39, the amount of side etching in the [110] direction of the first layer 14 using the second layer 16 as a mask is L00. A pattern obtained by reducing the pattern of the second layer 16 to the L00 inner side is referred to as a pattern 40. A tangent line between the pattern 40 and the (100) plane is defined as a straight line 42. The straight line 42 passes through the apex of the pattern 40 and becomes a straight line having an angle of 45 ° with respect to the side of the pattern 40. A straight line parallel to the straight line 42 and in contact with the apex of the pattern of the insulating film 32 is defined as a straight line 44. The distance between the straight line 42 and the straight line 44 is L02. As shown in FIG. 34, the side etching amount of the first layer 14 in the [100] direction is about five times that in the [110] direction. Therefore, L02 is preferably 5 times or more of L00.

  According to Example 4, the second layer 16 is GaInAs. When forming the mask 80, as shown in FIG. 36 (e), after the second layer 16 is removed, the first layer 14 is removed, and then the insulation is formed on the second layer 16 at the corners of the second region 52. A film 32 is formed. Thereby, abnormal side etching of the first layer 14 can be suppressed.

  Example 5 is an example of a mask manufacturing method for making the shield 60 difficult to hang down by making the second layer in the first region thinner than the second layer in the third region. FIG. 40A to FIG. 41E are diagrams showing the manufacturing method of the fifth embodiment. 40 (a) and 41 (a) are plan views, FIG. 40 (b) and FIG. 41 (b) are cross-sectional views taken along lines AA in FIG. 40 (a) and FIG. 41 (a), respectively. c) and FIG. 41 (c) are BB cross-sectional views of FIG. 40 (a) and FIG. 41 (a), respectively, and FIGS. 40 (d) and 41 (d) are FIG. 40 (a) and FIG. 41 (a) is a cross-sectional view taken along the line C-C, and FIGS. 40 (e) and 41 (e) are cross-sectional views taken along the line DD in FIGS. 40 (a) and 41 (a), respectively.

  Referring to FIGS. 40A to 40E, the second layer 16 includes a third layer 16a and a fourth layer 16b formed on the third layer 16a. The third layer 16a and the fourth layer 16b are, for example, an InP layer and a GaInAs layer, respectively. 22A to 22C of the second embodiment, an insulating film 46 is formed so as to cover the second region 52 and the third region 54. The insulating film 46 is hardly formed in the first region 50. Thereafter, the fourth layer 16b is etched using the insulating film 46 as a mask. The insulating film 46 is removed.

  Referring to FIGS. 41A to 41E, in the steps of FIGS. 23A to 23C of the second embodiment, the opening 19, the cavity 20, and the gap 21 are formed, and at the same time, the insulating film 46 is masked. The fourth layer 16b is etched. The insulating film 46 is removed. As a result, the second layer 16 in the first region 50 is thinner than the third region 54.

Assuming that the interval W5 of the second region 52 in FIG. 10, the volume of the shield 60 is Vm, and the volume of the beam 64 is Vs, the film thickness H2 of the second layer 16 can be shielded if the following expression is approximately satisfied. The body 60 does not sag. Α is a constant specific to the material, and the density in the second layer 16 is uniform.
H2 ≧ α × (W5) ² × (1+ (Vm / Vs))

  Thus, in order to reduce the film thickness H2, Vm / Vs may be reduced.

  According to the fifth embodiment, the second layer 16 in the first region 50 is thinner than the second layer 16 in the third region 54. Thereby, the shield 60 can be made thinner than the beam 64. Therefore, Vm / Vs can be reduced. Thereby, even if the film thickness of the second layer 16 of the beam 64 is reduced, the shield 60 is difficult to hang down.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Semiconductor layer 14 1st layer 16 2nd layer 18 Insulating film 32 Insulating film 50 1st area | region 52 2nd area | region 54 3rd area | region 56 4th area | region 80 Mask

Claims (8)

Forming the first layer and the second layer in order from the bottom on the substrate including the first region, the second region, the third region, and the fourth region;
A step of forming a mask after the step of forming the first layer and the second layer;
Using the mask to form a semiconductor layer in the first region and the fourth region on the substrate;
Have
The step of forming the mask includes
Removing the first layer by leaving the second layer in the first region whose width is modulated from one end to the other in the longitudinal direction;
Leaving the first layer and the second layer in the second region provided on both sides of the first region in the short direction and spaced from the first region;
Leaving the second layer and removing the first layer in the third region connecting the first region and the second region;
A step of removing the first layer and the second layer in the fourth region other than the third region between the first region and the second region. Production method. Forming the mask includes removing the second layer in the fourth region so as to leave the second layer in the first region, the second region, and the third region;
Removing the first layer of the first region, the third region, and the fourth region using the second layer remaining in the first region, the second region, and the third region as a mask, and The method of manufacturing a semiconductor device according to claim 1, further comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first layer and the second layer are semiconductors.   4. The method for manufacturing a semiconductor device according to claim 1, wherein an interval between the first region and the second region is 18 μm or more and 100 μm or less. 5.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a film thickness of the second layer is 3 μm or more and 8 μm or less. Said third region, a method of manufacturing a semiconductor device according to any one of claims 1 5, characterized in that it is formed symmetrically with respect to the longitudinal axis of the first region. The first layer is GaInAs;
The step of forming the mask includes a step of forming an insulating film on the second layer at the corner of the second region after the step of removing the second layer and before the step of removing the first layer. The method for manufacturing a semiconductor device according to claim 1, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein the second layer in the first region is thinner than the second layer in the third region.

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